AD ADG1234YRUZ Low capacitance, triple/quad spdt -15 v/12 v i cmos switch Datasheet

Low Capacitance, Triple/Quad SPDT
±15 V/+12 V i CMOS™ Switches
ADG1233/ADG1234
FUNCTIONAL BLOCK DIAGRAMS
ADG1233
S1A
D1
D3
S3A
S2B
D2
S2A
LOGIC
APPLICATIONS
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
GENERAL DESCRIPTION
The ADG1233 and ADG1234 are monolithic iCMOS analog
switches comprising three independently selectable single-pole,
double throw SPDT switches and four independently selectable
SPDT switches, respectively.
All channels exhibit break-before-make switching action
preventing momentary shorting when switching channels.
An EN input on the ADG1233 and ADG1234 is used to
enable or disable the device. When disabled, all channels are
switched off.
The iCMOS (industrial-CMOS) modular manufacturing process
combines a high voltage complementary metal-oxide semiconductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation of
high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased performance, dramatically lowered power consumption, and reduced
package size.
The ultralow capacitance and charge injection of these multiplexers
make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required.
S3B
S1B
IN1 IN2 IN3 EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT
05743-001
1.5 pF off capacitance
0.5 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP
Typical power consumption (<0.03 μW)
Figure 1.
ADG1234
S1A
S4A
D1
D4
S1B
S4B
S2B
S3B
D2
D3
S2A
S3A
LOGIC
IN1 IN2 IN3 IN4 EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT
05743-038
FEATURES
Figure 2.
Fast switching speed coupled with high signal bandwidth make the
parts suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the parts ideally
suited for portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1. 1.5 pF off capacitance (±15 V supply).
2. 0.5 pC charge injection.
3. 3 V logic-compatible digital input, VIH = 2.0 V, VIL = 0.8 V.
4. 16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADG1233/ADG1234
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................7
Applications....................................................................................... 1
ESD Caution...................................................................................7
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ............................8
Functional Block Diagrams............................................................. 1
Terminology .......................................................................................9
Product Highlights ........................................................................... 1
Typical Performance Characteristics ........................................... 10
Revision History ............................................................................... 2
Test Circuits..................................................................................... 13
Specifications..................................................................................... 3
Outline Dimensions ....................................................................... 15
Dual Supply ................................................................................... 3
Ordering Guide .......................................................................... 16
Single Supply ................................................................................. 5
REVISION HISTORY
8/06—Rev. 0 to Rev. A
Updated Format…………………………….….…………Universal
Changes to Table 1…………………………………………….…...3
Changes to Table 2………………………………………………....4
Changes to Figure 11……………………..………………………10
Changes to Figure 12……………………………………………..11
1/06—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADG1233/ADG1234
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT (ON))
LEAKAGE CURRENTS
Source Off Leakage IS (Off )
Drain Off Leakage ID (Off )
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tTRANSITION
tBBM
+25°C
Y Version1
−40°C to +85°C −40°C to +125°C
VSS to VDD
120
190
3.5
6
20
60
±0.02
±0.1
±0.02
±0.1
±0.02
±0.2
230
260
10
12
72
79
±0.6
±1
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −1 mA; see Figure 24
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
±1
2.0
0.8
V min
V max
μA typ
μA max
pF typ
VIN = VINL or VINH
±0.1
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 27
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = +10 V; see Figure 28
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 29
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 33
RL = 10 kΩ, 5 V rms, f = 20 Hz to
20 kHz; see Figure 34
RL = 50 Ω, CL = 5 pF; see Figure 32
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
3
150
170
Off Isolation
−80
dB typ
Channel-to-Channel Crosstalk
−85
dB typ
Total Harmonic Distortion, THD + N
0.14
% typ
−3 dB Bandwidth
CS (Off )
900
1.5
1.7
1.6
1.8
3.5
4
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
CD, CS (On)
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 25
±0.6
Charge Injection
CD (Off )
VDD = +16.5 V, VSS = −16.5 V
VD = ±10 V, VS = −10 V; see Figure 25
nA max
nA typ
nA max
120
140
40
45
0.5
tOFF (EN)
VS = −5 V, 0 V, +5 V; IS = −1 mA
±1
10
tON (EN)
Test Conditions/Comments
±0.6
±0.005
110
130
25
Unit
170
195
55
60
Rev. A | Page 3 of 16
VS = VD = ±10 V; see Figure 26
ADG1233/ADG1234
Parameter
POWER REQUIREMENTS
IDD
+25°C
Y Version 1
−40°C to +85°C −40°C to +125°C
0.002
1.0
IDD
260
420
ISS
0.002
1.0
ISS
0.002
VDD/VSS
1
2
1.0
±5/±16.5
Temperature range for the Y version: −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. A | Page 4 of 16
Unit
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
GND = 0 V
ADG1233/ADG1234
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT (ON))
LEAKAGE CURRENTS
Source Off Leakage IS (Off )
Drain Off Leakage ID (Off )
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
+25°C
Y Version1
−40°C to +85°C −40°C to +125°C
0 to VDD
300
tBBM
567
625
Ω max
Ω typ
16
60
26
27
Ω max
Ω typ
±0.02
nA typ
±0.1
±0.02
±0.6
±1
±0.1
±0.02
±0.2
±0.6
±1
±0.6
±1
2.0
0.8
±0.001
2
135
170
45
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
200
230
10
tON (EN)
V
Ω typ
475
5
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tTRANSITION
Unit
ns typ
ns min
ns typ
Charge Injection
150
195
45
60
−0.3
Off Isolation
−80
dB typ
Channel-to-Channel Crosstalk
−85
dB typ
−3 dB Bandwidth
CS (Off )
600
1.5
1.7
2
2.2
4
4.5
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
tOFF (EN)
CD (Off )
CD, CS (On)
230
265
70
75
ns typ
pC typ
Rev. A | Page 5 of 16
Test Conditions/Comments
VS = 0 V to10 V, IS = −1 mA;
see Figure 24
VDD = 10.8 V, VSS = 0 V
VS = 0 V to10 V, IS = −1 mA
VS = 3 V, 6 V, 9 V, IS = −1 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 25
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 25
VS = VD = 1 V or 10 V, see Figure 26
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 27
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 28
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 29
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 33
RL = 50 Ω, CL = 5 pF; see Figure 32
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
ADG1233/ADG1234
Parameter
POWER REQUIREMENTS
IDD
+25°C
Y Version 1
−40°C to +85°C −40°C to +125°C
0.002
1.0
IDD
260
VDD
1
2
440
5/16.5
Temperature range for the Y version: −40°C to +125°C
Guaranteed by design, not subject to production test.
Rev. A | Page 6 of 16
Unit
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
VSS = 0 V, GND = 0 V
ADG1233/ADG1234
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog, Digital Inputs1
Continuous Current, S or D
Peak Current, S or D (Pulsed at
1 ms, 10% Duty Cycle Mximum)
Operating Temperature Range
Automotive Temperature Range
(Y Version)
Storage Temperature Range
Junction Temperature
TSSOP, θJA, Thermal Impedance
LFCSP, θJA, Thermal Impedance
Reflow Soldering Peak Temperature,
Pb-Fee
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever
occurs first
24 mA
100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating is applied at any one time.
–40°C to +125°C
–65°C to +150°C
150°C
112°C/W
30.4°C/W
260°C
1
Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 7 of 16
ADG1233/ADG1234
ADG1233
14
EN
S1B
4
13
VSS
D1 1
S2B
5
TOP VIEW
(Not to Scale)
12
S3B
S1B 2
D3
10
S3A
IN2
8
9
IN3
D2 4
Figure 3. 16-Lead TSSOP Pin Configuration
D4
17
S4B
16
VDD
GND 6
15
EN
S2B 7
14
S3B
S1B 4
VSS 5
ADG1234
TOP VIEW
(Not to Scale)
D2 8
13
D3
S2A 9
12
S3A
IN2 10
11
IN3
S1A
IN1
EN
IN4
S4A
18
20
19
18
17
16
S4A
D1 3
D1
S1B
VSS
GND
S2B
1
2
3
4
5
PIN 1
INDICATOR
ADG1234
TOP VIEW
(Not to Scale)
15
14
13
12
11
D4
S4B
VDD
S3B
D3
6
7
8
9
10
IN4
19
9 D3
D2
S2A
IN2
IN3
S3A
20
11 VSS
10 S3B
Figure 5. 16-Lead, 4 mm × 4 mm LFCSP Pin Configuration,
Exposed Pad Tied to Substrate, VSS
05743-003
IN1 1
S1A 2
TOP VIEW
(Not to Scale)
12 EN
05743-005
11
7
ADG1233
S2A 5
6
05743-002
D2
S2A
S2B 3
PIN 1
INDICATOR
05743-004
3
14 GND
IN1
D1
13 IN1
GND
15
S3A 8
16
2
IN3 7
1
IN2 6
VDD
S1A
15 VDD
16 S1A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. 20-Lead, 4 mm × 4 mm LFCSP Pin Configuration
Exposed Pad Tied to Substrate, VSS
Figure 4. 20-Lead TSSOP Pin Configuration
Table 4. 16-Lead TSSOP/20-Lead TSSOP Pin Configurations
Table 5. 16-Lead LFCSP/20-Lead LFCSP Pin Configurations
Pin No. ADG1233
16-Lead TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
N/A
N/A
N/A
N/A
Pin No. ADG1233
16-Lead LFCSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
N/A
N/A
N/A
N/A
Pin No. ADG1234
20-Lead TSSOP
16
2
3
4
7
8
9
10
11
12
13
14
5
15
1
6
17
18
19
20
Mnemonic
VDD
S1A
D1
S1B
S2B
D2
S2A
IN2
IN3
S3A
D3
S3B
VSS
EN
IN1
GND
S4B
D4
S4A
IN4
Pin No. ADG1234
20-Lead LFCSP
1
2
5
6
7
8
9
10
11
12
3
18
19
4
13
20
14
15
16
17
Mnemonic
D1
S1B
S2B
D2
S2A
IN2
IN3
S3A
D3
S3B
VSS
EN
IN1
GND
VDD
S1A
S4B
D4
S4A
IN4
Table 6. ADG1233/ADG1234 Truth Table
EN
1
0
0
Rev. A | Page 8 of 16
INx
X
0
1
Switch xA
Off
Off
On
Switch xB
Off
On
Off
ADG1233/ADG1234
TERMINOLOGY
VDD
Most positive supply potential.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
VSS
Most negative power supply potential in dual supplies. In
single-supply applications, it can be connected to ground.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
GND
Ground (0 V) reference.
tBBM
RON
Ohmic resistance between D and S.
Off time measured between the 80% point of both switches
when switching from one address state to another.
ΔRON
Difference between the RON of any two channels.
VINL
Maximum input voltage for Logic 0.
IS (Off)
Source leakage current when switch is off.
VINH
Minimum input voltage for Logic 1.
ID (Off)
Drain leakage current when switch is off.
IINL, IINH
Input current of the digital input.
ID, IS (On)
Channel leakage current when switch is on.
IDD
Positive supply current.
VD, VS
Analog voltage on Terminal D, Terminal S.
ISS
Negative supply current.
CS (Off)
Channel input capacitance for off condition.
Off Isolation
A measure of an unwanted signal coupling through an off channel.
CD (Off)
Channel output capacitance for off condition.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CD, CS (On)
On switch capacitance.
Bandwidth
Frequency at which the output is attenuated by 3 dB.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
On Response
Frequency response of the on switch.
THD + N
Ratio of the harmonic amplitude plus noise of the signal to the
fundamental.
Rev. A | Page 9 of 16
ADG1233/ADG1234
TYPICAL PERFORMANCE CHARACTERISTICS
200
250
TA = 25°C
180
VDD = +13.5V
VSS = –13.5V
200
TA = +125°C
140
ON RESISTANCE (Ω)
120
VDD = +16.5V
VSS = –16.5V
100
80
60
40
TA = +85°C
150
TA = +25°C
100
TA = –40°C
05743-031
50
20
0
–18 –15 –12
–9 –6 –3
0
3
6
9
SOURCE OR DRAIN VOLTAGE (V)
12
15
0
–15
18
Figure 7. On Resistance as a Function of VD (VS ) for Dual Supply
05743-034
ON RESISTANCE (Ω)
160
VDD = +15V
VSS = –15V
VDD = +15V
VSS = –15V
–10
–5
0
5
TEMPERATURE (°C)
600
400
15
Figure 10. On Resistance as a Function of VD (VS ) for Different
Temperatures, Dual Supply
450
TA = 25°C
10
VDD = 10.8V
VSS = 0V
TA = +125°C
VDD = 12V
VSS = 0V
500
VDD = 12V
VSS = 0V
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
350
300
250
VDD = 13.2V
VSS = 0V
200
150
TA = +85°C
400
TA = +25°C
300
TA = –40°C
200
100
05743-033
0
2
4
6
8
10
SOURCE OR DRAIN VOLTAGE (V)
12
0
14
450
4
6
8
TEMPERATURE (°C)
12
10
250
TA = 25°C
400
VDD = 10.8V
VSS = 0V
350
150
LEAKAGE CURRENT (pA)
VDD = 12V
VSS = 0V
300
250
VDD = 13.2V
VSS = 0V
200
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
200
150
100
100
50
0
–50
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) – –
ID, IS (ON) + +
–100
–150
50
05743-033
ON RESISTANCE (Ω)
2
Figure 11. On Resistance as a Function of VD (VS ) for Different
Temperatures, Single Supply
Figure 8. On Resistance as a Function of VD (VS ) for Dual Supply
0
0
0
2
4
6
8
10
SOURCE OR DRAIN VOLTAGE (V)
12
14
Figure 9. On Resistance as a Function of VD (VS ) for Single Supply
Rev. A | Page 10 of 16
–200
–250
0
20
40
05743-017
0
05743-035
100
50
60
80
TEMPERATURE (°C)
100
120
Figure 12. Leakage Currents as a Function of Temperature, Dual Supply
ADG1233/ADG1234
130
220
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
180
160
TIME (ns)
30
–20
120
100
80
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) – –
ID, IS (ON) + +
0
20
BOFF AON 15V DS
60
BOFF AON 12V DS
40
40
60
80
TEMPERATURE (°C)
100
05743-011
–70
–120
AOFF BON 15V DS
140
05743-018
LEAKAGE CURRENT (pA)
80
AOFF BON 12V DS
200
20
0
–40
120
Figure 13. Leakage Currents as a Function of Temperature, Single Supply
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 16. tTRANSITION vs. Temperature
0
200
–10
IDD PER CHANNEL
TA = 25°C
180
–20
VDD = +15V
VSS = –15V
140
120
100
80
–40
–50
–60
–70
–80
60
–100
0
2
4
6
05743-006
VDD = 12V
VSS = 0V
20
8
10
LOGIC, INX (V)
12
14
–110
10k
100k
16
Figure 14. IDD vs. Logic Level
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 17. Off Isolation vs. Frequency
6
–10
TA = 25°C
VDD = +15V
VSS = –15V
4
–30
0
CROSSTALK (dB)
VDD = +5V
VSS = –5V
2
VDD = +15V
VSS = –15V
TA = 25°C
–20
VDD = 12V
VSS = 0V
–2
–40
SxA – SxB
–50
–60
–70
S1x – S2x
–80
–4
–6
–15
05743-008
CHARGE INJECTION (pC)
05743-036
–90
40
0
–30
–10
–5
0
VS (V)
5
10
15
05743-012
IDD (µA)
OFF ISOLATION (dB)
160
VDD = +15V
VSS = –15V
TA = 25°C
–90
–100
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 18. Crosstalk vs. Frequency
Figure 15. Charge Injection vs. Source Voltage
Rev. A | Page 11 of 16
100M
1G
ADG1233/ADG1234
0
5.0
VDD = +15V
VSS = –15V
TA = 25°C
4.0
CAPACITANCE (pF)
–10
–15
3.0
2.5
DRAIN OFF
2.0
1.5
SOURCE OFF
1.0
05743-013
–20
–25
10k
SOURCE/DRAIN ON
3.5
100k
1M
10M
100M
FREQUENCY (Hz)
1G
05743-009
ON RESPONSE (dB)
–5
VDD = 12V
VSS = 0V
TA = 25°C
4.5
0.5
0
10G
0
2
4
8
12
10
Figure 22. Capacitance vs. Source Voltage for Single Supply
Figure 19. On Response vs. Frequency
10
5.0
LOAD = 10kΩ
TA = 25°C
VDD = +5V
VSS = –5V
TA = 25°C
4.5
SOURCE/DRAIN ON
CAPACITANCE (pF)
4.0
1
THD + N (%)
6
VBIAS (V)
VDD = +5V, VSS = –5V, VS = +3.5V rms
VDD = +15V, VSS = –15V, VS = +5V rms
0.10
3.5
3.0
2.5
DRAIN OFF
2.0
SOURCE OFF
1.5
0.01
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 20. THD + N vs. Frequency
VDD = +15V
VSS = –15V
TA = 25°C
SOURCE/DRAIN ON
3.5
3.0
2.5
DRAIN OFF
2.0
1.5
SOURCE OFF
1.0
05743-010
CAPACITANCE (pF)
4.0
0.5
0
–15
–10
–5
0
VBIAS (V)
5
0.5
0
–5
–4
–3
–2
–1
0
1
VBIAS (V)
2
3
4
Figure 23. Capacitance vs. Source Voltage for Dual Supply
5.0
4.5
05743-007
05743-037
1.0
10
15
Figure 21. Capacitance vs. Source Voltage for Dual Supply
Rev. A | Page 12 of 16
5
ADG1233/ADG1234
TEST CIRCUITS
V
S
D
IDS
05743-020
VS
Figure 24. On Resistance
A
S
ID (OFF)
D
A
VS
05743-021
IS (OFF)
VD
Figure 25. Off Leakage
ID (ON)
S
D
A
VD
NC = NO CONNECT
05743-022
NC
Figure 26. On Leakage
VDD
VSS
SxB
D
SxA
VOUT
RL
300Ω
INx
VIN
VIN
50%
50%
VIN
50%
50%
VSS
VDD
VS
0.1µF
CL
35pF
90%
VOUT
GND
tON
90%
tOFF
05743-023
0.1µF
Figure 27. Switching Timing
VS
VDD
VSS
VDD
VSS
SxB
VIN
D
SxA
VOUT
RL
300Ω
INx
VIN
0.1µF
CL
35pF
VOUT
80%
tBBM
GND
tBBM
05743-024
0.1µF
Figure 28. Break-Before-Make Delay
Rev. A | Page 13 of 16
ADG1233/ADG1234
0.1µF
VDD
VSS
VDD
VSS
0.1µF
3V
VS
S1A
0V
S1B
tOFF (EN)
ADG1233
VO
D1
EN
VIN
50Ω
50%
50%
RL
300Ω
GND
CL
35pF
VO
0.9VO
0.9VO
OUTPUT
0V
05743-025
IN3
IN2
IN1
ENABLE
DRIVE (VIN)
tON (EN)
Figure 29. Enable Delay, tON (EN), tOFF (EN)
VDD
VSS
VDD
VSS
0.1µF
VIN (NORMALLY
CLOSED SWITCH)
ON
SxB
VS
VOUT
SxA
CL
1nF
INx
VIN
OFF
NC
D
VIN (NORMALLY
OPEN SWITCH)
VOUT
GND
ΔVOUT
QINJ = CL × ΔVOUT
05743-026
0.1µF
Figure 30. Charge Injection
VDD
VDD
VSS
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
NC
SxB
SxA
INx
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
50Ω
VOUT
VDD
VSS
SxA
RL
50Ω
50Ω
VS
SxB
D
D
VIN
RL
50Ω
GND
VOUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VDD
0.1µF
NETWORK
ANALYZER
NC
0.1µF
VDD
50Ω
RS
S
SxB
INx
VS
D
VIN
RL
50Ω
GND
VOUT
VIN
RL
10Ω
05743-028
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
VS
V p-p
D
GND
INSERTION LOSS = 20 log
AUDIO PRECISION
VSS
Figure 32. Bandwidth
Figure 34. THD + Noise
Rev. A | Page 14 of 16
VOUT
05743-030
INx
SxA
VSS
0.1µF
VSS
VOUT
VS
Figure 33. Channel-to-Channel Crosstalk
VSS
0.1µF
05743-029
05743-027
VOUT
Figure 31. Off Isolation
VDD
INx
VS
GND
OFF ISOLATION = 20 log
VDD
R
50Ω
ADG1233/ADG1234
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 36. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Rev. A | Page 15 of 17
0.75
0.60
0.45
ADG1233/ADG1234
4.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
PIN 1
INDICATOR
1
2.25
2.10 SQ
1.95
EXPOSED
PAD
0.75
0.60
0.50
9
8
5
4
0.25 MIN
1.95 BSC
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
0.35
0.30
0.25
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
010606-0
1.00
0.85
0.80
3.75
BSC SQ
16
13
12
0.65 BSC
TOP
VIEW
(BOTTOM VIEW)
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
0.60
MAX
4.00
BSC SQ
0.60
MAX
PIN 1
INDICATOR
TOP
VIEW
20 1
16
15
2.25
2.10 SQ
1.95
3.75
BCS SQ
0.75
0.55
0.35
12° MAX
1.00
0.85
0.80
SEATING
0.50
PLANE
BSC
PIN 1
INDICATOR
11
10
0.80 MAX
0.65 TYP
5
0.25 MIN
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20
REF
6
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 38. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG1233YRUZ1
ADG1233YRUZ-REEL71
ADG1233YCPZ-REEL1
ADG1233YCPZ-REEL71
ADG1234YRUZ1
ADG1234YRUZ-REEL71
ADG1234YCPZ-REEL1
ADG1234YCPZ-REEL71
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
20-Lead Thin Shrink Small Outline Package (TSSOP)
20-Lead Thin Shrink Small Outline Package (TSSOP)
20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05743-0-8/06(A)
Rev. A | Page 16 of 16
Package Option
RU-16
RU-16
CP-16-4
CP-16-4
RU-20
RU-20
CP-20-1
CP-20-1