Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Advance Information Freescale Semiconductor, Inc... 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM Order this document by MCM63P737K/D MCM63P737K MCM63P819K The MCM63P737K and MCM63P819K are 4M–bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache. The MCM63P737K (organized as 128K words by 36 bits) and the MCM63P819K (organized as 256K words by 18 bits) integrate input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). Addresses (SA), data inputs (DQx), and all control signals except output enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled through positive–edge–triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM63P737K and MCM63P819K (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, pipelined SRAMs output data is temporarily stored by an edge–triggered output register and then released to the output buffers at the next rising edge of clock (K). The MCM63P737K and MCM63P819K operate from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible. TQ PACKAGE TQFP CASE 983A–01 ZP PACKAGE PBGA CASE 999–02 • MCM63P737K / MCM63P819K–166 = 3.5 ns Access / 6 ns Cycle (166 MHz) MCM63P737K / MCM63P819K–150 = 3.8 ns Access / 6.7 ns Cycle (150 MHz) MCM63P737K / MCM63P819K–133 = 4 ns Access / 7.5 ns Cycle (133 MHz) • 3.3 V +10%, –5% Core Power Supply, 2.5 V or 3.3 V I/O Supply • ADSP, ADSC, and ADV Burst Control Pins • Selectable Burst Sequencing Order (Linear/Interleaved) • Single–Cycle Deselect Timing • Internally Self–Timed Write Cycle • Byte Write and Global Write Control • Sleep Mode (ZZ) • JEDEC Standard 100–Pin TQFP and 119–Pin PBGA Packages This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 1 1/24/00 Motorola, Inc. 2000 MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P737K•MCM63P819K 1 Freescale Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM LBO ADV K ADSC BURST COUNTER K2 2 17/18 128K x 36 / 256K x 18 ARRAY CLR ADSP 2 SA SA1 SA0 ADDRESS REGISTER 17/18 15/16 SGW Freescale Semiconductor, Inc... SW SBa SBb WRITE REGISTER a 36/18 36/18 WRITE REGISTER b 4/2 SBc* SBd* DATA–OUT REGISTER K WRITE REGISTER d* K2 SE1 SE2 SE3 DATA–IN REGISTER WRITE REGISTER c* ENABLE REGISTER K ENABLE REGISTER G DQa – DQd/ DQa–DQb ZZ * Valid only for MCM63P737K. MCM63P737K•MCM63P819K 2 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. DQc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQa A B C D 1 2 3 4 5 6 7 VDDQ SA SA ADSP SA SA VDDQ NC SE2 SA ADSC SA SE3 NC NC SA SA VDD SA SA NC DQc DQc VSS NC VSS DQb DQb DQc DQc VSS SE1 VSS DQb DQb VDDQ DQc VSS G VSS DQb VDDQ DQc DQc SBc ADV SBb DQb DQb DQc DQc VSS SGW VSS DQb DQb VDDQ VDD NC VDD NC VDD VDDQ E F G H J K DQd DQd VSS K VSS DQa DQa DQd DQd SBd NC SBa DQa DQa VDDQ DQd VSS SW VSS DQa VDDQ L M N P R DQd DQd VSS SA1 VSS DQa DQa DQd DQd VSS SA0 VSS DQa DQa NC SA LBO VDD NC SA NC NC NC SA SA SA NC ZZ VDDQ NC NC NC NC NC VDDQ T U LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA Freescale Semiconductor, Inc... SA SA SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA MCM63P737K PIN ASSIGNMENTS 100–PIN TQFP TOP VIEW 119–BUMP PBGA TOP VIEW Not to Scale MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P737K•MCM63P819K 3 Freescale Semiconductor, Inc. MCM63P737K TQFP PIN DESCRIPTIONS Pin Locations Symbol Type 85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception — chip deselect does not occur when ADSP is asserted and SE1 is high). 83 ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). DQx I/O 86 G Input Asynchronous Output Enable Input: Low — enables output buffers (DQx pins). High — DQx pins are high impedance. 89 K Input Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. 31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter. High — interleaved burst counter. 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 93, 94, 95, 96 (a) (b) (c) (d) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte a, b, c, d). SGW overrides SBx. 98 SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. 97 SE2 Input Synchronous Chip Enable: Active high for depth expansion. 92 SE3 Input Synchronous Chip Enable: Active low for depth expansion. 88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 87 SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. NOTE: An internal pull–down is included for compatibility with SRAM devices that do not support sleep mode. A 100% pin compatibility can be achieved if ZZ is left open or pulled low. 15, 41, 65, 91 VDD Supply Core Power Supply. 4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply I/O Power Supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS Supply Ground. 14, 16, 38, 39, 42, 43, 66 NC — Freescale Semiconductor, Inc... (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 MCM63P737K•MCM63P819K 4 Description Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b, c, d). No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. MCM63P737K PBGA PIN DESCRIPTIONS Pin Locations Symbol Type 4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception — chip deselect does not occur when ADSP is asserted and SE1 is high). 4G ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). DQx I/O 4F G Input Asynchronous Output Enable Input: Low — enables output buffers (DQx pins). High — DQx pins are high impedance. 4K K Input Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. 3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter. High — interleaved burst counter. 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 3T, 4T, 5T SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 5L, 5G, 3G, 3L (a) (b) (c) (d) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte a, b, c, d). SGW overrides SBx. 4E SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. 2B SE2 Input Synchronous Chip Enable: Active high for depth expansion. 6B SE3 Input Synchronous Chip Enable: Active low for depth expansion. 4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 4M SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 7T ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. NOTE: An internal pull–down is included for compatibility with SRAM devices that do not support sleep mode. A 100% pin compatibility can be achieved if ZZ is left open or pulled low. 4C, 2J, 4J, 6J, 4R VDD Supply Core Power Supply. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply I/O Power Supply. 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P VSS Supply Ground. 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R, 7R, 1T, 2T, 6T, 2U, 3U, 4U, 5U, 6U NC — Freescale Semiconductor, Inc... (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P MOTOROLA FAST SRAM Description Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b, c, d). No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MCM63P737K•MCM63P819K 5 Freescale Semiconductor, Inc. NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQb NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SA NC NC VDDQ VSS NC DQa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A B C D 1 2 3 4 5 6 7 VDDQ SA SA ADSP SA SA VDDQ NC SE2 SA ADSC SA SE3 NC NC SA SA VDD SA SA NC DQb NC VSS NC VSS DQa NC NC DQb VSS SE1 VSS NC DQa VDDQ NC VSS G VSS DQa VDDQ NC DQb SBb ADV VSS NC DQa DQb NC VSS SGW VSS DQa NC VDDQ VDD NC VDD NC VDD VDDQ E F G H J K NC DQb VSS K VSS NC DQa DQb NC VSS NC SBa DQa NC VDDQ DQb VSS SW VSS NC VDDQ L M N P R DQb NC VSS SA1 VSS DQa NC NC DQb VSS SA0 VSS NC DQa NC SA LBO VDD NC SA NC NC SA SA NC SA SA ZZ VDDQ NC NC NC NC NC VDDQ T U LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA Freescale Semiconductor, Inc... SA SA SE1 SE2 NC NC SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA MCM63P818 PIN ASSIGNMENTS 100–PIN TQFP TOP VIEW 119–BUMP PBGA TOP VIEW Not to Scale MCM63P737K•MCM63P819K 6 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. MCM63P819K TQFP PIN DESCRIPTIONS Pin Locations Symbol Type 85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception — chip deselect does not occur when ADSP is asserted and SE1 is high). 83 ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). DQx I/O 86 G Input Asynchronous Output Enable Input: Low — enables output buffers (DQx pins). High — DQx pins are high impedance. 89 K Input Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. 31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter. High — interleaved burst counter. 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 99, 100 SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 93, 94 (a) (b) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte a, b). SGW overrides SBx. 98 SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. 97 SE2 Input Synchronous Chip Enable: Active high for depth expansion. 92 SE3 Input Synchronous Chip Enable: Active low for depth expansion. 88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 87 SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. NOTE: An internal pull–down is included for compatibility with SRAM devices that do not support sleep mode. A 100% pin compatibility can be achieved if ZZ is left open or pulled low. Freescale Semiconductor, Inc... (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 Description Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b). 15, 41, 65, 91 VDD Supply Core Power Supply. 4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply I/O Power Supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS Supply Ground. 1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96 NC — MOTOROLA FAST SRAM No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MCM63P737K•MCM63P819K 7 Freescale Semiconductor, Inc. MCM63P819K PBGA PIN DESCRIPTIONS Pin Locations Symbol Type 4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception — chip deselect does not occur when ADSP is asserted and SE1 is high). 4G ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). DQx I/O 4F G Input Asynchronous Output Enable Input: Low — enables output buffers (DQx pins). High — DQx pins are high impedance. 4K K Input Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. 3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter. High — interleaved burst counter. 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 5L, 3G (a) (b) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte a, b). SGW overrides SBx. 4E SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. 2B SE2 Input Synchronous Chip Enable: Active high for depth expansion. 6B SE3 Input Synchronous Chip Enable: Active low for depth expansion. 4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 4M SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 7T ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. NOTE: An internal pull–down is included for compatibility with SRAM devices that do not support sleep mode. A 100% pin compatibility can be achieved if ZZ is left open or pulled low. Freescale Semiconductor, Inc... (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P Description Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b). 4C, 2J, 4J, 6J, 4R VDD Supply Core Power Supply. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply I/O Power Supply. 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P VSS Supply Ground. 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 5R, 7R, 1T, 4T, 2U, 3U, 4U, 5U, 6U NC — MCM63P737K•MCM63P819K 8 No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. TRUTH TABLE (See Notes 1 Through 5) Address Used SE1 SE2 SE3 ADSP ADSC ADV G3 DQx Write 2, 4 Deselect None 1 X X X 0 X X High–Z X Deselect None 0 X 1 0 X X X High–Z X Deselect None 0 0 X 0 X X X High–Z X Deselect None X X 1 1 0 X X High–Z X Deselect None X 0 X 1 0 X X High–Z X Begin Read External 0 1 0 0 X X X High–Z X Begin Read Freescale Semiconductor, Inc... Next Cycle External 0 1 0 1 0 X X High–Z READ Continue Read Next X X X 1 1 0 1 High–Z READ Continue Read Next X X X 1 1 0 0 DQ READ Continue Read Next 1 X X X 1 0 1 High–Z READ Continue Read Next 1 X X X 1 0 0 DQ READ Suspend Read Current X X X 1 1 1 1 High–Z READ Suspend Read Current X X X 1 1 1 0 DQ READ Suspend Read Current 1 X X X 1 1 1 High–Z READ Suspend Read Current 1 X X X 1 1 0 DQ READ Begin Write External 0 1 0 1 0 X X High–Z WRITE Continue Write Next X X X 1 1 0 X High–Z WRITE Continue Write Next 1 X X X 1 0 X High–Z WRITE Suspend Write Current X X X 1 1 1 X High–Z WRITE Suspend Write Current 1 X X X 1 1 X High–Z WRITE NOTES: 1. X = don’t care. 1 = logic high. 0 = logic low. 2. Write is defined as either 1) any SBx and SW low or 2) SGW is low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times. ASYNCHRONOUS TRUTH TABLE Operation ZZ G I/O Status Read L L Data Out (DQx) Read L H High–Z Write L X High–Z Deselected L X High–Z Sleep H X High–Z 4th Address (Internal) LINEAR BURST ADDRESS TABLE (LBO = VSS) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10 4th Address (Internal) INTERLEAVED BURST ADDRESS TABLE (LBO = VDD) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00 MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P737K•MCM63P819K 9 Freescale Semiconductor, Inc. WRITE TRUTH TABLE SGW SW SBa SBb SBc (See Note 1) SBd (See Note 1) Read H H X X X X Read H L H H H H Write Byte a H L L H H H Write Byte b H L H L H H Write Byte c (See Note 1) H L H H L H Write Byte d (See Note 1) H L H H H L Write All Bytes H L L L L L Write All Bytes L X X X X X Cycle Type NOTE: 1. Valid only for MCM63P737K. Freescale Semiconductor, Inc... ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Power Supply Voltage Symbol Value Unit VDD VSS – 0.5 to 4.6 V VDDQ VSS – 0.5 to VDD V Vin, Vout VSS – 0.5 to VDD + 0.5 V Input Voltage (Three–State I/O) VIT VSS – 0.5 to VDDQ + 0.5 V Output Current (per I/O) Iout ±20 mA Package Power Dissipation PD 1.6 W Tbias –10 to 85 °C Tstg –55 to 125 °C I/O Supply Voltage Input Voltage Relative to VSS for Any Pin Except VDD Temperature Under Bias Storage Temperature Notes This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. 2 NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics. PACKAGE THERMAL CHARACTERISTICS Rating Symbol Max Unit Notes RθJA 40 25 °C/W 1, 2 Junction to Board (Bottom) RθJB 17 °C/W 3 Junction to Case (Top) RθJC 9 °C/W 4 RθJA 38 22 °C/W 1, 2 Junction to Board (Bottom) RθJB 14 °C/W 3 Junction to Case (Top) RθJC 5 °C/W 4 TQFP Junction to Ambient (@ 200 lfm) Single–Layer Board Four–Layer Board PBGA Junction to Ambient (@ 200 lfm) Single–Layer Board Four–Layer Board NOTES: 1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38–87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). MCM63P737K•MCM63P819K 10 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V +10%, –5%, TA = 0° to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS (Voltages Referenced to VSS = 0 V) Parameter Symbol Min Typ Max Unit VDD 3.135 3.3 3.465 V I/O Supply Voltage VDDQ 2.375 2.5 2.9 V Input Low Voltage VIL –0.3* — 0.7 V Input High Voltage VIH 1.7 — VDD + 0.3** V Input High Voltage I/O Pins VIH2 1.7 — VDDQ + 0.3** V Output Low Voltage (IOL = 2 mA) VOL — — 0.7 V Output High Voltage (IOH = –2 mA) VOH 1.7 — — V VDD 3.135 3.3 3.465 V VDDQ 3.135 3.3 VDD V Input Low Voltage VIL –0.5* — 0.8 V Input High Voltage VIH 2 — VDD + 0.5*** V Input High Voltage I/O Pins VIH2 2 — VDDQ + 0.5*** V Output Low Voltage (IOL = 8 mA) VOL — — 0.4 V Output High Voltage (IOH = –4 mA) VOH 2.4 — — V 2.5 V I/O SUPPLY Supply Voltage Freescale Semiconductor, Inc... 3.3 V I/O SUPPLY Supply Voltage I/O Supply Voltage * Undershoot: VIL > –1.0 V for t < 20% tKHKH. ** Overshoot: VIH/VIH2 < VDD/VDDQ + 1.0 V (not to exceed 3.6 V) for t < 20% tKHKH. *** Overshoot: VIH/VIH2 < VDD/VDDQ + 1.0 V (not to exceed 4.6 V) for t < 20% tKHKH. SUPPLY CURRENTS Parameter Symbol Min Typ Max Unit Notes Input Leakage Current (0 V ≤ Vin ≤ VDD) Ilkg(I) — — ±1 µA 1 Output Leakage Current (0 V ≤ Vin ≤ VDDQ) Ilkg(O) — — ±1 µA IDDA — — 500/430 470/400 450/380 mA 2, 3, 4 CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at CMOS Levels) ISB2 — — 30 mA 5, 6 Sleep Mode Supply Current (Device Deselected, Freq = Max, VDD = Max, All Other Inputs Static at CMOS Levels, ZZ ≥ VDD – 0.2 V) IZZ — — 15 mA 1, 5, 6 TTL Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at TTL Levels) ISB3 — — 35 mA 5, 7 Clock Running (Device Deselected, Freq = Max, VDD = Max, All Inputs Toggling at CMOS Levels) MCM63P737K / 819K–166 MCM63P737K / 819K–150 MCM63P737K / 819K–133 ISB4 — — 185/170 175/160 160/145 mA 5, 6 Static Clock Running (Device Deselected, Freq = Max,VDD = Max, All Inputs Static at TTL Levels) MCM63P737K / 819K–166 MCM63P737K / 819K–150 MCM63P737K / 819K–133 ISB5 — — 75/65 70/60 65/55 mA 5, 7 AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes VDD Only MCM63P737K / 819K–166 MCM63P737K / 819K–150 MCM63P737K / 819K–133 NOTES: 1. LBO and ZZ pins have an internal pull–up and pull–down, respectively; and will exhibit leakage currents of ±5 µA. 2. Reference AC Operating Conditions and Characteristics for input and timing. 3. All addresses transition simultaneously low (LSB) then high (MSB). 4. Data states are all zero. 5. Device is deselected as defined by the Truth Table. 6. CMOS levels for I/Os are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V. 7. TTL levels for I/Os are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH. MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P737K•MCM63P819K 11 Freescale Semiconductor, Inc. CAPACITANCE (f = 1.0 MHz, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested) Symbol Min Typ Max Unit Input Capacitance Parameter Cin — 4 5 pF Input/Output Capacitance CI/O — 7 8 pF AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V +10%, –5%, TA = 0 to 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20% to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted READ/WRITE CYCLE TIMING (See Notes 1 and 2) Freescale Semiconductor, Inc... MCM63P737K–166 MCM63P819K–166 Parameter Symbol MCM63P737K–150 MCM63P819K–150 MCM63P737K–133 MCM63P819K–133 Min Max Min Max Min Max Unit Notes Cycle Time tKHKH 6 — 6.7 — 7.5 — ns Clock High Pulse Width tKHKL 2.4 — 2.6 — 3 — ns 3 Clock Low Pulse Width tKLKH 2.4 — 2.6 — 3 — ns 3 Clock Access Time tKHQV — 3.5 — 3.8 — 4 ns Output Enable to Output Valid tGLQV — 3.5 — 3.5 — 3.8 ns Clock High to Output Active tKHQX1 0 — 0 — 0 — ns Clock High to Output Change 4, 5 tKHQX2 1.5 — 1.5 — 1.5 — ns 4 Output Enable to Output Active tGLQX 0 — 0 — 0 — ns 4, 5 Output Disable to Q High–Z tGHQZ — 3.5 — 3.5 — 3.8 ns 4, 5 Clock High to Q High–Z tKHQZ 1.5 3.5 1.5 3.5 1.5 3.5 ns 4, 5 Setup Times: Address ADSP, ADSC, ADV Data In Write Chip Enable tADKH tADSKH tDVKH tWVKH tEVKH 1.5 — 1.5 — 1.5 — ns Hold Times: Address ADSP, ADSC, ADV Data In Write Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHEX 0.5 — 0.5 — 0.5 — ns NOTES: 1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 2. All read and write cycle timings are referenced from K or G. 3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 4. This parameter is sampled and not 100% tested. 5. Measured at ±200 mV from steady state. OUTPUT Z0 = 50 Ω RL = 50 Ω 1.5 V Figure 1. AC Test Load MCM63P737K•MCM63P819K 12 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. 2400 CLOCK ACCESS TIME DELAY (ps) 2200 OUTPUT CL 2000 1800 1600 1400 1200 1000 800 600 400 200 0 Freescale Semiconductor, Inc... 0 20 40 60 80 100 LUMPED CAPACITANCE, CL (pF) Figure 2. Lumped Capacitive Load and Typical Derating Curve OUTPUT LOAD OUTPUT BUFFER TEST POINT UNLOADED RISE AND FALL TIME MEASUREMENT INPUT WAVEFORM OUTPUT WAVEFORM 2.4 2.4 0.6 0.6 2.4 2.4 0.6 0.6 tr tf NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.6 to 2.4 V unloaded. 3. Fall time is measured from 2.4 to 0.6 V unloaded. Figure 3. Unloaded Rise and Fall Time Characterization MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P737K•MCM63P819K 13 MCM63P737K•MCM63P819K 14 For More Information On This Product, Go to: www.freescale.com Q(n) B SINGLE READ tKHQX1 A Q(A) Q(B) tKHQX2 t KHQV tKHKL NOTE: E low = SE2 high and SE3 low. W low = SGW low and/or SW and SBx low. DESELECTED tKHQZ DQx G W E SE1 ADV ADSC ADSP SA K tKHKH Q(B+2) BURST READ Q(B+1) tGHQZ Q(B+3) BURST WRAPS AROUND tKLKH Q(B) ADSP, SA SE2, SE3 IGNORED READ/WRITE CYCLES D(C) C D(C+2) BURST WRITE D(C+1) Freescale Semiconductor, Inc... D(C+3) D SINGLE READ tGLQX Q(D) t GLQV Freescale Semiconductor, Inc. MOTOROLA FAST SRAM tZZREC I ZZ For More Information On This Product, Go to: www.freescale.com IDD ZZ DQ G W E ADV ADDR ADS K NORMAL OPERATION MOTOROLA FAST SRAM NOTE: ADS low = ADSC low or ADSP low. ADS high = both ADSC, ADSP high. E low = SE1 low, SE2 high, SE3 low. IZZ (max) specifications will not be met if inputs toggle. tZZQZ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ tZZS NO READS OR WRITES ALLOWED IN SLEEP MODE ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ NO NEW READS OR WRITES ALLOWED SLEEP MODE TIMING Freescale Semiconductor, Inc... NORMAL OPERATION Freescale Semiconductor, Inc. MCM63P737K•MCM63P819K 15 Freescale Semiconductor, Inc. APPLICATION INFORMATION Freescale Semiconductor, Inc... SLEEP MODE A sleep mode feature, the ZZ pin, has been implemented on the MCM63P737K and MCM63P819K. It allows the system designer to place the RAM in the lowest possible power condition by asserting ZZ. The Sleep Mode Timing diagram shows the different modes of operation: Normal Operation, No READ/WRITE Allowed, and Sleep Mode. Each mode has its own set of constraints and conditions that are allowed. Normal Operation: All inputs must meet setup and hold times prior to sleep and t ZZREC nanoseconds after recovering from sleep. Clock (K) must also meet cycle, high, and low times during these periods. Two cycles prior to sleep, initiation of either a read or write operation is not allowed. No READ/WRITE: During the period of time just prior to sleep and during recovery from sleep, the assertion of either ADSC, ADSP, or any write signal is not allowed. If a write operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM can not be guaranteed immediately after ZZ is asserted (prior to being in sleep). Sleep Mode: The RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (IZZ). All inputs are allowed to toggle — the RAM will not be selected and perform any reads or writes. However, if inputs toggle, the IZZ (max) specification will not be met. Note: It is invalid to go from stop clock mode directly into sleep mode. NON–BURST SYNCHRONOUS OPERATION Although this BurstRAM has been designed for high end MPU–based systems, these SRAMs can be used in other high speed memory applications that do not require the burst address feature. Most L2 caches designed with a synchronous interface can make use of the MCM63P737K and MCM63P819K. The burst counter feature of the BurstRAMs can be disabled, and the SRAMs can be configured to act upon a continuous stream of addresses. See Figure 5. CONTROL PIN TIE VALUES EXAMPLE (H ≥ VIH, L ≤ VIL) Non–Burst ADSP ADSC ADV SE1 SE2 LBO Sync Non–Burst, Pipelined SRAM H L H L H X NOTE: Although X is specified in the table as a don’t care, the pin must be tied either high or low. K ADDR A B C D E F G H SE3 W G DQ Q(A) Q(B) Q(C) Q(D) D(E) D(F) READS D(G) D(H) WRITES Figure 4. Example Configuration as Non–Burst Synchronous SRAM MCM63P737K•MCM63P819K 16 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. ORDERING INFORMATION (Order by Full Part Number) MCM 63P737K 63P819K XX X X Motorola Memory Prefix Blank = Trays, R = Tape and Reel Part Number Speed (166 = 166 MHz, 150 = 150 MHz, 133 = 133 MHz) Package (TQ = TQFP, ZP = PBGA) MCM63P737KTQ150 MCM63P737KTQ150R MCM63P737KZP150 MCM63P737KZP150R MCM63P737KTQ133 MCM63P737KTQ133R MCM63P737KZP133 MCM63P737KZP133R MCM63P819KTQ166 MCM63P819KTQ166R MCM63P819KZP166 MCM63P819KZP166R MCM63P819KTQ150 MCM63P819KTQ150R MCM63P819KZP150 MCM63P819KZP150R MCM63P819KTQ133 MCM63P819KTQ133R MCM63P819KZP133 MCM63P819KZP133R Freescale Semiconductor, Inc... Full Part Numbers — MCM63P737KTQ166 MCM63P737KTQ166R MCM63P737KZP166 MCM63P737KZP166R MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P737K•MCM63P819K 17 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS TQ PACKAGE TQFP CASE 983A–01 e 4X 0.20 (0.008) H A–B D 2X 30 TIPS e/2 0.20 (0.008) C A–B D –D– 80 51 B 50 81 –A– –X– X=A, B, OR D B E/2 –B– VIEW Y E1 E BASE METAL PLATING Freescale Semiconductor, Inc... c 31 100 1 30 D1/2 0.13 (0.005) 0.20 (0.008) C A–B D A 2 0.10 (0.004) C –H– –C– 3 SEATING PLANE VIEW AB S S 0.25 (0.010) R2 A2 L2 L L1 GAGE PLANE VIEW AB MCM63P737K•MCM63P819K 18 C A–B S D S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). 1 R1 M SECTION B–B 2X 20 TIPS A1 c1 b D/2 D1 D 0.05 (0.002) ÉÉÉÉ ÇÇÇÇ ÇÇÇÇ ÉÉÉÉ b1 E1/2 For More Information On This Product, Go to: www.freescale.com DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2 1 2 3 MILLIMETERS MIN MAX ––– 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 ––– 0.08 ––– 0.08 0.20 0 7 0 ––– 11 13 11 13 INCHES MIN MAX ––– 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 ––– 0.003 ––– 0.003 0.008 0 7 0 ––– 11 13 11 13 MOTOROLA FAST SRAM Freescale Semiconductor, Inc. ZP PACKAGE 7 x 17 BUMP PBGA CASE 999–02 0.20 4X 119X E C B D E2 e 6X M A B C A A B C D E F G H J K L M N P R T U D1 16X M 0.15 7 6 5 4 3 2 1 D2 b 0.3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. ALL DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. DIM A A1 A2 A3 D D1 D2 E E1 E2 b e e Freescale Semiconductor, Inc... E1 TOP VIEW BOTTOM VIEW MILLIMETERS MIN MAX ––– 2.40 0.50 0.70 1.30 1.70 0.80 1.00 22.00 BSC 20.32 BSC 19.40 19.60 14.00 BSC 7.62 BSC 11.90 12.10 0.60 0.90 1.27 BSC 0.25 A A3 0.35 A 0.20 A A A2 A1 MOTOROLA FAST SRAM SIDE VIEW SEATING PLANE A For More Information On This Product, Go to: www.freescale.com MCM63P737K•MCM63P819K 19 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 Mfax : [email protected] – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, Motorola Fax Back System – US & Canada ONLY 1-800-774-1848 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. – http://sps.motorola.com /mfax / 852-26668334 HOME PAGE : http://motorola.com/sps / CUSTOMER FOCUS CENTER: 1-800-521-6274 MCM63P737K•MCM63P819K ◊For More Information On This Product, Go to: www.freescale.com 20 MOTOROLAMCM63P737K/D FAST SRAM