TI1 LM5575 Simple switcher 75v, 1.5a step-down switching regulator Datasheet

LM5575
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LM5575/LM5575Q SIMPLE SWITCHER® 75V, 1.5A Step-Down Switching Regulator
Check for Samples: LM5575
FEATURES
DESCRIPTION
•
The LM5575 is an easy to use SIMPLE SWITCHER®
buck regulator which allows design engineers to
design and optimize a robust power supply using a
minimum set of components. Operating with an input
voltage range of 6 - 75V, the LM5575 delivers 1.5A of
continuous output current with an integrated 330mΩ
N-Channel MOSFET. The regulator utilizes an
Emulated Current Mode architecture which provides
inherent line regulation, tight load transient response,
and ease of loop compensation without the usual
limitation of low-duty cycles associated with current
mode regulators. The operating frequency is
adjustable from 50kHz to 500kHz to allow
optimization of size and efficiency. To reduce EMI, a
frequency synchronization pin allows multiple IC’s
from the LM(2)557x family to self-synchronize or to
synchronize to an external clock. The LM5575
ensures robustness with cycle-by-cycle current limit,
short-circuit protection, thermal shut-down, and
remote shut-down. The device is available in a power
enhanced HTSSOP-16 package featuring an
exposed die attach pad for thermal dissipation. The
LM5575 is supported by the full suite of WEBENCH®
On-Line design tools.
1
23
•
•
•
•
•
•
•
•
•
•
•
LM5575Q is an Automotive Grade Product that
is AEC-Q100 Grade 1 Qualified (−40°C to +
125°C Operating Junction Temperature)
Integrated 75V, 330mΩ N-channel MOSFET
Ultra-wide Input Voltage Range from 6V to 75V
Adjustable Output Voltage as Low as 1.225V
1.5% Feedback Reference Accuracy
Operating Frequency Adjustable Between
50kHz and 500kHz with Single Resistor
Master or Slave Frequency Synchronization
Adjustable Soft-Start
Emulated Current Mode Control Architecture
Wide Bandwidth Error Amplifier
Built-in Protection
Automotive Grade Product Datasheet that is
AEC-Q100 Grade 0 Qualified is Available Upon
Request.
– (−40°C to + 150°C Operating Junction
Temperature)
APPLICATIONS
•
•
PACKAGE
Automotive
Industrial
•
HTSSOP-16EP (Exposed Pad)
Simplified Application Schematic
VIN
VIN
BST
SYNC
SW
VOUT
LM5575
SD
IS
RT
VCC
SS
RAMP
OUT
FB
COMP
GND
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Connection Diagram
1
VCC
BST
SD
PRE
VIN
SW
2
3
4
5
6
7
8
SYNC
IS
COMP
PGND
FB
OUT
RT
SS
RAMP
AGND
16
15
14
13
12
11
10
9
Figure 1. Top View
16-Lead HTSSOP
PIN DESCRIPTIONS
2
Pin(s)
Name
1
VCC
2
Description
Application Information
Output of the bias regulator
Vcc tracks Vin up to 9V. Beyond 9V, Vcc is regulated to 7 Volts.
A 0.1uF to 1uF ceramic decoupling capacitor is required. An
external voltage (7.5V – 14V) can be applied to this pin to
reduce internal power dissipation.
SD
Shutdown or UVLO input
If the SD pin voltage is below 0.7V the regulator will be in a low
power state. If the SD pin voltage is between 0.7V and 1.225V
the regulator will be in standby mode. If the SD pin voltage is
above 1.225V the regulator will be operational. An external
voltage divider can be used to set a line undervoltage shutdown
threshold. If the SD pin is left open circuit, a 5µA pull-up current
source configures the regulator fully operational.
3
Vin
Input supply voltage
Nominal operating range: 6V to 75V
4
SYNC
Oscillator synchronization input or output
The internal oscillator can be synchronized to an external clock
with an external pull-down device. Multiple LM5575 devices can
be synchronized together by connection of their SYNC pins.
5
COMP
Output of the internal error amplifier
The loop compensation network should be connected between
this pin and the FB pin.
6
FB
Feedback signal from the regulated output
This pin is connected to the inverting input of the internal error
amplifier. The regulation threshold is 1.225V.
7
RT
Internal oscillator frequency set input
The internal oscillator is set with a single resistor, connected
between this pin and the AGND pin.
8
RAMP
Ramp control signal
An external capacitor connected between this pin and the AGND
pin sets the ramp slope used for current mode control.
Recommended capacitor range 50pF to 2000pF.
9
AGND
Analog ground
Internal reference for the regulator control functions
10
SS
Soft-start
An external capacitor and an internal 10µA current source set
the time constant for the rise of the error amp reference. The SS
pin is held low during standby, Vcc UVLO and thermal
shutdown.
11
OUT
Output voltage connection
Connect directly to the regulated output voltage.
12
PGND
Power ground
Low side reference for the PRE switch and the IS sense resistor.
13
IS
Current sense
Current measurement connection for the re-circulating diode. An
internal sense resistor and a sample/hold circuit sense the diode
current near the conclusion of the off-time. This current
measurement provides the DC level of the emulated current
ramp.
14
SW
Switching node
The source terminal of the internal buck switch. The SW pin
should be connected to the external Schottky diode and to the
buck inductor.
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PIN DESCRIPTIONS (continued)
Pin(s)
Name
15
PRE
Pre-charge assist for the bootstrap
capacitor
Description
This open drain output can be connected to SW pin to aid
charging the bootstrap capacitor during very light load conditions
or in applications where the output may be pre-charged before
the LM5575 is enabled. An internal pre-charge MOSFET is
turned on for 250ns each cycle just prior to the on-time interval
of the buck switch.
Application Information
16
BST
Boost input for bootstrap capacitor
An external capacitor is required between the BST and the SW
pins. A 0.022µF ceramic capacitor is recommended. The
capacitor is charged from Vcc via an internal diode during the
off-time of the buck switch.
NA
EP
Exposed Pad
Exposed metal pad on the underside of the device. It is
recommended to connect this pad to the PWB ground plane, in
order to aid in heat dissipation.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
VIN to GND
76V
BST to GND
90V
PRE to GND
76V
SW to GND (Steady State)
-1.5V
BST to VCC
76V
SD, VCC to GND
14V
BST to SW
14V
OUT to GND
Limited to Vin
SYNC, SS, FB, RAMP to GND
ESD Rating (3)
7V
Human Body Model
Storage Temperature Range
(1)
(2)
(3)
2kV
-65°C to +150°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Operating Ratings (1)
VIN
6V to 75V
−40°C to + 125°C
Operation Junction Temperature
(1)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
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Electrical Characteristics
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, RT = 32.4kΩ unless otherwise stated. (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
6.85
7.15
7.45
V
STARTUP REGULATOR
VccReg
Vcc Regulator Output
Vcc LDO Mode turn-off
Vcc Current Limit
Vcc = 0V
Vcc UVLO Threshold
(Vcc increasing)
9
V
25
mA
VCC SUPPLY
5.03
Vcc Undervoltage Hysteresis
5.35
5.67
V
0.35
V
Bias Current (Iin)
FB = 1.3V
3.7
4.5
mA
Shutdown Current (Iin)
SD = 0V
57
85
µA
0.9
V
SHUTDOWN THRESHOLDS
Shutdown Threshold
(SD Increasing)
0.47
0.7
(Standby Increasing)
1.17
1.225
Shutdown Hysteresis
0.1
Standby Threshold
Standby Hysteresis
SD Pull-up Current Source
V
1.28
V
0.1
V
5
µA
SWITCH CHARACTERSICS
Buck Switch Rds(on)
330
BOOST UVLO
660
4
mΩ
V
BOOST UVLO Hysteresis
0.56
V
Pre-charge Switch Rds(on)
70
Ω
Pre-charge Switch on-time
250
ns
CURRENT LIMIT
Cycle by Cycle Current Limit
RAMP = 0V
Cycle by Cycle Current Limit Delay
RAMP = 2.5V
1.8
2.1
2.5
85
A
ns
SOFT-START
SS Current Source
7
10
14
µA
180
200
220
kHz
425
485
545
kHz
OSCILLATOR
Frequency1
Frequency2
RT = 11kΩ
SYNC Source Impedance
11
kΩ
SYNC Sink Impedance
110
Ω
SYNC Threshold (falling)
SYNC Frequency
1.3
RT = 11kΩ
SYNC Pulse Width Minimum
V
550
kHz
15
ns
RAMP GENERATOR
Ramp Current 1
Vin = 60V, Vout=10V
467
550
633
µA
Ramp Current 2
Vin = 10V, Vout=10V
36
50
64
µA
416
500
575
ns
PWM COMPARATOR
Forced Off-time
(1)
4
Min On-time
80
ns
COMP to PWM Comparator Offset
0.7
V
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Texas Instruments' Average Outgoing Quality Level
(AOQL).
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Electrical Characteristics (continued)
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, RT = 32.4kΩ unless otherwise stated.(1)
Symbol
Parameter
Conditions
Min
Typ
Max
1.207
1.225
1.243
Units
ERROR AMPLIFIER
Feedback Voltage
Vfb = COMP
FB Bias Current
V
17
DC Gain
nA
70
COMP Sink / Source Current
dB
3
Unity Gain Bandwidth
mA
3
MHz
83
mΩ
Thermal Shutdown Threshold
165
°C
Thermal Shutdown Hysteresis
25
°C
DIODE SENSE RESISTANCE
DSENSE
THERMAL SHUTDOWN
Tsd
THERMAL RESISTANCE
θJC
Junction to Case
14
°C/W
θJA
Junction to Ambient
50
°C/W
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Typical Performance Characteristics
Oscillator Frequency vs Temperature
FOSC = 200kHz
Oscillator Frequency vs RT
NORMALIZED OSCILLATOR FREQUENCY
OSCILLATOR FREQUENCY (kHz)
1000
100
10
1
10
100
1.010
1.005
1.000
0.995
0.990
-50
-25
0
25
50
75
100
125
o
1000
TEMPERATURE ( C)
RT (k:)
Figure 2.
Figure 3.
Soft Start Current vs Temperature
VCC vs ICC
VIN = 12V
8
6
1.05
VCC (V)
NORMALIZED SOFTSTART CURRENT
1.10
1.00
4
2
0.95
0.90
-50
0
-25
0
25
50
75
100
0
125
12
8
4
16
20
24
ICC (mA)
o
TEMPERATURE ( C)
Figure 4.
Figure 5.
VCC vs VIN
RL = 7kΩ
Error Amplifier Gain/Phase
AVCL = 101
10
50
225
40
180
30
135
4
Ramp Down
20
PHASE
10
45
0
0
GAIN
-10
2
-45
Ramp Up
-20
0
0
2
4
6
8
-30
10k
10
VIN (V)
-90
100k
1M
10M
-135
100M
FREQUENCY (Hz)
Figure 6.
6
90
PHASE (°)
6
GAIN (dB)
VCC (V)
8
Figure 7.
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Typical Performance Characteristics (continued)
Demoboard Efficiency vs IOUT and VIN
100
90
EFFICIENCY (%)
80
70
60
50
VIN = 24V
VIN = 7V
VIN = 48V
40
30
VIN = 75V
20
10
0
0.25
0.5
0.75
1
1.25
1.5
IOUT (A)
Figure 8.
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TYPICAL APPLICATION CIRCUIT AND BLOCK DIAGRAM
VIN
7V ± 75V
C1
1.0
VIN
3
C2
1.0
5 PA
R1
OPEN
LM5575
7V
REGULATOR
1.225V
2 SD
STANDBY
VCC
SHUTDOWN
0.7V
SD
C12
OPEN
R2
OPEN
10 SS
BST
UVLO
C7
0.022
DRIVER
S Q
1.225V
16
VIN
DIS
CLK
10 PA
C4
0.01
C8
0.47
THERMAL
SHUTDOWN
UVLO
1
R Q
LEVEL
SHIFT
PWM
0.7V
PRE 15
C_LIMIT
6 FB
C6
open
C5
0.01
R4
49.9k
ERROR
AMP
1V/A
+
5 COMP
CLK
Ir
OSCILLATOR
SYNC
4
RT
7
RAMP
8
SYNC
D1
CMSH3-100
CLK
2.1V
VIN
L1
47 PH
SW 14
TRACK
SAMPLE
and
HOLD
RAMP GENERATOR
Ir = (10 PA x (VIN ± VOUT))
+ 50 PA
IS
C11
330p
R7
10
C10
120
5V
C9
10
13
PGND 12
AGND 9
CLK
OUT
11
R5
5.11k
R6
1.65k
C3
470p
R3
21k
Figure 9. Functional Block Diagram
Detailed Operating Description
The LM5575 switching regulator features all of the functions necessary to implement an efficient high voltage
buck regulator using a minimum of external components. This easy to use regulator integrates a 75V N-Channel
buck switch with an output current capability of 1.5 Amps. The regulator control method is based on current
mode control utilizing an emulated current ramp. Peak current mode control provides inherent line voltage feedforward, cycle-by-cycle current limiting, and ease of loop compensation. The use of an emulated control ramp
reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable processing of very small duty
cycles necessary in high input voltage applications. The operating frequency is user programmable from 50kHz
to 500kHz. An oscillator synchronization pin allows multiple LM5575 regulators to self synchronize or be
synchronized to an external clock. The output voltage can be set as low as 1.225V. Fault protection features
include, current limiting, thermal shutdown and remote shutdown capability. The device is available in the
HTSSOP-16 package featuring an exposed pad to aid thermal dissipation.
The functional block diagram and typical application of the LM5575 are shown in Figure 9. The LM5575 can be
applied in numerous applications to efficiently step-down a high, unregulated input voltage. The device is well
suited for telecom, industrial and automotive power bus voltage ranges.
High Voltage Start-Up Regulator
The LM5575 contains a dual-mode internal high voltage startup regulator that provides the Vcc bias supply for
the PWM controller and boot-strap MOSFET gate driver. The input pin (VIN) can be connected directly to the
input voltage, as high as 75 Volts. For input voltages below 9V, a low dropout switch connects Vcc directly to
Vin. In this supply range, Vcc is approximately equal to Vin. For Vin voltage greater than 9V, the low dropout
switch is disabled and the Vcc regulator is enabled to maintain Vcc at approximately 7V. The wide operating
range of 6V to 75V is achieved through the use of this dual mode regulator.
The output of the Vcc regulator is current limited to 25mA. Upon power up, the regulator sources current into the
capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the Vcc UVLO threshold of 5.35V
and the SD pin is greater than 1.225V, the output switch is enabled and a soft-start sequence begins. The output
switch remains enabled until Vcc falls below 5.0V or the SD pin falls below 1.125V.
8
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An auxiliary supply voltage can be applied to the Vcc pin to reduce the IC power dissipation. If the auxiliary
voltage is greater than 7.3V, the internal regulator will essentially shut off, reducing the IC power dissipation. The
Vcc regulator series pass transistor includes a diode between Vcc and Vin that should not be forward biased in
normal operation. Therefore the auxiliary Vcc voltage should never exceed the Vin voltage.
In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute
maximum voltage rating of 76V. During line or load transients, voltage ringing on the Vin line that exceeds the
Absolute Maximum Ratings can damage the IC. Both careful PC board layout and the use of quality bypass
capacitors located close to the VIN and GND pins are essential.
VIN
9V
VCC
7V
5.25V
Internal Enable Signal
Figure 10. Vin and Vcc Sequencing
Shutdown / Standby
The LM5575 contains a dual level Shutdown (SD) circuit. When the SD pin voltage is below 0.7V, the regulator is
in a low current shutdown mode. When the SD pin voltage is greater than 0.7V but less than 1.225V, the
regulator is in standby mode. In standby mode the Vcc regulator is active but the output switch is disabled. When
the SD pin voltage exceeds 1.225V, the output switch is enabled and normal operation begins. An internal 5µA
pull-up current source configures the regulator to be fully operational if the SD pin is left open.
An external set-point voltage divider from VIN to GND can be used to set the operational input range of the
regulator. The divider must be designed such that the voltage at the SD pin will be greater than 1.225V when Vin
is in the desired operating range. The internal 5µA pull-up current source must be included in calculations of the
external set-point divider. Hysteresis of 0.1V is included for both the shutdown and standby thresholds. The SD
pin is internally clamped with a 1kΩ resistor and an 8V zener clamp. The voltage at the SD pin should never
exceed 14V. If the voltage at the SD pin exceeds 8V, the bias current will increase at a rate of 1 mA/V.
The SD pin can also be used to implement various remote enable / disable functions. Pulling the SD pin below
the 0.7V threshold totally disables the controller. If the SD pin voltage is above 1.225V the regulator will be
operational.
Oscillator and Sync Capability
The LM5575 oscillator frequency is set by a single external resistor connected between the RT pin and the
AGND pin. The RT resistor should be located very close to the device and connected directly to the pins of the IC
(RT and AGND).To set a desired oscillator frequency (F), the necessary value for the RT resistor can be
calculated from the following equation:
RT =
1 - 580 x 10-9
F
135 x 10-12
(1)
The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must be
of higher frequency than the free-running frequency set by the RT resistor. A clock circuit with an open drain
output is the recommended interface from the external clock to the SYNC pin. The clock pulse duration should
be greater than 15ns.
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LM5575
SYNC
SW
SYNC
AGND
CLK
SW
500 ns
Figure 11. Sync from External Clock
LM5575
SYNC
LM5575
SYNC
UP TO 5 TOTAL
DEVICES
Figure 12. Sync from Multiple Devices
Multiple LM5575 devices can be synchronized together simply by connecting the SYNC pins together. In this
configuration all of the devices will be synchronized to the highest frequency device. The diagram in Figure 13
illustrates the SYNC input/output features of the LM5575. The internal oscillator circuit drives the SYNC pin with
a strong pull-down / weak pull-up inverter. When the SYNC pin is pulled low either by the internal oscillator or an
external clock, the ramp cycle of the oscillator is terminated and a new oscillator cycle begins. Thus, if the SYNC
pins of several LM5575 IC’s are connected together, the IC with the highest internal clock frequency will pull the
connected SYNC pins low first and terminate the oscillator ramp cycles of the other IC’s. The LM5575 with the
highest programmed clock frequency will serve as the master and control the switching frequency of the all the
devices with lower oscillator frequency.
5V
SYNC
10k
I = f(RT)
2.5V
Q
S
Q
R
DEADTIME
ONE-SHOT
Figure 13. Simplified Oscillator Block Diagram and SYNC I/O Circuit
10
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Error Amplifier and PWM Comparator
The internal high gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision reference (1.225V). The output of the error amplifier is
connected to the COMP pin allowing the user to provide loop compensation components, generally a type II
network, as illustrated in Figure 9. This network creates a pole at DC, a zero and a noise reducing high
frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP generator to
the error amplifier output voltage at the COMP pin.
RAMP Generator
The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the
buck switch current. This switch current corresponds to the positive slope portion of the output inductor current.
Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and
provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current
signal for PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked.
Also, the current measurement may introduce significant propagation delays. The filtering, blanking time and
propagation delay limit the minimum achievable pulsewidth. In applications where the input voltage may be
relatively large in comparison to the output voltage, controlling small pulsewidths and duty cycles is necessary for
regulation. The LM5575 utilizes a unique ramp generator, which does not actually measure the buck switch
current but rather reconstructs the signal. Reconstructing or emulating the inductor current provides a ramp
signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays. The
current reconstruction is comprised of two elements; a sample & hold DC level and an emulated current ramp.
RAMP
(10 P x (VIN ± VOUT) + 50 P) x
tON
CRAMP
Sample and
Hold DC Level
1V/A
TON
Figure 14. Composition of Current Sense Signal
The sample & hold DC level illustrated in Figure 14 is derived from a measurement of the re-circulating Schottky
diode anode current. The re-circulating diode anode should be connected to the IS pin. The diode current flows
through an internal current sense resistor between the IS and PGND pins. The voltage level across the sense
resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The diode
current sensing and sample & hold provide the DC level of the reconstructed current signal. The positive slope
inductor current ramp is emulated by an external capacitor connected from the RAMP pin to AGND and an
internal voltage controlled current source. The ramp current source that emulates the inductor current is a
function of the Vin and Vout voltages per the following equation:
IRAMP = (10µ x (Vin – Vout)) + 50µA
(2)
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Proper selection of the RAMP capacitor depends upon the selected value of the output inductor. The value of
CRAMP can be selected from: CRAMP = L x 10-5, where L is the value of the output inductor in Henrys. With this
value, the scale factor of the emulated current ramp will be approximately equal to the scale factor of the DC
level sample and hold (1.0 V / A). The CRAMP capacitor should be located very close to the device and connected
directly to the pins of the IC (RAMP and AGND).
For duty cycles greater than 50%, peak current mode control circuits are subject to sub-harmonic oscillation.
Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch
node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this
oscillation. The 50µA of offset current provided from the emulated current source adds some fixed slope to the
ramp signal. In some high output voltage, high duty cycle applications, additional slope may be required. In these
applications, a pull-up resistor may be added between the VCC and RAMP pins to increase the ramp slope
compensation.
For VOUT > 7.5V:
Calculate optimal slope current, IOS = VOUT x 10µA/V.
For example, at VOUT = 10V, IOS = 100µA.
Install a resistor from the RAMP pin to VCC:
RRAMP = VCC / (IOS - 50µA)
VCC
RRAMP
RAMP
CRAMP
Figure 15. RRAMP to VCC for VOUT > 7.5V
Maximum Duty Cycle / Input Drop-out Voltage
There is a forced off-time of 500ns implemented each cycle to ensure sufficient time for the diode current to be
sampled. This forced off-time limits the maximum duty cycle of the buck switch. The maximum duty cycle will
vary with the operating frequency.
DMAX = 1 - Fs x 500ns
(3)
Where Fs is the oscillator frequency. Limiting the maximum duty cycle will raise the input dropout voltage. The
input dropout voltage is the lowest input voltage required to maintain regulation of the output voltage. An
approximation of the input dropout voltage is:
VinMIN =
Vout + VD
1 - Fs x 500 ns
(4)
Where VD is the voltage drop across the re-circulatory diode. Operating at high switching frequency raises the
minimum input voltage necessary to maintain regulation.
Current Limit
The LM5575 contains a unique current monitoring scheme for control and over-current protection. When set
correctly, the emulated current sense signal provides a signal which is proportional to the buck switch current
with a scale factor of 1.0 V / A. The emulated ramp signal is applied to the current limit comparator. If the
emulated ramp signal exceeds 2.1V (2.1A) the present current cycle is terminated (cycle-by-cycle current
limiting). In applications with small output inductance and high input voltage the switch current may overshoot
due to the propagation delay of the current limit comparator. If an overshoot should occur, the diode current
sampling circuit will detect the excess inductor current during the off-time of the buck switch. If the sample & hold
DC level exceeds the 2.1V current limit threshold, the buck switch will be disabled and skip pulses until the diode
current sampling circuit detects the inductor current has decayed below the current limit threshold. This approach
prevents current runaway conditions due to propagation delays or inductor saturation since the inductor current is
forced to decay following any current overshoot.
12
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Soft-Start
The soft-start feature allows the regulator to gradually reach the initial steady state operating point, thus reducing
start-up stresses and surges. The internal soft-start current source, set to 10µA, gradually increases the voltage
of an external soft-start capacitor connected to the SS pin. The soft-start capacitor voltage is connected to the
reference input of the error amplifier. Various sequencing and tracking schemes can be implemented using
external circuits that limit or clamp the voltage level of the SS pin.
In the event a fault is detected (over-temperature, Vcc UVLO, SD) the soft-start capacitor will be discharged.
When the fault condition is no longer present a new soft-start sequence will commence.
Boost Pin
The LM5575 integrates an N-Channel buck switch and associated floating high voltage level shift / gate driver.
This gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.022µF
ceramic capacitor, connected with short traces between the BST pin and SW pin, is recommended. During the
off-time of the buck switch, the SW pin voltage is approximately -0.5V and the bootstrap capacitor is charged
from Vcc through the internal bootstrap diode. When operating with a high PWM duty cycle, the buck switch will
be forced off each cycle for 500ns to ensure that the bootstrap capacitor is recharged.
Under very light load conditions or when the output voltage is pre-charged, the SW voltage will not remain low
during the off-time of the buck switch. If the inductor current falls to zero and the SW pin rises, the bootstrap
capacitor will not receive sufficient voltage to operate the buck switch gate driver. For these applications, the
PRE pin can be connected to the SW pin to pre-charge the bootstrap capacitor. The internal pre-charge
MOSFET and diode connected between the PRE pin and PGND turns on each cycle for 250ns just prior to the
onset of a new switching cycle. If the SW pin is at a normal negative voltage level (continuous conduction mode),
then no current will flow through the pre-charge MOSFET/diode.
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power reset state,
disabling the output driver and the bias regulator. This feature is provided to prevent catastrophic failures from
accidental device overheating.
Application Information
EXTERNAL COMPONENTS
The procedure for calculating the external components is illustrated with the following design example. The Bill of
Materials for this design is listed in Table 1. The circuit shown in Figure 9 is configured for the following
specifications:
• VOUT = 5V
• VIN = 7V to 75V
• Fs = 300kHz
• Minimum load current (for CCM) = 200mA
• Maximum load current = 1.5A
R3 (RT)
RT sets the oscillator switching frequency. Generally, higher frequency applications are smaller but have higher
losses. Operation at 300kHz was selected for this example as a reasonable compromise for both small size and
high efficiency. The value of RT for 300kHz switching frequency can be calculated as follows:
RT =
[(1 / 300 x 103) ± 580 x 10-9]
135 x 10-12
(5)
The nearest standard value of 21kΩ was chosen for RT.
L1
The inductor value is determined based on the operating frequency, load current, ripple current, and the
minimum and maximum input voltage (VIN(min), VIN(max)).
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L1 Current
IPK+
IRIPPLE
IO
IPK-
1/Fs
0 mA
Figure 16. Inductor Current Waveform
To keep the circuit in continuous conduction mode (CCM), the maximum ripple current IRIPPLE should be less
than twice the minimum load current, or 0.4Ap-p. Using this value of ripple current, the value of inductor (L1) is
calculated using the following:
L1 =
VOUT x (VIN(max) ± VOUT)
IRIPPLE x FS x VIN(max)
(6)
5V x (75V ± 5V)
L1 =
= 39 PH
0.4A x 300 kHz x 75V
(7)
This procedure provides a guide to select the value of L1. The nearest standard value (47µH) will be used. L1
must be rated for the peak current (IPK+) to prevent saturation. During normal loading conditions, the peak current
occurs at maximum load current plus maximum ripple. During an overload condition the peak current is limited to
2.1A nominal (2.5A maximum). The selected inductor (see Table 1) has a conservative 3.25 Amp saturation
current rating. For this manufacturer, the saturation rating is defined as the current necessary for the inductance
to reduce by 30%, at 20°C.
C3 (CRAMP)
With the inductor value selected, the value of C3 (CRAMP) necessary for the emulation ramp circuit is:
CRAMP = L x 10-5
(8)
Where L is in Henrys
With L1 selected for 47µH the recommended value for C3 is 470pF.
C9, C10
The output capacitors, C9 and C10, smooth the inductor ripple current and provide a source of charge for
transient loading conditions. For this design a 10µF ceramic capacitor and a 120µF AL organic capacitor were
selected. The ceramic capacitor provides ultra low ESR to reduce the output ripple voltage and noise spikes,
while the AL capacitor provides a large bulk capacitance in a small volume for transient loading conditions. An
approximation for the output ripple voltage is:
§
¨
©
§
1
'VOUT = 'IL x ¨ESR +
8
x
F
x COUT
S
©
(9)
D1
A Schottky type re-circulating diode is required for all LM5575 applications. Ultra-fast diodes are not
recommended and may result in damage to the IC due to reverse recovery current transients. The near ideal
reverse recovery characteristics and low forward voltage drop are particularly important diode characteristics for
high input voltage and low output voltage applications common to the LM5575. The reverse recovery
characteristic determines how long the current surge lasts each cycle when the buck switch is turned on. The
reverse recovery characteristics of Schottky diodes minimize the peak instantaneous power in the buck switch
occurring during turn-on each cycle. The resulting switching losses of the buck switch are significantly reduced
when using a Schottky diode. The reverse breakdown rating should be selected for the maximum VIN, plus some
safety margin.
14
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The forward voltage drop has a significant impact on the conversion efficiency, especially for applications with a
low output voltage. “Rated” current for diodes vary widely from various manufacturers. The worst case is to
assume a short circuit load condition. In this case the diode will carry the output current almost continuously. For
the LM5575 this current can be as high as 2.1A. Assuming a worst case 1V drop across the diode, the maximum
diode power dissipation can be as high as 2.1W. For the reference design a 100V Schottky in a SMC package
was selected.
C1, C2
The regulator supply voltage has a large source impedance at the switching frequency. Good quality input
capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current
during the on-time. When the buck switch turns on, the current into the VIN pin steps to the lower peak of the
inductor current waveform, ramps up to the peak value, then drops to zero at turn-off. The average current into
VIN during the on-time is the load current. The input capacitance should be selected for RMS current rating and
minimum ripple voltage. A good approximation for the required ripple current rating necessary is IRMS > IOUT / 2.
Quality ceramic capacitors with a low ESR should be selected for the input filter. To allow for capacitor
tolerances and voltage effects, two 1.0µF, 100V ceramic capacitors will be used. If step input voltage transients
are expected near the maximum rating of the LM5575, a careful evaluation of ringing and possible spikes at the
device VIN pin should be completed. An additional damping network or input voltage clamp may be required in
these cases.
C8
The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended value
of C8 should be no smaller than 0.1µF, and should be a good quality, low ESR, ceramic capacitor. A value of
0.47µF was selected for this design.
C7
The bootstrap capacitor between the BST and the SW pins supplies the gate current to charge the buck switch
gate at turn-on. The recommended value of C7 is 0.022µF, and should be a good quality, low ESR, ceramic
capacitor.
C4
The capacitor at the SS pin determines the soft-start time, i.e. the time for the reference voltage and the output
voltage, to reach the final regulated value. The time is determined from:
tss =
C4 x 1.225V
10 PA
(10)
For this application, a C4 value of 0.01µF was chosen which corresponds to a soft-start time of 1ms.
R5, R6
R5 and R6 set the output voltage level, the ratio of these resistors is calculated from:
R5/R6 = (VOUT / 1.225V) - 1
(11)
For a 5V output, the R5/R6 ratio calculates to 3.082. The resistors should be chosen from standard value
resistors, a good starting point is selection in the range of 1.0kΩ - 10kΩ. Values of 5.11kΩ for R5, and 1.65kΩ for
R6 were selected.
R1, R2, C12
A voltage divider can be connected to the SD pin to set a minimum operating voltage Vin(min) for the regulator. If
this feature is required, the easiest approach to select the divider resistor values is to select a value for R1
(between 10kΩ and 100kΩ recommended) then calculate R2 from:
§
¨
©
§
R1
R2 = 1.225 x ¨
-6
© VIN(min) + (5 x 10 x R1) ± 1.225
(12)
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Capacitor C12 provides filtering for the divider. The voltage at the SD pin should never exceed 8V, when using
an external set-point divider it may be necessary to clamp the SD pin at high input voltage conditions. The
reference design utilizes the full range of the LM5575 (6V to 75V); therefore these components can be omitted.
With the SD pin open circuit the LM5575 responds once the Vcc UVLO threshold is satisfied.
R7, C11
A snubber network across the power diode reduces ringing and spikes at the switching node. Excessive ringing
and spikes can cause erratic operation and couple spikes and noise to the output. Voltage spikes beyond the
rating of the LM5575 or the re-circulating diode can damage these devices. Selecting the values for the snubber
is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections
are very short. For the current levels typical for the LM5575 a resistor value between 5 and 20 Ohms is
adequate. Increasing the value of the snubber capacitor results in more damping but higher losses. Select a
minimum value of C11 that provides adequate damping of the SW pin waveform at high load.
R4, C5, C6
These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One
advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5.
The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of
the LM5575 is as follows:
DC Gain(MOD) = Gm(MOD) x RLOAD = 1 x RLOAD
(13)
The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD,) and output
capacitance (COUT). The corner frequency of this pole is:
fp(MOD) = 1 / (2π RLOAD COUT)
(14)
For RLOAD = 5Ω and COUT = 130µF then fp(MOD) = 245Hz
DC Gain(MOD) = 1 x 5 = 14dB
For the design example of Figure 9 the following modulator gain vs. frequency characteristic was measured as
shown in Figure 17.
REF LEVEL
0.000 dB
0.0 deg
/DIV
10.000 dB
45.000 deg
GAIN
0
PHASE
100
1k
START 100.000 Hz
10k
100k
STOP 100 000.000 Hz
Figure 17. Gain and Phase of Modulator
RLOAD = 5 Ohms and COUT = 130µF
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Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a
zero at fZ = 1 / (2πR4C5). The error amplifier zero cancels the modulator pole leaving a single pole response at
the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable
loop with 90 degrees of phase margin.
For the design example, a target loop bandwidth (crossover frequency) of 15kHz was selected. The
compensation network zero (fZ) should be selected at least an order of magnitude less than the target crossover
frequency. This constrains the product of R4 and C5 for a desired compensation network zero 1 / (2π R4 C5) to
be less than 2kHz. Increasing R4, while proportionally decreasing C5, increases the error amp gain. Conversely,
decreasing R4 while proportionally increasing C5, decreases the error amp gain. For the design example C5 was
selected for 0.01µF and R4 was selected for 49.9kΩ. These values configure the compensation network zero at
320Hz. The error amp gain at frequencies greater than fZ is: R4 / R5, which is approximately 10 (20dB).
/DIV
10.000 dB
45.000 deg
REF LEVEL
0.000 dB
0.0 deg
PHASE
GAIN
0
100
1k
START 50.000 Hz
10k
STOP 50 000.000 Hz
Figure 18. Error Amplifier Gain and Phase
The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.
REF LEVEL
0.000 dB
0.0 deg
/DIV
10.000 dB
45.000 deg
GAIN
PHASE
0
100
1k
START 100.000 Hz
10k
100k
STOP 100 000.000 Hz
Figure 19. Overall Loop Gain and Phase
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If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be
configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier
compensation components can be designed with the guidelines given. Step load transient tests can be
performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response.
C6 can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value
of C6 must be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer
function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of
the pole added by C6 is: fp2 = fz x C5 / C6.
BIAS POWER DISSIPATION REDUCTION
Buck regulators operating with high input voltage can dissipate an appreciable amount of power for the bias of
the IC. The VCC regulator must step-down the input voltage VIN to a nominal VCC level of 7V. The large voltage
drop across the VCC regulator translates into a large power dissipation within the Vcc regulator. There are several
techniques that can significantly reduce this bias regulator power dissipation. Figure 20 and Figure 21 depict two
methods to bias the IC from the output voltage. In each case the internal Vcc regulator is used to initially bias the
VCC pin. After the output voltage is established, the VCC pin potential is raised above the nominal 7V regulation
level, which effectively disables the internal VCC regulator. The voltage applied to the VCC pin should never
exceed 14V. The VCC voltage should never be larger than the VIN voltage.
LM5575
BST
VOUT
SW
L1
COUT
D1
IS
GND
VCC
D2
Figure 20. VCC Bias from VOUT for 8V < VOUT < 14V
LM5575
BST
VOUT
L1
SW
D1
COUT
IS
GND
D2
VCC
Figure 21. VCC Bias with Additional Winding on the Output Inductor
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PCB LAYOUT AND THERMAL CONSIDERATIONS
The circuit in Figure 9 serves as both a block diagram of the LM5575 and a typical application board schematic
for the LM5575. In a buck regulator there are two loops where currents are switched very fast. The first loop
starts from the input capacitors, to the regulator VIN pin, to the regulator SW pin, to the inductor then out to the
load. The second loop starts from the output capacitor ground, to the regulator PGND pins, to the regulator IS
pins, to the diode anode, to the inductor and then out to the load. Minimizing the loop area of these two loops
reduces the stray inductance and minimizes noise and possible erratic operation. A ground plane in the PC
board is recommended as a means to connect the input filter capacitors to the output filter capacitors and the
PGND pins of the regulator. Connect all of the low power ground connections (CSS, RT, CRAMP) directly to the
regulator AGND pin. Connect the AGND and PGND pins together through the topside copper area covering the
entire underside of the device. Place several vias in this underside copper area to the ground plane.
The two highest power dissipating components are the re-circulating diode and the LM5575 regulator IC. The
easiest method to determine the power dissipated within the LM5575 is to measure the total conversion losses
(Pin – Pout) then subtract the power losses in the Schottky diode, output inductor and snubber resistor. An
approximation for the Schottky diode loss is P = (1-D) x Iout x Vfwd. An approximation for the output inductor
power is P = IOUT2 x R x 1.1, where R is the DC resistance of the inductor and the 1.1 factor is an approximation
for the AC losses. If a snubber is used, an approximation for the damping resistor power dissipation is P = Vin2 x
Fsw x Csnub, where Fsw is the switching frequency and Csnub is the snubber capacitor. The regulator has an
exposed thermal pad to aid power dissipation. Adding several vias under the device to the ground plane will
greatly reduce the regulator junction temperature. Selecting a diode with an exposed pad will aid the power
dissipation of the diode.
The most significant variables that affect the power dissipated by the LM5575 are the output current, input
voltage and operating frequency. The power dissipated while operating near the maximum output current and
maximum input volatge can be appreciable. The operating frequency of the LM5575 evaluation board has been
designed for 300kHz. When operating at 1.5A output current with a 70V input the power dissipation of the
LM5575 regulator is approximately 1.25W.
The junction-to-ambient thermal resistance of the LM5575 will vary with the application. The most significant
variables are the area of copper in the PC board, the number of vias under the IC exposed pad and the amount
of forced air cooling provided. Referring to the evaluation board artwork, the area under the LM5575 (component
side) is covered with copper and there are 5 connection vias to the solder side ground plane. Additional vias
under the IC will have diminishing value as more vias are added. The integrity of the solder connection from the
IC exposed pad to the PC board is critical. Excessive voids will greatly diminish the thermal dissipation capacity.
The junction-to-ambient thermal resistance of the LM5575 mounted in the evaluation board varies from 50°C/W
with no airflow to 28°C/W with 900 LFM (Linear Feet per Minute). With a 25°C ambient temperature and no
airflow, the predicted junction temperature for the LM5575 will be 25 + (50 x 1.25) = 88°C. If the evaluation board
is operated at 1.5A output current, 70V input voltage and high ambient temperature for a prolonged period of
time the thermal shutdown protection within the IC may activate. The IC will turn off allowing the junction to cool,
followed by restart with the soft-start capacitor reset to zero.
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Table 1. 5V, 1.5A Demo Board Bill of Materials
ITEM
20
PART NUMBER
DESCRIPTION
VALUE
C
1
C3225X7R2A105M
CAPACITOR, CER, TDK
C
2
C3225X7R2A105M
CAPACITOR, CER, TDK
C
3
C0805A471K1GAC
CAPACITOR, CER, KEMET
470p, 100V
C
4
C2012X7R2A103K
CAPACITOR, CER, TDK
0.01µ, 100V
C
5
C2012X7R2A103K
CAPACITOR, CER, TDK
0.01µ, 100V
C
6
OPEN
NOT USED
C
7
C2012X7R2A223K
CAPACITOR, CER, TDK
0.022µ, 100V
C
8
C2012X7R1C474M
CAPACITOR, CER, TDK
0.47µ, 16V
C
9
C3225X7R1C106M
CAPACITOR, CER, TDK
C
10
APXE6R3ARA121ME61G
CAPACITOR, AL, NIPPON
120µ, 6.3V
C
11
C0805C331G1GAC
CAPACITOR, CER, KEMET
330p, 100V
C
12
OPEN
NOT USED
D
1
CMSH3-100
DIODE, 100V, CENTRAL
L
1
DR125-470
INDUCTOR, COOPER
R
1
OPEN
NOT USED
R
2
OPEN
NOT USED
R
3
CRCW08052102F
RESISTOR
21kΩ
R
4
CRCW08054992F
RESISTOR
49.9kΩ
R
5
CRCW08055111F
RESISTOR
5.11kΩ
R
6
CRCW08051651F
RESISTOR
1.65kΩ
R
7
CRCW2512100J
RESISTOR
10, 1W
U
1
LM5575
REGULATOR, TEXAS INSTRUMENTS
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1µ, 100V
1µ, 100V
10µ, 16V
47µH
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PCB Layout
Figure 22. Component Side
Figure 23. Solder Side
Figure 24. Silkscreen
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REVISION HISTORY
Changes from Revision F (April 2013) to Revision G
•
22
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
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15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
LM5575BLDT/NOPB
ACTIVE
LM5575MH
NRND
HTSSOP
LM5575MH/NOPB
ACTIVE
LM5575MHX/NOPB
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
0
1
TBD
Call TI
Call TI
PWP
16
92
TBD
Call TI
Call TI
-40 to 125
LM5575
MH
HTSSOP
PWP
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM5575
MH
ACTIVE
HTSSOP
PWP
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM5575
MH
LM5575Q0MH/NOPB
ACTIVE
HTSSOP
PWP
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5575QMH/NOPB
ACTIVE
HTSSOP
PWP
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM5575
QMH
LM5575QMHX/NOPB
ACTIVE
HTSSOP
PWP
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM5575
QMH
LM5575
Q0MH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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15-Apr-2017
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5575, LM5575-Q1 :
• Catalog: LM5575
• Automotive: LM5575-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM5575MHX/NOPB
HTSSOP
PWP
16
2500
330.0
12.4
LM5575QMHX/NOPB
HTSSOP
PWP
16
2500
330.0
12.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.95
5.6
1.6
8.0
12.0
Q1
6.95
5.6
1.6
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5575MHX/NOPB
HTSSOP
PWP
16
2500
367.0
367.0
35.0
LM5575QMHX/NOPB
HTSSOP
PWP
16
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016A
PowerPAD
TM
HTSSOP - 1.2 mm max height
SCALE 2.400
PLASTIC SMALL OUTLINE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
4.55
5.1
4.9
NOTE 3
8
9
B
4.5
4.3
16X
0.30
0.19
0.1
C A B
(0.15) TYP
SEE DETAIL A
4X 0.166 MAX
NOTE 5
2X 1.34 MAX
NOTE 5
THERMAL
PAD
3.3
2.7
17
0.25
GAGE PLANE
1.2 MAX
0.15
0.05
0 -8
0.75
0.50
(1)
3.3
2.7
DETAIL A
TYPICAL
4214868/A 02/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016A
PowerPAD
TM
HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
17
SYMM
(3.3)
(5)
NOTE 9
14X (0.65)
8
9
( 0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
0.05 MAX
ALL AROUND
EXPOSED
METAL
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4214868/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016A
PowerPAD
TM
HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3.3)
BASED ON
0.125 THICK
STENCIL
17
SYMM
14X (0.65)
9
8
SYMM
METAL COVERED
BY SOLDER MASK
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
3.69 X 3.69
3.3 X 3.3 (SHOWN)
3.01 X 3.01
2.79 X 2.79
4214868/A 02/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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