AD AD9250 Dual analog-to-digital converter Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and
250 MSPS
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz
AIN and 250 MSPS
Total power consumption: 711 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
APPLICATIONS
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
I/Q demodulation systems
Smart antenna systems
Electronic test and measurement equipment
Radar receivers
COMSEC radio architectures
IED detection/jamming systems
General-purpose software radios
Broadband data applications
AVDD DRVDD
DVDD
AGND DGND DRGND
AD9250
VIN+A
VIN–A
PIPELINE
14-BIT ADC
VCM
VIN+B
VIN–B
PIPELINE
14-BIT ADC
JESD204B
INTERFACE
SERDOUT0±
CML, TX
OUTPUTS
HIGH
SPEED
SERIALIZERS
SERDOUT1±
CONTROL
REGISTERS
SYSREF±
SYNCINB±
CLK±
RFCLK
CLOCK
GENERATION
CMOS
DIGITAL
INPUT/OUTPUT
RST
SDIO SCLK
CS
FAST
DETECT
CMOS
DIGITAL
INPUT
PDWN
CMOS
DIGITAL
OUTPUT
FDA
FDB
10559-001
Data Sheet
14-Bit, 170 MSPS/250 MSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9250
Figure 1.
PRODUCT HIGHLIGHTS
1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
2. The configurable JESD204B output block supports up to
5 Gbps per lane.
3. An on-chip, phase-locked loop (PLL) allows users to provide
a single ADC sampling clock; the PLL multiplies the ADC
sampling clock to produce the corresponding JESD204B
data rate clock.
4. Support for an optional RF clock input to ease system board
design.
5. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
6. Operation from a single 1.8 V power supply.
7. Standard serial port interface (SPI) that supports various
product features and functions such as controlling the clock
DCS, power-down, test modes, voltage reference mode, over
range fast detection, and serial output configuration.
This product may be protected by one or more U.S. or international patents.
Rev. E
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Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9250
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
JESD204B Overview .................................................................. 25
Applications ....................................................................................... 1
JESD204B Synchronization Details ......................................... 26
Functional Block Diagram .............................................................. 1
Link Setup Parameters ............................................................... 26
Product Highlights ........................................................................... 1
Frame and Lane Alignment Monitoring and Correction ..... 30
Revision History ............................................................................... 3
Digital Outputs and Timing ..................................................... 30
General Description ......................................................................... 4
ADC Overrange and Gain Control.......................................... 32
Specifications..................................................................................... 5
ADC Overrange (OR)................................................................ 32
ADC DC Specifications ............................................................... 5
Gain Switching ............................................................................ 32
ADC AC Specifications ............................................................... 6
DC Correction ................................................................................ 33
Digital Specifications ................................................................... 7
DC Correction Bandwidth........................................................ 33
Switching Specifications .............................................................. 9
DC Correction Readback .......................................................... 33
Timing Specifications ................................................................ 10
DC Correction Freeze ................................................................ 33
Absolute Maximum Ratings .......................................................... 11
DC Correction (DCC) Enable Bits .......................................... 33
Thermal Characteristics ............................................................ 11
Serial Port Interface (SPI) .............................................................. 34
ESD Caution ................................................................................ 11
Configuration Using the SPI ..................................................... 34
Pin Configuration and Function Descriptions ........................... 12
Hardware Interface ..................................................................... 34
Typical Performance Characteristics ........................................... 14
SPI Accessible Features .............................................................. 35
Equivalent Circuits ......................................................................... 18
Memory Map .................................................................................. 36
Theory of Operation ...................................................................... 20
Reading the Memory Map Register Table............................... 36
ADC Architecture ...................................................................... 20
Memory Map Register Table ..................................................... 37
Analog Input Considerations.................................................... 20
Memory Map Register Description ......................................... 41
Voltage Reference ....................................................................... 21
Applications Information .............................................................. 42
Clock Input Considerations ...................................................... 21
Design Guidelines ...................................................................... 42
Power Dissipation and Standby Mode ..................................... 24
SPI Initialization Sequence ....................................................... 42
Digital Outputs ............................................................................... 25
Outline Dimensions ....................................................................... 45
JESD204B Transmit Top Level Description ............................ 25
Ordering Guide .......................................................................... 45
Rev. E | Page 2 of 45
Data Sheet
AD9250
REVISION HISTORY
9/2017—Rev. D to Rev. E
Changes to Channel-Specific Registers Section ................................. 36
Changes to Table 18 ................................................................................... 37
Changes to Figure 63 and Table 19 ........................................................ 43
5/2017—Rev. C to Rev. D
Change to Differential Output Voltage (VOD) Parameter, Table 3 .... 8
Deleted Synchronization Section ..................................................26
Changes to Link Setup Parameters Section .................................26
Deleted Clock Adjustment Register Writes Section ...................27
Added Internal FIFO Timing Optimization Section .................28
Changes to Table 14 ........................................................................30
Changes to Channel-Specific Registers Section ..........................36
Deleted Transfer Register Map Section ........................................37
Changes to Table 18 ........................................................................37
Added SPI Initialization Sequence Section..................................42
Added Figure 63 and Table 19; Renumbered Sequentially ........43
Deleted JESD204B Configuration Section ...................................44
Updated Outline Dimensions ........................................................45
1/2016—Rev. B to Rev. C
Moved Revision History Section ..................................................... 3
Changes to Nyquist Clock Input Options ....................................22
Added Synchronization Section ....................................................26
Added Click Adjustment Register Writes Section ......................27
Changes to Link Setup Parameters Section .................................27
Change to Additional Digital Output Configuration Options
Section ..............................................................................................29
Added Table 14, Renumbered Sequentially .................................30
Changes to Table 18 ........................................................................38
Added JESD204B Configuration Section ....................................43
12/2013—Rev. A to Rev. B
Change to Features Section .............................................................. 1
Change to Functional Block Diagram ............................................ 1
Change to SYNCIN Input (SYNCINB+/SYNCINB−), Logic
Compliance Parameter, Table 3 ....................................................... 6
Changes to Data Output Parameters, Table 4 ............................... 8
Changes to Figure 3 .......................................................................... 9
Change to Figure 30, Added Figure 34 through Figure 37;
Renumbered Sequentially .............................................................. 17
Changes to Table 9 .......................................................................... 20
Change to Figure 47 ........................................................................ 21
Changes to JESD204B Overview Section .................................... 24
Change to Configure Details Options Section ............................ 26
Change to Check FCHK, Checksum of JESD204B Interface
Parameters Section .......................................................................... 27
Changes to Figure 54 ...................................................................... 28
Changes to Figure 57 and Figure 58 ............................................. 29
Changes to Figure 59 and Figure 60 ............................................. 30
Changes to Table 17 ........................................................................ 36
Updated Outline Dimensions........................................................ 42
3/2013—Rev. 0 to Rev. A
Changes to High Level Input Current and Low Level Input
Current; Table 3 ................................................................................. 6
Changes to Table 4 ............................................................................ 8
Changes to Figure 3 Caption ........................................................... 9
Changes to Digital Inputs Description; Table 8 .......................... 11
Changes to JESD204B Synchronization Details Section ........... 24
Changes to Configure Detailed Options Section........................ 25
Changes to Fast Threshold Detection (FDA and FDB) Section ...30
Deleted Built-In Self-Test (BIST) and Output Test Section ...... 32
Changes to Transfer Register Map Section .................................. 34
Changes to Table 17 ........................................................................ 35
10/2012—Revision 0: Initial Version
Rev. E | Page 3 of 45
AD9250
Data Sheet
GENERAL DESCRIPTION
The AD9250 is a dual, 14-bit ADC with sampling speeds of up
to 250 MSPS. The AD9250 is designed to support communications
applications where low cost, small size, wide bandwidth, and
versatility are desired.
The ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC cores feature wide bandwidth inputs supporting a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided
to compensate for variations in the ADC clock duty cycle, allowing
the converters to maintain excellent performance. The JESD204B
high speed serial interface reduces board routing requirements
and lowers pin count requirements for the receiving device.
By default, the ADC output data is routed directly to the two
JESD204B serial output lanes. These outputs are at CML voltage
levels. Four modes support any combination of M = 1 or 2 (single
or dual converters) and L = 1 or 2 (one or two lanes). For dual
ADC mode, data can be sent through two lanes at the maximum
sampling rate of 250 MSPS. However, if data is sent through
one lane, a sampling rate of up to 125 MSPS is supported.
Synchronization inputs (SYNCINB± and SYSREF±) are provided.
Flexible power-down options allow significant power savings,
when desired. Programmable overrange level detection is
supported for each channel via the dedicated fast detect pins.
Programming for setup and control are accomplished using a
3-wire SPI-compatible serial interface.
The AD9250 is available in a 48-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C.
Rev. E | Page 4 of 45
Data Sheet
AD9250
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, duty cycle stabilizer (DCS) enabled, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL) 1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span
Input Capacitance 2
Input Resistance 3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
DVDD
Supply Current
IAVDD
IDRVDD + IDVDD
POWER CONSUMPTION
Sine Wave Input
Standby Power 4
Power-Down Power
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Min
14
AD9250-170
Typ
Max
Min
14
Guaranteed
−16
−6
AD9250-250
Typ
Max
Guaranteed
+16
+2
±0.75
−16
−6
±0.25
+16
+2.5
±0.75
±0.25
±2.1
±3.5
±1.5
−15
−2
Unit
Bits
±1.5
+15
+3.5
−15
−2
+15
+3
mV
%FSR
LSB
LSB
LSB
LSB
mV
%FSR
Full
Full
±2
±16
±2
±44
ppm/°C
ppm/°C
25°C
1.49
1.49
LSB rms
Full
Full
Full
Full
1.75
2.5
20
0.9
1.75
2.5
20
0.9
V p-p
pF
kΩ
V
Full
Full
Full
1.7
1.7
1.7
1.8
1.8
1.8
1.9
1.9
1.9
Full
Full
233
104
260
113
Full
Full
Full
607
280
9
Measured with a low input frequency, full-scale sine wave.
Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3
Input resistance refers to the effective resistance between one differential input pin and its complement.
4
Standby power is measured with a dc input and the CLK± pin active.
1
2
Rev. E | Page 5 of 45
1.7
1.7
1.7
1.8
1.8
1.8
1.9
1.9
1.9
V
V
V
255
140
280
160
mA
mA
711
339
9
mW
mW
mW
AD9250
Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
Temperature
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
Min
AD9250-170
Typ
Max
Min
AD9250-250
Typ
Max
72.5
72.0
72.1
71.7
71.4
70.7
71.2
70.6
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
70.7
69.3
70.1
70.0
71.3
70.9
70.7
70.5
70.3
69.6
70.0
69.5
Unit
68.9
68.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
25°C
11.5
11.4
11.3
11.1
10.9
11.5
11.4
11.3
11.2
11.0
Bits
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
Full
25°C
92
95
89
86
91
86
86
88
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
Rev. E | Page 6 of 45
69.6
68.0
78
80
85
88
−92
−95
−89
−87
−78
−91
−86
−86
−88
−85
−88
−95
−94
−94
−96
−80
−78
−97
−96
−96
−88
−93
−91
−80
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Data Sheet
Parameter 1
TWO-TONE SFDR
fIN = 184.12 MHz (−7 dBFS), 187.12 MHz (−7 dBFS)
CROSSTALK 2
FULL POWER BANDWIDTH 3
AD9250
Temperature
25°C
Full
25°C
Min
AD9250-170
Typ
Max
Min
AD9250-250
Typ
Max
87
95
1000
Unit
84
95
1000
dBc
dB
MHz
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
3
Full power bandwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 dB.
1
2
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, DCS enabled, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Input CLK± Clock Rate
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
RF CLOCK INPUT (RFCLK)
Input CLK± Clock Rate
Logic Compliance
Internal Bias
Input Voltage Range
Input Voltage Level
High
Low
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance (AC-Coupled)
SYNCIN INPUT (SYNCINB+/SYNCINB−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage Range
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Temperature
Min
Full
40
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. E | Page 7 of 45
Typ
Max
Unit
625
MHz
CMOS/LVDS/LVPECL
0.9
12
V
V p-p
V
V
µA
µA
pF
kΩ
1500
MHz
AGND
AVDD
V
V
1.2
AGND
0
−150
AVDD
0.6
+150
0
0.3
AGND
0.9
0
−60
8
3.6
AVDD
1.4
+60
0
4
10
650
CMOS/LVDS/LVPECL
0.9
8
1
10
12
CMOS/LVDS
0.9
0.3
DGND
0.9
−5
−5
12
3.6
DVDD
1.4
+5
+5
1
16
20
V
V
µA
µA
pF
kΩ
V
V p-p
V
V
µA
µA
pF
kΩ
AD9250
Parameter
SYSREF INPUT (SYSREF±)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage Range
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (RST, CS) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/PDWN) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS (SERDOUT0±/SERDOUT1±)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
DIGITAL OUTPUTS (SDIO/FDA/FDB)
High Level Output Voltage (VOH)
IOH = 50 µA
IOH = 0.5 mA
Low Level Output Voltage (VOL)
IOL = 1.6 mA
IOL = 50 µA
1
2
Data Sheet
Temperature
Min
Typ
Max
Unit
LVDS
Full
Full
Full
Full
Full
Full
Full
Full
0.9
0.3
AGND
0.9
−5
−5
8
Full
Full
Full
Full
Full
Full
1.22
0
−5
−100
Full
Full
Full
Full
Full
Full
1.22
0
45
−10
Full
Full
Full
Full
Full
Full
1.22
0
45
−10
Full
Full
Full
Full
Full
Full
Full
Full
Full
Pull-up.
Pull-down.
Rev. E | Page 8 of 45
3.6
AVDD
1.4
+5
+5
4
10
12
2.1
0.6
+5
−45
V
V
µA
µA
kΩ
pF
2.1
0.6
100
+10
V
V
µA
µA
kΩ
pF
2.1
0.6
100
10
V
V
µA
µA
kΩ
pF
750
1.05
mV p-p
V
26
2
26
2
26
5
400
0.75
CML
600
DRVDD/2
V
V p-p
V
V
µA
µA
pF
kΩ
1.79
1.75
V
V
0.2
0.05
V
V
Data Sheet
AD9250
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Conversion Rate 1
SYSREF± Setup Time to Rising Edge CLK± 2
SYSREF± Hold Time from Rising Edge CLK±2
SYSREF± Setup Time to Rising Edge RFCLK2
SYSREF± Hold Time from Rising Edge RFCLK2
CLK± Pulse Width High
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-by-8 Mode
Aperture Delay
Aperture Uncertainty (Jitter)
DATA OUTPUT PARAMETERS
Data Output Period or Unit Interval (UI)
Data Output Duty Cycle
Data Valid Time
PLL Lock Time (tLOCK)
Wake-Up Time
Standby
ADC (Power-Down) 3
Output (Power-Down) 4
Subclass 0: SYNCINB± Falling Edge to First Valid
K.28 Characters (Delay Required for Rx CGS Start)
Subclass 1: SYSREF± Rising Edge to First Valid K.28
Characters (Delay Required for SYNCB± Rising
Edge/Rx CGS Start)
CGS Phase K.28 Characters Duration
Pipeline Delay
JESD204B M1, L1 Mode (Latency)
JESD204B M1, L2 Mode (Latency)
JESD204B M2, L1 Mode (Latency)
JESD204B M2, L2 Mode (Latency)
Fast Detect (Latency)
Data Rate per Lane
Uncorrelated Bounded High Probability (UBHP) Jitter
Random Jitter
At 3.4 Gbps
At 5.0 Gbps
Output Rise/Fall Time
Differential Termination Resistance
Out-of-Range Recovery Time
AD9250-170
Min Typ Max
AD9250-250
Min Typ Max
Full
Full
Full
Full
Full
40
40
Full
Full
Full
Full
Full
2.61
2.76
0.8
Full
25°C
25°C
25°C
L/(20 × M × fS)
50
0.84
25
Symbol
Temperature
fS
tREFS
tREFH
tREFSRF
tREFHRF
tCH
tA
tJ
170
0.31
0
0.50
0
2.9
2.9
250
MSPS
ns
ns
ns
ns
2.2
2.1
ns
ns
ns
ns
ps rms
0.31
0
0.50
0
3.19
3.05
1.8
1.9
0.8
1.0
0.16
2.0
2.0
1.0
0.16
L/(20 × M × fS)
50
0.78
25
10
250
50
Unit
Seconds
%
UI
µs
25°C
25°C
25°C
Full
5
5
µs
µs
µs
Multiframes
Full
6
6
Multiframes
Full
1
1
Multiframes
Full
Full
Full
Full
Full
Full
25°C
36
59
25
36
7
3.4
6
Full
Full
Full
25°C
Full
2.3
10
250
50
36
59
25
36
7
2
Rev. E | Page 9 of 45
1.7
60
100
3
ps rms
ps rms
ps
Ω
Cycles
5.0
60
100
3
Conversion rate is the clock rate after the divider.
Refer to Figure 3 for timing diagram.
3
Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode.
4
Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode.
5
Cycles refers to ADC conversion rate cycles.
1
8
Cycles 5
Cycles
Cycles
Cycles
Cycles
Gbps
ps
5.0
AD9250
Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
SPI TIMING REQUIREMENTS (See Figure 62)
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
tSPI_RST
Test Conditions/Comments
Min
Typ
Max
Unit
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CS and SCLK
Hold time between CS and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge (not shown in figures)
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge (not shown in figures)
Time required after hard or soft reset until SPI access is available
(not shown in figures)
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
500
µs
Timing Diagrams
SAMPLE N
N – 36
N+1
N – 35
ANALOG
INPUT
SIGNAL
N – 34
N–1
N – 33
CLK–
CLK+
CLK–
CLK+
SERDOUT1±
SAMPLE N – 36
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE N – 35
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE N – 34
ENCODED INTO 2
8b/10b SYMBOLS
Figure 2. Data Output Timing
RFCLK
CLK+
SYSREF+
tREFS
tREFSRF
tREFH
SYSREF+
SYSREF–
SYSREF–
NOTES
1. CLOCK INPUT IS EITHER RFCLK OR CLK±, NOT BOTH.
Figure 3. SYSREF± Setup and Hold Timing
Rev. E | Page 10 of 45
tREFHRF
10559-003
CLK–
10559-002
SERDOUT0±
Data Sheet
AD9250
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
ELECTRICAL
AVDD to AGND
DRVDD to AGND
DVDD to DGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
RFCLK to AGND
VCM to AGND
CS, PDWN to AGND
SCLK to AGND
SDIO to AGND
RST to DGND
FDA, FDB to DGND
SERDOUT0+, SERDOUT0−,
SERDOUT1+, SERDOUT1− to AGND
SYNCINB+, SYNCINB− to DGND
SYSREF+, SYSREF− to AGND
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +85°C
150°C
The exposed paddle must be soldered to the ground plane for
the LFCSP package. This increases the reliability of the solder
joints, maximizing the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
48-Lead LFCSP
7 mm × 7 mm
(CP-48-13)
Airflow
Velocity
(m/sec)
0
1.0
2.5
θJA1, 2
25
22
20
θJC1, 3
2
θJB1, 4
14
Unit
°C/W
°C/W
°C/W
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-STD-883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
1
2
Typical θJA is specified for a 4-layer printed circuit board (PCB)
with a solid ground plane. As shown in Table 7, airflow increases
heat dissipation, which reduces θJA. In addition, metal in direct
contact with the package leads from metal traces, through holes,
ground, and power planes reduces the θJA.
ESD CAUTION
−65°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. E | Page 11 of 45
AD9250
Data Sheet
48
47
46
45
44
43
42
41
40
39
38
37
AVDD
AVDD
VIN–B
VIN+B
AVDD
AVDD
VCM
AVDD
AVDD
VIN+A
VIN–A
AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
AD9250
TOP VIEW
(Not to Scale)
AVDD
DNC
PDWN
CS
SCLK
SDIO
DVDD
DNC
DNC
FDA
FDB
DVDD
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE
PACKAGE PROVIDES THE GROUND REFERENCE FOR
DRVDD AND AVDD. THIS EXPOSED PADDLE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
10559-004
DVDD
SYNCINB+
SYNCINB–
DVDD
DGND
SERDOUT1+
SERDOUT1–
DRVDD
SERDOUT0–
SERDOUT0+
DGND
DVDD
13
14
15
16
17
18
19
20
21
22
23
24
AVDD 1
RFCLK 2
CLK– 3
CLK+ 4
AVDD 5
SYSREF+ 6
SYSREF– 7
AVDD 8
DVDD 9
RST 10
DVDD 11
DNC 12
Figure 4. Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
ADC Power Supplies
1, 5, 8, 36, 37, 40, 41, 43, 44, 47, 48
9, 11, 13, 16, 24, 25, 30
12, 28, 29, 35
17, 23
20
Exposed Paddle
ADC Analog
2
3
4
38
39
42
45
46
ADC Fast Detect Outputs
26
27
Digital Inputs
6
7
14
15
Mnemonic
Type
Description
AVDD
DVDD
DNC
DGND
DRVDD
Supply
Supply
AGND/DRGND
Ground
Analog Power Supply (1.8 V Nominal).
Digital Power Supply (1.8 V Nominal).
Do Not Connect.
Ground Reference for DVDD.
JESD204B PHY Serial Output Driver Supply (1.8 V Nominal).
Note that the DRVDD power is referenced to the AGND Plane.
The exposed thermal paddle on the bottom of the package
provides the ground reference for DRVDD and AVDD. This
exposed paddle must be connected to ground for proper
operation.
RFCLK
CLK−
CLK+
VIN−A
VIN+A
VCM
Input
Input
Input
Input
Input
Output
VIN+B
VIN−B
Input
Input
ADC RF Clock Input.
ADC Nyquist Clock Input—Complement.
ADC Nyquist Clock Input—True.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel A.
Common-Mode Level Bias Output for Analog Inputs. Decouple
this pin to ground using a 0.1 µF capacitor.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
FDB
FDA
Output
Output
Channel B Fast Detect Indicator (CMOS Levels).
Channel A Fast Detect Indicator (CMOS Levels).
SYSREF+
SYSREF−
SYNCINB+
SYNCINB−
Input
Input
Input
Input
JESD204B LVDS SYSREF Input—True.
JESD204B LVDS SYSREF Input—Complement.
JESD204B LVDS SYNC Input—True.
JESD204B LVDS SYNC Input—Complement.
Supply
Rev. E | Page 12 of 45
Data Sheet
Pin No.
Data Outputs
18
19
21
22
DUT Controls
10
31
32
33
34
AD9250
Mnemonic
Type
Description
SERDOUT1+
SERDOUT1−
SERDOUT0−
SERDOUT0+
Output
Output
Output
Output
Lane B CML Output Data—True.
Lane B CML Output Data—Complement.
Lane A CML Output Data—Complement.
Lane A CML Output Data—True.
RST
SDIO
SCLK
CS
PDWN
Input
Input/Output
Input
Input
Input
Digital Reset (Active Low).
SPI Serial Data I/O.
SPI Serial Clock.
SPI Chip Select (Active Low).
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as powerdown or standby (see Table 18).
Rev. E | Page 13 of 45
AD9250
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, sample rate is maximum for speed grade, DCS enabled, 1.75 V p-p differential input,
VIN = −1.0 dBFS, 32k sample, TA = 25°C, link parameters used were M = 2 and L = 2, unless otherwise noted.
SNR: 71.8dBFS
SFDR: 91dBc
100
SNR/SFDR (dBc AND dBFS)
–20
–40
–60
–80
–100
0
20
40
60
80
FREQUENCY (MHz)
Figure 5. AD9250-170 Single-Tone FFT with fIN = 90.1 MHz
0
–70
–50
–30
–10
Figure 8. AD9250-170 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 185.1 MHz
100
95
SNR: 71.6dBFS
SFDR: 86dBc
SFDR
SNR/SFDR (dBc AND dBFS)
–40
–60
–80
90
85
80
75
SNR
70
65
20
40
60
80
FREQUENCY (MHz)
Figure 6. AD9250-170 Single-Tone FFT with fIN = 185.1 MHz
0
60
10559-006
0
50
100
150
200
250
300
FREQUENCY (MHz)
Figure 9. AD9250-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
0
fIN: 305.1MHz
fS: 170MSPS
SNR: 69.4dBFS
SFDR: 85dBc
–20
SFDR/IMD (dBc AND dBFS)
–20
0
10559-009
AMPLITUDE (dBFS)
SNR
SNRFS
SFDR
SFDR dBc
INPUT AMPLITUDE (dBFS)
–100
–40
–60
–80
SFDR (dBc)
–40
IMD (dBc)
–60
–80
SFDR (dBFS)
–100
–100
–120
–120
–90
IMD (dBFS)
0
20
40
60
80
FREQUENCY (MHz)
Figure 7. AD9250-170 Single-Tone FFT with fIN = 305.1 MHz
10559-007
AMPLITUDE (dBFS)
40
0
–90
fIN: 185.1MHz
fS: 170MSPS
–20
–120
60
20
10559-005
–120
80
–70
–50
–30
INPUT AMPLITUDE (dBFS)
–10
10559-010
AMPLITUDE (dBFS)
120
fIN: 90.1MHz
fS: 170MSPS
10559-008
0
Figure 10. AD9250-170 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 170 MSPS
Rev. E | Page 14 of 45
Data Sheet
AD9250
0
100
–20
95
SNR/SFDR (dBc AND dBFS)
–40
SFDR (dBc)
IMD (dBc)
–60
–80
SFDR (dBFS)
–100
90
SFDR_B (dBc)
85
80
75
SNRFS_A (dBFS)
IMD (dBFS)
–50
–70
–30
–10
INPUT AMPLITUDE (dBFS)
600,000
2,096,064 TOTAL HITS
1.4925 LSB rms
555924
498226
500,000
–40
NUMBER OF HITS
AMPLITUDE (dBFS)
140
Figure 14. AD9250-170 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90.1 MHz
170 MSPS
89.12MHz AT –7dBFS
92.12MHz AT –7dBFS
SFDR: 91dBc
–20
90
SAMPLE RATE (MHz)
Figure 11. AD9250-170 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 170 MSPS
0
SNRFS_B (dBFS)
70
40
10559-011
–120
–90
10559-014
SFDR/IMD (dBc AND dBFS)
SFDR_A (dBc)
–60
–80
400,000
387659
300,000
281445
200,000
177569
109722
–100
100,000
47521
20
40
60
80
FREQUENCY (MHz)
N–6
24220
8529
N–4
3479
N–2
N
N+2
N+4
450
N+6
OUTPUT CODE
0
0
170 MSPS
184.12MHz AT –7dBFS
187.12MHz AT –7dBFS
SFDR: 86dBc
fIN: 90.1MHz
fS: 250MSPS
AMPLITUDE (dBFS)
SNR: 71.8dBFS
–20 SFDR: 85dBc
–40
–60
–80
–100
–40
–60
–80
–120
0
20
40
60
80
FREQUENCY (MHz)
–120
0
50
FREQUENCY (MHz)
100
125
Figure 16. AD9250-250 Single-Tone FFT with fIN = 90.1 MHz
Figure 13. AD9250-170 Two-Tone FFT with fIN1 = 184.12 MHz,
fIN2 = 187.12 MHz, fS = 170 MSPS
Rev. E | Page 15 of 45
10559-016
–100
10559-013
AMPLITUDE (dBFS)
1184
Figure 15. AD9250-170 Grounded Input Histogram
Figure 12. AD9250-170 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz,
fS = 170 MSPS
–20
136
10559-015
0
0
10559-012
–120
AD9250
0
100
fIN: 185.1MHz
fS: 250MSPS
SFDR (dBFS)
SNR: 70.7dBFS
SFDR: 85dBc
SNR/SFDR (dBc AND dBFS)
–20
AMPLITUDE (dBFS)
Data Sheet
–40
–60
–80
90
80
SNR (dBc)
70
0
50
60
10559-017
–120
100
FREQUENCY (MHz)
100
200
300
FREQUENCY (MHz)
Figure 20. AD9250-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
Figure 17. AD9250-250 Single-Tone FFT with fIN = 185.1 MHz
0
0
fIN: 305.1MHz
fS: 250MSPS
SNR: 69.1dBFS
SFDR: 82dBc
–20
SFDR/IMD (dBc and dBFS)
–20
AMPLITUDE (dBFS)
0
10559-020
–100
–40
–60
–80
SFDR (dBc)
–40
IMD (dBc)
–60
–80
SFDR (dBFS)
–100
–100
–120
–120
–100
50
100
FREQUENCY (MHz)
–80
–60
–40
–20
0
AIN (dBFS)
10559-021
0
10559-018
IMD (dBFS)
Figure 21. AD9250-250 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS
Figure 18. AD9250-250 Single-Tone FFT with fIN = 305.1 MHz
0
120
SFDR (dBFS)
–20
80
SFDR/IMD (dBc and dBFS)
SNR/SFDR (dBc and dBFS)
100
SNR (dBFS)
60
SFDR (dBc)
40
SNR (dBc)
SFDR (dBc)
–40
IMD (dBc)
–60
–80
SFDR (dBFS)
–100
20
–60
–40
AIN (dBFS)
–20
0
10559-019
–80
–120
–100
–80
–60
–40
INPUT AMPLITUDE (dBFS)
Figure 19. AD9250-250 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 185.1 MHz
–20
0
10559-022
IMD (dBFS)
0
–100
Figure 22. AD9250-250 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS
Rev. E | Page 16 of 45
Data Sheet
AD9250
100
0
250MSPS
89.12MHz AT –7dBFS
92.12MHz AT –7dBFS
SFDR: 86.4dBc
95
SNR/SFDR (dBc AND dBFS)
–40
–60
–80
90
85
SFDR_B (dBc)
80
75
SNR_B (dBc)
SNR_A (dBc)
0
50
FREQUENCY (MHz)
100
70
40 50
10559-023
–120
2,095,578 TOTAL HITS
1.4535 LSB rms
NUMBER OF HITS
–60
–80
250
570587
498242
500k
400k
380706
300k
276088
200k
163389
109133
–100
100k
52008
26647
–120
0
50
100
FREQUENCY (MHz)
10559-024
AMPLITUDE (dBFS)
600k
–40
200
Figure 25. AD9250-250 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90.1 MHz
250MSPS
184.12MHz AT –7dBFS
187.12MHz AT –7dBFS
SFDR: 84dBc
–20
150
SAMPLE RATE (MSPS)
Figure 23. AD9250-250 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz,
fS = 250 MSPS
0
100
10559-025
–100
Figure 24. AD9250-250 Two-Tone FFT with
fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS
0
418
N–6
2142
10549
N–4
4856
N–2
N
N+2
N+4
OUTPUT CODE
Figure 26. AD9250-250 Grounded Input Histogram
Rev. E | Page 17 of 45
913
N+6
10559-026
AMPLITUDE (dBFS)
–20
SFDR_A (dBc)
AD9250
Data Sheet
EQUIVALENT CIRCUITS
AVDD
AVDD
VIN
400Ω
SDIO
10559-226
10559-027
31kΩ
Figure 31. Equivalent SDIO Circuit
Figure 27. Equivalent Analog Input Circuit
AVDD
AVDD
AVDD
AVDD
0.9V
15kΩ
15kΩ
CLK+
CLK–
400Ω
SCLK/PWDN
10559-028
10559-225
31kΩ
Figure 32. Equivalent SCLK or PDWN Input Circuit
Figure 28. Equivalent Clock lnput Circuit
0.5pF
AVDD
AVDD
AVDD
INTERNAL
CLOCK DRIVER
RFCLK
28kΩ
400Ω
CS
BIAS
CONTROL
10559-224
10559-029
10kΩ
Figure 29. Equivalent RF Clock lnput Circuit
Figure 33. Equivalent CS Input Circuit
AVDD
DRVDD
DRVDD
3mA
DRVDD
RTERM
AVDD
3mA
AVDD
0.9V
17kΩ
VCM
SERDOUTx+
17kΩ
SYSREF+
SYSREF–
3mA
Figure 30. Digital CML Output Circuit
10559-134
10559-030
3mA
SERDOUTx–
Figure 34. Equivalent SYSREF± Input Circuit
Rev. E | Page 18 of 45
Data Sheet
AD9250
DVDD
DVDD
DVDD
400Ω
DVDD
0.9V
SYNCINB+
17kΩ
17kΩ
SYNCINB–
10559-122
10559-333
RST
DVDD
28kΩ
Figure 37. SYNCINB± Circuit
Figure 35. Equivalent RST Input Circuit
AVDD
10559-136
400 Ω
VCM
Figure 36. Equivalent VCM Circuit
Rev. E | Page 19 of 45
AD9250
Data Sheet
THEORY OF OPERATION
The AD9250 has two analog input channels and two JESD204B
output lanes. The signal passes through several stages before
appearing at the output port(s).
The dual ADC design can be used for diversity reception of signals,
where the ADCs operate identically on the same carrier but from
two separate antennae. The ADCs can also be operated with
independent analog inputs. The user can sample frequencies
from dc to 300 MHz using appropriate low-pass or band-pass
filtering at the ADC inputs with little loss in ADC performance.
Operation to 400 MHz analog input is permitted but occurs at
the expense of increased ADC noise and distortion.
A synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9250 are accomplished
using a 3-pin, SPI-compatible serial interface.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, reduce
the shunt capacitors. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth.
Refer to the AN-742 Application Note, Frequency Domain
Response of Switched-Capacitor ADCs; the AN-827 Application
Note, A Resonant Approach to Interfacing Amplifiers to SwitchedCapacitor ADCs; and the Analog Dialogue article, “TransformerCoupled Front-End for Wideband A/D Converters,” for more
information on this subject.
BIAS
ADC ARCHITECTURE
S
The AD9250 architecture consists of a dual, front-end, sampleand-hold circuit, followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or singleended modes. The output staging block aligns the data, corrects
errors, and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing digital output noise to
be separated from the analog core.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9250 is a differential, switched capacitor
circuit that has been designed for optimum performance while
processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see the configuration shown in Figure 38).
When the input is switched into sample mode, the signal source
must be capable of charging the sampling capacitors and settling
within 1/2 clock cycle.
S
CFB
CS
VIN+
CPAR1
CPAR2
H
S
S
CS
CPAR1
CPAR2
S
CFB
S
BIAS
10559-034
VIN–
Figure 38. Switched-Capacitor Input
For best dynamic performance, match the source impedances
driving VIN+ and VIN− and differentially balance the inputs.
Input Common Mode
The analog inputs of the AD9250 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD (or
0.9 V) is recommended for optimum performance. An on-board
common-mode voltage reference is included in the design and is
available from the VCM pin. Using the VCM output to set the
input common mode is recommended. Optimum performance
is achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically 0.5 × AVDD). Decouple
the VCM pin to ground by using a 0.1 µF capacitor, as described
in the Applications Information section. Place this decoupling
capacitor close to the pin to minimize the series resistance and
inductance between the part and this capacitor.
Differential Input Configurations
Optimum performance is achieved while driving the AD9250
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, ADA4938-2, and ADA4930-2 differential drivers provide excellent performance and a flexible
interface to the ADC.
Rev. E | Page 20 of 45
Data Sheet
AD9250
The output common-mode voltage of the ADA4930-2 is easily
set with the VCM pin of the AD9250 (see Figure 39), and the
driver can be configured in a Sallen-Key filter topology to
provide band-limiting of the input signal.
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters,
the value of the input resistors and capacitors may need to be
adjusted or some components may need to be removed. Table 9
displays recommended values to set the RC network for different
input frequency ranges. However, these values are dependent on
the input signal and bandwidth and should be used only as a
starting guide. Note that the values given in Table 9 are for each
R1, R2, C1, C2, and R3 components shown in Figure 40 and
Figure 41.
15pF
200Ω
33Ω
90Ω
15Ω
VIN–
AVDD
5pF
ADA4930-2
0.1µF
ADC
33Ω
15Ω
VCM
VIN+
120Ω
15pF
200Ω
Table 9. Example RC Network
0.1µF
Frequency
Range
(MHz)
0 to 100
100 to 400
>400
10559-035
33Ω
Figure 39. Differential Input Configuration Using the ADA4930-2
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 40. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
R2
VIN+
R1
49.9Ω
C1
R2
R1
0.1µF
1000pF
ADC
VIN–
VCM
AD8376
33Ω
R3
0.1µF
C2
1µH
R2
S
P
0.1µF
33Ω
0.1µF
VIN+
ADC
C1
R1
R2
R3
VIN–
33Ω
C2
Figure 41. Differential Double Balun Input Configuration
301Ω
VCM
165Ω
1nF
20kΩ║2.5pF
68nH
CLOCK INPUT CONSIDERATIONS
VCM
0.1µF
10559-037
S
1nF
ADC
3.9pF
A stable and accurate voltage reference is built into the AD9250.
The full-scale input range can be adjusted by varying the reference
voltage via the SPI. The input span of the ADC tracks the reference
voltage changes linearly.
33Ω
PA
5.1pF
15pF
VOLTAGE REFERENCE
C2
R3
R1
165Ω
VPOS
Figure 42. Differential Input Configuration Using the AD8376
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9250. For applications where
SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 41). In this
configuration, the input is ac-coupled and the VCM voltage is
provided to each input through a 33 Ω resistor. These resistors
compensate for losses in the input baluns to provide a 50 Ω
impedance to the driver.
2V p-p
R3
Shunt
(Ω)
24.9
24.9
24.9
1000pF
NOTES
1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS WITH THE
EXCEPTION OF THE 1µH CHOKE INDUCTORS (COILCRAFT 0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER
CENTERED AT 140MHz.
Consider the signal characteristics when selecting a transformer.
Most RF transformers saturate at frequencies below a few
megahertz. Excessive signal power can also cause core saturation,
which leads to distortion.
0.1µF
C2
Shunt
(pF)
15
8.2
≤3.9
180nH 220nH
Figure 40. Differential Transformer-Coupled Configuration
0.1µF
R2
Series
(Ω)
0
0
0
180nH 220nH
1µH
10559-036
2V p-p
C1
Differential
(pF)
8.2
8.2
≤3.9
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use an amplifier with variable
gain. The AD8375 or AD8376 digital variable gain amplifier
(DVGAs) provides good performance for driving the AD9250.
Figure 42 shows an example of the AD8376 driving the AD9250
through a band-pass antialiasing filter.
C2
R3
R1
Series
(Ω)
33
15
15
10559-038
76.8Ω
VIN
The AD9250 has two options for deriving the input sampling
clock, a differential Nyquist sampling clock input or an RF clock
input (which is internally divided by 4). The clock input is selected
in Register 0x09 and by default is configured for the Nyquist clock
input. For optimum performance, clock the AD9250 Nyquist
sample clock input, CLK+ and CLK−, with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased internally
(see Figure 43) and require no external bias. If the clock inputs
are floated, CLK− is pulled slightly lower than CLK+ to prevent
spurious clocking.
Rev. E | Page 21 of 45
AD9250
Data Sheet
The AD9250 Nyquist clock input supports a differential clock
between 40 MHz to 625 MHz. The clock input structure supports
differential input voltages from 0.3 V to 3.6 V and is therefore
compatible with various logic family inputs, such as CMOS,
LVDS, and LVPECL. A sine wave input is also accepted, but
higher slew rates typically provide optimal performance. Clock
source jitter is a critical parameter that can affect performance, as
described in the Jitter Considerations section. If the inputs are
floated, pull the CLK− pin low to prevent spurious clocking.
The Nyquist clock input pins, CLK+ and CLK−, are internally
biased to 0.9 V and have a typical input impedance of 4 pF in
parallel with 10 kΩ (see Figure 43). The input clock is typically
ac-coupled to CLK+ and CLK−. Some typical clock drive circuits
are presented in Figure 44 through Figure 47 for reference.
AVDD
AD9517-4 device family, AD9518-0 through AD9518-4 device
family, AD9520-0 through AD9520-5 device family, AD9522-0
through AD9522-5 device family, AD9523, AD9524, and
ADCLK905/ADCLK907/ADCLK925
0.1µF
ADC
0.1µF
CLOCK
INPUT
CLK+
AD95xx
0.1µF
CLOCK
INPUT
100Ω
PECL DRIVER
0.1µF
CLK–
50kΩ
240Ω
240Ω
50kΩ
10559-042
Nyquist Clock Input Options
Figure 46. Differential PECL Sample Clock (Up to 625 MHz)
Analog Devices also offers LVDS clock drivers with excellent jitter
performance. A typical circuit is shown in Figure 47 and uses LVDS
drivers such as the AD9510, AD9511, AD9512, AD9513, AD9514,
AD9515, AD9516-0 through AD9516-5 device family, AD9517-0
through AD9517-4 device family, AD9518-0 through AD9518-4
device family, AD9520-0 through AD9520-5 device family,
AD9522-0 through AD9522-5 device family, AD9523, and AD9524.
0.9V
0.1µF
CLK–
AD95xx
0.1µF
50Ω
The AD9250 RF clock input supports a single-ended clock
between 625 GHz to 1.5 GHz. The equivalent RF clock input
circuit is shown in Figure 48. The input is self biased to 0.9 V and
is typically ac-coupled. The input has a typical input impedance
of 10 kΩ in parallel with 1 pF at the RFCLK pin.
1pF
10kΩ
BIAS
CONTROL
ADC
CLK+
Figure 48. Equivalent RF Clock Input Circuit
10559-040
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 44. Transformer-Coupled Differential Clock (Up to 200 MHz)
25Ω
ADC
390pF
CLK+
390pF
1nF
SCHOTTKY
DIODES:
HSMS2822
10559-041
CLK–
25Ω
INTERNAL
CLOCK DRIVER
RFCLK
100Ω
390pF
10559-043
Figure 47. Differential LVDS Sample Clock (Up to 625 MHz)
RF Clock Input Options
390pF
CLOCK
INPUT
50kΩ
Figure 45. Balun-Coupled Differential Clock (Up to 625 MHz)
In some cases, it is desirable to buffer or generate multiple
clocks from a single source. In those cases, Analog Devices, Inc.,
offers clock drivers with excellent jitter performance. Figure 46
shows a typical PECL driver circuit that uses PECL drivers such
as the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515,
AD9516-0 through AD9516-5 device family, AD9517-0 through
It is recommended to drive the RF clock input of the AD9250 with
a PECL or sine wave signal with a minimum signal amplitude of
600 mV peak to peak. Regardless of the type of signal being used,
clock source jitter is of the most concern, as described in the Jitter
Considerations section. Figure 49 shows the preferred method of
clocking when using the RF clock input on the AD9250. It is
recommended to use a 50 Ω transmission line to route the clock
signal to the RF clock input of the AD9250 due to the high
frequency nature of the signal and terminate the transmission
line close to the RF clock input.
Rev. E | Page 22 of 45
ADC
RF CLOCK
INPUT
50Ω Tx LINE
0.1µF
RFCLK
50Ω
10559-045
390pF
0.1µF
CLK–
50kΩ
For applications where a single-ended low jitter clock between
40 MHz to 200 MHz is available, an RF transformer is recommended. An example using an RF transformer in the clock network
is shown in Figure 44. At frequencies above 200 MHz, an RF balun
is recommended, as seen in Figure 45. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions into
the AD9250 to approximately 0.8 V p-p differential. This limit helps
prevent the large voltage swings of the clock from feeding through
to other portions of the AD9250, yet preserves the fast rise and fall
times of the clock, which are critical to low jitter performance.
Mini-Circuits®
ADT1-1WT, 1:1Z
390pF
XFMR
100Ω
LVDS DRIVER
CLOCK
INPUT
Figure 43. Equivalent Nyquist Clock Input Circuit
CLOCK
INPUT
CLK+
4pF
10559-039
4pF
ADC
0.1µF
CLOCK
INPUT
10559-044
CLK+
Figure 49. Typical RF Clock Input Circuit
Data Sheet
AD9250
VDD
127Ω
0.1µF
ADC
127Ω
50Ω Tx LINE
0.1µF
0.1µF
RFCLK
CLOCK INPUT
AD9515
0.1µF
50Ω
LVPECL
DRIVER
0.1µF
CLOCK INPUT
82.5Ω
10559-046
82.5Ω
Figure 50. Differential PECL RF Clock Input Circuit
Figure 50 shows the RF clock input of the AD9250 being driven
from the LVPECL outputs of the AD9515. The differential
LVPECL output signal from the AD9515 is converted to a singleended signal using an RF balun or RF transformer. The RF balun
configuration is recommended for clock frequencies associated
with the RF clock input.
Input Clock Divider
The AD9250 contains an input clock divider with the ability to
divide the Nyquist input clock by integer values between 1 and 8.
The RF clock input uses an on-chip predivider to divide the clock
input by four before it reaches the 1 to 8 divider. This allows
higher input frequencies to be achieved on the RF clock input. The
divide ratios can be selected using Register 0x09 and Register 0x0B.
Register 0x09 is used to set the RF clock input, and Register 0x0B
can be used to set the divide ratio of the 1-to-8 divider for both
the RF clock input and the Nyquist clock input. For divide ratios
other than 1, the duty-cycle stabilizer is automatically enabled.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The duty
cycle control loop does not function for clock rates less than
40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate can change
dynamically. A wait time of 1.5 μs to 5 μs is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time that the
loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input frequency
(fIN) due to jitter (tJ) can be calculated by
SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 (  SNR LF /10 ) ]
÷4
NYQUIST
CLOCK
Figure 51. AD9250 Clock Divider Circuit
The AD9250 clock divider can be synchronized using the external
SYSREF input. Bit 1 and Bit 2 of Register 0x3A allow the clock
divider to be resynchronized on every SYSREF signal or only on
the first signal after the register is written. A valid SYSREF causes
the clock divider to reset to its initial state. This synchronization
feature allows multiple parts to have their clock dividers aligned to
guarantee simultaneous input sampling.
Clock Duty Cycle
In the equation, the rms aperture jitter represents the root-meansquare of all jitter sources, which include the clock input, the
analog input signal, and the ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter,
as shown in Figure 52.
80
75
70
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9250 contains a DCS that retimes the nonsampling (falling)
edge, providing an internal clock signal with a nominal 50% duty
cycle. This allows the user to provide a wide range of clock input
duty cycles without affecting the performance of the AD9250.
Rev. E | Page 23 of 45
65
60
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
55
50
1
10
100
INPUT FREQUENCY (MHz)
1000
Figure 52. AD9250-250 SNR vs. Input Frequency and Jitter
10559-048
10559-047
÷1 TO ÷8
DIVIDER
SNR (dBc)
RFCLK
AD9250
Data Sheet
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9250. Separate the
power supplies for the clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter, crystal controlled oscillators make the best clock
sources. If the clock is generated from another type of source (by
gating, dividing, or another method), retime it by the original
clock at the last step.
Refer to the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance and the AN-756 Application Note,
Sampled Systems and the Effects of Clock Phase Noise and Jitter for
more information about jitter performance as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 53, the power dissipated by the AD9250 is
proportional to its sample rate. The data in Figure 53 was taken
using the same operating conditions as those used for the Typical
Performance Characteristics section.
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9250 is placed in power-down mode.
In this state, the ADC typically dissipates about 9 mW. Asserting the
PDWN pin low returns the AD9250 to its normal operating mode.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section and the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI, for additional details.
0.8
0.7
TOTAL POWER
0.5
POWER (AVDD)
0.4
0.3
POWER (DVDD)
0.2
0.1
0
40
90
140
190
ENCODE FREQUENCY (MSPS)
240
10559-149
TOTAL POWER (W)
0.6
Figure 53. AD9250-250 Power vs. Encode Rate
Rev. E | Page 24 of 45
Data Sheet
AD9250
DIGITAL OUTPUTS
JESD204B TRANSMIT TOP LEVEL DESCRIPTION
The AD9250 digital output uses the JEDEC Standard No.
JESD204B, Serial Interface for Data Converters. JESD204B is a
protocol to link the AD9250 to a digital processing device over a
serial interface of up to 5 Gbps link speeds (3.5 Gbps, 14-bit
ADC data rate). The benefits of the JESD204B interface include
a reduction in required board area for data interface routing
and the enabling of smaller packages for converter and logic
devices. The AD9250 supports single or dual lane interfaces.
JESD204B OVERVIEW
The JESD204B data transmit block assembles the parallel data from
the ADC into frames and uses 8b/10b encoding as well as optional
scrambling to form serial output data. Lane synchronization is
supported using special characters during the initial establishment
of the link, and additional synchronization is embedded in the
data stream thereafter. A matching external receiver is required
to lock onto the serial data stream and recover the data and clock.
For additional details on the JESD204B interface, refer to the
JESD204B standard.
The AD9250 JESD204B transmit block maps the output of the
two ADCs over a link. A link can be configured to use either
single or dual serial differential outputs that are called lanes.
The JESD204B specification refers to a number of parameters to
define the link, and these parameters must match between the
JESD204B transmitter (AD9250 output) and receiver.
The JESD204B link is described according to the following
parameters:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
S = samples transmitted/single converter/frame cycle
(AD9250 value = 1)
M = number of converters/converter device
(AD9250 value = 2 by default, or can be set to 1)
L = number of lanes/converter device
(AD9250 value = 1 or 2)
N = converter resolution (AD9250 value = 14)
N’ = total number of bits per sample (AD9250 value = 16)
CF = number of control words/frame clock cycle/converter
device (AD9250 value = 0)
CS = number of control bits/conversion sample
(configurable on the AD9250 up to 2 bits)
K = number of frames per multiframe (configurable on
the AD9250)
HD = high density mode (AD9250 value = 0)
F = octets/frame (AD9250 value = 2 or 4, dependent upon
L = 2 or 1)
C = control bit (overrange, overflow, underflow; available
on the AD9250)
T = tail bit (available on the AD9250)
SCR = scrambler enable/disable (configurable on the AD9250)
FCHK = checksum for the JESD204B parameters
(automatically calculated and stored in register map)
Figure 54 shows a simplified block diagram of the AD9250
JESD204B link. By default, the AD9250 is configured to use
two converters and two lanes. Converter A data is output to
SERDOUT0+/SERDOUT0−, and Converter B is output to
SERDOUT1+/SERDOUT1−. The AD9250 allows for other
configurations such as combining the outputs of both converters
onto a single lane or changing the mapping of the A and B
digital output paths. These modes are setup through a quick
configuration register in the SPI register map, along with
additional customizable options.
By default in the AD9250, the 14-bit converter word from each
converter is broken into two octets (8 bits of data). Bit 13 (MSB)
through Bit 6 are in the first octet. The second octet contains
Bit 5 through Bit 0 (LSB), and two tail bits are added to fill the
second octet. The tail bits can be configured as zeros, pseudorandom number sequence or control bits indicating overrange,
underrange, or valid data conditions.
The two resulting octets can be scrambled. Scrambling is
optional; however, it is available to avoid spectral peaks when
transmitting similar digital data patterns. The scrambler uses a
self synchronizing, polynomial-based algorithm defined by the
equation 1 + x14 + x15. The descrambler in the receiver should be
a self-synchronizing version of the scrambler polynomial.
The two octets are then encoded with an 8b/10b encoder. The
8b/10b encoder works by taking eight bits of data (an octet) and
encoding them into a 10-bit symbol. Figure 55 shows how the
14-bit data is taken from the ADC, the tail bits are added, the two
octets are scrambled, and how the octets are encoded into two
10-bit symbols. Figure 55 illustrates the default data format.
At the data link layer, in addition to the 8b/10b encoding, the
character replacement is used to allow the receiver to monitor
frame alignment. The character replacement process occurs on the
frame and multiframe boundaries, and implementation depends
on which boundary is occurring, and if scrambling is enabled.
If scrambling is disabled, the following applies. If the last scrambled
octet of the last frame of the multiframe equals the last octet of
the previous frame, the transmitter replaces the last octet with
the control character /A/ = /K28.3/. On other frames within the
multiframe, if the last octet in the frame equals the last octet of
the previous frame, the transmitter replaces the last octet with
the control character /F/= /K28.7/.
If scrambling is enabled, the following applies. If the last octet of
the last frame of the multiframe equals 0x7C, the transmitter
replaces the last octet with the control character /A/ = /K28.3/.
On other frames within the multiframe, if the last octet equals
0xFC, the transmitter replaces the last octet with the control
character /F/ = /K28.7/.
Refer to JEDEC Standard No. 204B-July 2011 for additional
information about the JESD204B interface. Section 5.1 covers
the transport layer and data format details and Section 5.2
covers scrambling and descrambling.
Rev. E | Page 25 of 45
AD9250
Data Sheet
JESD204B SYNCHRONIZATION DETAILS
Data Transmission Phase
The AD9250 supports JESD204B Subclass 0 and Subclass 1 and
establishes synchronization of the link through one or two
control signals, SYNC and Subclass 1 also use SYSREF, and a
common device clock. SYSREF and SYNC are common to all
converter devices for alignment purposes at the system level.
In the data transmission phase, frame alignment is monitored
with control characters. Character replacement is used at the
end of frames. Character replacement in the transmitter occurs
in the following instances:
The synchronization process is accomplished over three phases:
code group synchronization (CGS), initial lane alignment
sequence (ILAS), and data transmission. If scrambling is
enabled, scrambling begins with the first data byte following
the last alignment character of the ILAS. CGS and ILAS
phases are not scrambled.
CGS Phase
In the CGS phase, the JESD204B transmit block transmits
/K28.5/ characters. The receiver (external logic device) must
locate K28.5 characters in its input data stream using clock
and data recovery (CDR) techniques.
When in Subclass 1 mode, the receiver locks onto the K28.5
characters. Once detected, the receiver initiates a SYSREF edge
so that the AD9250 transmit data establishes a local multiframe
clock (LMFC) internally.
The SYSREF edge also resets any sampling edges within the
ADC to align sampling instances to the LMFC. This is important
to maintain synchronization across multiple devices.
If Subclass 0: at the next receiver’s internal clock; if Subclass 1: at
the next receiver’s LMFC boundary, the receiver or logic device
de-asserts the SYNC~ signal (SYNCINB± goes high), and the
transmitter block begins the ILAS phase.
ILAS Phase
In the ILAS phase, the transmitter sends out a known pattern,
and the receiver aligns all lanes of the link and verifies the
parameters of the link.
The ILAS phase begins after SYNC~ has been de-asserted
(goes high). If Subclass 0: the transmitter begins ILAS at the
next transmitter’s internal clock; if Subclass 1: at the next
transmitter’s internal LMFC boundary, the transmit block
begins to transmit four multiframes. Dummy samples are
inserted between the required characters so that full
multiframes are transmitted. The four multiframes include
the following:
•
•
•
•
•
•
If scrambling is disabled and the last octet of the frame or
multiframe equals the octet value of the previous frame.
If scrambling is enabled and the last octet of the multiframe is
equal to 0x7C, or the last octet of a frame is equal to 0xFC.
Table 10. Fourteen Configuration Octets of the ILAS Phase
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4 Bit 3
DID[7:0]
Bit 2
Bit 1
Bit 0
(LSB)
BID[3:0]
LID[4:0]
L[4:0]
SCR
F[7:0]
K[4:0]
M[7:0]
CS[1:0]
SUBCLASS[2:0]
JESDV[2:0]
HD
N[4:0]
N’[4:0]
S[4:0]
CF[4:0]
Reserved, Don’t Care
Reserved, Don’t Care
FCHK[7:0]
LINK SETUP PARAMETERS
The following demonstrates how to configure the AD9250
JESD204B interface paremeters. These details are a subset of the
SPI initialization sequence shown in Figure 63 and Table 19.
The steps to configure the output include the following:
1.
2.
3.
4.
5.
6.
Disable lanes before changing the configuration.
Select the quick configuration option.
Configure the detailed options.
Check FCHK, checksum of JESD204B interface parameters.
Set the additional digital output configuration options.
Re-enable lane(s).
Disable Lanes Before Changing Configuration
Multiframe 1: Begins with an /R/ character [K28.0] and
ends with an /A/ character [K28.3].
Multiframe 2: Begins with an /R/ character followed by a /Q/
[K28.4] character, followed by link configuration parameters
over 14 configuration octets (see Table 10), and ends with
an /A/ character. Many of the parameters values are of the
notation of the value − 1.
Multiframe 3: Is the same as Multiframe 1.
Multiframe 4: Is the same as Multiframe 1.
Before modifying the JESD204B link parameters, disable the link
and hold it in reset. This is accomplished by writing Logic 1 to
Register 0x5F, Bit 0.
Select Quick Configuration Option
Write to Register 0x5E, the 204B quick configuration register to
select the configuration options. See Table 13 for configuration
options and resulting JESD204B parameter values.
•
•
•
•
Rev. E | Page 26 of 45
0x11 = one converter, one lane
0x12 = one converter, two lanes
0x21 = two converters, one lane
0x22 = two converters, two lanes
Data Sheet
AD9250
Configure Detailed Options
Select lane synchronization options.
Configure the tail bits and control bits.
Most of the synchronization features of the JESD204B interface
are enabled by default for typical applications. In some cases,
these features can be disabled or modified as follows:
•
•
•
With N’ = 16 and N = 14, there are two bits available per
sample for transmitting additional information over the
JESD204B link. The options are tail bits or control bits. By
default, tail bits of 0b00 value are used.
Tail bits are dummy bits sent over the link to complete the
two octets and do not convey any information about the input
signal. Tail bits can be fixed zeros (default) or psuedo
random numbers (Register 0x5F, Bit 6).
One or two control bits can be used instead of the tail bits
through Register 0x72, Bits[7:6]. The tail bits can be set
using Register 0x14, Bits[7:5], and can be enabled using
Address 0x5F, Bit 6.
Set lane identification values.
•
JESD204B allows parameters to identify the device and
lane. These parameters are transmitted during the ILAS
phase, and they are accessible in the internal registers.
There are three identification values: device identification
(DID), bank identification (BID), and lane identification
(LID). DID and BID are device specific; therefore, they can
be used for link identification.
•
ILAS enabling is controlled in Register 0x5F, Bits[3:2] and
by default is enabled. Optionally, to support some unique
instances of the interfaces (such as NMCDA-SL), the
JESD204B interface can be programmed to either disable
the ILAS sequence or continually repeat the ILAS sequence.
The AD9250 has fixed values of some of the JESD204B interface
parameters, and they are as follows:
•
•
•
[N] = 14: number of bits per converter is 14, in Register 0x72,
Bits[4:0]; Register 0x72 represents a value of N − 1.
[N’] = 16: number of bits per sample is 16, in Register 0x73,
Bits[4:0]; Register 0x73 represents a value of N’ − 1.
[CF] = 0: number of control words/ frame clock
cycle/converter is 0, in Register 0x75, Bits[4:0].
Set number of frames per multiframe, K
Verify read only values: lanes per link (L), octets per frame (F),
number of converters (M), and samples per converter per frame
(S). The AD9250 calculates values for some JESD204B parameters
based on other settings, particularly the quick configuration
register selection. The read only values here are available in the
register map for verification.
•
•
•
•
Per the JESD204B specification, a multiframe is defined as a
group of K successive frames, where K is between 1 and 32,
and it requires that the number of octets be between 17 and
1024. The K value is set to 32 by default in Register 0x70,
Bits[7:0]. Note that Register 0x70 represents a value of K − 1.
The K value can be changed; however, it must comply with
a few conditions. The AD9250 uses a fixed value for octets
per frame [F] based on the JESD204B quick configuration
setting. K must also be a multiple of 4 and conform to the
following equation.
32 ≥ K ≥ Ceil (17/F)
•
Table 11. JESD204B Configurable Identification Values
Register, Bits
0x66, [4:0]
0x67, [4:0]
0x64, [7:0]
0x65, [3:0]
Value Range
0…31
0…31
0…255
0…15
Scramble, SCR.
•
•
•
•
Check FCHK, Checksum of JESD204B Interface Parameters
The JESD204B specification also calls for the number of
octets per multiframe (K × F) to be between 17 and 1024.
The F value is fixed through the quick configuration
setting to ensure this relationship is true.
DID Value
LID (Lane 0)
LID (Lane 1)
DID
BID
•
[L] = lanes per link can be 1 or 2, read the values from
Register 0x6E, Bit 0
[F] = octets per frame can be 1, 2, or 4, read the value from
Register 0x6F, Bits[7:0]
[HD] = high density mode can be 0 or 1, read the value
from Register 0x75, Bit 7
[M] = number of converters per link can be 1 or 2, read the
value from Register 0x71, Bits[7:0]
[S] = samples per converter per frame can be 1 or 2, read
the value from Register 0x74, Bits[4:0]
Scrambling can be enabled or disabled by setting Register 0x6E,
Bit 7. By default, scrambling is enabled. Per the JESD204B
protocol, scrambling is only functional after the lane
synchronization has completed.
The JESD204B parameters can be verified through the checksum
value [FCHK] of the JESD204B interface parameters. Each lane has
a FCHK value associated with it. The FCHK value is transmitted
during the ILAS second multiframe and can be read from the
internal registers.
The checksum value is the modulo 256 sum of the parameters
listed in the No. column of Table 12. The checksum is calculated
by adding the parameter fields before they are packed into the
octets shown in Table 12.
The FCHK for the lane configuration for data coming out of
Lane 0 can be read from Register 0x78. Similarly, the FCHK for
the lane configuration for data coming out of Lane 1 can be read
from Register 0x79.
Rev. E | Page 27 of 45
AD9250
Data Sheet
Re-Enable Lanes After Configuration
Table 12. JESD204B Configuration Table Used in ILAS and
CHKSUM Calculation
No.
0
1
2
3
4
5
6
7
8
9
10
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4 Bit 3
DID[7:0]
Bit 2
Bit 1
After modifying the JESD204B link parameters, enable the link so
that the synchronization process can begin. This is accomplished
by writing Logic 0 to Register 0x5F, Bit 0.
Bit 0
(LSB)
Internal FIFO Timing Optimization
BID[3:0]
LID[4:0]
L[4:0]
SCR
Each lane of the of the AD9250 JESD204B digital path includes
an internal FIFO situated between the framer and serializer,
which operate from two different clock domains, the ADC
sample clock and JESD204B PLL domains. To optimize the
write and read pointers against possible FIFO overflow (or
underflow) under extreme temperature changes and inconsistent
power-up conditions, additional steps are required to increase the
timing margin. The procedures described in Step 15 of Table 19
adjust the write clock phase (via Register 0xEE and Register
0xEF) with respect to the read clock to optimize the timing
margin.
F[7:0]
K[4:0]
M[7:0]
CS[1:0]
SUBCLASS[2:0]
JESDV[2:0]
N[4:0]
N’[4:0]
S[4:0]
CF[4:0]
Additional Digital Output Configuration Options
Other data format controls include the following:




Invert polarity of serial output data: Register 0x60, Bit 1.
ADC data format (offset binary or twos complement):
Register 0x14, Bits[1:0].
Options for interpreting single on SYSREF± and SYNCINB±:
Register 0x3A. See Table 14 for additional descriptions of
Register 0x3A controls.
Option to remap converter and lane assignments, Register 0x82
and Register 0x83. See Figure 54 for simplified block diagram.
AD9250 DUAL ADC
CONVERTER A
INPUT
CONVERTER A
CONVERTER A
SAMPLE
A
PRIMARY CONVERTER
INPUT [0]
PRIMARY LANE
OUTPUT [0]
SERDOUT0
LANE 0
JESD204B LANE CONTROL
(M = 1, 2; L = 1, 2)
B
SECONDARY CONVERTER
INPUT [1]
SECONDARY LANE
OUTPUT [1]
LANE 1
LANE MUX
(SPI REGISTER
MAPPING: 0x82,0x83)
A
CONVERTER B
INPUT
SECONDARY CONVERTER
INPUT [1]
SECONDARY LANE
OUTPUT [1]
LANE 1
JESD204B LANE CONTROL
(M = 1, 2; L = 1, 2)
CONVERTER B
CONVERTER B
SAMPLE
B
PRIMARY CONVERTER
INPUT [0]
PRIMARY LANE
OUTPUT [0]
LANE 0
10559-049
SYSREF
SERDOUT1
SYNCINB
Figure 54. AD9250 Transmit Link Simplified Block Diagram
Rev. E | Page 28 of 45
Data Sheet
VINA–
A PATH
(LSB)
JESD204B
TEST PATTERN
10-BIT
8B/10B
ENCODER/
CHARACTER
REPLACEMENT
OPTIONAL
SCRAMBLER
1 + x14 + x15
A6
A7
A8
A9
A10
A11
A12
A13
C0
C1
A0
A1
A2
A3
A4
A5
S8
S9
S10
S11
S12
S13
S14
S15
S0
S1
S2
S3
S4
S5
S6
S7
SERIALIZER
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
SERDOUT±
E19 . . . E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
~SYNC
t
SYSREF
10559-050
ADC
JESD204B
TEST PATTERN
8-BIT
OCTET1
VINA+
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ADC
TEST PATTERN
16-BIT
OCTET0
(MSB)
AD9250
Figure 55. AD9250 Digital Processing of JESD204B Lanes
Table 13. AD9250 JESD204B Typical Configurations
M (No. of Converters),
Register 0x71,
Bits[7:0]
1
1
2
2
DATA
FROM
ADC
L (No. of Lanes),
Register 0x6E,
Bit 0
1
2
1
2
FRAME
ASSEMBLER
(ADD TAIL BITS)
F (Octets/Frame),
Register 0x6F,
Bits[7:0], Read Only
2
1
4
2
OPTIONAL
SCRAMBLER
1 + x14 + x15
S (Samples/ADC/Frame),
Register 0x74, Bits[4:0],
Read Only
1
1
1
1
8B/10B
ENCODER
Figure 56. AD9250 ADC Output Data Path
Rev. E | Page 29 of 45
TO
RECEIVER
HD (High Density Mode),
Register 0x75, Bit 7,
Read Only
0
1
0
0
10559-052
JESD204B
Configure
Setting
0x11
0x12
0x21
0x22 (Default)
AD9250
Data Sheet
Table 14. AD9250 JESD204B Configuration, Register 0x3A
Bit No.
0
Register Description
Enable internal
SYSREF buffer
1
SYSREF± enable
2
SYSREF± mode
3
Realign on SYSREF;
forSubclass 1 only
4
Realign on SYNCB;
for Subclass 1 only
Functional Description
This bit controls the on-chip buffer for the SYSREF singal. By default, this bit is 0, which disables the buffer. If the
AD9250 is configured for JESD204B Subclass 1 operation, SYSREF is required to align the JESD204B link and this
bit must be set to 1.
To avoid a false trigger as a result of transients caused when enabling the buffer (particularly for one-shot SYSREF
configuration), set this bit first and then in a consecutive SPI register write, configure all remaining bits in Register 0x3A
to the desired JESD204B link configuration, including keeping this bit at 1.
A setting of 0 (default) gates the SYSREF signal such that the internal logic is not affected by an external SYSREF.
Set this bit to 0 when in Subclass 0, that is, when SYSREF is not used.
If using Subclass 1 with one-shot SYSREF mode, enable the buffer while the SYSREF is established, but then
disable it during normal operation.
If using Subclass 1 with continuous SYSREF mode, the buffer must remain enabled for normal operation.
This bit enables the circuitry that uses the SYSREF input signal and must be on to enable Subclass 1 operation.
Set this bit to 1 when using JESD204B Subclass 1 operation.
This bit is self clearing after a valid SYSREF occurs when SYSREF± mode (Register 0x3A, Bit 2) is set to 1
(configured for one-shot SYSREF operation).
Note that SYSREF is still used in some digital circuitry even if this bit is 0; to disable the SYSREF signal internally,
Register 0x3A Bit 0 must be set to 0.
This bit is used in Subclass 1 operation to define one shot or continuous SYSREF mode. To configure continuous
(or gapped periodic) SYSREF, this bit is set to 0. For one-shot operation, this bit is set to 1. In one-shot mode, it is
recommended that the SYSREF buffer be disabled after SYSREF has occurred by setting Register 0x3A, Bit 0 to 0.
When this bit is set to 1, the internal clock alignment for the JESD204B timing is forced when an active SYSREF
occurs. This is recommended only for one-shot mode and must only be done prior to initially establishing a link. This
resets the JESD204B link on active SYSREF.
For continuous SYSREF mode, this bit must be set to 0 during normal operation.
When this bit is set to 1, the internal clock alignment for the JESD204B timing is forced when an active SYNC
occurs. An active SYNC requires the SYNCINB input to be logic low for at least four consecutive LMFCs.
Table 15. AD9250 JESD204B Frame Alignment Monitoring and Correction Replacement Characters
Scrambling
Off
Off
Off
On
On
On
Lane Synchronization
On
On
Off
On
On
Off
Character to be Replaced
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame equals D28.7
Last octet in frame equals D28.3
Last octet in frame equals D28.7
Last Octet in Multiframe
No
Yes
Not applicable
No
Yes
Not applicable
Replacement Character
K28.7
K28.3
K28.7
K28.7
K28.3
K28.7
FRAME AND LANE ALIGNMENT MONITORING
AND CORRECTION
each output equal to a nominal 4 mA. Each output presents a 100 Ω
dynamic internal termination to reduce unwanted reflections.
Frame alignment monitoring and correction is part of the JESD204B
specification. The 14-bit word requires two octets to transmit all
the data. The two octets (MSB and LSB), where F = 2, make up
a frame. During normal operating conditions, frame alignment
is monitored via alignment characters, which are inserted under
certain conditions at the end of a frame. Table 15 summarizes the
conditions for character insertion along with the expected characters
under the various operation modes. If lane synchronization is
enabled, the replacement character value depends on whether
the octet is at the end of a frame or at the end of a multiframe.
Place a 100 Ω differential termination resistor at each receiver input
to result in a nominal 300 mV peak-to-peak swing at the receiver
(see Figure 57). Alternatively, single-ended 50 Ω termination
can be used. When single-ended termination is used, the
termination voltage should be DRVDD/2; otherwise, ac coupling
capacitors can be used to terminate to any single-ended voltage.
DRVDD
100Ω
DIFFERENTIAL
0.1µF TRACE PAIR
SERDOUTx+
100Ω
The AD9250 has differential digital outputs that power up by default.
The driver current is derived on-chip and sets the output current at
Rev. E | Page 30 of 45
RECEIVER
0.1µF
OUTPUT SWING = VOD
(SEE TABLE 3)
DIGITAL OUTPUTS AND TIMING
OR
SERDOUTx–
VCM = Rx VCM
Figure 57. AC-Coupled Digital Output Termination Example
10559-053
Based on the operating mode, the receiver can ensure that it is
still synchronized to the frame boundary by correctly receiving
the replacement characters.
VRXCM
Data Sheet
AD9250
The AD9250 digital outputs can interface with custom ASICs and
FPGA receivers, providing superior switching performance in
noisy environments. Single point-to-point network topologies are
recommended with a single differential 100 Ω termination resistor
placed as close to the receiver logic as possible. The common mode
of the digital output automatically biases itself to half the supply
of the receiver (that is, the common-mode voltage is 0.9 V for a
receiver supply of 1.8 V) if dc-coupled connecting is used (see
Figure 58). For receiver logic that is not within the bounds of
the DRVDD supply, use an ac-coupled connection. Simply place
a 0.1 µF capacitor on each output pin and derive a 100 Ω
differential termination close to the receiver side.
If there is no far-end receiver termination, or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches, and that the differential output traces be
close together and at equal lengths.
Figure 59 shows an example of the digital output (default) data eye
and time interval error (TIE) jitter histogram and bathtub curve
for the AD9250 lane running at 5 Gbps.
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs to drive longer
trace lengths (see Register 0x15 in Table 18). The power
dissipation of the DRVDD supply increases when this option is
used. See the Memory Map section for more details.
100Ω
DIFFERENTIAL
TRACE PAIR
DRVDD
The format of the output data is twos complement by default.
To change the output data format to offset binary, see the
Memory Map section (Register 0x14 in Table 18).
SERDOUTx+
100Ω
RECEIVER
OUTPUT SWING = VOD
(SEE TABLE 3)
VCM = DRVDD/2
10559-054
SERDOUTx–
Figure 58. DC-Coupled Digital Output Termination Example
HEIGHT1: EYE DIAGRAM
400
1
3
–
6000
200
–
1–2
1–4
5000
100
4000
BER
HITS
1–6
0
1–8
3000
–100
1–10
2000
–300
1–12
1000
EYE: TRANSITION BITS OFFSET: –0.0072
UIs: 8000; 999992 TOTAL: 8000.999992
–200
–100
0
TIME (ps)
100
0
200
1–14
–10
0
TIME (ps)
1–16
–0.5
10
0.78 UI
0
UIs
10559-056
–200
–400
TJ@BER1: BATHTUB
2
–
300
VOLTAGE (mV)
PERIOD1: HISTOGRAM
7000
1
0.5
Figure 59. AD9250 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 5 Gbps
HEIGHT1: EYE DIAGRAM
400
–
300
1
3
–
1–4
3000
1–6
2500
BER
HITS
0
–
1–2
3500
100
TJ@BER1: BATHTUB
2
4000
200
2000
–100
1–8
1–10
1500
–200
1–12
1000
–300
1–14
500
EYE: TRANSITION BITS OFFSET: 0
–400 UIs: 8000; 679999 TOTAL: 8000; 679999
0
–250
–150
–50 0 50
TIME (ps)
150
250
–10
0
TIME (ps)
10
1–16
–0.5
0.84 UI
0
UIs
Figure 60. AD9250 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 3.4 Gbps
Rev. E | Page 31 of 45
0.5
10559-156
VOLTAGE (mV)
PERIOD1: HISTOGRAM
4500
1
AD9250
Data Sheet
ADC OVERRANGE AND GAIN CONTROL
Fast Threshold Detection (FDA and FDB)
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides delayed information on
the state of the analog input that is of limited value in preventing
clipping. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce the gain
before the clip occurs. In addition, because input signals can
have significant slew rates, latency of this function is of concern.
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located in Register 0x47 and Register 0x48. The selected threshold
register is compared with the signal magnitude at the output of
the ADC. The fast upper threshold detection has a latency of
7 clock cycles. The approximate upper threshold magnitude is
defined by
Upper Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/213)
Using the SPI port, the user can provide a threshold above which
the FD output is active. Bit 0 of Register 0x45 enables the fast
detect feature. Register 0x47 to Register 0x4A allow the user to
set the threshold levels. As long as the signal is below the selected
threshold, the FD output remains low. In this mode, the magnitude
of the data is considered in the calculation of the condition, but
the sign of the data is not considered. The threshold detection
responds identically to positive and negative signals outside the
desired range (magnitude).
Or, alternatively, the register value can be calculated by the
target threshold using the following equation:
Value = 10(Threshold Magnitude [dBFS]/20) × 213
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Register 0x49 and Register 0x4A. The fast
detect lower threshold register is a 13-bit register that is compared
with the signal magnitude at the output of the ADC. This
comparison is subject to the ADC pipeline latency but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 36 ADC clock cycles. An overrange at the
input is indicated by this bit 36 clock cycles after it occurs.
Lower Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/213)
GAIN SWITCHING
For example, to set an upper threshold of −6 dBFS, write
0x0FFF to those registers; and to set a lower threshold of
−10 dBFS, write 0x0A1D to those registers.
The AD9250 includes circuitry that is useful in applications
either where large dynamic ranges exist, or where gain ranging
amplifiers are employed. This circuitry allows digital thresholds
to be set such that an upper threshold and a lower threshold can
be programmed.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located in Register 0x4B and Register 0x4C.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
The operation of the upper threshold and lower threshold registers,
along with the dwell time registers, is shown in Figure 61.
UPPER THRESHOLD
DWELL TIME
LOWER THRESHOLD
DWELL TIME
FDA OR FDB
Figure 61. Threshold Settings for FDA and FDB Signals
Rev. E | Page 32 of 45
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE LT
10559-057
MIDSCALE
TIMER RESET BY
RISE ABOVE LT
Data Sheet
AD9250
DC CORRECTION
Because the dc offset of the ADC may be significantly larger than
the signal being measured, a dc correction circuit is included to
null the dc offset before measuring the power. The dc correction
circuit can also be switched into the main signal path; however,
this may not be appropriate if the ADC is digitizing a time-varying
signal with significant dc content, such as GSM.
DC CORRECTION READBACK
DC CORRECTION BANDWIDTH
Setting Bit 6 of Register 0x40 freezes the dc correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
The dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.29 Hz and 2.387 kHz
at 245.76 MSPS). The bandwidth is controlled by writing to
the 4-bit dc correction bandwidth select register, located at
Register 0x40, Bits[5:2]. The following equation can be used
to compute the bandwidth value for the dc correction circuit:
The current dc correction value can be read back in Register 0x41
and Register 0x42 for each channel. The dc correction value is a
16-bit value that can span the entire input range of the ADC.
DC CORRECTION FREEZE
DC CORRECTION (DCC) ENABLE BITS
Setting Bit 1 of Register 0x40 enables dc correction for use in
the output data signal path.
DC_Corr_BW = 2−k−14 × fCLK/(2 × π)
where:
k is the 4-bit value programmed in Bits[5:2] of Register 0x40
(values between 0 and 13 are valid for k).
fCLK is the AD9250 ADC sample rate in hertz.
Rev. E | Page 33 of 45
AD9250
Data Sheet
SERIAL PORT INTERFACE (SPI)
The AD9250 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields. These fields are documented
in the Memory Map section. For detailed operational information,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CS pin (see Table 16). The SCLK (serial clock) pin is
used to synchronize the read and write data presented from/to the
ADC. The SDIO (serial data input/output) pin is a dual-purpose
pin that allows data to be sent and read from the internal ADC
memory map registers. The CS (chip select bar) pin is an active low
control that enables or disables the read and write cycles.
Table 16. Serial Port Interface Pins
Pin
SCLK
SDIO
CS
Function
Serial Clock. The serial shift clock input, which is used to
synchronize serial interface, reads and writes.
Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip Select Bar. An active low control that gates the read
and write cycles.
The falling edge of CS, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 62 and
Table 5.
Other modes involving the CS are available. The CS can be held
low indefinitely, which permanently enables the device; this is
called streaming. The CS can stall high between bytes to allow for
additional external timing. When CS is tied high, SPI functions
are placed in a high impedance mode. This mode turns on any
SPI pin secondary functions.
All data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether a read or write command is
issued. This allows the SDIO pin to change direction from an
input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the SDIO pin to change
direction from an input to an output at the appropriate point in
the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 16 comprise the physical interface
between the user programming device and the serial port of the
AD9250. The SCLK pin and the CS pin function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
Do not activate the SPI port during periods when the full dynamic
performance of the converter is required. Because the SCLK signal,
the CS signal, and the SDIO signal are typically asynchronous to
the ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9250 to prevent these signals from transitioning at the
converter inputs during critical sampling periods.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and the W1 bits.
Rev. E | Page 34 of 45
Data Sheet
AD9250
SPI ACCESSIBLE FEATURES
Table 17 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9250 part-specific features are described in the
Memory Map Register Description section.
Table 17. Features Accessible Using the SPI
Feature Name
Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
Description
Allows the user to set either power-down mode or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the converter offset
Allows the user to set test modes to have known data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
tDS
tS
tHIGH
tCLK
tDH
tH
tLOW
CS
SDIO DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 62. Serial Port Interface Timing Diagram
Rev. E | Page 35 of 45
D4
D3
D2
D1
D0
DON’T CARE
10559-058
DON’T CARE
SCLK DON’T CARE
AD9250
Data Sheet
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Logic Levels
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into three sections: the
chip configuration registers (Address 0x00 to Address 0x02);
the channel index and transfer registers (Address 0x05 and
Address 0xFF); and the ADC functions registers, including
setup, control, and test (Address 0x08 to Address 0xA8).
An explanation of logic level terminology follows:
The memory map register table (see Table 18) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the
default hexadecimal value given. For example, Address 0x14,
the output mode register, has a hexadecimal default value of
0x01. This means that Bit 0 = 1, and the remaining bits are 0s.
This setting is the default output format value, which is twos
complement. For more information on this function and others,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI. This document details the functions controlled
by Register 0x00 to Register 0x25. The remaining registers,
Register 0x3A and Register 0x59, are documented in the
Memory Map Register Description section.
Open and Reserved Locations
All address and bit locations that are not included in Table 18
are not currently supported for this device. Unused bits of a valid
address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), do not write to this
address location.
Default Values
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Channel-Specific Registers
Some channel setup functions, such as dc offset adjust or ouput
data format, can be programmed to a different value for each
channel. In these cases, channel address locations are internally
duplicated or shadowed for each channel. These registers and bits
are designated as local in Table 18. Note that all other listed
registers are considered as global; write operations to these
registers affect the entire device upon completion of the write
operation.
Local registers and bits can be accessed by setting the appropriate
Channel A or Channel B bits in Register 0x05. If both bits are
set, the subsequent write affects the registers of both channels.
In a read cycle, set only Channel A or Channel B to read one of
the two registers. If both bits are set during an SPI read cycle,
the device returns the value for Channel A.
To write to a specific channel, the following three steps must
occur:
1.
2.
3.
After the AD9250 is reset, critical registers are loaded with
default values. The default values for the registers are given
in the memory map register table, Table 18.
Rev. E | Page 36 of 45
Select the desired channel(s) for SPI write operation via
Register 0x05.
Perform the specific write operation to desired local SPI
register.
Transfer of the write operation contents to the target local
register occurs by setting the self clearing transfer bit of
Register 0xFF. Writing 0x01 allows the target local channel
register(s) to be updated internally and simultaneously
when the transfer bit is set. The internal update takes place
when the transfer bit is set and then the bit automatically
clears.
Data Sheet
AD9250
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 18 are not currently supported for this device.
Table 18. Memory Map Registers
Reg
Addr
(Hex)
0x00
0x01
Register
Name
Global SPI
config
CHIP ID
Bit 7
(MSB)
0
0x02
Chip info
0x05
Channel
index
0x08
PDWN
modes
0x09
Global clock
(local)
Reserved
0x0A
PLL status
PLL locked
status
0x0B
Global clock
divider
(local)
0x0D
Test control
reg
(local)
Bit 6
LSB first
Bit 5
Soft reset
Bit 4
1
Bit 3
1
Bit 2
Soft reset
Bit 1
LSB first
Bit 0 (LSB)
0
AD9250 8-bit chip ID is 0xB9
Reserved for chip die revision currently
0x0
Speed grade
00 = 250 MSPS
11 = 170 MSPS
External
PDWN
mode;
0=
PDWN is
full
power
down;
1=
PDWN
puts
device in
standby
User test mode cycle;
00 = repeat pattern
(user pattern 1, 2, 3, 4, 1,
2, 3, 4, 1, …);
10 = single pattern (user
pattern 1, 2, 3, 4, then all
zeros)
JTX in
standby;
0=
JESD204B
core is
unaffected
in standby;
1=
JESD204B
core is
powered
down
except for
PLL during
standby
JESD204B power modes;
00 = normal mode
(power up);
01 = power-down
mode: PLL off, serializer
off, clocks stopped,
digital held in reset;
10 = standby mode: PLL
on, serializer off, clocks
stopped, digital held in
reset
Clock selection:
00 = Nyquist clock
10 = RF clock divide by 4
11 = clock off
SPI write to
SPI write
ADC A path
to ADC B
path
Chip power modes;
00 = normal mode
(power up);
01 = power-down mode,
digital datapath clocks
disabled, digital
datapath held in reset;
most analog paths
powered off;
10 = standby mode;
digital datapath clocks
disabled, digital
datapath held in reset,
some analog paths
powered off
(Local)
Clock duty
cycle
stabilizer
(DCS)
enable
JESD204B
link is
ready
Clock divider ratio of the divide by 1 to
Clock divider phase output of the
divide by 8 divider circuit to generate
internal divide by 1 to divide by 8
the encode clock;
divider circuit, clock cycles are relative
0x00 = divide by 1;
to the input clock to this block;
0x01 = divide by 2;
0x0 = 0 input clock cycles delayed;
0x02 = divide by 3;
0x1 = 1 input clock cycles delayed;
…
0x2 = 2 input clock cycles delayed;
0x7 = divide by 8;
…
using a CLKDIV_DIVIDE_RATIO > 0
0x7 = 7 input clock cycles delayed
(Divide Ratio > 1) causes the DCS to be
Note that the RF clock divider phase is
automatically enabled
not selectable
Data output test generation mode;
Short
Long
0000 = off (normal mode);
psuedo
psuedo
0001 = midscale short;
random
random
0010 = positive full scale;
number
number
0011 = negative full scale;
generator generator
0100 = alternating checkerboard;
reset;
reset;
0101 = PN23 sequence long;
0 = short
0 = long
0110 = PN9 sequence short;
PRN
PRN
0111 = one-/zero-word toggle;
enabled;
enabled;
1000 = user test mode (use with Register 0x0D, Bit 7
1 = short
1 = long
and user pattern 1, 2, 3, 4);
PRN held in
PRN held
1001 to 1110 = unused;
reset
in reset
1111 = ramp output
Rev. E | Page 37 of 45
Default
0x18
Notes
0xB9
Read
only
0x00
or 0x30
0x03
0x00
0x01
Local,
DCS
enabled
if clock
divider
enabled
Read
only
0x00
Local
0x00
Local
AD9250
Reg
Addr
(Hex)
0x10
Register
Name
Customer
offset
(local)
0x14
Output
mode
(local)
0x15
CML output
adjust
0x18
ADC VREF
0x19
User Test
Pattern 1 L
User Test
Pattern 1 M
User Test
Pattern 2 L
User Test
Pattern 2 M
User Test
Pattern 3 L
User Test
Pattern 3 M
User Test
Pattern 4 L
User Test
Pattern 4 M
PLL low
encode
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
Data Sheet
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Offset adjust in LSBs from +31 to −32 (twos complement format);
01 1111 = adjust output by +31;
01 1110 = adjust output by +30;
…
00 0001 = adjust output by +1;
00 0000 = adjust output by 0 (default);
…
10 0001 = adjust output by −31;
10 0000 = adjust output by −32
Digital datapath output
Invert ADC
Disable
JTX CS bits assignment (in
data format select (DFS)
data;
output
conjunction with Register 0x72)
(local);
0 = normal
from ADC
000 = (overrange||underrange, valid)
00 = offset binary;
(default);
001 = (overrange||underrange)
01 = twos complement
1=
010 = (overrange||underrange, blank)
inverted
011 = (blank, valid)
100 = (blank, blank)
All others = (overrange||underrange,
valid)
JESD204B CML differential output drive
level adjustment;
000 = 81% of nominal (that is, 478 mV);
001 = 89% of nominal (that is, 526 mV);
010 = 98% of nominal (that is, 574 mV);
011 = nominal (default) (that is, 588 mV);
110 = 126% of nominal (that is, 738 mV)
Main reference full-scale VREF adjustment;
0 1111 = internal 2.087 V p-p;
…
0 0001 = internal 1.772 V p-p;
0 0000 = internal 1.75 V p-p (default);
1 1111 = internal 1.727 V p-p;
…
1 0000 = internal 1.383 V p-p
User Test Pattern 1 LSB; use in conjunction with Register 0x0D and Register 0x61
Default
0x00
Notes
Local
0x01
Local
0x03
0x00
0x00
User Test Pattern 1 MSB
0x00
User Test Pattern 2 LSB
0x00
User Test Pattern 2 MSB
0x00
User Test Pattern 3 LSB
0x00
User Test Pattern 3 MSB
0x00
User Test Pattern 4 LSB
0x00
User Test Pattern 4 MSB
0x00
00 = for lane speeds >
2 Gbps;
01 = for lane speeds <
2 Gbps
0x00
Rev. E | Page 38 of 45
Local
Data Sheet
Reg
Addr
(Hex)
0x3A
Register
Name
SYNCINB±/
SYSREF±
CTRL (local)
0x40
DCC CTRL
(local)
0x41
DCC value
LSB (local)
DCC value
MSB (local)
Fast detect
control
(local)
0x42
0x45
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x5E
FD upper
threshold
(local)
FD upper
threshold
(local)
FD lower
threshold
(local)
FD lower
threshold
(local)
FD dwell
time (local)
FD dwell
time (local)
204B quick
config
AD9250
Bit 7
(MSB)
Bit 6
Freeze dc
correction;
0=
calculate;
1=
freezeval
Bit 5
Bit 4
SYNCINB±
OPERATION
0 = normal
mode;
1 = realign
lanes on
every
active
SYNCINB±
Bit 3
Bit 2
SYSREF±
For
mode;
Subclass
0=
1 Only:
continuous
0=
reset clock
normal
dividers;
mode;
1 = sync on
1=
next
realign
SYSREF±
lanes on
rising edge
every
only
active
SYSREF±;
use with
single
shot
SYSREF in
Subclass 1
mode
DC correction bandwidth select;
correction bandwidth is 2387.32 Hz/reg val;
there are 14 possible values;
0000 = 2387.32 Hz;
0001 = 1193.66 Hz;
1101 = 0.29 Hz
DC Correction Value[7:0]
Bit 1
SYSREF±
enable;
0=
disabled;
1=
enabled.
NOTE:
This bit
self-clears
after
SYSREF if
SYSREF±
mode = 1
Bit 0 (LSB)
Enable
internal
SYSREF±
buffer;
0 = buffer
disabled,
external
SYSREF±
pin
ignored;
1 = buffer
enabled,
use
external
SYSREF±
pin
Enable
DCC
Default
0x00
Notes
Local
See
Table 14
for more
details
0x00
Local
0x00
Local
0x00
Local
0x00
Local
0x00
Local
0x00
Local
0x00
Local
0x00
Local
Fast Detect Dwell Time[7:0]
0x00
Local
Fast Detect Dwell Time[15:8]
0x00
Local
Quick configuration register, always reads back 0x00;
0x11 = M = 1, L = 1; one converter, one lane; second converter is not automatically powered down;
0x12 = M = 1, L = 2; one converter, two lanes; second converter is not automatically powered down;
0x21 = M = 2, L = 1; two converters, one lane;
0x22 = M = 2, L = 2; two converters, two lanes
0x00
Always
reads
back
0x00
DC Correction Value[15:8]
Force
value of
FDA/FDB
pins
if force
pins is true,
this value
is output
on FD pins
Fast Detect Upper Threshold[7:0]
Pin
function;
0 = fast
detect;
1=
overrange
Force
FDA/FDB
pins;
0=
normal
function;
1 = force
to value
Enable fast
detect
output
Fast Detect Upper Threshold[14:8]
Fast Detect Lower Threshold[7:0]
Fast Detect Lower Threshold[14:8]
Rev. E | Page 39 of 45
AD9250
Reg
Addr
(Hex)
0x5F
Data Sheet
Register
Name
204B Link
CTRL 1
Bit 7
(MSB)
0x60
204B Link
CTRL 2
Reserved;
set to 0
Bit 6
Tail bits: If
CS bits
are not
enabled;
0 = extra
bits are 0;
1 = extra
bits are 9bit PN
Reserved;
set to 0
0x61
204B Link
CTRL 3
Reserved;
set to 0
Reserved;
set to 0
0x62
204B Link
CTRL 4
204B Link
CTRL 5
204B DID
config
204B BID
config
204B LID
Config 0
204B LID
Config 1
204B
parameters
SCR/L
0x63
0x64
0x65
0x66
0x67
0x6E
0x6F
0x70
0x71
0x72
204B
parameters
F
204B
parameters
K
204B
parameters
M
204B
parameters
CS/N
Bit 5
JESD204B
test
sample
enabled
Bit 4
Reserved;
set to 1
Bit 3
Bit 2
ILAS mode;
01 = ILAS normal mode
enabled;
11 = ILAS always on, test
mode
Bit 1
Reserved;
set to 0
Bit 0 (LSB)
Powerdown
JESD204B
link; set
high while
configuring
link
parameters
Reserved;
set to 0
Invert
logic of
JESD204B
bits
Test data injection point;
JESD204B test mode patterns;
01 = 10-bit data at
0000 = normal operation (test mode disabled);
8B/10B output;
0001 = alternating checker board;
10 = 8-bit data at
0010 = 1/0 word toggle;
scrambler input
0011 = PN sequence PN23;
0100 = PN sequence PN9;
0101= continuous/repeat user test mode;
0110 = single user test mode;
0111 = reserved;
1000 = modified RPAT test sequence, must be used
with JTX_TEST_GEN_SEL = 01 (output of 8b/10b);
1100 = PN sequence PN7;
1101 = PN sequence PN15;
other setting are unused
Reserved
Default
0x14
0x00
0x00
0x00
Reserved
0x00
JESD204B DID value
0x00
JESD204B BID value
0x00
Lane 0 LID value
0x00
Lane 1 LID value
0x01
JESD204B
lanes (L);
0 = 1 lane;
1 = 2 lanes
JESD204B
scrambling
(SCR);
0=
disabled;
1=
enabled
0x81
JESD204B number of octets per frame (F); calculated value
(Note that this value is in x − 1 format)
0x01
JESD204B number of frames per multiframe (K); set value of K per JESD204B specifications, but also must be a
multiple of 4 octets
(Note that this value is in x − 1 format)
JESD204B number of converters (M);
0 = 1 converter;
1 = 2 converters
ADC converter resolution (N),
Number of control bits
0xD = 14-bit converter (N = 14)
(CS);
(Note that this value is in x − 1 format)
00 = no control bits
(CS = 0);
01 = 1 control bit
(CS = 1);
10 = 2 control bits
(CS = 2)
0x1F
Rev. E | Page 40 of 45
Notes
0x01
0x0D
Read
Only
Data Sheet
Reg
Addr
(Hex)
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x82
Register
Name
204B
parameters
subclass/Np
204B
parameters S
204B
parameters
HD and CF
204B RESV1
204B RESV2
204B
CHKSUM0
204B
CHKSUM1
204B Lane
Assign 1
AD9250
Bit 7
(MSB)
Bit 6
Bit 5
JESD204B subclass;
0x0 = Subclass 0;
0x1 = Subclass 1
(default)
Reserved;
set to 1
JESD204B
HD value;
read only
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
JESD204B N’ value; 0xF = N’ = 16
(Note that this value is in x – 1 format)
JESD204B samples per converter frame cycle (S); read only
(Note that this value is in x − 1 format)
JESD204B control words per frame clock cycle per link (CF);
read only
204B Lane
Assign 2
0x8B
204B LMFC
offset
0xA8
204B preemphasis
0xEE
Internal
digital clock
delay
Enable
internal
clock delay
0xEF
Internal
digital clock
delay
Enable
internal
clock delay
JESD204B serial checksumvalue for Lane 1
0x43
0xF3
Internal
digital clock
alignment
0xFF
Device
update
(global)
Reserved;
set to 0
00 = assign Logical Lane
1 to Physical Lane A;
01 = assign Logical Lane 1
to Physical Lane B
(default)
Local multiframe clock (LMFC) phase offset value; reset value for
LMFC phase counter when SYSREF is asserted; used for
deterministic delay applications
JESD204B pre-emphasis enable option (consult factory for more detail);
set value to 0x04 for pre-emphasis off;
set value to 0x14 for pre-emphasis on
Use incrementing values from 0 to 7 to increase
Set to 0
Set to 0
Set to 0
internal digital clock delay. For internal data latching
purposes, this does not affect external timing.
Set to 0
0x00
0x00
0x00
0x42
Reserved;
set to 1
Set to 0
Set to 0
Use incrementing values from 0 to 7 to increase
internal digital clock delay. For internal data latching
purposes, this does not affect external timing.
Force
manual
re-align
on Lane 1,
self
clearing
Lane 1
Alignment
complete
Force
manual
realign on
Lane 0,
self
clearing
Lane 0
alignment
complete
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00
to Register 0x25, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
Rev. E | Page 41 of 45
Read
Only
0x02
0x31
0x00
0x04
0x00
0x00
0x14
Transfer
settings
Notes
0x20
Reserved Field Number 1
Reserved Field Number 2
JESD204B serial checksumvalue for Lane 0
00 = assign Logical Lane 0
to Physical Lane A
(default);
01 = assign Logical Lane 0
to Physical Lane B
Reserved; Reserved;
set to 1
set to 1
0x83
Default
0x2F
Typically
not
required
See
JESD
Section
for use
See
JESD
Section
for use
See
JESD
Section
for use
AD9250
Data Sheet
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting system level design and layout of the AD9250, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9250, use two separate 1.8 V
power supplies. The power supply for AVDD can be isolated and
for DVDD and DRVDD it can be tied together, in which case
isolation between DVDD and DRVDD is required. Isolation can
be achieved using a ferrite bead or an inductor of approximately
1 µH. An unfiltered switching regulator is not recommended for
the DRVDD supply as it impacts the performance of the JESD204B
serial transmission lines and may result in link problems. Alternately, the JESD204B PHY power (DRVDD) and analog (AVDD)
supplies can be tied together, and a separate supply can be used
for the digital outputs (DVDD).
The designer can employ several different decoupling capacitors
to cover both high and low frequencies. Locate these capacitors
close to the point of entry at the PC board level and close to the
pins of the part with minimal trace length. Each power supply
domain must have local high frequency decoupling capacitors.
This is especially important for DRVDD and AVDD to
maintain analog performance.
When using the AD9250, a single PCB ground plane should be
sufficient. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. Mate a continuous,
exposed (no solder mask) copper plane on the PCB to the
AD9250 exposed paddle, Pin 0.
The copper plane must have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the
bottom of the PCB. Fill or plug these vias with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, overlay a silkscreen to partition the continuous plane
on the PCB into several uniform sections. This provides several tie
points between the ADC and the PCB during the reflow process.
Using one continuous plane with no partitions guarantees only
one tie point between the ADC and the PCB. See the evaluation
board for a PCB layout example. For detailed information about
the packaging and PCB layout of chip scale packages, refer to
the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).
VCM
Decouple the VCM pin to ground with a 0.1 µF capacitor, as
shown in Figure 40. For optimal channel-to-channel isolation,
include a 33 Ω resistor between the AD9250 VCM pin and the
Channel A analog input network connection, as well as between
the AD9250 VCM pin and the Channel B analog input network
connection.
SPI Port
When the full dynamic performance of the converter is required,
do not activate the SPI port during periods. Because the
SCLK, CS, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9250 to keep these signals from transitioning at the converter
input pins during critical sampling periods.
SPI INITIALIZATION SEQUENCE
On power-up of the AD9250, a host processor is required to
initialize and configure the AD9250 via its SPI port. Figure 63
shows a flowchart of the sequential steps required to bring the
AD9250 to an operational state. The number of SPI writes and
total initialization time is dependent on how many SPI registers
need to be changed from the default setting, usage of the clock
divider, and whether JESD204B Subclass 1 synchronization is
required. Table 19 shows the minimum SPI writes required to
enable the AD9250. Note the following in the sequence of steps
shown in Table 19:
•
•
Rev. E | Page 42 of 45
Steps that are listed as optional can be ignored if the default
SPI settings are sufficient.
Steps that are listed as conditional can be ignored if the
specific condition is not applicable.
Data Sheet
AD9250
APPLY POWER AND CLOCK
ALLOW TIME TO SETTLE
OPTIONAL
MODIFY ANY OTHER
JESD204B PARAMETERS
FROM DEFAULT SETTING
ISSUE SOFTWARE RESET
THEN WAIT 500µs MIN
JESD204B
SUBCLASS1
SYNC
YES
APPLY EXTERNAL SYSREF
WAIT >6LMFC CLOCKS
DISABLE SYSREF BUFFER
(ONE-SHOT MODE ONLY)
NO
USE CLOCK
DIVIDER?
DISABLE THE JESD204B
TxPHY DURING SET-UP
(AS WELL AS JESD204B Rx)
YES
ISSUE SOFTWARE
POWER-UP
WAIT 250ms
FIFO WRITE/READ
CLOCK ADJUSTMENT
WAIT >6LMFC CLOCKS
NO
OPTIONAL
CONFIGURE ANY
NON-JESD204
REGISTERS FROM
DEFAULT SETTING
USE CLOCK
DIVIDER?
YES
JESD204B
SUBCLASS1
SYNC
ISSUE SOFTWARE
POWER-DOWN
SET DIVIDER VALUE
YES
ENABLE
SYSREF BUFFER
CONFIGURE
SYSREF MODE
NO
READBACKPLL LOCK BIT
ENABLE PHY TO BEGIN CGS PHASE
FORCE FIFO ALIGNMENT
WAIT >6LMFC CLOCKS
NO
10559-063
SET THE QUICK JESD204
CONFIGURATION MODE
(REFER TO TABLE 13)
RESET INTERNAL CLOCKS
TO MINIMUM SETTING
Figure 63. Flowchart Showing Sequence of Steps Required to Initialize the AD9250
Table 19. SPI Initialization Sequence
Address
Write
Value
0x00
0x3C
0x5F
0x15
6
0x0B
0x01
7
8
9
0xFF
0x5E
0xEE
0x21
0x01
0xML
0x80
0x00
0x14
0x15
0x66
0x67
0x6E
0x70
0x82
0x01
0x03
0x00
0x01
0x81
0x1F
0x0D
0xFF
0x01
Step
1
2
3
4
5
10
Comments
Apply power to the AD9250 and allow the voltages and clocks to stabilize.
Software reset.
Wait 500 μs minimum.
Disable the JESD204B PHY.
Optional: modify any other non-JESD204B register from default setting depending on application
requirements. Note, any local register must be followed by a transfer command (0xFF= 0x01)
Optional: set the clock divider ratio if using a clock divider. Note that the 0x01 value shown corresponds to a
divide-by-2 clock ratio.
Transfer command for local Register
Set the JESD204B quick configuration register based on the desired M and L values.
Enable the internal clock delay block for minimum delay.
Conditional: configure the PLL low encode register. Only set to 0x01 if the lane rate is < 2 GBPS. The default
setting is 0x00.
Optional: modify the JESD204B centric registers from the default setting as follows:
Configure the data output with 0x01 being the default (twos complement).
Set the JESD204B CML differential drive level with 0x03 being default (588 mV).
Set the Lane 0 and Lane 1 LID value (defaults shown).
Set the Lane 0 and Lane 1 LID value (defaults shown).
Enable the JESD204B scrambling in Bit 7 while keeping desired JESD204B lane value, L, in Bit 0. Default shown.
Modify the JESD204B K and CS values. Default shown.
Modify the JESD204B K and CS values. Default shown.
Modify other JESD204B centric configurations in Register 0x82 to Register 0x8B and Register 0xA8.
Transfer command for local Register
Rev. E | Page 43 of 45
AD9250
Step
11
Data Sheet
Address
Write
Value
0x3A
0x01
0xFF
0x3A
0xFF
0x01
0x0F or
0x03
0x01
0x0A
0x5F
0xF3
0x14
0xFF
0x3A
0xFF
0x04
0x01
0xEE
0xEF
0xEE
0xEF
0xEE
0xEF
0xEE
0xEF
0xEE
0xEF
0xEE
0xEF
0xEE
0xEF
0x81
0x81
0x82
0x82
0x83
0x83
0x84
0x84
0x85
0x85
0x86
0x86
0x87
0x87
12
13
14
1
Comments
Optional: JESD204B Subclass 1 synchronization setup.
Enable the SYSREF buffer first to avoid false triggering (especially one-shot operation) before setting the
remaining bits in Register 0x3A.
Transfer command for local Register
Configure the method of SYSREF operation. For one-shot operation, set to 0x0F. For continuous or gapped
periodic SYSREF operation, set to 0x03.
Transfer command for local Register
Begin JESD204B link establishment.
Optional: read back Register 0x0A with 0x81 indicating that the JESD204B PLL is locked.
Enable the JESD204B PHY. This begins the CGS phase for establishing a link.
Force an internal FIFO alignment.
Wait at least six LMFC cycles.
Note that the JESD204B link must be established at this time before continuing.
Optional: When operating in SubClass 1 mode, apply external SYSREF signal for LMFC alignment.
Wait at least six LMFC cycles for LMFC alignment between JESD204B Tx and Rx to occur.
Conditional: disable the internal SYSREF buffer if configured for one-shot operation.
Transfer command for local Register
Internal FIFO clock adjustment.
Clock adjustment procedure. 1
Clock adjustment procedure.1
Clock adjustment procedure.1
Clock adjustment procedure.1
Clock adjustment procedure.1
Clock adjustment procedure.1
Clock adjustment procedure.1
Clock adjustment procedure.1
Clock adjustment procedure.1
Clock adjustment procedure.1
Clock adjustment procedure.1
Clock adjustment procedure.1
Clock adjustment procedure.1
Clock adjustment procedure.1
Wait at least six LMFC cycles.
Following this procedure optimizes write and read clock delays of internal FIFO to avoid possible overflow, overtemperature, and supply variations.
Rev. E | Page 44 of 45
Data Sheet
AD9250
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
7.10
7.00 SQ
6.90
0.30
0.25
0.18
37
36
48
1
0.50
BSC
5.70
5.60 SQ
5.50
EXPOSED
PAD
TOP VIEW
0.80
0.75
0.70
END VIEW
PKG-004452
SEATING
PLANE
0.50
0.40
0.30
24
13
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
0.20 MIN
5.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4.
02-29-2016-A
PIN 1
INDICATOR
Figure 64. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9250BCPZ-170
AD9250BCPZRL7-170
AD9250-170EBZ
AD9250BCPZ-250
AD9250BCPZRL7-250
AD9250-250EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board with AD9250-170
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board with AD9250-250
Z = RoHS Compliant Part.
©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10559-0-9/17(E)
Rev. E | Page 45 of 45
Package Option
CP-48-13
CP-48-13
CP-48-13
CP-48-13