CY28346-2 Clock Synthesizer with Differential CPU Outputs Features • Compliant with Intel® CK 408 Mobile Clock Synthesizer specifications • Spread Spectrum electromagnetic interference (EMI) reduction • 3.3V power supply • Dial-a-Frequency£ features • 3 differential CPU clocks • Dial-a-dB™ features • 10 copies of PCI clocks • Extended operating temperature range, 0qC to 85qC • 5/6 copies of 3V66 clocks • 56-pin TSSOP packages • SMBus support with Read Back capabilities Table 1. Frequency Table[1] S2 S1 S0 CPU (0:2) 3V66 66BUFF(0:2)/ 3V66(0:4) 66IN/ 3V66-5 PCIF/PCI REF USB/ DOT 1 0 0 66M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 1 0 1 100M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 1 1 0 200M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 1 1 1 133M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 0 0 0 66M 66M 66M 66M 33 M 14.318M 48M 0 0 1 100M 66M 66M 66M 33 M 14.318M 48M 0 1 0 200M 66M 66M 66M 33 M 14.318M 48M 0 1 1 133M 66M 66M 66M 33 M 14.318M 48M M 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z M 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2 Block Diagram Pin Configuration XIN XOUT REF CPUT(0:2) CPUC(0:2) PLL1 CPU_STP# IREF VSSIREF 3V66_1/VCH MULT0 VTT_PWRGD# /2 PCI_STP# PCI(0:6) PCI_F(0:2) PLL2 48M_USB 48M_DOT PD# SDATA SCLK WD Logic I2C Logic 66B[0:2]/3V66[2:4] VDDA Power Up Logic 66IN/3V66-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CY28346-2 3V66_0 S(0:2) VDD XIN XOUT VSS PCIF0 PCIF1 PCIF2 VDD VSS PCI0 PCI1 PCI2 PCI3 VDD VSS PCI4 PCI5 PCI6 VDD VSS 66B0/3V66_2 66B1/3V66_3 66B2/3V66_4 66IN/3V66_5 PD# VDDA VSSA VTT_PWRGD# 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF S1 S0 CPU_STP# CPUT0 CPUC0 VDD CPUT1 CPUC1 VSS VDD CPUT2 CPUC2 MULT0 IREF VSSIREF S2 48M_USB 48M_DOT VDD VSS 3V66_1/VCH PCI_STP# 3V66_0 VDD VSS SCLK SDATA Note: 1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a 0 state will be latched into the devices internal state register. Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Page 1 of 19 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com CY28346-2 Pin Description Pin Name PWR I/O Description 2 XIN VDD I Oscillator Buffer Input. Connect to a crystal or to an external clock. 3 XOUT VDD O Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN. VDD O Differential host output clock pairs. See Table 1 for frequencies and functionality. VDDP O PCI clock outputs. Are synchronous to 66IN or 3V66 clock. See Table 1. 52, 51, 49, 48, CPUT(0:2), 45, 44 CPUC(0:2) 10, 11, 12, 13, PCI(0:6) 16, 17, 18 5, 6, 7 PCIF (0:2) VDD O 33-MHz PCI clocks, which are y2 copies of 66IN or 3V66 clocks, may be free running (not stopped when PCI_STP# is asserted LOW) or may be stoppable depending on the programming of SMBus register Byte3, Bits (3:5). 56 REF VDD O Buffered output copy of the device’s XIN clock. 42 IREF VDD I Current reference programming input for CPU buffers. A resistor is connected between this pin and VSSIREF. 28 VTT_PWRGD# VDD I Qualifying input that latches S(0:2) and MULT0. When this input is at a logic low, the S(0:2) and MULT0 are latched. 39 48M_USB VDD48 O Fixed 48-MHz USB clock outputs. 38 48M_DOT VDD48 O Fixed 48-MHZ DOT clock outputs. 33 3V66_0 VDD O 3.3V 66-MHz fixed frequency clock. 35 3V66_1/VCH VDD O 3.3V clock selectable with SMBus byte0, Bit5, when Byte5, Bit5. When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When byte0, Bit5 is a logic 0, then this is a 66M output clock (default). 25 PD# VDD I PU This pin is a power-down mode pin. A logic LOW level causes the device to enter a power-down state. All internal logic is turned off except for the SMBus logic. All output buffers are stopped. 43 MULT0 VDD I PU Programming input selection for CPU clock current multiplier. 55, 54 S(0,1) I I Frequency select inputs. See Table 1 29 SDATA I I Serial data input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. 30 SCLK I I Serial clock input. Conforms to the SMBus specification. 40 S2 VDD I T Frequency select input. See Table 1. This is a Tri-level input that is driven HIGH, LOW, or driven to a intermediate level. 34 PCI_STP# VDD I PU PCI clock disable input. When asserted LOW, PCI (0:6) clocks are synchronously disabled in a LOW state. This pin does not effect PCIF (0:2) clocks’ outputs if they are programmed to be PCIF clocks via the device’s SMBus interface. 53 CPU_STP# VDD I PU CPU clock disable input. When asserted LOW, CPUT (0:2) clocks are synchronously disabled in a HIGH state and CPUC(0:2) clocks are synchronously disabled in a LOW state. 24 66IN/3V66_5 VDD I/O Input connection for 66CLK(0:2) output clock buffers if S2 = 1, or output clock for fixed 66-MHz clock if S2 = 0. See Table 1. 21, 22, 23 66B(0:2)/ 3V66(2:4) VDD O 3.3V clock outputs. These clocks are buffered copies of the 66IN clock or fixed at 66 MHz. See Table 1. 1, 8, 14, 19, 32, VDD 37, 46, 50 – PWR 3.3V power supply. 4, 9, 15, 20, 27, VSS 31, 36, 47 – PWR Common ground. Rev 1.0, November 20, 2006 Page 2 of 19 CY28346-2 Pin Description (continued) Pin Name PWR I/O Description 41 VSSIREF – PWR Current reference programming input for CPU buffers. A resistor is connected between this pin and IREF. This pin should also be returned to device VSS. 26 VDDA – PWR Analog power input. Used for PLL and internal analog circuits. It is also specifically used to detect and determine when power is at an acceptable level to enable the device to operate. Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The clock driver serial protocol accepts block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The block write and block read protocol is outlined in Table 2. The slave receiver address is 11010010 (D2h). Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits Block Read Protocol Bit 1 2:8 Description Start Slave address – 7 bits 9 Write = 0 9 Write = 0 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 28 29:36 37 38:45 Command Code – 8 bit ‘00000000’ stands for block operation 11:18 Command Code – 8 bit ‘00000000’ stands for block operation Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits 20 Repeat start Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits 21:27 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 46 Acknowledge from slave .... ...................... .... Data Byte (N–1) –8 bits 47 .... Acknowledge from slave 48:55 .... Data Byte N –8 bits 56 Acknowledge .... Acknowledge from slave .... Data bytes from slave/Acknowledge .... Stop .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop Rev 1.0, November 20, 2006 38 Byte count from slave – 8 bits 39:46 Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Page 3 of 19 CY28346-2 Byte 0: CPU Clock Register Bit @Pup 7 Name Description 0 Spread Spectrum Enable, 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit. 6 0 CPU clock Power-down Mode Select. 0 = Drive CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) to low when PD# is asserted LOW. 1 = Three-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to CPU_STP#. 5 0 4 Pin 53 3 Pin 34 2 Pin 40 Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read-only. 1 Pin 55 Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read-only. 0 Pin 54 Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read-only. 3V66_1/VCH 3V66_1/VCH frequency Select, 0 = 66M selected, 1 = 48M selected This is a Read and Write control bit. CPUT,CPUC CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read-only. PCI Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is a logical AND function of the internal SMBus register bit and the external PCI_STP# pin. Byte 1: CPU Clock Register Bit @Pup Name Description 7 Pin 43 MULT0 MULT0 (Pin 43) Value. This bit is Read-only. 6 0 CPU_STP# 5 0 CPUT2 CPUC2 Controls CPU2 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. 4 0 CPUT1 CPUC1 Controls CPU1 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. 3 0 CPUT0 CPUC0 Controls CPUT0 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. 2 1 CPUT2 CPUC2 CPUT/C2 Output Control, 1 = enabled, 0 = disable HIGH and CPUC2 disables LOW This is a Read and Write control bit. 1 1 CPUT1 CPUC1 CPUT/C1 Output Control, 1 = enabled, 0 = disable HIGH and CPUC1 disables LOW This is a Read and Write control bit. 0 1 CPUT0 CPUC0 CPUT/C0 Output Control, 1 = enabled, 0 = disable HIGH and CPUC0 disables LOW This is a Read and Write control bit. Controls functionality of CPUT/C(0:2) outputs when CPU_STP# is asserted. 0 = Drive CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) to low when CPU_STP# asserted LOW. 1 = Three-state all CPU outputs. This bit will override Byte0, Bit6 such that even if it is a 0, when PD# goes low the CPU outputs will be three-stated. Byte 2: PCI Clock Control Register (all bits are read and write functional) Bit @Pup 7 0 REF REF Output Control. 0 = high strength, 1 = low strength 6 1 PCI6 PCI6 Output Control. 1 = enabled, 0 = forced LOW 5 1 PCI5 PCI5 Output Control. 1 = enabled, 0 = forced LOW 4 1 PCI4 PCI4 Output Control. 1 = enabled, 0 = forced LOW 3 1 PCI3 PCI3 Output Control. 1 = enabled, 0 = forced LOW 2 1 PCI2 PCI2 Output Control. 1 = enabled, 0 = forced LOW 1 1 PCI1 PCI1 Output Control. 1 = enabled, 0 = forced LOW 0 1 PCI0 PCI0 Output Control. 1 = enabled, 0 = forced LOW Rev 1.0, November 20, 2006 Name Description Page 4 of 19 CY28346-2 Byte 3: PCIF Clock and 48M Control Register (all bits are read and write functional) Bit @Pup Name Description 7 1 48M_DOT 48M_DOT Output Control,1 = enabled, 0 = forced LOW 6 1 48M_USB 48M_USB Output Control,1 = enabled, 0 = forced LOW 5 0 PCIF2 PCI_STP#, control of PCIF2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW 4 0 PCIF1 PCI_STP#, control of PCIF1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW 3 0 PCIF0 PCI_STP#, control of PCIF0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW 2 1 PCIF2 PCIF2 Output Control. 1=running, 0=forced LOW 1 1 PCIF1 PCIF1 Output Control. 1= running, 0=forced LOW 0 1 PCIF0 PCIF0 Output Control. 1= running, 0=forced LOW Byte 4: DRCG Control Register(all bits are read and write functional) Bit @Pup 7 0 Name Description 6 0 5 1 3V66_0 4 1 3V66_1/VCH 3 1 3V66_5 2 1 66B2/3V66_4 66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled 1 1 66B1/3V66_3 66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled 0 1 66B0/3V66_2 66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread) Reserved 3V66_0 Output Enabled. 1 = enabled, 0 = disabled 3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled 3V66_5 Output Enable. 1 = enabled, 0 = disabled Byte 5: Clock Control Register (all bits are read and write functional) Bit @Pup Name Description 7 0 SS1 Spread Spectrum control bit 6 1 SS0 Spread Spectrum control bit 5 0 66IN to 66M delay Control MSB 4 0 66IN to 66M delay Control LSB 3 0 Reserved 2 0 48M_DOT edge rate control. When set to 1, the edge is slowed by 15%. 1 0 Reserved 0 0 USB edge rate control. When set to 1, the edge is slowed by 15% Byte 6: Silicon Signature Register[2] (all bits are read-only) Bit @Pup 7 0 6 0 5 0 4 1 3 0 2 0 1 1 0 1 Name Description Vendor Code, 011 = IMI Note: 2. When writing to this register the device will acknowledge the write operation, but the data itself will be ignored. Rev 1.0, November 20, 2006 Page 5 of 19 CY28346-2 Byte 7: Watchdog Time Stamp Register Bit @Pup Name Description 7 0 Reserved 6 0 Reserved 5 0 Reserved 4 0 Reserved 3 0 Reserved 2 0 Reserved 1 0 Reserved 0 0 Reserved Byte 8: Dial-a-Frequency Control Register N (all bits are read and write functional) Bit @Pup Name Description 7 0 N7, MSB 6 0 N6 5 0 N5 4 0 N4 3 0 N3 2 0 N2 1 0 N3 0 0 N0, LSB Byte 9: Dial-a-Frequency Control Register R (all bits are read and write functional) Bit @Pup 7 0 Name R6 MSB Description 6 0 R5 5 0 R4 4 0 R3 3 0 R2 2 0 R1 1 0 R0, LSB 0 0 R and N register load gate 0 = gate closed (data is latched), 1 = gate open (data is loading from SMBus registers into R and N) Dial-a-Frequency Feature Dial-a-dB Features SMBus Dial-a-Frequency feature is available in this device via Byte8 and Byte9. See our App Note AN-0025 for details on our Dial-a-Frequency feature. SMBus Dial-a-dB feature is available in this device via Byte8 and Byte9. P is a large value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from Table 3. Table 3. P Value S(1:0) P 00 32005333 01 48008000 10 96016000 11 64010667 Rev 1.0, November 20, 2006 Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique used to minimizing EMI radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control Bytes. Table 4 is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. Page 6 of 19 CY28346-2 Configured as DRCG (66M), SMBus Byte0, Bit 5 = ‘0’ Table 4. Spread Spectrum The default condition for this pin is to power up in a 66M operation. In 66M operation this output is SSCG capable and when spreading is turned on, this clock will be modulated. SS2 SS1 SS0 Spread Mode Spread% 0 0 0 Down +0.00, –0.25 0 0 1 Down +0.00, –0.50 Configured as VCH (48M), SMBus Byte0, Bit 5 = ‘1’ 0 1 0 Down +0.00, –0.75 0 1 1 Down +0.00, –1.00 1 0 0 Center +0.13, –0.13 1 0 1 Center +0.25, –0.25 1 1 0 Center +0.37, –0.37 In this mode, the output is configured as a 48-MHz non-spread spectrum output. This output is phase aligned with the other 48M outputs (USB and DOT), to within 1 ns pin-to-pin skew. The switching of 3V66_1/VCH into VCH mode occurs at system power on. When the SMBus Bit 5 of Byte 0 is programmed from a ‘0’ to a ‘1’, the 3V66_1/VCH output may glitch while transitioning to 48M output mode. 1 1 1 Center +0.50, –1.50 Special Functions PCIF and IOAPIC Clock Outputs The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. ANY two of the PCIF clock outputs can be used as IOAPIC 33-MHz clock outputs. They are 3.3V outputs will be divided down via a simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event these clocks are not required, then these clocks can be used as general PCI clocks or disabled via the assertion of the PCI_STP# pin. 3V66_1/VCH Clock Output The 3V66_1/VCH pin has a dual functionality that is selectable via SMBus. PD# (Power-down) Clarification The PD# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ‘stopped’ state. PD#—Assertion When PD# is sampled LOW by two consecutive rising edges of the CPUC clock, then on the next HIGH-to-LOW transition of PCIF, the PCIF clock is stopped LOW. On the next HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped LOW. From this time, each clock will stop LOW on its next HIGH-to-LOW transition, except the CPUT clock. The CPU clocks are held with the CPUT clock pin driven HIGH with a value of 2 x Iref, and CPUC undriven. After the last clock has stopped, the rest of the generator will be shut down. 66Buff PCIF PW RDW N# CPU 133MHz CPU# 133MHz 3V66 66In USB 48MHz REF 14.318MHz Figure 1. Power-down Assertion Timing Waveforms—Buffered Mode Rev 1.0, November 20, 2006 Page 7 of 19 CY28346-2 PW RDW N# C P U T 133M H z C P U C 133M H z P C I 33M H z A G P 66M H z U S B 48M H z R E F 1 4 .3 1 8 M H z D D R T 133M H z D D R C 133M H z S D R A M 133M H z Figure 2. Power-down Assertion Timing Waveforms—Unbuffered Mode PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 ms. 30uS min 400uS max <1.8mS 66Buff1 / GMCH 66Buff PCIF / APIC 33MHz PCI 33MHz PWRDWN# CPU 133MHz CPU# 133MHz 3V66 66In USB 48MHz REF 14.318MHz Figure 3. Power-down Deassertion Timing Waveforms Table 5. PD# Functionality PD# DRCG 66CLK (0:2) PCIF/PCI PCI USB/DOT 1 66M 66Input 66Input/2 66Input/2 48M 0 Low Low Low Low Low Rev 1.0, November 20, 2006 Page 8 of 19 CY28346-2 CPU_STP# Clarification The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. CPU_STP# Assertion When CPU_STP# pin is asserted, all CPUT/C outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two falling CPUT/C clock edges. The final state of the stopped CPU signals is CPUT = HIGH and CPU0C = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to (Mult 0 ‘select’) x (Iref), and the CPUC signal will not be driven. Due to external pull-down circuitry CPUC will be LOW during this stopped state. CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPUT/C outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produces when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPUC clock cycles. C P U _S TP # CPUT CPUC CPUT CPUC Figure 4. CPU_STP# Assertion Waveforms CPU_STP# CPUT CPUC CPUT CPUC Figure 5. CPU_STP# Deassertion Waveforms Rev 1.0, November 20, 2006 Page 9 of 19 CY28346-2 Three-state Control of CPU Clocks Clarification PCI_STP# Deassertion During CPU_STP# and PD# modes, CPU clock outputs may be set to driven or undriven (three-state) by setting the corresponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1. The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level. PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tsetup). (See Figure 2.) The PCIF (0:2) clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free running. Note that the PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs to the function are logically ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the devices stoppable PCI clocks are not running. Table 6. Cypress Clock Power Management Truth Table CPU_STP# Stoppable CPUT Stoppable CPUC B0b6 B1b6 PD# Non-Stop CPUT Non-Stop CPUC 0 0 1 1 Running Running Running Running 0 0 1 0 Iref x6 Iref x6 Running Running 0 0 0 1 Iref x2 Low Iref x2 Low 0 0 0 0 Iref x2 Low Iref x2 Low 0 1 1 1 Running Running Running Running 0 1 1 0 Hi Z Hi Z Running Running 0 1 0 1 Hi Z Hi Z Hi Z Hi Z 0 1 0 0 Hi Z Hi Z Hi Z Hi Z 1 0 1 1 Running Running Running Running 1 0 1 0 Iref x6 Iref x6 Running Running 1 0 0 1 Hi Z Hi Z Hi Z Hi Z 1 0 0 0 Hi Z Hi Z Hi Z Hi Z 1 1 1 1 Running Running Running Running 1 1 1 0 Hi Z Hi Z Running Running 1 1 0 1 Hi Z Hi Z Hi Z Hi Z 1 1 0 0 Hi Z Hi Z Hi Z Hi Z t setup P C I_S T P # P C IF 33M P C I 33M Figure 6. PCI_STP# Assertion Waveforms Rev 1.0, November 20, 2006 Page 10 of 19 CY28346-2 t setup PCI_STP# PCIF PCI Figure 7. PCI_STP# Deassertion Waveforms VID SEL VTT_PWRGD# PWRGD 0.2-0.3mS Delay VDD Clock Gen Clock State Clock Outputs Clock VCO State 0 Wait for Sample Sels VTT_PWRGD# State 1 State 2 Off Device is not affected, VTT_PWRGD# is ignored. State 3 On On Off Figure 8. VTT_PWRGD# Timing Diagram S2 S1 VTT_PWRGD# = Low Delay >0.25mS Sample Inputs straps VDDA = 2.0V Wait for <1.8ms S0 Power Off S3 Normal Operation VDD3.3= off Enable Outputs VTT_PWRGD# = toggle Figure 9. Clock Generator Power-up/Run State Program Iout is selectable depending on implementation. The parameters above apply to all configurations. Vout is the voltage at the pin of the device. Rev 1.0, November 20, 2006 The various output current configurations are shown in the host swing select functions table. For all configurations, the deviation from the expected output current is ±7% as shown in the current accuracy table. Page 11 of 19 CY28346-2 Table 7. Host Clock (HCSL) Buffer Characteristics Characteristic Minimum Maximum Ro 3000 Ohms (recommended) N/A N/A 1.2V Ros Vout Table 8. CPU Clock Current Select Function Mult0 Board Target Trace/Term Z Reference R, Iref – Vdd (3*Rr) Output Current Voh @ Z 0 50 Ohms Rr = 221 1%, Iref = 5.00 mA Ioh = 4*Iref 1.0V @ 50 1 50 Ohms Rr = 475 1%, Iref = 2.32 mA Ioh = 6*Iref 0.7V @ 50 Table 9. Group Timing Relationship and Tolerances Description Offset Tolerance Conditions 3V66 to PCI 2.5 ns r1.0 ns 3V66 Leads PCI (unbuffered mode) 48M_USB to 48M_DOT Skew 0.0 ns r1.0 ns 0 degrees phase shift 66B to PCI offset 2.5 ns r1.0 ns 66B leads PCI (buffered mode) Table 10.Maximum Lumped Capacitive Output Loads Clock 66IN to 66B Buffered Prop Delay Max Load Unit PCI Clocks 30 pF 3V66 30 pF 66B 30 pF 48M_USB Clock 20 pF 48M_DOT 10 pF 66B to PCI Buffered Clock Skew REF Clock 50 pF Figure 12 shows the difference (skew) between the 3V33(0:5) outputs when the 66M clocks are connected to 66IN. This offset is described in the Group Timing Relationship and Tolerances section of this data sheet. The measurements were taken at 1.5V. USB and DOT 48M Phase Relationship The 48M_USB and 48M_DOT clocks are in phase. It is understood that the difference in edge rate will introduce some in inherent offset. When 3V66_1/VCH clock is configured for VCH (48-MHz) operation it is also in phase with the USB and DOT outputs. See Figure 10. The 66IN to 66B(0:2) output delay is shown in Figure 11. The Tpd is the prop delay from the input pin (66IN) to the output pins (66B[0:2]). The outputs’ variation of Tpd is described in the AC parameters section of this data sheet. The measurement is taken at 1.5V. 3V66 to PCI Unbuffered Clock Skew Figure 13 shows the timing relationship between 3V66(0:5) and PCI(0:6) and PCIF when configured to run in the unbuffered mode. 48MUSB 48MDOT Figure 10. 48M_USB and 48M_DOT Phase Relationship 66IN Tpd 66B Figure 11. 66IN to 66B(0:2) Output Delay Figure Rev 1.0, November 20, 2006 Page 12 of 19 CY28346-2 66B 1.53.5ns PCI PCIF Figure 12. Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship 3V66 Tpci PCI PCIF Figure 13. Unbuffered Mode – 3V66(0:5) to PCI (0:6) and PCIF(0:2) Phase Relationship Buffer Characteristics Current Mode CPU Clock Buffer Characteristics The current mode output buffer detail and current reference circuit details are contained in the previous table of this data sheet. The following parameters are used to specify output buffer characteristics: 1. Output impedance of the current mode buffer circuit – Ro (see Figure 14). 2. Minimum and maximum required voltage operation range of the circuit – Vop (see Figure 14). 3. Series resistance in the buffer circuit – Ros (see Figure 14). 4. Current accuracy at given configuration into nominal test load for given configuration. VDD3 (3.3V +/- 5%) Slope ~ 1/R0 Ro Iout Ros 0V 1.2V Iout Vout = 1.2V max Vout Figure 14. Rev 1.0, November 20, 2006 Page 13 of 19 CY28346-2 Absolute Maximum Conditions Parameter Description VDD Core Supply Voltage VDD_A Analog Supply Voltage VIN Input Voltage Condition Min. Max. Unit –0.5 4.6 V –0.5 4.6 V Relative to VSS –0.5 VDD + 0.5 VDC –65 150 °C 0 85 °C TS Temperature, Storage Non-functional TA Temperature, Operating Ambient Functional TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 – 45 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 15 °C/W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V Ul-94 Flammability Rating V–0 @1/8 in. 10 ppm MSL Moisture Sensitivity Level – 1 DC Parameters (VDD = VDDA = 3.3V ±5%) Parameter Description Conditions Min. Idd3.3V Dynamic Supply Current All frequencies at maximum values[3] Ipd3.3V Power-down Supply Current PD# Asserted Typ. Max. Unit 280 mA Note 4 mA Input Pin Capacitance 5 pF Cout Output Pin Capacitance 6 pF Lpin Pin Inductance 7 nH Cxtal Crystal Pin Capacitance 42 pF Cin Measured from the Xin or Xout Pin to Ground. 30 36 AC Parameters (VDD = VDDA = 3.3V ±5%) 66 MHz Parameter Description Min. Max. 100 MHz Min. Max. 133 MHz Min. Max. 200 MHz Min. Max. Unit Notes Crystal Tdc Xin Duty Cycle 47.5 52.5 47.5 52.5 47.5 52.5 47.5 52.5 % 5, 6, 7 Tperiod Xin Period 69.84 71.0 69.84 71.0 69.84 71.0 69.84 71.0 ns 5, 8, 9, 6 Vhigh Xin High Voltage 0.7Vdd Vdd 0.7Vdd Vdd 0.7Vdd Vdd 0.7Vdd Vdd V Vlow Xin Low Voltage 0 0.3Vdd 0 0.3Vdd 0 0.3Vdd 0 0.3Vdd V Tr/Tf Xin Rise and Fall Times 10.0 10.0 10.0 10.0 ns 10 Tccj Xin Cycle to Cycle Jitter 500 500 500 500 ps 8, 11, 6 CPU at 0.7V Timing Tdc CPUT and CPUC Duty Cycle Tperiod CPUT and CPUC Period 45 55 45 55 45 55 45 55 % 11, 12, 13 14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 11, 12, 13 Notes: 3. All outputs loaded as per maximum capacitive load table. 4. Absolute value = ((Programmed CPU Iref) x (2)) + 10 mA. 5. This parameter is measured as an average over 1-Ps duration, with a crystal center frequency of 14.31818 MHz 6. When Xin is driven from an external clock source. 7. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within data sheet specifications. 8. All outputs loaded as perTable 10. 9. Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet). 10. Measured between 0.2Vdd and 0.7Vdd. 11. This measurement is applicable with Spread ON or Spread OFF. 12. Measured at crossing point (Vx) or where subtraction of CLK-CLK# crosses 0 volts Measured from Vol = 0.175V to Voh = 0.525V. 13. Test load is Rta = 33.2 ohms, Rd = 49.9 ohms. Rev 1.0, November 20, 2006 Page 14 of 19 CY28346-2 AC Parameters (VDD = VDDA = 3.3V ±5%) (continued) 66 MHz Parameter Description Min. Max. 100 MHz Min. Max. 133 MHz Min. Max. 200 MHz Min. Max. Unit Notes Tskew Any CPU to CPU Clock Skew 100 100 100 100 ps 8, 11, 12 Tccj CPU Cycle to Cycle Jitter 150 150 150 150 ps 11, 12, 13 Tr/Tf CPUT and CPUC Rise and Fall Times 700 ps 11, Notes:, 16 175 Rise/Fall Matching 700 175 20% 700 175 20% 700 175 20% 20% Notes:, 15, 13 DeltaTr Rise Time Variation 125 125 125 125 ps Notes:, 13 DeltaTf Fall Time Variation 125 125 125 125 ps Notes:, 13 Vcross Crossing Point Voltage at 0.7V Swing CPU at 1.0V Timing Tdc CPUT and CPUC Duty Cycle 280 430 280 430 280 430 280 430 mV 11, 13 45 55 45 55 45 55 45 55 % 11, 12 14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 nS 11, 12 Tperiod CPUT and CPUC Period Tskew Any CPU to Any CPU Clock Skew 100 100 100 100 pS 8, 11, 12 Tccj CPU Cycle to Cycle Jitter 150 150 150 150 pS 8, 12 467 ps 11, 16 325 ps 17, 18 Differential CPUT and CPUC Tr/Tf Rise and Fall Times 175 467 175 467 175 467 175 SEDeltaSlew Absolute Singleended Rise/Fall Waveform Symmetry Vcross Cross Point at 1.0V swing 510 760 510 760 510 760 510 760 mV 18 3V66 Tdc 3V66 Duty Cycle 45 55 45 55 45 55 45 55 % 8, 9 Tperiod 3V66 Period 15.0 15.3 15.0 15.3 15.0 15.3 15.0 15.3 Thigh 3V66 High Time 4.95 Tlow 3V66 Low Time 4.55 Tr / Tf 3V66 Rise and Fall Times 0.5 325 325 4.95 4.95 4.55 2.0 0.5 325 4.95 4.55 2.0 0.5 4.55 2.0 0.5 2.0 ns 5, 8, 9 ns 19 ns 20 ns 21 Notes: 14. Measured from Vol = 0.175V to Voh = 0.525V. 15. Determined as a fraction of 2*(Trise – Tfall)/ (Trise + Tfall). 16. Measurement taken from differential waveform, from –0.35V to +0.35V. 17. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as “the instantaneous difference between maximum clk rise (fall) and minimum clk# fall (rise) time or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is designed form waveform symmetry. 18. Measured in absolute voltage, i.e. single-ended measurement. 19. THIGH is measured at 2.4V for non host outputs. 20. TLOW is measured at 0.4V for all outputs. 21. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data sheet). Rev 1.0, November 20, 2006 Page 15 of 19 CY28346-2 AC Parameters (VDD = VDDA = 3.3V ±5%) (continued) 66 MHz Parameter Description Min. Max. 100 MHz Min. Max. 133 MHz Min. Max. 200 MHz Min. Max. Unit Notes Tskew 3V66 to 3V66 Clock Unbuffered Skew 500 500 500 500 ps 8, 9 Tskew Buffered 3V66 to 3V66 Clock Skew 250 250 250 250 ps 8, 9 Tccj DRCG Cycle to Cycle Jitter 250 250 250 250 ps 8, 9 66B Tdc 66B(0:2) Duty Cycle 45 55 45 55 45 55 45 55 % 8, 9 Tr / Tf 66B(0:2) Rise and Fall Times 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 8, 21 Tskew Any 66B to Any 66B Skew 175 ps 8, 9 Tpd 66IN to 66B(0:2) Propagation Delay 4.5 ns 8, 9 Tccj 66B(0:2) Cycle to Cycle Jitter 100 ps 8, 9, 22 55 % 8, 9 PCI Tdc 175 2.5 4.5 175 2.5 100 2.5 100 100 Tperiod PCIF(0:2) PCI (0:6) period 30.0 30.0 30.0 30 nS 5, 8, 9 Thigh PCIF(0:2) PCI (0:6) high time 12.0 12.0 12.0 12.0 nS 19 Tlow PCIF(0:2) PCI (0:6) low time 12.0 12.0 12.0 12.0 nS 20 Tr/Tf PCIF(0:2) PCI (0:6) rise and fall times 0.5 2.0 nS 21 Tskew Any PCI clock to Any PCI clock Skew 500 500 500 500 pS 8, 9 Tccj PCIF(0:2) PCI (0:6) Cycle to Cycle Jitter 250 250 250 250 ps 8, 9 55 % 8, 9 ns 8, 9 2.10 ns 8, 21 350 ps 5, 8, 9 55 % 8, 9 Tperiod 48M_USB Period Tr/Tf 48M_USB Rise and Fall Times Tccj 48M_USB Cycle to Cycle Jitter 48M_DOT Tdc 48M_DOT Duty Cycle Tperiod 48M_DOT Period Tr/Tf 48M_DOT Rise and Fall Times Tccj 48M_DOT Cycle to Cycle Jitter 45 55 0.5 45 55 2.5 45 2.0 45 4.5 PCIF(0:2) PCI (0:6) Duty Cycle 48M_USB Tdc 48M_USB Duty Cycle 55 4.5 175 2.0 55 45 0.5 45 55 2.0 55 45 0.5 45 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 1.0 2.0 1.0 350 45 55 20.837 0.5 2.0 350 45 55 20.837 1.0 350 1.0 0.5 2.0 350 45 55 20.837 1.0 350 1.0 0.5 45 20.837 1.0 350 0.5 ns 8, 9 1.0 ns 8, 9 350 ps 8, 9 Note: 22. This figure is additive to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500-ps jitter figure is specified. Rev 1.0, November 20, 2006 Page 16 of 19 CY28346-2 AC Parameters (VDD = VDDA = 3.3V ±5%) (continued) 66 MHz Parameter Description Min. 100 MHz Max. Min. Max. 133 MHz Min. Max. REF Tdc REF Duty Cycle Tperiod REF Period Tr / Tf REF Rise and Fall Times Tccj REF Cycle to Cycle Jitter Tpzl/Tpzh Output Enable Delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 Tplz/Tpzh Output disable delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 Tstable All Clock Stabilization from Power-up Tss Stopclock Set-up Time Tsh Stopclock Hold Time Tsu Oscillator Start-up Time 200 MHz Min. Max. Unit Notes 45 55 45 55 45 55 45 55 % 8, 9 69.84 71.0 69.84 71.0 69.84 71.0 69.84 71.0 ns 8, 9 1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns 8, 21 1000 ps 8, 9 1.0 10.0 ns 6 1.0 10.0 ns 6 3 ms 6 1000 1000 3 1000 3 3 10.0 10.0 10.0 10.0 ns 23 0 0 0 0 ns 23 ms 24 1.2 1.2 1.2 1.2 Test and Measurement Set-up For Differential CPU Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs. T PC B : CPUT M easurem ent P oint 2p F : M U LT S E L CPUC : T PC B : : M easurem ent P oint 2p F : Figure 15. 1.0V Test Load Termination Notes: 23. CPU_STP# and PCI _STP# setup time with respect to any PCIF clock to guarantee that the effected clock will stop or start at the next PCIF clock’s rising edge. 24. When Crystal meets minimum 40-ohm device series resistance specification. Rev 1.0, November 20, 2006 Page 17 of 19 CY28346-2 TPCB : Measurement Point CPUT VDD : 2pF MULTSEL TPCB : Measurement Point CPUC 2pF : : Figure 16. 0.7V Test Load Termination For Single-Ended Output Signals Output under Test Probe Load Cap 3.3V signals tDC - - 3.3V 2.4V 1.5V 0.4V 0V Tr Tf Figure 17. Rev 1.0, November 20, 2006 Page 18 of 19 CY28346-2 Ordering Information Part Number Package Type Product Flow CY28346ZC-2 56-pin TSSOP–Tube Commercial, 0q to 70qC CY28346ZC-2T 56-pin TSSOP–Tape and Reel Commercial, 0q to 70qC CY28346ZI-2 56-pin TSSOP–Tube Industrial, 0q to 85qC CY28346ZI-2T 56-pin TSSOP–Tape and Reel Industrial, 0q to 85qC CY28346ZXC-2 56-pin TSSOP–Tube Commercial, 0q to 70qC CY28346ZXC-2T 56-pin TSSOP–Tape and Reel Commercial, 0q to 70qC Lead-free Package Drawings and Dimensions 56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56 0.249[0.009] 28 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 7.950[0.313] 8.255[0.325] PACKAGE WEIGHT 0.42gms 5.994[0.236] 6.198[0.244] PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. 29 56 13.894[0.547] 14.097[0.555] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] 0°-8° 0.508[0.020] 0.762[0.030] 0.100[0.003] 0.200[0.008] SEATING PLANE While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 20, 2006 Page 19 of 19