PD - 95483C
IRF1010EZPbF
IRF1010EZSPbF
IRF1010EZLPbF
Features
l
l
l
l
l
l
l
HEXFET® Power MOSFET
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
D
RDS(on) = 8.5mΩ
G
Description
ID = 75A
S
This HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating.These features
combine to make this design an extremely efficient
and reliable device for use in a wide variety of
applications.
VDSS = 60V
TO-220AB
IRF1010EZPbF
D2Pak
TO-262
IRF1010EZSPbF IRF1010EZLPbF
Absolute Maximum Ratings
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Parameter
84
A
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (See Fig. 9)
60
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Package Limited)
75
IDM
Pulsed Drain Current
340
PD @TC = 25°C
Maximum Power Dissipation
140
W
Linear Derating Factor
VGS
Gate-to-Source Voltage
0.90
± 20
W/°C
V
EAS
Single Pulse Avalanche Energy (Thermally Limited)
99
mJ
c
EAS (tested)
Single Pulse Avalanche Energy Tested Value
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
TJ
Operating Junction and
TSTG
Storage Temperature Range
c
i
d
h
180
See Fig.12a,12b,15,16
A
mJ
°C
-55 to + 175
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
Mounting torque, 6-32 or M3 screw
10 lbf•in (1.1N•m)
Thermal Resistance
Typ.
Max.
Units
RθJC
Junction-to-Case
Parameter
–––
1.11
°C/W
RθCS
Case-to-Sink, Flat, Greased Surface
0.50
–––
RθJA
Junction-to-Ambient
–––
62
RθJA
Junction-to-Ambient (PCB Mount, steady state)
–––
40
HEXFET®
j
is a registered trademark of International Rectifier.
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1
07/06/10
IRF1010EZ/S/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
∆ΒVDSS/∆TJ
RDS(on)
VGS(th)
Min. Typ. Max. Units
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
LD
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
60
–––
–––
2.0
200
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
LS
Internal Source Inductance
–––
7.5
–––
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
2810
420
200
1440
320
510
–––
–––
–––
–––
–––
–––
gfs
IDSS
IGSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
–––
–––
0.058 –––
6.8
8.5
–––
4.0
–––
–––
–––
20
–––
250
–––
200
––– -200
58
86
19
28
21
32
19
–––
90
–––
38
–––
54
–––
4.5
–––
V
V/°C
mΩ
V
S
µA
nA
nC
ns
nH
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 51A
VDS = VGS, ID = 100µA
VDS = 25V, ID = 51A
VDS = 60V, VGS = 0V
VDS = 60V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
ID = 51A
VDS = 48V
VGS = 10V
VDD = 30V
ID = 51A
RG = 7.95Ω
VGS = 10V
D
Between lead,
f
f
f
6mm (0.25in.)
from package
pF
G
S
and center of die contact
VGS = 0V
VDS = 25V
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 48V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 48V
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
84
ISM
(Body Diode)
Pulsed Source Current
–––
–––
340
VSD
trr
Qrr
ton
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
41
54
1.3
62
81
c
Conditions
MOSFET symbol
A
V
ns
nC
showing the
integral reverse
D
G
p-n junction diode.
TJ = 25°C, IS = 51A, VGS = 0V
TJ = 25°C, IF = 51A, VDD = 30V
di/dt = 100A/µs
S
f
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Coss eff. is a fixed capacitance that gives the same charging time
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
as Coss while VDS is rising from 0 to 80% VDSS .
Limited by TJmax, starting TJ = 25°C, L = 0.077mH, Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
RG = 25Ω, IAS = 51A, VGS =10V. Part not
avalanche performance.
recommended for use above this value.
This value determined from sample failure population. 100%
ISD ≤ 51A, di/dt ≤ 260A/µs, VDD ≤ V(BR)DSS,
tested to this value in production.
TJ ≤ 175°C.
This is applied to D2Pak, when mounted on 1" square PCB
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.
2
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IRF1010EZ/S/LPbF
10000
1000
1000
BOTTOM
100
100
10
1
4.5V
1
10
BOTTOM
10
4.5V
1
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
0.1
0.1
0.1
100
0.01
V DS, Drain-to-Source Voltage (V)
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
100
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current (Α)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
T J = 175°C
10
T J = 25°C
1
VDS = 25V
≤60µs PULSE WIDTH
90
T J = 25°C
80
70
60
50
T J = 175°C
40
30
20
10
0
0.1
4
5
6
7
8
9
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
0
20
40
60
80
100
120
140
ID,Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
vs. Drain Current
3
IRF1010EZ/S/LPbF
100000
12.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
ID= 51A
VGS, Gate-to-Source Voltage (V)
C rss = C gd
C, Capacitance(pF)
C oss = C ds + C gd
10000
Ciss
1000
Coss
Crss
VDS= 48V
VDS= 30V
10.0
VDS= 12V
8.0
6.0
4.0
2.0
0.0
100
1
10
100
0
0.10
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
50
60
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
100
T J = 175°C
T J = 25°C
VGS = 0V
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
40
10000
100.00
1.00
30
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
10.00
20
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
1000.00
10
1msec
10
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF1010EZ/S/LPbF
100
90
RDS(on) , Drain-to-Source On Resistance
(Normalized)
2.5
Limited By Package
ID, Drain Current (A)
80
70
60
50
40
30
20
10
0
ID = 84A
VGS = 10V
2.0
1.5
1.0
0.5
25
50
75
100
125
150
-60 -40 -20 0
175
T C , Case Temperature (°C)
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 10. Normalized On-Resistance
vs. Temperature
Fig 9. Maximum Drain Current vs.
Case Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.1
τJ
0.02
0.01
R1
R1
τJ
τ1
R2
R2
τ2
τ1
τ2
Ci= τi/Ri
Ci i/Ri
0.01
R3
R3
τ3
τC
τ
τ3
Ri (°C/W) τi (sec)
0.415
0.000246
0.410
0.000898
0.285
0.009546
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF1010EZ/S/LPbF
400
DRIVER
L
VDS
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
15V
ID
TOP
5.7A
9.1A
BOTTOM 51A
350
300
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGS
QGD
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
4.5
4.0
3.5
3.0
ID = 250µA
2.5
2.0
1.5
1.0
-75 -50 -25
VGS
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage vs. Temperature
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IRF1010EZ/S/LPbF
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
0.01
0.05
10
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
100
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 51A
75
50
25
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
vs. Temperature
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175
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRF1010EZ/S/LPbF
D.U.T
Driver Gate Drive
+
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
*
RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
Period
P.W.
+
V DD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRF1010EZ/S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
AS SEMBLED ON WW 19, 2000
IN T HE AS S EMBLY LINE "C"
Note: "P" in assembly line position
indicates "Lead - Free"
INTERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 19
LINE C
Notes:
1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/datasheets/data/auirf1010ez.pdf
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
IRF1010EZ/S/LPbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
THIS IS AN IRF530S WITH
LOT CODE 8024
ASSEMBLED ON WW 02, 2000
IN THE ASS EMBLY LINE "L"
INTERNAT IONAL
RECT IFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
F530S
DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L
OR
INT ERNAT IONAL
RECT IFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
F530S
DATE CODE
P = DESIGNATES LEAD - FREE
PRODUCT (OPTIONAL)
YEAR 0 = 2000
WEEK 02
A = ASS EMB LY SITE CODE
Notes:
1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/datasheets/data/auirf1010ez.pdf
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRF1010EZ/S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
AS S EMBLE D ON WW 19, 1997
IN THE AS S E MBLY LINE "C"
INTERNATIONAL
RECTIFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBE R
DATE CODE
YEAR 7 = 1997
WEE K 19
LINE C
OR
INTERNATIONAL
RECTIFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DATE CODE
P = DES IGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEE K 19
A = AS S EMBLY S ITE CODE
Notes:
1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/datasheets/data/auirf1010ez.pdf
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
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11
IRF1010EZ/S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
3
4
TO-220AB package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/2010
12
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