MOTOROLA MPC961C Low voltage zero delay buffer Datasheet

Freescale Semiconductor, Inc.
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
Low Voltage Zero Delay
Buffer
MPC961C
Freescale Semiconductor, Inc...
The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay
buffer. With output frequencies of up to 200MHz, output skews of 150ps
the device meets the needs of the most demanding clock tree
applications.
•
•
•
•
•
•
•
•
LOW VOLTAGE
ZERO DELAY BUFFER
Fully Integrated PLL
Up to 200MHz I/O Frequency
LVCMOS Outputs
Outputs Disable in High Impedance
LVCMOS Reference Clock Options
LQFP Packaging
±50ps Cycle–Cycle Jitter
150ps Output Skews
The MPC961 is offered with two different input configurations. The
MPC961C offers an LVCMOS reference clock while the MPC961P offers
an LVPECL reference clock.
When pulled high the OE pin will force all of the outputs (except QFB)
into a high impedance state. Because the OE pin does not affect the QFB
output, down stream clocks can be disabled without the internal PLL
losing lock.
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A–02
The MPC961 is fully 2.5V or 3.3V compatible and requires no external
loop filter components. All control inputs accept LVCMOS compatible
levels and the outputs provide low impedance LVCMOS outputs capable
of driving terminated 50 transmission lines. For series terminated lines
the MPC961 can drive two lines per output giving the device an effective
fanout of 1:36. The device is packaged in a 32 lead LQFP.
W
Q0
CCLK
50k
FB_IN
Q1
Ref PLL
100 – 200 MHz
O
Q2
50 – 100 MHz
1
Q3
FB
50k
Q14
F_RANGE
Q15
50k
Q16
OE
50k
QFB
The MPC961C requires an external RC filter for the analog power supply pin VCCA. Please see applications section for details.
Figure 1. MPC961C Logic Diagram
03/01
 Motorola, Inc. 2001
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VCC
Q6
Q7
Q8
GND
Q9
Q10
Q11
MPC961C
24
23
22
21
20
19
18
17
Q5
25
16
VCC
Q4
26
15
Q12
Q3
27
14
Q13
GND
28
13
Q14
Q15
Q0
31
10
Q16
VCC
32
9
QFB
1
2
3
4
5
6
7
8
VCC
11
FB_IN
30
OE
Q1
VCCA
GND
F_RANGE
12
NC
29
CCLK
Q2
GND
Freescale Semiconductor, Inc...
MPC961C
Figure 2. 32–Lead Pinout (Top View)
Table 1: PIN CONFIGURATIONS
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
PLL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to a QFB output
F_RANGE
Input
LVCMOS
PLL frequency range select
OE
Input
LVCMOS
Output enable/disable
Q0 - Q16
Output
LVCMOS
Clock outputs
QFB
Output
LVCMOS
PLL feedback signal output, connect to a FB_IN
GND
Supply
Ground
Negative power supply
VCCA
Supply
VCC
PLL positive power supply (analog power supply). The MPC961C requires
an external RC filter for the analog power supply pin VCCA. Please see applications section for details.
VCC
Supply
VCC
Positive power supply for I/O and core
NC
Not connected
Table 2: FUNCTION TABLE
Control
Default
0
1
F_RANGE
0
PLL high frequency range. MPC961C input reference
and output clock frequency range is 100 – 200 MHz
PLL low frequency range. MPC961C input reference
and output clock frequency range is 50 – 100 MHz
OE
0
Outputs enabled
Outputs disabled (high–impedance state)
MOTOROLA
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MPC961C
Table 3: ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
3.6
V
VIN
DC Input Voltage
–0.3
VCC + 0.3
V
VOUT
DC Output Voltage
–0.3
VCC + 0.3
V
IIN
DC Input Current
±20
mA
IOUT
DC Output Current
±50
mA
TS
Storage Temperature Range
125
°C
–40
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
Freescale Semiconductor, Inc...
Table 4: DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
VOH
Input LOW Voltage
–0.3
0.8
V
LVCMOS
Output HIGH Voltage
2.4
V
VOL
Output LOW Voltage
IOH = –20mAa
IOL = 20mAa
ZOUT
Output Impedance
IIN
Input Current
CIN
Input Capacitance
4.0
CPD
Power Dissipation Capacitance
8.0
10
pF
Per Output
ICCA
Maximum PLL Supply Current
2.0
5.0
mA
VCCA Pin
ICC
Maximum Quiescent Supply Current
mA
All VCC Pins
VTT
Output Termination Voltage
0.55
14
VCC
V
20
W
±120
µA
pF
B2
V
a. The MPC961C is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50Ω series terminated transmission lines.
Table 5: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C)a
Max
Unit
fref
Symbol
Input Frequency
Characteristic
F_RANGE = 0
F_RANGE = 1
Min
100
50
200
100
MHz
fmax
Maximum Output Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
frefDC
Reference Input Duty Cycle
tr, tf
TCLK Input Rise/Fall Time
t(∅)
Propagation Delay
(static phase offset)
tsk(O)
Output–to–Output Skewb
DCO
Output Duty Cycle
tr, tf
Output Rise/Fall Time
tPLZ,HZ
Output Disable Time
tPZL,LZ
Output Enable Time
tJIT(CC)
Cycle–to–Cycle Jitter
tJIT(PER)
Period Jitter
tJIT(∅)
I/O Phase Jitter
tlock
Maximum PLL Lock Time
25
CCLK to FB_IN
–80
F_RANGE = 0
F_RANGE = 1
42
45
s)c
RMS (1 s)
RMS (1 s)
Condition
75
%
3.0
ns
0.8 to 2.0V
120
ps
PLL locked
90
150
ps
50
50
55
55
%
1.0
ns
10
ns
10
ns
15
ps
10
ps
15
ns
10
ms
0.1
RMS (1
7.0
0.55 to 2.4V
W
a. AC characteristics apply for parallel output termination of 50 to VTT
b. See applications section for part–to–part skew calculation
c. See applications section for calculation for other confidence factors than 1
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Typ
s
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MPC961C
Table 6: DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)
Freescale Semiconductor, Inc...
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
VOH
Input LOW Voltage
–0.3
0.7
V
LVCMOS
Output HIGH Voltage
1.8
V
VOL
Output LOW Voltage
IOH = –15mAa
IOL = 15mAa
ZOUT
Output Impedance
IIN
Input Current
CIN
Input Capacitance
4.0
CPD
Power Dissipation Capacitance
8.0
10
pF
Per Output
ICCA
Maximum PLL Supply Current
2.0
5.0
mA
VCCA Pin
ICC
Maximum Quiescent Supply Current
mA
All VCC Pins
0.6
18
V
26
W
±120
µA
pF
B
VTT
Output Termination Voltage
VCC
2
V
a. The MPC961C is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50Ω series terminated transmission lines.
Table 7: AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)a
Max
Unit
fref
Symbol
Input Frequency
Characteristic
F_RANGE = 0
F_RANGE = 1
Min
100
50
Typ
200
100
MHz
fmax
Maximum Output Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
frefDC
Reference Input Duty Cycle
tr, tf
TCLK Input Rise/Fall Time
t(∅)
Propagation Delay
(static phase offset)
tsk(O)
Output–to–Output Skewb
DCO
Output Duty Cycle
tr, tf
Output Rise/Fall Time
tPLZ,HZ
Output Disable Time
tPZL,LZ
Output Enable Time
tJIT(CC)
Cycle–to–Cycle Jitter
tJIT(PER)
Period Jitter
tJIT(∅)
I/O Phase Jitter
25
CCLK to FB_IN
–80
F_RANGE = 0
F_RANGE = 1
40
45
75
%
3.0
ns
0.7 to 1.7V
120
ps
PLL locked
90
150
ps
50
50
60
55
%
1.0
ns
10
ns
10
ns
15
ps
10
ps
15
ns
10
ms
0.1
s)c
RMS (1 s)
RMS (1 s)
RMS (1
tlock
Maximum PLL Lock Time
a. AC characteristics apply for parallel output termination of 50 to VTT
b. See applications section for part–to–part skew calculation
c. See applications section for calculation for other confidence factors than 1
7.0
W
MOTOROLA
Condition
0.6 to 1.8V
s
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MPC961C
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Power Supply Filtering
The MPC961C is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC961C provides separate
power supplies for the output buffers (VCC) and the
phase–locked loop (VCCA) of the device. The purpose of this
design technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC961C.
Figure 3. illustrates a typical power supply filter scheme.
The MPC961C is most susceptible to noise with spectral
content in the 10kHz to 10MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC961C. From the data sheet the ICCA current
(the current sourced through the VCCA pin) is typically 2mA
(5mA maximum), assuming that a minimum of 2.375V (VCC =
3.3V or VCC = 2.5V) must be maintained on the VCCA pin.
The resistor RF shown in Figure 3. must have a resistance of
270Ω (VCC = 3.3V) or 5 to 15Ω (VCC = 2.5V) to meet the
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20kHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL.
RF = 270Ω for VCC = 3.3V
RF = 5–15Ω for VCC = 2.5V
adequate to eliminate power supply noise related problems
in most designs.
Driving Transmission Lines
The MPC961C clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 15Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091.
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC961C clock driver. For
the series terminated case however there is no DC current
draw, thus the outputs can drive multiple series terminated
lines. Figure 4. illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC961C clock
driver is effectively doubled due to its capability to drive
multiple lines.
MPC961
OUTPUT
BUFFER
IN
14Ω
MPC961
OUTPUT
BUFFER
IN
RS = 36Ω
ZO = 50Ω
OutA
RS = 36Ω
ZO = 50Ω
OutB0
14Ω
RS = 36Ω
ZO = 50Ω
OutB1
RF
VCCA
VCC
22 µF
10 nF
MPC961C
Figure 4. Single versus Dual Transmission Lines
VCC
33...100 nF
Figure 3. Power Supply Filter
Although the MPC961C has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
TIMING SOLUTIONS
DL207 — Rev 0
The waveform plots of Figure 5. show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC961C output buffer is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC961C. The output
waveform in Figure 5. shows a step in the waveform, this
step is caused by the impedance mismatch seen looking into
the driver. The parallel combination of the 36Ω series resistor
plus the output impedance does not match the parallel
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combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50Ω || 50Ω
Rs = 36Ω || 36Ω
Ro = 14Ω
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.62V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
2.5
VOLTAGE (V)
Freescale Semiconductor, Inc...
3.0
OutA
tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
SPICE level and IBIS output buffer models are available
for engineers who want to simulate their specific interconnect
schemes.
Using the MPC961C in zero-delay applications
Nested clock trees are typical applications for the
MPC961C. Designs using the MPC961C as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC961C clock driver allows for its use as a zero delay
buffer. By using the QFB output as a feedback to the PLL the
propagation delay through the device is virtually eliminated.
The PLL aligns the feedback clock output edge with the clock
input reference edge resulting a near zero delay through the
device. The maximum insertion delay of the device in
zero-delay applications is measured between the reference
clock input and any output. This effective delay consists of
the static phase offset, I/O jitter (phase or long-term jitter),
feedback path delay and the output-to-output skew error
relative to the feedback output.
Calculation of part-to-part skew
The MPC961C zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC961C are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
1.0
0.5
0
2
4
6
8
TIME (nS)
10
12
14
Figure 5. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 6. should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
MPC961
OUTPUT
BUFFER
tSK(PP) = t( ∅) + tSK(O) + tPD, LINE(FB) + tJIT( ∅) CF
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
CCLKCommon
QFBDevice 1
tJIT(∅)
Any QDevice 1
+tSK(O)
+t(∅)
RS = 22Ω
ZO = 50Ω
RS = 22Ω
ZO = 50Ω
14Ω
QFBDevice2
Any QDevice 2
Max. skew
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 6. Optimized Dual Line Termination
MOTOROLA
tPD,LINE(FB)
–t(∅)
tJIT(∅)
+tSK(O)
tSK(PP)
Figure 7. MPC961C max. device-to-device skew
Due to the statistical nature of I/O jitter a rms value (1 s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
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convection and thermal conductivity of package and board.
This section describes the impact of these parameters on the
junction temperature and gives a guideline to estimate the
MPC961C die junction temperature and the associated
device reliability. For a complete analysis of power
consumption as a function of operating conditions and
associated long term device reliability please refer to the
application note AN1545. According the AN1545, the
long-term device reliability is a function of the die junction
temperature:
Freescale Semiconductor, Inc...
Table 8: Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1s
0.68268948
± 2s
0.95449988
± 3s
0.99730007
± 4s
0.99993663
± 5s
0.99999943
± 6s
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3s) is assumed,
resulting in a worst case timing uncertainty from input to any
output of -275 ps to 315 ps relative to CCLK:
tSK(PP) =
[–80ps...120ps] + [–150ps...150ps] +
[(15ps –3)...(15ps 3)] + tPD, LINE(FB)
tSK(PP) =
[–275ps...315ps] + tPD, LINE(FB)
@
Table 9: Die junction temperature and MTBF
@
Junction temperature (°C)
MTBF (Years)
100
20.4
110
9.1
120
4.2
130
2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable MTBF,
the die junction temperature of the MPC961C needs to be
controlled and the thermal impedance of the board/package
should be optimized. The power dissipated in the MPC961C
is represented in equation 1.
Due to the frequency dependence of the I/O jitter,
Figure 8. “Max. I/O Jitter versus frequency” can be used for
a more precise timing performance analysis.
Where ICCQ is the static current consumption of the
MPC961C, CPD is the power dissipation capacitance per
output, (Μ)ΣCL represents the external capacitive output
load, N is the number of active outputs (N is always 27 in
case of the MPC961C). The MPC961C supports driving
transmission lines to maintain high signal integrity and tight
timing parameters. Any transmission line will hide the lumped
capacitive load at the end of the board trace, therefore, ΣCL is
zero for controlled transmission line systems and can be
eliminated from equation 1. Using parallel termination output
termination results in equation 2 for power dissipation.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, VOL, IOL, VOH and IOH are a
function of the output termination technique and DCQ is the
clock signal duty cyle. If transmission lines are used ΣCL is
zero in equation 2 and can be eliminated. In general, the use
of controlled transmission line techniques eliminates the
impact of the lumped capacitive loads at the end lines and
greatly reduces the power dissipation of the device. Equation
3 describes the die junction temperature TJ as a function of
the power consumption.
Figure 8. Max. I/O Jitter versus frequency
Power Consumption of the MPC961C and Thermal
Management
The MPC961C AC specification is guaranteed for the
entire operating frequency range up to 200 MHz. The
MPC961C power consumption and the associated long-term
reliability may decrease the maximum frequency limit,
depending on operating conditions such as clock frequency,
supply voltage, output loading, ambient temperature, vertical
P TOT
+V @
CC
ƪ
P TOT
I CCQ
+
ƪ
)V @f
CC
I CCQ
CLOCK
)V @f
ǒ
CC
@ [email protected]
TJ
f CLOCK,MAX
TIMING SOLUTIONS
DL207 — Rev 0
ȍ
)ȍ
) ȍƪ
PD
CL
M
Ǔƫ
+T )P @R
A
+ C @ N1 @ V @
PD
ǒ
@ [email protected] )
CLOCK
2
CC
ƪ
TOT
PD
CL
M
DC Q
P
Ǔƫ
@V
@ I @ ǒV * V Ǔ ) ǒ1 * DC Ǔ @ I @ V
OH
thja
* * ǒI @ V
T J,MAX T A
R thja
CCQ
Equation 1
CC
CC
CC
OH
ƫ
Ǔ
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Q
OL
OL
ƫ
Equation 2
Equation 3
Equation 4
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MPC961C
Where Rthja is the thermal impedance of the package
(junction to ambient) and TA is the ambient temperature.
According to Table 9, the junction temperature can be used to
estimate the long-term device reliability. Further, combining
equation 1 and equation 2 results in a maximum operating
frequency for the MPC961C in a series terminated
transmission line system.
Convection, LFPM
Rthja (1P2S board), K/W
Still air
80
100 lfpm
70
200 lfpm
61
300 lfpm
57
400 lfpm
56
500 lfpm
55
200
If the calculated maximum frequency is below 200 MHz, it
becomes the upper clock speed limit for the given application
conditions. The following two derating charts describe the
safe frequency operation range for the MPC961C. The charts
were calculated for a maximum tolerable die junction
temperature of 110°C, corresponding to an estimated MTBF
of 9.1 years, a supply voltage of 3.3V and series terminated
transmission line or capacitive loading. Depending on a given
set of these operating conditions and the available device
convection a decision on the maximum operating frequency
can be made. There are no operating frequency limitations if
a 2.5V power supply or the system specifications allow for a
MTBF of 4 years (corresponding to a max. junction
temperature of 120°C.
200
fMAX (AC)
180
OPERATING FREQUENCY (MHz)
OPERATING FREQUENCY (MHz)
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Table 10: Thermal package impedance of the 32ld
LQFP
TJ,MAX should be selected according to the MTBF system
requirements and Table 9. Rthja can be derived from Table 10.
The Rthja represent data based on 1S2P boards, using 2S2P
boards will result in a lower thermal impedance than
indicated below.
TA = 85°C
160
140
120
100
80
60
Safe operation
40
20
fMAX (AC)
180
TA = 75°C
160
140
TA = 85°C
120
100
80
60
Safe operation
40
20
0
0
500
400
300
200
IFPM, CONVECTION
100
0
Figure 9. Maximum MPC961C frequency, VCC = 3.3V, MTBF
9.1 years, driving series terminated transmission lines
500
400
300
200
IFPM, CONVECTION
100
0
Figure 10. Maximum MPC961C frequency,
VCC = 3.3V, MTBF 9.1 years, 4 pF load per line
MPC961C DUT
Pulse
Generator
Z = 50
ZO = 50Ω
ZO = 50Ω
W
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 11. TCLK MPC961C AC test reference for Vcc = 3.3V and Vcc = 2.5V
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TIMING SOLUTIONS
DL207 — Rev 0
Freescale Semiconductor, Inc.
MPC961C
VCC
VCC 2
B
GND
VCC
VCC 2
B
CCLK
GND
VOH
VCC 2
B
GND
VCC
VCC 2
B
FB_IN
GND
tSK(O)
t(∅)
The pin–to–pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device
Freescale Semiconductor, Inc...
Figure 12. Output–to–output Skew tSK(O)
VCC
VCC 2
B
Figure 13. Propagation delay (tPD, static phase
offset) test reference
CCLK
GND
tP
FB_IN
T0
DC = tP /T0 x 100%
TJIT 〈∅) = |T0 –T1 mean|
The time from the PLL controlled edge to the non controlled edge,
divided by the time between PLL controlled edges, expressed as a
percentage
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles
Figure 14. Output Duty Cycle (DC)
TN
TN+1
TJIT(CC) = |TN –TN+1 |
TJIT(PER) = |TN –1/f0 |
T0
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
Figure 16. Cycle–to–cycle Jitter
tF
Figure 15. I/O Jitter
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
Figure 17. Period Jitter
VCC=3.3V
2.4
VCC=2.5V
1.8V
0.55
0.6V
tR
Figure 18. Output Transition Time Test
Reference
TIMING SOLUTIONS
DL207 — Rev 0
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Freescale Semiconductor, Inc.
MPC961C
OUTLINE DIMENSIONS
A
–T–, –U–, –Z–
FA SUFFIX
LQFP PACKAGE
CASE 873A–02
ISSUE A
4X
A1
32
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
AE
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
G
–AB–
0.10 (0.004) AC
AC T–U Z
–AC–
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
ÉÉ
F
8X
M_
R
J
D
SECTION AE–AE
H
W
K
X
DETAIL AD
Q_
0.250 (0.010)
C E
MOTOROLA
M
N
0.20 (0.008)
SEATING
PLANE
GAUGE PLANE
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P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
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INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
TIMING SOLUTIONS
DL207 — Rev 0
Freescale Semiconductor, Inc.
MPC961C
Freescale Semiconductor, Inc...
NOTES
TIMING SOLUTIONS
DL207 — Rev 0
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MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MPC961C
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TIMING
SOLUTIONS
MPC961C/D
DL207 — Rev 0
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