Sony CXA1782CQ Rf signal processing servo amplifier for cd player Datasheet

CXA1782CQ/CR
RF Signal Processing Servo Amplifier for CD players
For the availability of this product, please contact the sales office.
Description
The CXA1782CQ/CR is a bipolar IC with built-in
RF signal processing and various servo ICs. A CD
player servo can be configured by using this IC,
DSP and driver.
Features
• Low operating voltage (VCC – VEE = 3.0 to 11.0V)
• Low power consumption (39mW, VCC = 3.0V)
• Supports pickup of either current output, voltage
output
• Automatic adjustment comparator for tracking
balance gain
• Single power supply and positive/negative dual
power supplies
Applications
• RF I-V amplifier, RF amplifier
• Focus and tracking error amplifier
• APC circuit
• Mirror detection circuit
• Defect detection and prevention circuits
• Focus servo control
• Tracking servo control
• Sled servo control
• Comparators of tracking adjustment for balance
and gain
CXA1782CQ
48 pin QFP (Plastic)
CXA1782CR
48 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
12
V
• Supply voltage
VCC
• Operating temperature Topr
–20 to +75
°C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation
PD
833 (CXA1782CQ) mW
457 (CXA1782CR) mW
Recommended Operating Condition
Operating supply voltage
VCC – VEE 3.0 to 11.0
V
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95908C78
CXA1782CQ/CR
PHD2
PHD1
PHD
LD
RF_M
RF_O
RF_I
CP
CB
CC1
CC2
FOK
Block Diagram
36
35
34
33
32
31
30
29
28
27
26
25
APC
LEVEL S
I IL
24 SENS
TTL
23 C.OUT
RF IV AMP1
22 XRST
MIRR
FOK
DFCT
TTL
21 DATA
RF IV AMP2
FE_BIAS 37
•I IL DATA REGISTER •INPUT SHIFT REGISTER
•ADRESS.DECODER
TTL
FE AMP
F 38
I IL
I IL
•OUTPUT DECODER
20 XLT
19 CLK
F IV AMP
E 39
TOG1 to 3 FS1 to 4 TG1 to 2 TM1 to 7
BAL1 to 3
FZC COMP
PS1 to 4
18 Vcc
E IV AMP
EI 40
BAL2
HPF COMP LPF COMP
BAL3
BAL1
TE AMP
•TRACKING
PHASE COMPENSATION
•I SET
17 ISET
TM6
VEE 41
16 SL_O
TEO 42
TG1
TOG3
TOG2
TOG1
TM5
15 SL_M
TM4
TZC COMP
LPFI 43
ATSC 45
TZC 46
•FCS PHASE COMPENSATION
DFCT
TEI 44
TM1
TM2
TM3
FS1
•WINDOW COMP.
13 TA_O
TM7
ATSC
FS2
TDFCT 47
•
•
•
•
•F SET
TG2
DFCT
VC 48
14 SL_P
FGD
FLB
8
9
10
11
12
TA_M
FDFCT
7
FSET
FEI
6
TG2
5
TGU
4
SRCH
3
FE_M
2
FE_O
1
FEO
FS4
The switch state in Block Diagram is for initial resetting.
Switch turns to ° side for 1 and to • side for 0 in Serial Data Truth Table.
DFCT switch turns to ° side when defect signal generates for DEFECT = E in Serial Data Truth Table.
TG1 switch turns to ° side and TG2 switch is left open when TG1 and TG2 (address 1 : D3) is 1.
–2–
CXA1782CQ/CR
Pin Description
Pin
No.
Symbol
I/O
Equivalent circuit
Description
25p
147
1
FEO
O
1
174k
51k
Focus error amplifier output.
Connected internally to the FZC
comparator input.
300µ
10k
2
FEI
I
9k
Focus error input.
147
2
100k
147
3
FDFCT
I
Capacitor connection pin for defect
time constant.
3
68k
147
4
FGD
I
4
130k
5
FLB
I
6
FE_O
O
20µ
Ground this pin through a capacitor
when decreasing the focus servo
high-frequency gain.
External time constant setting pin
for increasing the focus servo lowfrequency.
40k
5
Focus drive output.
6
13
TA_O
O
Tracking drive output.
13
16
16
SL_O
250µ
O
147
7
FE_M
I
Sled drive output.
90k
Focus amplifier inverted input.
7
50k
–3–
CXA1782CQ/CR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
147
8
SRCH
I
External time constant setting pin for
generating focus servo waveform.
8
11µ
50k
110k
9
TGU
External time constant setting pin for
switching tracking high-frequency
gain.
20k
I
9
82k
10
TG2
I
External time constant setting pin for
switching tracking high-frequency
gain.
10
470k
2µ
High cut-off frequency setting pin for
focus and tracking phase
compensation amplifier.
147k
11
FSET
I
11
15k
15k
100k
12
TA_M
I
147
Tracking amplifier inverted input.
12
11µ
14
SL_P
I
15
SL_M
I
147
Sled amplifier non-inverted input.
14
147
Sled amplifier inverted input.
15
22µ
–4–
CXA1782CQ/CR
Pin
No.
Symbol
I/O
Description
Equivalent circuit
147
17
ISET
I
19
CLK
I
Setting pin for Focus search, Track
jump, and Sled kick current.
17
Serial data transfer clock input from
CPU. (no pull-up resistance)
15µ
20
XLT
I
19
147
Latch input from CPU.
(no pull-up resistance)
1k
20
21
DATA
I
Serial data input from CPU.
(no pull-up resistance)
21
22
22
XRST
I
23
C. OUT
O
Reset input; resets at Low.
(no pull-up resistance)
Track number count signal output.
20k
147
23
24
24
SENS
O
Outputs FZC, DFCT, TZC, gain,
balance, and others according to
the command from CPU.
100k
20k
25
FOK
147
O
Focus OK comparator output.
40k
25
100k
26
CC2
Input for the DEFECT bottom hold
output with capacitance coupled.
I
147
147
27
28
27
CC1
O
DEFECT bottom hold output.
147
26
28
CB
Connection pin for DEFECT bottom
hold capacitor.
I
–5–
CXA1782CQ/CR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
147
29
CP
I
Connection pin for MIRR hold
capacitor.
MIRR comparator non-inverted
input.
30
RF_I
I
Input for the RF summing amplifier
output with capacitance coupled.
29
147
30
31
RF_O
RF sunning amplifier output.
Eye-pattern check point.
O
147
147
31
32
32
RF_M
I
RF summing amplifier inverted
input.
The RF amplifier gain is determined
by the resistance connected
between this pin and RFO pin.
10k
1k
33
LD
O
APC amplifier output.
33
17µ
34
PHD
I
147
APC amplifier input.
34
10k
35
36
PHD1
PHD2
I
I
147
35
36
100µ
–6–
11.6k
RF I-V amplifier inverted input.
Connect these pins to the photo
diode A + C and B + D pins.
CXA1782CQ/CR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
32k
164k
37
FE_BIAS
I
Bias adjustment of focus error
amplifier.
37
25p
8µ
12p
260k
38
39
F
E
I
I
147
38
39
513
F I-V and E I-V amplifier inverted
input.
Connect these pins to photo diodes
F and E.
10µ
6.8k 102k 57k
I-V amplifier E gain adjustment.
(When not using automatic balance
adjustment)
260k
40
EI
—
40
20.3k
147
42
TEO
O
42
28k
12k 23k 11k
4.8k
150k
10k
Tracking error amplifier output.
E-F signal is output.
150k
Comparator input for balance
adjustment.
(Input from TEO through LPF)
147
43
LPFI
I
43
–7–
CXA1782CQ/CR
Pin
No.
44
Symbol
TEI
I/O
Description
Equivalent circuit
I
Tracking error input.
100k
147
44
147
47
TDFCT
Capacitor connection pin for defect
time constant.
47
I
1k
100k
10k
45
ATSC
I
Window comparator input for ATSC
detection.
45
100k
1k
10k
46
TZC
I
Tracking zero-cross comparator
input.
46
75k
48
VC
O
50
120
(VCC + VEE)/2 DC voltage output.
48
120
VC
–8–
–9–
O
1
10
11
12
13
14
15
16
17
18
3F
RST
Voltage gain E0
Voltage gain E1
Voltage gain E2
T19
T20
Voltage gain F3
O
O
2.4
–0.6
0.1
0.4
V1 = 1kHz TOG1, 2, 3: OFF
V1 = 1kHz BAL1: ON
Reference to E0
V1 = 1kHz BAL2: ON
Reference to E0
37
35
36
–6.19
–6.69
V1 = 1kHz TOG3: ON
Reference to F0
3B
0.7
0.4
–3.43
–1.83
3.5
0
–1.3
1.3
–3.93
0.5
–25
—
1.0
0
–3.0
30.0
27.0
30.0
0
–120
27.0
–0.9
1.3
1.2
—
28.1
25.1
0
–14
14
Typ.
V1 = 1kHz TOG2: ON
Reference to F0
V1 = 1kHz TOG1, 2, 3: OFF
V1 = 100mVDC
V1 = 100mVDC
V1 = 1kHz I/O ratio
V1 = 1kHz I/O ratio
V1 = –100mVDC
V1 = 100mVDC
1kHz input ratio
–50
–20
10
Min.
Ratings
–2.33
42
1
31
41
18
Measurement conditions
1.0
0.7
5.4
–5.69
–2.93
–1.33
6.5
25
–1.0
—
3.0
33.0
33.0
120
–0.3
—
31.1
50
–10
20
Max.
dB
dB
dB
dB
dB
dB
dB
mV
V
V
dB
dB
dB
mV
V
V
dB
mV
mA
mA
Unit
(VCC = 1.5V, VEE = –1.5V, Ta = 25°C)
V1 = 1kHz TOG1: ON
Reference to F0
O
9
3D
8
O
7
Voltage gain F2
6
3E
5
O
O
4
Voltage gain F1
O
O
3
Measure-
SD ment pin
O
O
O
O
O
2
SW conditions
Voltage gain F0
Offset
Max. output voltage-Low
Max. output voltage-High
Voltage gain difference
Voltage gain 1
Voltage gain 1
Offset
Max. output voltage-Low
Max. output voltage-High O
Voltage gain
T18
T17
T16
T15
T14
T13
T12
T11
T10
T9
T8
T7
T6
T5
T4
Offset
Current consumption 2
T2
FE amplifier
TE amplifier
T3
Current consumption 1
RF amplifier
T1
Item
Electrical Characteristics
CXA1782CQ/CR
O
O
13
14
15
O
16
17
– 10 –
T40
T39
T38
T37
T36
T35
T34
T33
T32
T31
T30
T26
T25
APC
FCS servo
TRK servo
T24
–180
–200
V2 = 170mV
0.8mA sink
00
FZC threshold
Output gain difference between
SD = 20 and SD = 25.
O
O
Feed through
Max. output voltage-High
V1 = –0.5VDC
T37 + T14
13
Pin 1 threshold (preliminary)
TRK total gain
25
03
Search voltage (+)
DC voltage gain
02
Search voltage (–)
08
1.0
16.1
12.25
185
360
–640
1.3
18.1
14.6
225
500
–500
–1.3
–39
20.1
17.6
265
640
–360
–1.0
—
V1 = –200mVDC
O
Max. output voltage-Low
O
—
1.3
1.0
V1 = 200mVDC
08
O
Max. output voltage-High
53
24
100
500
1120
380
–480
–0.5
—
1.68
–35
51
21.0
–0.6
0.6
1.38
Max.
Output gain difference between
SD = 00 and SD = 08.
49
18
–100
–900
V2 = 145mV
—
V1 = 1VDC BAL2: ON
–900
0.5
V1 = 1VDC BAL2: ON
V2 = 120mV
1.08
V1 = 1kHz BAL3: ON
Reference to E0
Typ.
O
24
6
48
33
42
Min.
Ratings
Feed through
00
08
3F
3F
33
Measurement conditions
T29 + T8 (or T9)
18
Measure-
SD ment pin
FCS total gain
DC voltage gain
12
T29
O
11
Center amplifier output
offset
O
10
T28
O
9
O
8
Output voltage 4
7
T27
O
6
O
5
Output voltage 3
O
O
4
O
O
3
Output voltage 2
2
O
Max. output voltage-Low
Max. output voltage-High
Voltage gain E3
1
SW conditions
Output voltage 1
T23
T22
T21
TE amplifier
Item
V
dB
dB
dB
mV
mV
mV
V
V
dB
dB
dB
mV
mV
mV
mV
mV
V
V
dB
Unit
CXA1782CQ/CR
25
O
O
Max. output voltage-Low
T62
T61
T60
T59
T58
T57
T56
T55
T54
T53
O
O
O
O
Min. input operating voltage
Max. input operating voltage
O
O
Min. input operating voltage O
O
Max. input operating voltage
O
O
Max. operating frequency
Min. operating frequency O
O
O
10
14
23
24
Measures at SENS pin.
Measures at SENS pin.
Measures at SENS pin.
Measures at SENS pin.
Measures at C. OUT pin.
Measures at C. OUT pin.
Measures at C. OUT pin.
1.8
2.5
1.8
30
600
450
22
Kick voltage (+)
Max. operating frequency
–600
–750
–1.3
1.3
23
1.0
50
Kick voltage (–)
V1 = –0.4VDC
V1 = +0.4VDC
25
O
Max. output voltage-High
T52
Output gain difference between
SD = 20 and SD = 25.
20
O
Feed through
T51
16
DC open gain
T50
25
FOK threshold
T49
25
24
10
GAIN COMP threshold
25
25
O
T48
TZC threshold
ATSC threshold (+)
ATSC threshold (–)
–356
–1.3
–400
V1 = +0.5VDC
130
13
Typ.
120
25
Min.
38
O
18
17
17
12
16
30
O
15
0
O
14
–20
O
13
15
12
7
11
–15
10
–25
9
500
O
8
360
7
28
O
6
Jump output voltage (+)
O
5
–500
4
BAL COMP threshold
MIRR
– 11 –
DEFECT
Ratings
–640
3
Measurement conditions
2C
O
2
Measure-
SD ment pin
Jump output voltage (–)
Max. output voltage-Low
1
SW conditions
T47
T46
T45
T44
T43
T42
T41
TRK Servo
Sled
Item
0.5
1
0.3
750
–450
–1.0
–34
–330
140
22
20
25
–7
640
–360
–1.0
Max.
Vp-p
Vp-p
kHz
kHz
Vp-p
Vp-p
kHz
mV
mV
V
V
dB
dB
mV
mV
mV
mV
mV
mV
mV
mV
V
Unit
CXA1782CQ/CR
CXA1782CQ/CR
Electrical Characteristics Measurement Circuit
VEE Vcc
390k
1000p
35
34
33
32
31
30
29
28
27
26
PD
LD
RF_M
RF_O
RF_I
CP
CB
CC1
CC2
FE_BIAS
10k
25
FOK
3000p
S15
S16
S17
36
PD1
10k
S4
10k
3300p
PD2
37
S3
22k
10k
S1
S2
10k
V2
SENS
Vcc
24
10k
38 F
C. OUT 23
39 E
XRST 22
XRST
40 EI
DATA 21
DATA
Vcc
10k
390k
A
VEE
S18
41 VEE
XLT 20
XLT
42 TEO
CLK 19
CLK
43 LPFI
Vcc 18
S5
A
Vcc
S6
ISET 17
44 TEI
SL_O 16
46 TZC
SL_M 15
47 TDFCT
SL_P 14
60k
45 ATSC
FE_O
FE_M
SRCH
TGU
TG2
FSET
4
5
6
7
8
9
10
11
S13
47k
100k
510k
10k
S11
– 12 –
10k
13
12
S12
200k
5.1k
100k
FLB
3
TA_O
S14
13k
200k
FGD
2
0.1µ
FDFCT
1
S10
48 VC
FEI
0.1µ
S9
10k
V
FEO
S8
TA_M
AC
DC
VEE
240k
S7
0.015µ
V1
CXA1782CQ/CR
Application Circuit (Dual ±5V power supplies)
Vcc
MICRO
COMPUTER
10
1µ/0.3V
10µH
100
500
22k 0.01µ
35
34
33
32
31
30
29
28
27
PD
LD
RF M
RF O
RF I
CP
CB
CC1
47k
36
PD1
Vcc
37
VEE FE_BIAS
38 F
F
E
0.033µ
PD2
D
26
25
CC2
VEE
B
FOK
C
0.033µ
A
0.01µ
1k
100µ/6.3V
1µ/6.3V
Vcc
SENS
DSP
24
C. OUT 23
DSP
39 E
XRST 22
MICRO
COMPUTER
40 EI
DATA 21
DSP
41 VEE
XLT 20
DSP
42 TEO
CLK 19
VEE
0.01µ
0.01µ
DSP
Vcc
100k 150k
Vcc 18
43 LPFI
120k
44 TEI
ISET 17
45 ATSC
SL O 16
46 TZC
SL M 15
FDFCT
FGD
FLB
FE O
FE M
SRCH
TGU
TG2
FSET
3
4
5
6
7
8
9
10
11
0.015µ
3.3µ
13
22µ 15k
12
4.7µ
0.1µ
100k
Driver
0.015µ
Driver
0.033µ
510k
100k
0.1µ
2200p 0.1µ
22k
TA M
FEI
2
680k
FEO
1
TA O
82k
0.022µ
10µ
Driver
SL P 14
47 TDFCT
0.1µ
48 VC
8.2k 100k
VEE
BPF
Vcc
Application Circuit (Single +3V power supply)
Vcc
MICRO
COMPUTER
10
1µ/0.3V
10µH
A
34
33
32
31
30
29
28
27
PD1
PD
LD
RF M
RF O
RF I
CP
CB
CC1
26
25
24
DSP
C. OUT 23
DSP
39 E
XRST 22
MICRO
COMPUTER
40 EI
DATA 21
DSP
41 VEE
XLT 20
DSP
42 TEO
CLK 19
FE_BIAS
SENS
SL O 16
46 TZC
SL M 15
SRCH
TGU
TG2
FSET
6
7
8
9
10
11
TA O
22µ 15k
12
4.7µ
Vcc
0.015µ
100k
0.033µ
510k
100k
3.3µ
13
82k
FE M
5
TA M
FE O
4
Driver
3
FGD
2
22k
FLB
FDFCT
1
0.1µ
Vcc
10µ
0.1µ 680k
10µ
SL P 14
47 TDFCT
48 VC
Driver
0.015µ
45 ATSC
FEI
0.1µ
120k
ISET 17
2200p 0.1µ
0.022µ
BPF
DSP
Vcc
Vcc 18
43 LPFI
44 TEI
FEO
0.01µ
0.01µ
100k 150k
8.2k 100k
E
35
38 F
37
47k
F
36
PD2
Vcc
0.033µ
CC2
22k 0.01µ
D
0.01µ
100
500
B
0.033µ
C
FOK
1k
100µ/6.3V
1µ/6.3V
Vcc
Driver
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 13 –
CXA1782CQ/CR
Description of Functions
RF Amplifier
The photo diode currents input to the input pins (PD1 and PD2) are each I-V converted via a 58kΩ equivalent
resistor by the PD I-V amplifiers. these signals are added by the RF summing amplifier, and the photo diode
(A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check can be
performed at this pin.
1k
22k
3.3µ
RF_M
32
A
RF_O
31
58k
C
PD1
35
iPD1→
PD1 IV AMP
B
D
10k
VA
VC
RF SUMMING AMP
58k
VC
PD2
iPD2→
10k
VB
36
PD2 IV AMP
VC
The low frequency component of the RFO output voltage is VRFO = 2.2 × (VA + VB) = 127.6kΩ × (iPD1 + iPD2).
Focus Error Amplifier
The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and
output current-voltage converted voltage of the photo diode (A + C – B – D).
25p
174k
– (B + D)
– (A + C)
VB
32k
1 FEO
VA
FE AMP
32k
25p
87k
164k
VC
FE_BIAS
37
VEE
VCC
47k
The FEO output voltage (low frequency) is VFEO = 5.4 × (VA – VB) = (iPD2 – iPD1) × 315kΩ.
Be aware that the rotation of the focus bias volume has reversed for the usual CD RF IC.
– 14 –
CXA1782CQ/CR
Tracking Error Amplifier
The photo diode currents input to E and F pins are each current-voltage converted by the E I-V and F I-V
amplifiers.
1k
RF1
3.3µ
260k
12p
TE AMP
30k
12k
96k
VC
VC
TEO
RE3
28k
BAL3
57k
VC
BAL2
E I-V AMP
RE2
VC
BAL1 102k
VE
39
6.8k
E
→
iE
20.3k
260k
12p
TOG3 4.8k
10k
RF3
42
TOG2 10k
13k
RE1
96k
30k
F I-V AMP
26k
VC
RF2
VF
38
→
iF
TOG1 22k
F
VC
40
EI
The CXA1782 tracking block has built-in circuits for balance and gain adjustments to enable software-based
automatic adjustment.
The balance adjustment is performed by varying the combined resistance value of the T-configured feedback
resistance at E I-V AMP.
F I-V AMP feedback resistance = RF1 + RF2 + RF1 x RF2 = 403kΩ
RF3
E I-V AMP feedback resistance = RE1 + RE2 +
RE1 x RE2
RE3
Vary the value of RE3 in the formula above by using the balance adjustment switches (BAL1 to BAL3).
For the gain adjustment, the TE AMP output is resistance-divided by the gain adjustment switches (TOG1 to
TOG3), and it is output at Pin 42.
These balance and gain adjustment switches are controlled through software commands.
– 15 –
CXA1782CQ/CR
Tracking Automatic Adjustment for Gain/Balance
µ-CON
TZC
100k
SENS
BUFFER
AMP
150k
42
24
0.01µ
Balance OK
Gain OK
LPF
43
0.01µ
TEO
DFCT FZC
LPFI
HPF
C. OUT
23
LPF
Frequency
check
–
+
Balance
Gain
Resistance
switching
The CXA1782 has balance control, gain control, and comparator circuits required to perform tracking
automatic adjustment. LPF is set externally at approximately 100Hz.
• Balance adjustment
This adjustment is performed by routing the tracking error signal (TE signal) through the LPF, extracting the
offset DC, and comparing it to the reference level.
However, the TE signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through
the LPF leaves lower frequency components, and the complete DC offset can not be extracted. To extract it,
monitor the TE signal frequency at all times, and perform adjustment only when, a frequency that can lower a
sufficient gain appears on the LPF. Use the C. OUT output to check this frequency.
• Gain adjustment
This adjustment is performed by passing the TE signal through the HPF and comparing the AC component to
the reference level. The HPF signal is implemented by taking the difference between the TE signal and the
LPF component input to Pin 43.
The comparison signal is output from Pin 24 (SENS). Address 3 selects the automatic adjustment
comparator output, and HPF for data (D3) = 1 or LPF for data (D3) = 0 is selected.
• The anti-shock circuit always operates in the CXA1782 so that TG1 and TG2 (address 1 : D3) should be set
to 1 for tracking adjustment to prevent this effect.
When the anti-shock function is not used, Pin 45 (ATSC) should be fixed to VC.
– 16 –
CXA1782CQ/CR
Center Voltage Generation Circuit
(Single voltage application; Connect to GND when it’s positive/negative dual power supplies.)
Maximum current is approximately ±3mA. Output impedance is approximately 50Ω.
30k
Vcc
VC
VC
50
30k
48
VEE
APC Circuit
When the laser diode is driven with constant current, the optical output possesses large negative temperature
characteristics. Therefore, the current must be controlled with the monitor photo diode to ensure the output
remains constant.
100µ/6.3V
Vcc
LD
33
Vcc
1k
10µH
56k
PD
34
10k
1µ/6.3V
55k
10k
VREF
1.25V
PD
LD
VEE
GND
56k
10k
VEE
– 17 –
VEE
CXA1782CQ/CR
Focus Servo
FE
9k
51k
FEO
10k
22k
FZC
1
2
FEI
2200p
100k
3
0.47µ
DFCT
FS4
68k
FDFCT
FOCUS COIL
FE_O
Focus
100k
phase
Compensation
6
FGD
4
50k
100k
FE_M
7
680k
40k
11µ
22µ
0.1µ
ISET 120k
17
50k
FS2
FLB
5
0.1µ
FSET
11
510k
FS1
SRCH
8
0.01µ
4.7µ
The above figure shows a block diagram of the focus servo.
Ordinarily the FE signal is input to the focus phase compensation circuit through a 68kΩ resistance; however,
when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal
100kΩ resistance and the capacitance connected to Pin 3. When this DFCT prevention circuit is not used,
leave Pin 3 open. The defect switch operation can be enabled and disabled with command.
The capacitor connected between Pin 5 and GND is a time constant to raise the low frequency in the normal
playback state.
The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510Ω is
connected to Pin 11.
The focus search height is approximately ±1.1Vp-p when using the constants indicated in the above figure.
This height is inversely proportional to the resistance connected between Pin 17 and VEE. However, changing
this resistance also changes the height of the track jump and sled kick as well.
The FZC comparator inverted input is set to 15% of VCC and VC (Pin 48); (VCC – VC) × 15%.
∗ 510kΩ resistance is recommended for Pin 11.
– 18 –
CXA1782CQ/CR
Tracking Sled Servo
TE
+
42
TEO
HPF
–
130mV
BUFFER AMP
150k
LPF
LPFI
0.01µ
0.01µ
43
17mV
SLED MOTOR
SL_O
16
TM1
44
680k
TG1
SL_M
100k
100k
0.47µ
TDFCT
47
0.047µ 470k
66p
15
TM6
1k
ATSC
TM4 11µA
82k
100k
TA_M
47p
12
46
TM3
TZC
10
14
ATSC
100k
TZC
0.033µ
SL_P
TM2
22µA
3.3µ
1k
9
22µA
8.2k
45
330k
680k
TM5
0.022µ
20k
TGU
TG2
M
DFCT
120k
TEI
0.015µ
100k
TG2
Tracking Phase
Compensation
10k
22µ
15k
11µA
90k
TA_O
TRACKING
COIL
13
TM7
470k
FSET
11
510k
0.01µ
The above figure shows a block diagram of the tracking and sled servo.
The capacitor connected between Pins 9 and 10 is a time constant to decrease the high-frequency gain when
TG2 is OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510kΩ
resistance connected to Pin 11. In the CXA1782, TG1 and TG2 are inter-linked switches.
To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to
the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be
more specific,
Track jump peak voltage = TM3 (or TM4) current × feedback resistance value
The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage
applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15;
Sled kick peak voltage = TM5 ( or TM6) current × feedback resistance
The values of the current for each switch are determined by the resistance connected between Pin 17 and
VEE. When this resistance is 120kΩ:
TM3 ( or TM4) = ±11µA, and TM5 (or TM6) = ±22µA.
As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the
internal resistance (100kΩ) and the capacitance connected to Pin 47.
– 19 –
CXA1782CQ/CR
Focus OK Circuit
RF
VCC
RF_O
20k
31
54k
×1
C5
0.01µ
RF_I
30
25 FOK
VG
92k
15k
0.625V
FOCUS OK
COMPARATOR
FOCUS OK AMP
The focus OK circuit creates the timing window okaying the focus servo from the focus search state.
The HPF output is obtained at Pin 30 from Pin 31 (RF signal), and the LPF output (opposite phase) of the
focus OK amplifier output is also obtained.
The focus OK output reverses when VRFI – VRFO ≈ –0.37V.
Note that, C5 determines the time constant of the HPF for the EFM comparator and mirror circuit and the LPF
of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01µF selected, the fc is equal to 1kHz, and block
error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented.
DEFECT Circuit
After the RFI signal is reverted, two time constants, long and short, are held at bottom. The short time constant
bottom hold responds to 0.1ms or greater disc mirror defects, and the long time constant bottom hold holds the
pre-defect mirror level. By differentiating and level-shifting these constants with capacitor coupling and
comparing both signals, the mirror defect detection signal is generated.
0.033µ
CC1
27
RF_O 31
a
×2
b
CC2
26
c
e
24 SENS
DEFECT AMP
d
DEFECT SW
CB
a
RFO
b
DEFECT
AMP
DEFECT BOTTOM
HOLD
28
DEFECT COMPARATOR
0.01µ
BOTTOM
c HOLD (1) ;
solid Line:
CC1
e
d
H
DEFECT
L
– 20 –
BOTTOM
HOLD (2) ;
dotted Line:
CC2
CXA1782CQ/CR
Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been amplified.
The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time
constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope
fluctuation.
RF_O
31
RF
MIRROR HOLD AMP
0.033µ
29
RF_I
30
× 1.4
G
PEAK&
BOTTOM
HOLD
H
CP
×1
I
J
K
MIRROR AMP
20k
LOGIC
MIRROR
COMPARATOR
RF_O
0V
G
(RF_I)
0V
H
(PEAK HOLD)
0V
I
(BOTTOM HOLD)
0V
J
K
(MIRROR HOLD)
H
MIRR
L
The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold
signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by
comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when
between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time
constant must be sufficiently large compared with the traverse signal.
In the CXA1782, this mirror output is used only during braking operations, and no external output pin is
attached. Accordingly, when connecting DSP such as the CXD2500 with MIRR input pin, input the C. OUT
output to the MIRR input of the DSP.
– 21 –
CXA1782CQ/CR
Commands
The input data to operate this IC is configured as 8-bit data; however, below, this input data is represented by
2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F.
Commands for the CXA1782 can be broadly divided into four groups ranging in value from $0X to $3X.
1. $0X (“FZC” at SENS pin (Pin 24))
These commands are related to focus servo control.
The bit configuration is as shown below.
D7
0
D6
0
D5
0
D4
0
D3
FS4
D2
DEFECT
D1
FS2
D0
FS1
Four focus-servo related switches exist: FS1, FS2, FS4, and DEFECT corresponding to D0 to D3, respectively.
$00
$02
When FS1 = 0, Pin 8 is charged to (22µA – 11µA) × 50kΩ = 0.55V.
If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 6 becomes 0V.
From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output
to Pin 6. This voltage level is obtained by equation 1 below.
(22µA – 11µA) × 50kΩ ×
$03
resistance between Pins 6 and 7
50kΩ
Equation 1
....
From the state described above, FS1 becomes 1, and a current source of +22µA is split off.
Then, a CR charge/discharge circuit is formed, and the voltage at Pin 8 decreases with the time as
shown in Fig. 1 below.
0V
Fig. 1. Voltage at Pin 8 when FS1 gose from 0 → 1
This time constant is obtained with the 50kΩ resistance and an external capacitor.
By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)
0V
$
00 02
03
02
03
02
00
Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 6)
$04
When the fact that the RF signal is missing is detected and the scratches on the disc are detected with
DEFECT = 0, DFCT (FS3) is turned ON.
– 22 –
CXA1782CQ/CR
1-1. FS4
This switch is provided between the focus error input (Pin 2) and the focus phase compensation, and is in
charge of turning the focus servo ON and OFF.
$00
→ $08
Focus OFF ← Focus ON
1-2. Procedure of focus activation
For description, suppose that the polarity is as described below.
a) The lens is searching the disc from far to near;
b) The output voltage (Pin 6) is changing from negative to positive; and
c) The focus S-curve is varying as shown below.
A
t
Fig. 3. S-curve
The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and the
turning the focus servo switch ON are performed during the focus S-curve transits the point A indicated in Fig. 3.
To prevent misoperation, this signal is ANDed with the focus OK signal.
In this IC, FZC (Focus Zero Cross) signal is output from the SENS pin (Pin 24) as the point A transit signal. In
addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case).
Following the line of the above description, focusing can be well obtained by observing the following timing
chart.
(20ms) (200ms)
$02
($00)
$03
$08
Drive voltage
∗ The broken lines in the figure
indicate the voltage assuming
the signal is not in focus.
Focus error
SENS pin
(FZC)
The instant the signal is brought into focus.
Focus OK
Fig. 4. Focus ON timing chart
– 23 –
CXA1782CQ/CR
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be
minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC ↓ ?
Transfer $08
NO
YES
F. OK ?
F. OK ?
NO
NO
YES
YES
Transfer $08
FZC ↓ ?
NO
YES
Latch
Latch
(A)
(B)
Fig. 5. Poor and good software command sequences
1-3. SENS pin (Pin 24)
The output of the SENS pin differs depending on the input data as shown below.
$0X: FZC
$1X: DEFECT
$2X: TZC
$3X: Automatic adjustment comparator output
$4X to 7X: HIGH-Z
2. $1X (“DEFECT” at SENS pin (Pin 24))
These commands deal with switching TG1/TG2, brake circuit ON/OFF, and the sled kick output.
The bit configuration is as follows
Sled kick height
Relative
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
value
(PS1)
(PS0)
0
0
0
1
TG1, TG2 Break
Sled kick
±1
0
0
circuit
height
±2
0
1
ON/OFF
ON/OFF
±3
1
0
±4
1
1
TG1, TG2
The purpose of these switches is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked
switches. The brake circuit (TM7) is to prevent the occurrence of such frequently occurring phenomena as
extremely degraded actuator settling due to the servo motor exceeding the linear range causing what should
be a 100-track jump to fall back down to a 10-track jump after a 100 or 10-track jump has been performed. To
do this, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of
the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope
and the tracking error is 180˚out-of-phase to cut the unneeded portion of the tracking error and apply braking.
– 24 –
CXA1782CQ/CR
[∗A]
RF_I 30
[∗B]
Envelope Detection
[∗D]
Tracking error
(TZC) 46
D2
Waveform Shaping
(MIRR)
[∗C]
[∗E]
Waveform Shaping
[∗F]
Edge Detection
D Q
[∗G]
BRK
TM7
Low: open
High: make
CK
(Latch)
CXA1782
Fig. 6. TMI movement during braking operation
From inner to outer track
From outer to inner track
[∗A]
[∗B]
[∗C]
(“MIRR”)
[∗D]
(“TZC”)
[∗E]
[∗F]
[∗G]
[∗H]
Braking is
applied from
here.
0V
Fig. 7. Internal waveform
3. $2X (“TZC” at SENS pin (Pin 24))
These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse
and fast forward pulse during access operations.
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
Tracking
control
00: OFF
01: Servo ON
10: F-JUMP
11: R-JUMP
↓
TM1, TM3, TM4
– 25 –
Sled
control
00: OFF
01: Servo ON
10: F-FAST FORWARD
11: R-FAST FORWARD
↓
TM2, TM5, TM6
CXA1782CQ/CR
4. $3X
These commands control the balance and gain control circuit switches used during automatic tracking
adjustment.
In the initial resetting state, BAL1 to BAL3 switches are OFF and TOG1 to TOG3 switches are ON.
• Balance adjustment
The balance adjustment switches BAL1 to BAL3 can be controlled by setting D3 = 0. The switches are set
using D0 to D2.
At this time, the balance adjustment LPF comparator output is selected at the SENS pin.
Data is set by specifying switch conditions D0 to D2 and sending a latch pulse with D3 = 0.
Sending a latch pulse with D3 = 1 does not change the balance switch settings.
START
C. OUT
Is the frequency
high enough ?
BAL1 to BAL3
Switch Control
NO
YES
SENS output
Balance OK ?
Adjustment Completed
Balance adjustment
• Gain adjustment
The gain adjustment switches TOG1 to TOG3 can be controlled by setting D3 = 1. These switches are set
using D0 to D2. At this time, the balance adjustment HPF comparator output is selected for SENS pin.
In a fashion similar to the method used with the balance adjustment, set the data by sending a latch pulse
with D3 = 1, specifying the switch conditions D0 to D2.
START
TOG1 to TOG3
Switch control
SENS
GAIN OK ?
NO
YES
Adjustment Completed
Gain adjustment
– 26 –
CXA1782CQ/CR
CPU Serial Interface Timing Chart
D0
DATA
D1
tWCK
D2
D3
tWCK
tSU
D4
D5
D6
D7
D0
th
CLK
tCD
1/fck
tD
XLT
tWL
(VCC = 3.0V)
Item
Symbol
Min.
Type.
Max.
Unit
1
MHz
Clock frequency
fck
Clock pulse width
fwck
500
ns
Setup time
tsu
th
tD
tWL
tCD
500
ns
500
ns
500
ns
1000
ns
1000
ns
Hold time
Delay time
Latch pulse width
Data transfer interval
System Control
DATA
ADRESS
Item
D7 D6 D5 D4
D3
D2
D1
D0
0
0
0
FS4
FS1
DEFECT (FS3) FS2
0 Focus
Search
Disable = 1
Search
ON = 1, OFF = 0 Enable = 0
ON = 1, OFF = 0 Up = 1, Down = 0
Tracking Control 0
0
0
1
Tracking Mode 0
0
1
TG1, TG2
Brake
Sled
ON = 1, OFF = 0 ON = 1, OFF = 0 Kick + 2
0 Tracking Mode ∗1
Sled Mode ∗2
0
0
1
1
Focus Control
Select
∗1 TRACKING MODE
Automatic tracking adjustment mode
∗2 SLED MODE
D3
D2
D1
D0
OFF
0
0
OFF
0
0
ON
0
1
ON
0
1
FWD JUMP
1
0
FWD MOVE
1
0
REV JUMP
1
1
REV MOVE
1
1
– 27 –
Sled
Kick + 1
SENS
output
FZC
DEFECT
TZC
Gain/Bal
CXA1782CQ/CR
Serial Data Truth Table
Hex
Serial Data
FOCUS CONTROL
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
TRACKING MODE
Hex
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FS = 4321
DEFECT FS2
FS4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Functions
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
E
E
E
E
D
D
D
D
E
E
E
E
D
D
D
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TM = 6 5 4 3 2 1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
– 28 –
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
FS1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DEFECT
E: enable
D: disable
CXA1782CQ/CR
Automatic
adjustment mode
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TOG SW
BAL SW
Hex
3 2 1
3 2 1
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
$3B
$3C
$3D
$3E
$3F
–
–
–
–
–
–
–
–
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
0
0
1
1
0
0
–
–
–
–
–
–
–
–
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
–
–
–
–
–
–
–
–
1
0
1
0
1
0
1
0
–
–
–
–
–
–
–
–
DATA D3 = 0: Balance switch setting
DATA D3 = 1: Gain switch setting
Note) 0 means OFF and 1 means ON for TOG SW and BAL SW. These are not equal to the setting values of
each bit for serial data.
Initial State (resetting state)
ADDRESS
Item
DATA
HEXADECIMAL
D7 D6 D5 D4 D3 D2 D1 D0
Focus Control
0
0
0
0
0
0
0
0
$00
Tracking Control
0
0
0
1
0
0
0
0
$10
Tracking Mode
0
0
1
0
0
0
0
0
$20
0
0
1
1
0
1
1
1
$37
Select
1
0
0
0
$38
The above data means the following operation modes.
Focus Control
Tracking Control
Tracking Mode
Select
Focus off, Defect enable, Focus Search off, Focus Search down
TG1 – TG2 off, Brake off, Sled Kick + 2 off, Sled Kick + 1 off
Tracking off, Sled off
Tracking gain → min. (TOG SW: 1 1 1)
Tracking balance: RE3 → max. (TBAL SW: 0 0 0)
– 29 –
CXA1782CQ/CR
Notes on Operation
1. FSET pin
The FSET pin determines the fc for the focus and tracking high-frequency phase compensation.
2. ISET pin
ISET current = 1.27V/R
= Focus search current
= Tracking jump current
1
= Sled kick current ($1X: PS1 = PS0 = 0) ×
2
Use the setting resistance within the range of 120kΩ to 240kΩ. If the resistance value is out of this range,
the oscillation may be occurred in the ISET block.
3. FE (focus error)/TE (tracking error) gain changing method
1) High gain: Resistance between FE pins (pins 6 and 7) 100kΩ → Large
Resistance between TE pins (pins 12 and 13) 100kΩ → Large
2) Low gain: A signal, whose resistance is divided between Pins 1 and 2, is input to FE. The internal gain
adjustment circuit is used for TE.
4. Input voltage at Pins 19 to 22 of the microcomputer interface should be as follows:
VIH VCC × 90% or more
VIL VCC × 10% or less
5. Focus OK circuit
1) Refer to the “Description of Operation” for the time constant setting of the focus OK amplifier LPF and the
mirror amplifier HPF.
VCC
20k
FOK
25
40k
The FOK and comparator output are as follows:
Output voltage High: VFOKH ≈ near VCC
Output voltage Low: VFOKL ≈ Vsat (NPN)
RL
100k
VCC
VEE
VEE
6. Sled amplifier
The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB.
Sled/Tracking internal phase compensation and reference design material
TRK
FCS
Item
SD
1.2kHz gain
08
1.2kHz phase
08
1.2kHz gain
25
1.2kHz phase
25
2.7kHz gain
25→13
2.7kHz phase
25→13
Measurement pin
6
13
Conditions
Typ.
Unit
CFLB = 0.1µF
CFGD = 0.1µF
21.5
dB
63
deg
13
dB
–125
deg
26.5
dB
–130
deg
CTGU = 0.1µF
– 30 –
CXA1782CQ/CR
Package Outline
Unit: mm
CXA1782CQ
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
36
25
0.15
24
48
13
13.5
37
12
+ 0.15
0.3 – 0.1
0.8
0.9 ± 0.2
1
+ 0.2
0.1 – 0.1
± 0.12 M
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
SONY CODE
QFP-48P-L04
EIAJ CODE
∗QFP048-P-1212-B
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.7g
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
CXA1782CR
48PIN LQFP (PLASTIC)
9.0 ± 0.2
7.0 ± 0.1
36
24
48
13
(8.0)
25
37
A
(0.22)
0.5 ± 0.2
∗
12
1
+ 0.05
0.127 – 0.02
0.5 ± 0.08
+ 0.2
1.5 – 0.1
+ 0.08
0.18 – 0.03
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SOLDER PLATING
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
EIAJ CODE
∗QFP048-P-0707-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.2g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 31 –