ON NCP1207A Pwm current−mode controller for free running quasi−resonant operation Datasheet

NCP1207A
PWM Current−Mode
Controller for Free Running
Quasi−Resonant Operation
The NCP1207A combines a true current mode modulator and a
demagnetization detector to ensure full borderline/critical Conduction
Mode in any load/line conditions and minimum drain voltage switching
(Quasi−Resonant operation). Due to its inherent skip cycle capability,
the controller enters burst mode as soon as the power demand falls
below a predetermined level. As this happens at low peak current, no
audible noise can be heard. An internal 8.0 ms timer prevents the
free−run frequency to exceed 100 kHz (therefore below the 150 kHz
CISPR−22 EMI starting limit), while the skip adjustment capability lets
the user select the frequency at which the burst foldback takes place.
The Dynamic Self−Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1207A. This feature is particularly useful in
applications where the output voltage varies during operation (e.g.
battery chargers). Due to its high−voltage technology, the IC is
directly connected to the high−voltage DC rail. As a result, the
short−circuit trip point is not dependent upon any VCC auxiliary level.
The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin, also enables fast
Overvoltage Protection (OVP). Once an OVP has been detected, the
IC permanently latches off.
Finally, the continuous feedback signal monitoring implemented
with an overcurrent fault protection circuitry (OCP) makes the final
design rugged and reliable.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Free−Running Borderline/Critical Mode Quasi−Resonant Operation
Current−Mode with Adjustable Skip−Cycle Capability
No Auxiliary Winding VCC Operation
Auto−Recovery Overcurrent Protection
Latching Overvoltage Protection
External Latch Triggering, e.g. Via Overtemperature Signal
500 mA Peak Current Source/Sink Capability
Undervoltage Lockout for VCC Below 10 V
Internal 1.0 ms Soft−Start
Internal 8.0 ms Minimum TOFF
Adjustable Skip Level
Internal Temperature Shutdown
Direct Optocoupler Connection
SPICE Models Available for TRANsient Analysis
Pb−Free Packages are Available
Typical Applications
•
•
•
•
AC/DC Adapters for Notebooks, etc.
Offline Battery Chargers
Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.)
Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 3
1
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MARKING
DIAGRAM
8
SOIC−8
D1, D2 SUFFIX
CASE 751
8
1
1207A
AYWW
G
1
8
PDIP−8
N SUFFIX
CASE 626
8
1207AP
AWL
YYWWG
1
1
1207A/P
A
L, WL
Y, YY
W, WW
G
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Pb−Free Package
PIN CONNECTIONS
Dmg
1
8
HV
FB
2
7
NC
CS
3
6
VCC
GND
4
5
Drv
ORDERING INFORMATION
Device
NCP1207ADR2
NCP1207ADR2G
NCP1207AP
NCP1207APG
Package
Shipping †
SOIC−8
2500/Tape & Reel
SOIC−8
(Pb−Free)
2500/Tape & Reel
PDIP−8
50 Units / Rail
PDIP−8
(Pb−Free)
50 Units / Rail
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NCP1207A/D
NCP1207A
Vout
*
+
+
OVP and
Demag
NCP1207A
1
8
2
7
3
6
4
5
GND
Universal Network
+
*Please refer to the application information section
Figure 1. Typical Application
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PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Description
1
Demag
Core reset detection and OVP
The auxiliary FLYBACK signal ensures discontinuous operation and
offers a fixed overvoltage detection level of 7.2 V.
2
FB
Sets the peak current setpoint
By connecting an Optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand. By bringing this pin
below the internal skip level, device shuts off.
3
CS
Current sense input and skip
cycle level selection
This pin senses the primary current and routes it to the internal
comparator via an L.E.B. By inserting a resistor in series with the pin, you
control the level at which the skip operation takes place.
4
GND
The IC ground
5
Drv
Driving pulses
The driver’s output to an external MOSFET.
6
VCC
Supplies the IC
This pin is connected to an external bulk capacitor of typically 10 mF.
7
NC
−
8
HV
High−voltage pin
−
This unconnected pin ensures adequate creepage distance.
Connected to the high−voltage rail, this pin injects a constant current into
the VCC bulk capacitor.
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2
NCP1207A
+
VUVLO
+
4.5 ms
Delay
Demag
HV
PON
+
+
8.0 ms
Blanking
/1.44
+
5.0 V
S
−
+
Resd
−
OVP
7.0
mA
VCC
−
10 V
50 mV
Driver: src = 20
sink = 10
Q
VCC
S*
R* R Q
− +
Rint
+
Drv
12 V, 10 V,
5.3 V (fault)
To Internal
Supply
Demag
4.2 V
Fault
Mngt.
+
GND
Soft−Start = 1 ms
−
1.0 V
Overload?
*S and R are level triggered whereas S is edge
triggered. R has priority over the other inputs.
5.0 ms
Timeout
/3
FB
200 mA
when Drv
is OFF
380 ns
L.E.B.
Timeout
Reset
CS
Demag
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Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating
Symbol
Value
Units
Power Supply Voltage, VCC Pin, Continuous Voltage
VCC Static
18
V
Transient Power Supply Voltage, Duration < 10 ms, IVCC < 20 mA
VCC Pulse
25
V
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) Pin 5 (Drv) and Pin 1 (Demag)
−
−0.3 to 10
V
Maximum Current into all pins except VCC (6), HV (8) and Demag (1) when 10 V ESD diodes are
activated
−
5.0
mA
Maximum Current in Pin 1
Idem
+3.0/−2.0
mA
Thermal Resistance, Junction−to−Case
RqJC
57
°C/W
Thermal Resistance, Junction−to−Air, SOIC version
RqJA
178
°C/W
RqJA
100
°C/W
Operating Junction Temperature
TJ
−40 to +125
°C
Maximum Junction Temperature
TJMAX
150
°C
Temperature Shutdown
−
155
°C
Hysteresis in Shutdown
−
30
°C
Storage Temperature Range
−
−60 to +150
°C
ESD Capability, HBM Model (All pins except HV)
−
2.0
kV
ESD Capability, Machine Model
−
200
V
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Thermal Resistance, Junction−to−Air, DIP8 version
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NCP1207A
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MAXIMUM RATINGS
Rating
Symbol
Value
Units
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 mF
VHVMAX
500
V
Minimum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 mF
VHVMIN
40
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NCP1207A
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
VCC = 11 V unless otherwise noted)
Rating
Pin
Symbol
Min
Typ
Max
Unit
VCC Increasing Level at which the Current Source Turns−off
6
VCCOFF
10.8
12
12.9
V
VCC Decreasing Level at which the Current Source Turns−on
6
VCCON
9.1
10
10.6
V
VCC Decreasing Level at which the Latchoff Phase Ends
6
VCClatch
−
5.3
−
V
VCC Level at which Output Pulses are Disabled
6
UVLO
−
VCCON
−200mV
−
V
Internal IC Consumption, No Output Load on Pin 5,
FSW = 60 kHz
6
ICC1
−
1.0
1.3
(Note 1)
mA
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
FSW = 60 kHz
6
ICC2
−
1.6
2.0
(Note 1)
mA
Internal IC Consumption in Latchoff Phase
6
ICC3
−
330
−
mA
High−voltage Current Source, VCC = 10 V
8
IC1
4.3
7.0
9.6
mA
High−voltage Current Source, VCC = 0
8
IC2
−
8.0
−
mA
Output Voltage Rise−time @ CL = 1.0 nF, 10−90% of Output Signal
5
Tr
−
40
−
ns
Output Voltage Fall−time @ CL = 1.0 nF, 10−90% of Output Signal
5
Tf
−
20
−
ns
Source Resistance
5
ROH
12
20
36
W
Sink Resistance
5
ROL
5.0
10
19
W
DYNAMIC SELF−SUPPLY
INTERNAL STARTUP CURRENT SOURCE (TJ u 0°C)
DRIVE OUTPUT
CURRENT COMPARATOR (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
3
IIB
−
0.02
−
mA
Maximum Internal Current Setpoint
3
ILimit
0.92
1.0
1.12
V
Propagation Delay from Current Detection to Gate OFF State
3
TDEL
−
100
160
ns
Leading Edge Blanking Duration
3
TLEB
−
380
−
ns
Internal Current Offset Injected on the CS Pin during OFF Time
3
Iskip
−
200
−
mA
Sampling Delay after ON Time
1
Tsample
−
4.5
−
ms
OVP Internal Reference Level
1
Vref
6.4
7.2
8.0
V
OVERVOLTAGE SECTION (VCC = 11 V)
FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 kW)
Internal Pull−up Resistor
2
Rup
−
20
−
kW
Pin 3 to Current Setpoint Division Ratio
−
Iratio
−
3.3
−
−
Internal Soft−start
−
Tss
−
1.0
−
ms
Input Threshold Voltage (Vpin 1 Decreasing)
1
Vth
35
50
90
mV
Hysteresis (Vpin 1 Decreasing)
1
VH
−
20
−
mV
Input Clamp Voltage
High State (Ipin 1 = 3.0 mA)
Low State (Ipin 1 = −2.0 mA)
1
1
VCH
VCL
8.0
−0.9
10
−0.7
12
−0.5
V
V
Demag Propagation Delay
1
Tdem
−
210
−
ns
Internal Input Capacitance at Vpin 1 = 1.0 V
1
Cpar
−
10
−
pF
Minimum TOFF (Internal Blanking Delay after TON)
1
Tblank
−
8.0
−
ms
Timeout After Last Demag Transition
1
Tout
−
5.0
−
ms
Pin 1 Internal Impedance
1
Rint
−
28
−
kW
DEMAGNETIZATION DETECTION BLOCK
1. Max value at TJ = 0°C.
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5
1.6
2.3
1.4
2.1
1.2
1.9
ICC2 (mA)
ICC1 (mA)
NCP1207A
1.0
0.8
1.5
0.6
1.3
0.4
−50
−25
0
25
50
75
100
1.1
−50
125
0
25
50
75
100
TEMPERATURE (°C)
Figure 3. Internal IC Consumption (No Output
Load) versus Temperature
Figure 4. Internal IC Consumption (1.0 nF
Output Load) versus Temperature
125
10.8
12.4
10.3
VCCON (V)
VCCOFF (V)
−25
TEMPERATURE (°C)
12.9
11.9
11.4
9.8
9.3
10.9
10.4
−50
−25
0
25
50
75
100
8.8
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. VCC Increasing Level at which the
Current Source Turns−Off versus Temperature
Figure 6. VCC Decreasing Level at which the
Current Source Turns−On versus Temperature
12
40
11
35
10
30
ROH & ROL (W)
9
IC1 (mA)
1.7
8
7
6
5
ROH
20
15
10
4
ROL
5
3
2
−50
25
−25
0
25
50
75
100
0
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Internal Startup Current Source at
VCC = 10 V versus Temperature
Figure 8. Source and Sink Resistance versus
Temperature
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1.20
100
1.15
80
1.10
Ilimit (V)
120
60
1.05
40
1.00
20
0.95
0
−50
−25
0
25
50
75
100
0.90
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Input Voltage (Vpin1 Decreasing)
versus Temperature
Figure 10. Maximum Internal Current Setpoint
versus Temperature
8.0
7.8
7.6
7.4
Vref (V)
VTH (mV)
NCP1207A
7.2
7.0
6.8
6.6
6.4
6.2
6.0
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
Figure 11. OVP internal Reference Level
versus Temperature
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125
NCP1207A
APPLICATION INFORMATION
Introduction
The NCP1207A implements a standard current mode
architecture where the switch−off time is dictated by the
peak current setpoint whereas the core reset detection
triggers the turn−on event. This component represents the
ideal candidate where low part−count is the key parameter,
particularly in low−cost AC/DC adapters, consumer
electronics, auxiliary supplies, etc. Thanks to its
high−performance High−Voltage
technology,
the
NCP1207A incorporates all the necessary components /
features needed to build a rugged and reliable Switch−Mode
Power Supply (SMPS):
•
• Transformer core reset detection: borderline / critical
•
•
•
VRIPPLE = 2 V
VCCOFF = 12 V
VCC
•
Dynamic Self−Supply
The DSS principle is based on the charge/discharge of the
VCC bulk capacitor from a low level up to a higher level. We
can easily describe the current source operation with some
simple logical equations:
POWER−ON: IF VCC < VCCOFF THEN Current Source
is ON, no output pulses
IF VCC decreasing > VCCON THEN Current Source is
OFF, output is pulsing
IF VCC increasing < VCCOFF THEN Current Source is
ON, output is pulsing
Typical values are: VCCOFF = 12 V, VCCON = 10 V
To better understand the operational principle, Figure 12’s
sketch offers the necessary light.
VCCON = 10 V
CURRENT
SOURCE
•
operation is ensured whatever the operating conditions
are. As a result, there are virtually no primary switch
turn−on losses and no secondary diode recovery losses.
The converter also stays a first−order system and
accordingly eases the feedback loop design.
Quasi−resonant operation: by delaying the turn−on
event, it is possible to re−start the MOSFET in the
minimum of the drain−source wave, ensuring reduced
EMI / video noise perturbations. In nominal power
conditions, the NCP1207A operates in Borderline
Conduction Mode (BCM) also called Critical
Conduction Mode.
Dynamic Self−Supply (DSS): due to its Very High
Voltage Integrated Circuit (VHVIC) technology,
ON Semiconductor’s NCP1207A allows for a direct pin
connection to the high−voltage DC rail. A dynamic
current source charges up a capacitor and thus provides
a fully independent VCC level to the NCP1207A. As a
result, there is no need for an auxiliary winding whose
management is always a problem in variable output
voltage designs (e.g. battery chargers).
Overvoltage Protection (OVP): by sampling the plateau
voltage on the demagnetization winding, the
NCP1207A goes into latched fault condition whenever
an over−voltage condition is detected. The controller
stays fully latched in this position until the VCC is
cycled down 4.0 V, e.g. when the user un−plugs the
power supply from the mains outlet and re−plugs it.
External latch trip point: by externally forcing a level
on the OVP greater than the internal setpoint, it is
possible to latchoff the IC, e.g. with a signal coming
from a temperature sensor.
Adjustable skip cycle level: by offering the ability to
tailor the level at which the skip cycle takes place, the
designer can make sure that the skip operation only
occurs at low peak current. This point guarantees a
noise−free operation with cheap transformer. This
option also offers the ability to fix the maximum
switching frequency when entering light load
conditions.
Overcurrent Protection (OCP): by continuously
monitoring the FB line activity, NCP1207A enters burst
mode as soon as the power supply undergoes an
overload. The device enters a safe low power operation
which prevents from any lethal thermal runaway. As
soon as the default disappears, the power supply
resumes operation. Unlike other controllers, overload
detection is performed independently of any auxiliary
winding level. In presence of a bad coupling between
both power and auxiliary windings, the short circuit
detection can be severely affected. The DSS naturally
shields you against these troubles.
ON
OFF
Output Pulses
Figure 12. The Charge/Discharge Cycle Over a 10 mF
VCC Capacitor
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NCP1207A
The DSS behavior actually depends on the internal IC
consumption and the MOSFET’s gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg equals 22 nC
(max). With a maximum switching frequency selected at
75 kHz, the average power necessary to drive the MOSFET
(excluding the driver efficiency and neglecting various
voltage drops) is:
Fsw ⋅ Qg ⋅ VCC with:
Fsw = maximum switching frequency
Qg = MOSFET’s gate charge
VCC = VGS level applied to the gate
To obtain the output current, simply divide this result by
VCC: Idriver = FSW ⋅ Qg = 1.6 mA. The total standby power
consumption at no−load will therefore heavily rely on the
internal IC consumption plus the above driving current
(altered by the driver’s efficiency). Suppose that the IC is
supplied from a 350 VDC line. The current flowing through
pin 8 is a direct image of the NCP1207A consumption
(neglecting the switching losses of the HV current source).
If ICC2 equals 2.3 mA @ TJ = 60°C, then the power
dissipated (lost) by the IC is simply: 350 V x 2.3 mA =
805 mW. For design and reliability reasons, it would be
interested to reduce this source of wasted power that
increase the die temperature. This can be achieved by using
different methods:
1. Use a MOSFET with lower gate charge Qg.
2. Connect pin 8 through a diode (1N4007 typically) to
one of the mains input. The average value on pin 8
When using Figure 13 option, it is important to check
the absence of any negative ringing that could occur
on pin 8. The resistor in series should help to damp
any parasitic LC network that would ring when
suddenly applying the power to the IC. Also, since
the power disappears during 10 ms (half−wave
rectification), CVCC should be calculated to supply
the IC during these holes in the supply
3. Permanently force the VCC level above VCCH with
an auxiliary winding. It will automatically
disconnect the internal startup source and the IC will
be fully self−supplied from this winding. Again, the
total power drawn from the mains will significantly
decrease. Make sure the auxiliary voltage never
exceeds the 16 V limit.
Skipping Cycle Mode
The NCP1207A automatically skips switching cycles
when the output power demand drops below a given level.
This is accomplished by monitoring the FB pin. In normal
operation, Pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 14) and
follows the following formula:
1 @ Lp @ Ip 2 @ Fsw @ D
burst with:
2
V
@ 2. Our power contribution
becomes mainsPEAK
p
example drops to: 223 V x 2.3 mA = 512 mW. If a
resistor is installed between the mains and the diode,
you further force the dissipation to migrate from the
package to the resistor. The resistor value should
account for low−line startups.
HV
Lp = primary inductance
Fsw = switching frequency within the burst
Ip = peak current at which skip cycle occurs
Dburst = burst width / burst recurrence
CURRENT SENSE SIGNAL (mV)
1N4007
5
MAINS
1
2
Cbulk
1
8
2
7
3
6
4
5
6
Figure 13. A simple diode naturally reduces the
average voltage on Pin 8
300
MAX PEAK
CURRENT
NORMAL CURRENT
MODE OPERATION
SKIP CYCLE
CURRENT LIMIT
200
100
0
WIDTH
RECURRENCE
Figure 14. The skip cycle takes place at low peak
currents which guaranties noise free operation
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NCP1207A
current sense comparator permanently resets the latch and the
next clock cycle (given by the demagnetization detection) is
ignored: we are skipping cycles as shown by Figure 16. As
soon as the feedback voltage goes up again, there can be two
situations: the recurrent period is small and a new
demagnetization detection (next wave) signal triggers the
NCP1207A. To the opposite, in low output power conditions,
no more ringing waves are present on the drain and the toggling
of the current sense comparator together with the internal 5 ms
timeout initiates a new cycle start. In normal operating
conditions, e.g. when the drain oscillations are generous, the
demagnetization comparator can detect the 50 mV crossing
and gives the “green light”, alone, to re−active the power
switch. However, when skip cycle takes place (e.g. at low
output power demands), the re−start event slides along the
drain ringing waveforms (actually the valley locations) which
decays more or less quickly, depending on the
Lprimary−Cparasitic network damping factor. The situation can
thus quickly occur where the ringing becomes too weak to be
detected by the demagnetization comparator: it then
permanently stays locked in a given position and can no longer
deliver the “green light” to the controller. To help in this
situation, the NCP1207A implements a 5 ms timeout generator:
each time the 50 mV crossing occurs, the timeout is reset. So,
as long as the ringing becomes too low, the timeout generator
starts to count and after 5 ms, it delivers its “green light”. If the
skip signal is already present then the controller re−starts;
otherwise the logic waits for it to set the drive output high.
Figure 16 depicts these two different situations:
DRIVER
DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200 mA
RESET
3
−
+
2
Rskip
Rsense
+
Figure 15. A patented method allows for skip level
selection via a series resistor inserted in series
with the current
The skip level selection is done through a simple resistor
inserted between the current sense input and the sense element.
Every time the NCP1207A output driver goes low, a 200 mA
source forces a current to flow through the sense pin
(Figure 15): when the driver is high, the current source is off
and the current sense information is normally processed. As
soon as the driver goes low, the current source delivers 200 mA
and develops a ground referenced voltage across Rskip. If this
voltage is below the feedback voltage, the current sense
comparator stays in the high state and the internal latch can be
triggered by the next clock cycle. Now, if because of a low load
mode the feedback voltage is below Rskip level, then the
Drain
Signal
Timeout
Signal
Demag Re−start
Current Sense and Timeout Re−start
Drain
Signal
Timeout
Signal
5 ms
5 ms
Figure 16. When the primary natural ringing becomes too low, the internal timeout together with the sense
comparator initiates a new cycle when FB passes the skip level.
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10
NCP1207A
Demagnetization Detection
The core reset detection is done by monitoring the voltage
activity on the auxiliary winding. This voltage features a
FLYBACK polarity. The typical detection level is fixed at
50 mV as exemplified by Figure 17.
DRAIN VOLTAGE (V)
400
DEMAG SIGNAL (V)
7.0
5.0
POSSIBLE
RE−STARTS
300
200
100
0
3.0
1.0
Figure 19. The NCP1207A Operates in
Borderline / Critical Operation
50 mV
0V
−1.0
Overvoltage Protection
The overvoltage protection works by sampling the plateau
voltage 4.5 ms after the turn−off sequence. This delay
guarantees a clean plateau, providing that the leakage
inductance ringing has been fully damped. If this would not
be the case, the designer should install a small RC damper
across the transformer primary inductance connections.
Figure 20 shows where the sampling occurs on the auxiliary
winding.
Figure 17. Core reset detection is done through a
dedicated auxiliary winding monitoring
TO INTERNAL
COMPARATOR
Resd
2
Rint
ESD2
1
1
Rdem
5
ESD1
4
4
Aux
SAMPLING HERE
8.0
3
DEMAG SIGNAL (V)
Resd + Rint = 28 k
Figure 18. Internal Pad Implementation
An internal timer prevents any re−start within 8.0 ms
further to the driver going−low transition. This prevents the
switching frequency to exceed (1 / (TON + 8.0 ms)) but also
avoid false leakage inductance tripping at turn−off. In some
cases, the leakage inductance kick is so energetic, that a
slight filtering is necessary.
The 1207 demagnetization detection pad features a
specific component arrangement as detailed by Figure 18. In
this picture, the zener diodes network protect the IC against
any potential ESD discharge that could appear on the pins.
The first ESD diode connected to the pad, exhibits a parasitic
capacitance. When this parasitic capacitance (10 pF
typically) is combined with Rdem, a re−start delay is created
and the possibility to switch right in the drain−source wave
exists. This guarantees QR operation with all the associated
benefits (low EMI, no turn−on losses etc.). Rdem should be
calculated to limit the maximum current flowing through
pin 1 to less than +3 mA/−2 mA. If during turn−on, the
auxiliary winding delivers 30 V (at the highest line level),
then the minimum Rdem value is defined by: (30 V + 0.7 V)
/ 2 mA = 14.6 kW. This value will be further increased to
introduce a re−start delay and also a slight filtering in case
of high leakage energy.
Figure 19 portrays a typical VDS shot at nominal output
power.
6.0
4.0
2.0
4.5 ms
0
Figure 20. A voltage sample is taken 4.5 ms after
the turn−off sequence
When an OVP condition has been detected, the
NCP1207A enters a latchoff phase and stops all switching
operations. The controller stays fully latched in this position
and the DSS is still active, keeping the VCC between 5.3
V/12 V as in normal operations. This state lasts until the VCC
is cycled down 4 V, e.g. when the user unplugs the power
supply from the mains outlet.
By default, the OVP comparator is biased to a 5.0 V
reference level and pin1 is routed via a divide by 1.44
network. As a result, when Vpin 1 reaches 7.2 V, the OVP
comparator is triggered. The threshold can thus be adjusted
by either modifying the power winding to auxiliary winding
turn ratios to match this 7.2 V level, or insert a resistor from
Pin 1 to ground to cope with your design requirement.
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11
NCP1207A
Latching Off the NCP1207A
In certain cases, it can be very convenient to externally
shut down permanently the NCP1207A via a dedicated
signal, e.g. coming from a temperature sensor. The reset
occurs when the user unplugs the power supply from the
mains outlet. To trigger the latchoff, a CTN (Figure 21) or
a simple NPN transistor (Figure 22) can do the work.
Power Dissipation
The NCP1207A is directly supplied from the DC rail
through the internal DSS circuitry. The DSS being an
auto−adaptive circuit (e.g. the ON/OFF duty−cycle adjusts
itself depending on the current demand), the current flowing
through the DSS is therefore the direct image of the
NCP1207A current consumption. The total power
dissipation
can
be
evaluated
using:
(VHVDC * 11 V) @ ICC2. If we operate the device on a 250
Vac rail, the maximum rectified voltage can go up to 350
Vdc. As a result, the worse case dissipation occurs at the
maximum switching frequency and the highest line. The
dissipation is actually given by the internal consumption of
the NCP1207A when driving the selected MOSFET. The
best method to evaluate this total consumption is probably
to run the final circuit from a 50 Vdc source applied to pin 8
and measure the average current flowing into this pin.
Suppose that we find 2.0 mA, meaning that the DSS
duty−cycle
will
be
2.0/7.0
=
28.6%.
From the 350 Vdc rail, the part will dissipate:
350 V @ 2.0 mA + 700 mW (however this 2.0 mA number
will drop at higher operating junction temperatures).
A DIP8 package offers a junction−to−ambient thermal
resistance RqJA of 100°C/W. The maximum power
dissipation can thus be computed knowing the maximum
operating ambient temperature (e.g. 70°C) together with
the maximum allowable junction temperature (125°C):
CTN
NCP1207A
Aux
1
8
2
7
3
6
4
5
Figure 21. A simple CTN triggers the latchoff as
soon as the temperature exceeds a given setpoint
NCP1207A
ON/OFF
Aux
1
8
2
7
3
6
P max +
4
5
do not reach the worse consumption budget imposed by the
operating conditions. Several solutions exist to cure this
trouble:
• The first one consists in adding some copper area around
the NCP1207A DIP8 footprint. By adding a min pad area
of 80 mm2 of 35 mm copper (1 oz.), RqJA drops to about
75°C/W. Maximum power then grows up to 730 mW.
• A resistor Rdrop needs to be inserted with pin 8 to a) avoid
negative spikes at turn−off (see below)
b) split the power budget between this resistor and the
package. The resistor is calculated by leaving at least 50 V
on pin 8 at minimum input voltage (suppose 100 Vdc in
Figure 22. A simple transistor arrangement allows
to trigger the latchoff by an external signal
Shutting Off the NCP1207A
Shutdown can easily be implemented through a simple
NPN bipolar transistor as depicted by Figure 23. When OFF,
Q1 is transparent to the operation. When forward biased, the
transistor pulls the FB pin to ground (VCE(sat) ≈ 200 mV) and
permanently disables the IC. A small time constant on the
transistor base will avoid false triggering (Figure 23).
ON/OFF
10 k
3
2
10 nF
Q1
1
8
2
7
3
6
4
5
RqJA
t 550 mW. As we can see, we
V
* 50 V
t 7.1 kW . The
our case): Rdrop v bulkmin
7.0 mA
power dissipated by the resistor is thus:
NCP1207A
1
Tjmax * TAmax
Pdrop + VdropRMS 2ńRdrop
+
+
ǒIDSS @ Rdrop @ ǸDSSduty * cycleǓ
Rdrop
2
ǒ7.0 mA @ 7.1 kW @ Ǹ0.286Ǔ
7.1 kW
2
+ 99.5 mW
Please refer to the application note AND8069 available
from www.onsemi.com/pub/ncp1200.
Figure 23. A simple bipolar transistor totally
disables the IC
http://onsemi.com
12
NCP1207A
• If the power consumption budget is really too high for the
NCP1207A hosts a dedicated overload detection circuitry.
Once activated, this circuitry imposes to deliver pulses in a
burst manner with a low duty−cycle. The system recovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. This period of time depends on
normal output load conditions and the maximum peak
current allowed by the system. The time−out used by this IC
works with the VCC decoupling capacitor: as soon as the
VCC decreases from the VCCOFF level (typically 12 V) the
device internally watches for an overload current situation.
If this condition is still present when the VCCON level is
reached, the controller stops the driving pulses, prevents the
self−supply current source to restart and puts all the circuitry
in standby, consuming as little as 330 mA typical (ICC3
parameter). As a result, the VCC level slowly discharges
toward 0. When this level crosses 5.3 V typical, the
controller enters a new startup phase by turning the current
source on: VCC rises toward 12 V and again delivers output
pulses at the VCCOFF crossing point. If the fault condition
has been removed before VCCON approaches, then the IC
continues its normal operation. Otherwise, a new fault cycle
takes place. Figure 24 shows the evolution of the signals in
presence of a fault.
DSS alone, connect a diode between the auxiliary
winding and the VCC pin which will disable the DSS
operation (VCC u 10 V).
The SOIC package offers a 178°C/W thermal resistor.
Again, adding some copper area around the PCB footprint
will help decrease this number: 12 mm
12 mm to drop
RqJA down to 100°C/W with 35 mm copper thickness (1 oz)
or 6.5 mm 6.5 mm with 70 mm copper thickness (2 oz).
As one can see, we do not recommend using the SO−8
package and the DSS if the part operates at high switching
frequencies. In that case, an auxiliary winding is the best
solution.
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short−circuit protection. A
short−circuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
Optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please note
that this can also happen in case of feedback loss, e.g. a
broken Optocoupler. To account for this situation,
VCC
REGULATION
OCCURS HERE
12 V
10 V
LATCHOFF
PHASE
5.3 V
TIME
DRV
DRIVER
PULSES
TIME
If the fault is relaxed during the Vcc
natural fall down sequence, the IC
automatically resumes.
If the fault still persists when Vcc
reached VCCON, then the controller
cuts everything off until recovery.
INTERNAL
FAULT FLAG
FAULT IS
RELAXED
STARTUP PHASE
TIME
FAULT OCCURS HERE
Figure 24.
Soft−Start
The NCP1207A features an internal 1 ms soft−start to
soften the constraints occurring in the power supply during
startup. It is activated during the power on sequence. As
soon as VCC reaches VCCOFF , the peak current is gradually
increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). The soft−start is also activated during the
overcurrent burst (OCP) sequence. Every restart attempt is
followed by a soft−start activation. Generally speaking, the
soft−start will be activated when VCC ramps up either from
zero (fresh power−on sequence) or 5.3 V, the latchoff
voltage occurring during OCP.
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13
NCP1207A
Calculating the Vcc Capacitor
As the above section describes, the fall down sequence
depends upon the VCC level: how long does it take for the
VCC line to go from 12 V to 10 V? The required time depends
on the startup sequence of your system, i.e. when you first
apply the power to the IC. The corresponding transient fault
duration due to the output capacitor charging must be less
than the time needed to discharge from 12 V to 10 V,
otherwise the supply will not properly start. The test consists
in either simulating or measuring in the lab how much time
the system takes to reach the regulation at full load. Let’s
suppose that this time corresponds to 6.0 ms. Therefore a
VCC fall time of 10 ms could be well appropriated in order
to not trigger the overload detection circuitry. If the
corresponding IC consumption, including the MOSFET
drive, establishes at 1.8 mA (e.g. with an 11 nC MOSFET),
we can calculate the required capacitor using the following
Figure 25.
This plot gathers waveforms captured at three different
operating points:
1st upper plot: free run, valley switching operation,
Pout = 26 W
2nd middle plot: min Toff clamps the switching frequency
and selects the second valley
3rd lowest plot: the skip slices the second valley pattern
and will further expand the burst as Pout goes low
formula: Dt + DV @ C, with DV = 2.0 V. Then for a wanted
i
Dt of 10 ms, C equals 9.0 mF or 22 mF for a standard value.
When an overload condition occurs, the IC blocks its
internal circuitry and its consumption drops to 330 mA
typical. This happens at VCC = 10 V and it remains stuck
until VCC reaches 5.3 V: we are in latchoff phase. Again,
using the calculated 22 mF and 330 mA current consumption,
this latchoff phase lasts: 313 ms.
HV Pin Recommended Protection
When the user unplugs a power supply built with a QR
controller such as the NCP1207A, one instance can occur:
A negative ringing can take place on pin8 due to a
resonance between the primary inductance and the bulk
capacitor. As any CMOS device, the NCP1207A is sensitive
to negative voltages that could appear on it’s pins and could
create an internal latch−up condition.
For this reason, we recommend adding a resistor between
the bulk capacitor and the VCC pin.
VGATE (5 V/div)
VRsense (200 mV/div)
200 mA X RSKIP
Operation Shots
Below are some oscilloscope shots captured at
Vin = 120 VDC with a transformer featuring a 800 mH
primary inductance.
Current Sense Pin (200 mV/div)
Figure 26.
This picture explains how the 200 mA internal offset
current creates the skip cycle level.
http://onsemi.com
14
NCP1207A
The short−circuit protection forces the IC to enter burst in
presence of a secondary overload.
VCC (5 V/div)
VGATE (5 V/div)
Figure 27.
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15
NCP1207A
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
H
0.10 (0.004)
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
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16
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP1207A
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
N
SEATING
PLANE
D
H
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10 _
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10_
0.030
0.040
M
K
G
0.13 (0.005)
M
T A
M
B
M
The product described herein (NCP1207A), may be covered by one or more of the following U.S. patents: 6,362,067, 6,385,060, 6,385,061, 6,429,709,
6,587,357, 6,633,193. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP1207A/D