TECHNICAL DATA IN74HC30A 8-Input NAND Gate The IN74HC30A is high-speed Si-gate CMOS device and is compatible with low power Schottky TTL (LSTTL) . The device provide the 8-input NAND function. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC30AN Plastic IN74HC30AD SOIC TA = -55° ÷ 125° C for all packages LOGIC DIAGRAM A PIN ASSIGNMENT B A 1 14 V CC B 2 13 - C 3 12 H D 4 11 G E 5 10 -. F F 6 9 - G GND 7 8 Y C D Y E H FUNCTION TABLE PIN 14 =VCC PIN 7 = GND Inputs Output A B С D E F G H Y L X X X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H H H H L X = don’t care Rev. 00 IN74HC30A MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP** SOIC Package** 750 500 mW -65 to +150 °C 260 °C VOUT IIN Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Rev. 00 IN74HC30A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions VCC Guaranteed Limit V 25 °C to -55°C ≤85 °C ≤125 °C Unit VIH Minimum High-Level Input Voltage VOUT≤0.1V or VOUT ≥VCC-0.1V ⎢IOUT⎢≤ 20 µA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT≤0.1V or VOUT ≥VCC-0.1V ⎢IOUT⎢≤ 20 µA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL ⎢IOUT⎢ ≤ - 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V VIN= VIH or VIL ⎢IOUT⎢ ≤ - 2.4 mA 3.0 2.48 2.34 2.20 VIN= VIH or VIL ⎢IOUT⎢ ≤ - 4.0 mA 4.5 3.98 3.84 3.70 VIN= VIH or VIL ⎢IOUT⎢ ≤ - 5.2 mA 6.0 5.48 5.34 5.20 VIN= VIH or VIL ⎢IOUT⎢ ≤ 20 µA 2.0 4.5 6.0 3.0 0.1 0.1 0.1 0.26 0.1 0.1 0.1 0.33 0.1 0.1 0.1 0.4 4.5 0.26 0.33 0.4 6.0 0.26 0.33 0.4 6.0 -0.1 -1.0 -1.0 µA VOL Maximum Low-Level Output Voltage VIN= VIH or VIL ⎢IOUT⎢ ≤ 2.4 mA VIN= VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA VIN= VIH or VIL ⎢IOUT⎢ ≤ 5.2 mA VIN= 0 V V IIL Maximum Low-Level Input Leakage Current IIH Maximum High-Level Input Leakage Current VIN= VCC 6.0 0.1 1.0 1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or 0 V IOUT=0 µA 6.0 2.0 20 40 µA Rev. 00 IN74HC30A AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit tPHL, tPLH Maximum Propagation Delay (Figure 1) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tTHL, tTLH Maximum Output Transition Time (Figure 1) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Maximum Input Capacitance 5.0 10 10 10 pF CIN Power Dissipation Capacitance (Per Gate) CPD TA=25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 27 pF tr tf V1 0.9 0.9 Input V2 V2 0.1 GND 0.1 tPHL tPLH VCC 0.9 0.9 V2 Output V2 0.1 0.1 0V tTHL tTLH V1 = VCC V2 = 0.5 VCC Figure 1. Switching Waveforms VCC VI VO PULSE GENERATOR RT Termination resistance RT – should be equal to ZOUT of pulse generators DEVICE UNDER TEST CL 50 pF Figure 2. Test Circuit Rev. 00 IN74HC30A N SUFFIX PLASTIC DIP (MS - 001AA) A Dimension, mm 8 14 B 7 1 Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE N G M K J H D 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AB) Dimension, mm A 14 8 H B 1 G P 7 R x 45 C -TK D SEATING PLANE M Symbol MIN MAX A 8.55 8.75 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G 1.27 H 5.27 J 0° 8° K 0.1 0.25 1. Dimensions A and B do not include mold flash or protrusion. M 0.19 0.25 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. P 5.8 6.2 R 0.25 0.5 J 0.25 (0.010) M T C M NOTES: F Rev. 00