AD AD9732BRS 10-bit, 200 msps d/a converter Datasheet

a
ANALOG
RETURN
D1
D3
D4
TTL
DRIVE
LOGIC
D5
D6
D7
D8
D9
The AD9732 is a 10-bit, 200 MSPS, bipolar D/A converter that
is optimized to provide high dynamic performance, yet offers
lower power dissipation and a more economical price than previous high speed DAC solutions. The AD9732 was primarily
designed for demanding communications systems applications
where maximum spurious-free dynamic range (SFDR) is required
at high throughput rates. The proliferation of digital communications into base station and high volume subscriber-end markets has created a demand for high performance bipolar DACs
delivered at CMOS associated levels of power dissipation and
cost. The AD9732 is the answer to that demand.
Optimized for direct digital synthesis (DDS) and digital modulator waveform reconstruction, the AD9732 provides >50 dB of
wideband harmonic suppression over the dc to 80 MHz analog
output bandwidth. This signal bandwidth addresses the transmit
IOUT
IOUT
D10
REFIN
CLOCK
INTERNAL
VOLTAGE
REFERENCE
GENERAL DESCRIPTION
REGISTER
D2
SWITCH NETWORK
APPLICATIONS
Digital Communications
Direct Digital Synthesis
Waveform Reconstruction
High Speed Imaging
FUNCTIONAL BLOCK DIAGRAM
DECODERS AND DRIVERS
FEATURES
200 MSPS Throughput Rate
3.3 V PECL Digital Input
65 dB SFDR @ 2 MHz A OUT, 200 MSPS/54 dB @ 40 MHz
A OUT, 200 MSPS
Low Power: 305 mW
Fast Settling: 5 ns to 1/2 LSB
Low Glitch Energy: 6 pVs
Internal Reference
28-Lead SSOP Packaging
10-Bit, 200 MSPS
D/A Converter
AD9732
CONTROL
AMP
AD9732
RSET
REFOUT
CONTROL
AMP IN
CONTROL
AMP OUT
DIGITAL
+VS
spectrum in many of the emerging digital communications applications where signal purity is critical. Narrowband (± 1 MHz
window), the AD9732 provides an SFDR of greater than 75 dB.
This level of wideband and narrowband ac performance, coupled
with its 200 MSPS throughput rate, enables the AD9732 to
present outstanding value in the high speed DAC function.
The AD9732 is packaged in a 28-lead SSOP and is specified to
operate over the extended industrial temperature range of –40°C
to +85°C. Digital inputs and clock are positive-ECL compatible.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD9732–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+V
S
Parameter
Temp
Test
Level
Min
AD9732BRS
Typ
THROUGHPUT RATE
+25°C
IV
165
200
MHz
10
Bits
= +5 V, ENCODE = 125 MSPS, RSET = 1.95 k⍀ (for 20 mA I OUT) unless otherwise noted)
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Max
Units
+25°C
Full
+25°C
Full
I
VI
I
VI
0.25
0.36
0.6
0.7
1
1
1.5
1.5
LSB
LSB
LSB
LSB
+25°C
Full
+25°C
Full
I
VI
I
VI
V
35
40
2.5
2.5
0.04
70
100
5
5
µA
µA
% FS
% FS
µA/°C
REFERENCE/CONTROL AMP
Internal Reference Voltage2
Internal Reference Voltage Drift
Internal Reference Output Current3
Amplifier Input Impedance
Amplifier Bandwidth
+25°C
Full
Full
+25°C
+25°C
I
IV
VI
I
I
3.75
150
3.85
50
2.5
V
µV/°C
µA
kΩ
MHz
REFERENCE INPUT4
Reference Input Impedance
Reference Multiplying Bandwidth5
+25°C
+25°C
V
V
4.6
75
kΩ
MHz
OUTPUT PERFORMANCE
Output Current4, 6
Output Compliance
Output Resistance
Output Capacitance
Voltage Settling Time to 1/2 LSB (tST)7
Propagation Delay (tPD)8
Glitch Impulse9
Output Slew Rate10
Output Rise Time10
Output Fall Time10
Full
Full
+25°C
+25°C
+25°C
+25°C
Full
Full
Full
Full
V
IV
V
V
V
V
V
V
V
V
Full
Full
+25°C
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
+25°C
VI
VI
I
I
V
IV
IV
IV
IV
IV
IV
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
I
VI
I
VI
V
V
V
Integral Nonlinearity
INITIAL OFFSET ERROR
Zero-Scale Offset Error
Full-Scale Gain Error1
Offset Drift Coefficient
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Minimum Data Setup Time (tS )11
Minimum Data Hold Time (tH)12
Clock Pulsewidth Low (pwMIN)
Clock Pulsewidth High (pwMAX)
POWER SUPPLY13
Digital +V Supply Current
Analog +V Supply Current
Power Dissipation14
Power Supply Rejection Ratio (PSRR)
–2–
3.65
–50
+500
20
2
5.75
240
5
4.75
2.7
5.9
450
1
1
2.4
–1
1.7
0.01
2
0.7
1
0.7
1
1.6
10
1
1.5
1.5
1.5
1.5
2
2
15
10
10
10
25
20
305
350
200
35
40
30
30
mA
V
Ω
pF
ns
ns
pVs
V/µs
ns
ns
V
V
µA
µA
pF
ns
ns
ns
ns
ns
ns
mA
mA
mA
mA
mW
mW
µA/V
REV. A
AD9732
Temp
Test
Level
SFDR PERFORMANCE (Wideband)
2 MHz AOUT
10 MHz AOUT
20 MHz AOUT
40 MHz AOUT
2 MHz AOUT (Clock = 165 MHz)
10 MHz AOUT (Clock = 165 MHz)
20 MHz AOUT (Clock = 165 MHz)
40 MHz AOUT (Clock = 165 MHz)
65 MHz AOUT (Clock = 165 MHz)
65 MHz AOUT (Clock = 200 MHz)
80 MHz AOUT (Clock = 200 MHz)
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
V
V
V
V
V
V
V
V
V
V
V
66
63
57
52
63
62
56
51
48
45
43
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
SFDR PERFORMANCE (Narrowband)15
2 MHz; 2 MHz Span
25 MHz; 2 MHz Span
10 MHz; 5 MHz Span (Clock = 200 MHz)
+25°C
+25°C
+25°C
V
V
V
77
65
70
dB
dB
dB
+25°C
V
69
dB
+25°C
V
61
dB
Parameter
Min
AD9732BRS
Typ
Max
Units
15
INTERMODULATION DISTORTION16
F1 = 800 kHz, F2 = 900 kHz to Nyquist
F1 = 800 kHz, F2 = 900 kHz, Narrowband
(2 MHz)
NOTES
1
Measured as an error in ratio of full-scale current to current through R SET (640 µA nominal); ratio is nominally 32. DAC load is virtual ground.
2
Internal reference voltage is tested under load conditions specified in Internal Reference Output Current specification.
3
Internal reference output current defines load conditions applied during Internal Reference Voltage test.
4
Full-scale current variations among devices are higher when driving REFERENCE IN directly.
5
Frequency at which a 3 dB change in output of DAC is observed; R L = 50 Ω; 100 mV modulation at midscale.
6
Based on I FS = 32 ([CONTROL AMP IN – (+VS )]/RSET) when using internal control amplifier. DAC load is virtual ground.
7
Measured as voltage settling at midscale transition to 0.1%; R L = 50 Ω.
8
Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.
9
Peak glitch impulse is measured as the largest area under a single positive or negative transient.
10
Measured with R L = 50 Ω and DAC operating in latched mode.
11
Data must remain stable for a specified time prior to rising edge of CLOCK.
12
Data must remain stable for a specified time after rising edge of CLOCK.
13
Supply voltages should remain stable with ±5% for nominal operation.
14
Power dissipation calculation includes current through a 50 Ω load.
15
SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencies in the output spectrum window.
The frequency span dc to Nyquist unless otherwise noted.
16
Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products
created will manifest themselves at sum and difference frequencies of the two tones.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
IV Parameter is guaranteed by design and characterization
testing.
I
V Parameter is a typical value only.
100% production tested.
II 100% production tested at +25°C and sample tested at
specified temperatures.
III Sample tested only.
VI 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature
range.
ORDERING GUIDE
REV. A
Model
Temperature
Range
Package
Description
Package
Option
AD9732BRS
AD9732/PCB
–40°C to +85°C
+25°C
28-Lead Small Outline (SSOP)
Evaluation Board
RS-28
–3–
AD9732
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Control Amplifier Input Voltage Range . . . . . . . . . 0 V to +VS
Reference Input Voltage Range . . . . . . . . . . . . . . . 0 V to +VS
Internal Reference Output Current . . . . . . . . . . . . . . . 500 µA
Control Amplifier Output Current . . . . . . . . . . . . . . ± 2.5 mA
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
Lead Temperature (10 sec) Soldering . . . . . . . . . . . . +300°C
D9 (MSB) 1
28
DIGITAL +VS
D8 2
27
GND
D7 3
26
CONTROL AMP IN
D6 4
25
REF OUT
D5 5
24
CONTROL AMP OUT
D4 6
23
REF IN
AD9732
D3 7
TOP VIEW 22 GND
D2 8 (Not to Scale) 21 IOUTB
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
D1 9
20
IOUT
D0 (LSB) 10
19
ANALOG RETURN
CLOCK 11
18
ANALOG +VS
NC 12
17
RSET
NC 13
16
GND
DIGITAL +VS 14
15
DIGITAL +VS
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin Number
Name
Function
1
2–9
10
11
12, 13
14, 15, 28
16, 22, 27
18
17
D9 (MSB)
D8–D1
D0 (LSB)
CLOCK
NC
DIGITAL +VS
GND
ANALOG +VS
RSET
19
ANALOG RETURN
20
IOUT
21
IOUTB
23
REF IN
24
CONTROL AMP OUT
25
REF OUT
26
CONTROL AMP IN
Most significant data bit of digital input word.
Eight bits of 10-bit digital input word.
Least significant data bit of digital input word.
TTL-compatible edge-triggered latch enable signal for on-board registers.
No internal connection to this pin. Recommend tie to ground.
+5 V supply voltage for digital circuitry.
Converter Ground.
+5 V supply voltage for analog circuitry.
Connection for external reference set resistor; nominal 1.96 kΩ. Full-scale output
current = 32 [Control Amp + VS] (Reset).
Analog Return. This point and the reference side of the DAC load resistors should be
connected to the same potential (Analog +VS).
Analog current output; full-scale current occurs with a digital word input of all “1s”
with external load resistor, output voltage = IOUT (RLOAD储RINTERNAL ). RINTERNAL is
nominally 240 Ω.
Complementary analog current output; full-scale current occurs with a digital word
input of all “0s.”
Normally connected to CONTROL AMP OUT (Pin 24). Direct line to DAC current
source network. Voltage changes (noise) at this point have a direct effect on the fullscale output current of the DAC. Full-scale current output = 32 (CONTROL AMP IN/
RSET) when using internal amplifier. DAC load is virtual ground.
Normally connected to REF IN (Pin 23). Output of internal control amplifier, which
provides a reference for the current switch network.
Normally connected to CONTROL AMP IN (Pin 26). Internal voltage reference,
nominally 3.75 V.
Normally connected to REF OUT (Pin 25) if not connected to external reference.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9732 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A
AD9732
pwMIN
pwMAX
CLOCK
tS
tH
CODE 1
DATA
DATA
CODE 2
DATA
CODE 3
DATA
CODE 4
DATA
CODE 2
ANALOG OUTPUT
CODE 4
CODE 1
CODE 3
a.
DETAIL OF SETTLING TIME
GLITCH AREA = 1/2 HEIGHT 3 WIDTH
H
CLOCK
SPECIFIED
ERROR BAND
tPD
W
ANALOG OUTPUT
tST
b.
c.
Figure 1. Timing Diagrams
REV. A
–5–
AD9732
75
55
70
65
50
SFDR – dB
SFDR – dB
60
55
50
45
45
40
35
30
0
10
20
30
40
50
60
AOUT – MHz
70
80
90
40
20
100
18
Figure 2. Narrowband SFDR (Clock = 200 MHz) vs. AOUT
Frequency
16
14
12
10
IOUT – mA
8
6
2
4
Figure 5. SFDR vs. IOUT
90
56
54
80
52
50
SFDR – dB
SFDR – dB
70
60
50
48
46
44
40
42
30
5
10
15
20
25
30
35
40
AOUT – MHz
45
50
55
40
60
Figure 3. Narrowband SFDR (Clock = 125 MHz) vs. AOUT
Frequency
25
45
65
85 105 125
CLOCK – MHz
145
165
185
205
Figure 6. SFDR vs. Clock for f CLK/AOUT = 3.125
65
0.4
60
0.3
0.2
55
0.1
50
LSB
SFDR – dB
5
0
45
–0.1
40
–0.2
35
–0.3
30
10
20
30
40
50
60
AOUT – MHz
70
80
–0.4
90
Figure 4. Wideband SFDR (200 MHz Clock) vs. A OUT
Figure 7. Typical Differential Nonlinearity Performance
(DNL)
–6–
REV. A
AD9732
0.6
0
1
ENCODE = 125MHz
AOUT = 20MHz
SPAN = 62.5MHz
SFDR = 57dB
–10
0.4
–20
–30
0.2
LSB
–40
0
–50
–60
1
–0.2
–70
–80
–0.4
–90
–0.6
–100
START 0Hz
Figure 8. Typical Integral Nonlinearity Performance (INL)
0
ENCODE = 125MHz
AOUT = 2MHz
SPAN = 62.5MHz
SFDR = 66dB
–20
–10
–20
–30
–30
–40
–40
–50
–50
–60
–60
1
–80
–90
–90
–100
START 0Hz
6.25MHz/
1
–100
STOP 62.5MHz
START 0Hz
Figure 9. Wideband SFDR 2 MHz A OUT; 125 MHz Clock
ENCODE = 125MHz
AOUT = 10MHz
SPAN = 62.5MHz
SFDR = 63dB
–20
6.25MHz/
1
ENCODE = 200MHz
AOUT = 40MHz
SPAN = 100MHz
SFDR = 54dB
–10
–20
–30
–30
–40
–40
–50
–50
–60
1
–60
1
–70
STOP 62.5MHz
Figure 12. Wideband SFDR 40 MHz AOUT; 125 MHz Clock
0
1
–10
–70
–80
–80
–90
–90
–100
–100
START 0Hz
6.25MHz/
STOP 62.5MHz
START 0Hz
Figure 10. Wideband SFDR 10 MHz A OUT; 125 MHz Clock
REV. A
1
ENCODE = 125MHz
AOUT = 40MHz
SPAN = 62.5MHz
SFDR = 52dB
–70
–80
0
STOP 62.5MHz
Figure 11. Wideband SFDR 20 MHz AOUT; 125 MHz Clock
0
1
–10
–70
6.25MHz/
10MHz/
STOP 100MHz
Figure 13. Wideband SFDR 40 MHz AOUT; 200 MHz Clock
–7–
AD9732
1
0
–10
–20
0
1
ENCODE = 200MHz
AOUT = 65MHz
SPAN = 200MHz
SFDR = 45dB
ENCODE = 125MHz
AOUT1 = 800kHz
AOUT2 = 900kHz
SPAN = 2MHz
IMD = 61dB
–10
–20
–30
–30
–40
–40
1
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
START 0Hz
10MHz/
1
–100
STOP 100MHz
START 0Hz
Figure 14. Wideband SFDR 65 MHz A OUT; 200 MHz Clock
200MHz/
STOP 2MHz
Figure 16. Wideband Intermodulation Distortion F1 =
800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 2 MHz
1
0
–10
–20
0
1
ENCODE = 200MHz
AOUT = 80MHz
SPAN = 100MHz
SFDR = 43dB
ENCODE = 125MHz
AOUT1 = 800kHz
AOUT2 = 900kHz
SPAN = 62.5MHz
IMD = 69dB
–10
–20
–30
–30
–40
–40
1
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
1
–100
–100
START 0Hz
10MHz/
START 0Hz
STOP 100MHz
Figure 15. Wideband SFDR 80 MHz A OUT; 200 MHz Clock
6.25MHz/
STOP 62.5MHz
Figure 17. Wideband Intermodulation Distortion F1 =
800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 62.5 MHz
–8–
REV. A
AD9732
However, it should be noted that output settling time, for
changes in the digital word, will be degraded.
APPLICATION NOTES
THEORY OF OPERATION
The AD9732 high speed digital-to-analog converter utilizes most
significant bit decoding and segmentation techniques to reduce
glitch impulse and deliver high dynamic performance on lower
power consumption than previous bipolar DAC technologies.
+VS
RSET
RSET
AD9732
The design is based on four main subsections: the decode/driver
circuits, the edge-triggered data register, the switch network and
the control amplifier. An internal bandgap reference is included
to allow operation of the device with minimum external support
components.
3.8V TO 4.4V
2.5MHz TYPICAL
CONTROL
AMP IN
RT
CONTROL
AMP OUT
Digital Inputs/Timing
REFERENCE IN
The AD9732 has PECL high speed single-ended inputs for data
inputs and clock. The switching threshold is +2.0 V.
0.1mF
In the decode/driver section, the three MSBs are decoded to
seven “thermometer code” lines. An equalizing delay is included
for the seven least significant bits and the clock signals. This
delay minimizes data skew and data setup-and-hold times at the
register inputs.
Figure 18. Lower Frequency Multiplying Circuit
The REFERENCE IN pin can also be driven directly for wider
bandwidth multiplying operation. The analog signal for this
mode of operation must have a signal swing in the range of
0.95 V to 1.9 V. This can be implemented by capacitively coupling into REFERENCE IN a signal with a dc bias of 1.9 V (IOUT
= 22.5 mA) to 0.95 V (IOUT = 3 mA), as shown in Figure 19, or
by dividing REFERENCE IN with a low impedance op amp
whose signal swing is limited to the stated range.
The on-board register is rising-edge triggered and should be
used to synchronize data to the current switches by applying a
pulse with proper data setup-and-hold times as shown in the
timing diagram. Although the AD9732 is designed to provide
isolation of the digital inputs to the analog output, some coupling of digital transitions is inevitable. Digital feedthrough can
be minimized by forming a low-pass filter at the digital input by
using a resistor in series with the capacitance of each digital
input. This common high speed DAC application technique has
the effect of isolating digital input noise from the analog output.
AD9732
APPROX
1.4V
REFERENCE IN
References
The internal bandgap reference, control amplifier and reference
input are pinned out to provide maximum user flexibility in
configuring the reference circuitry for the AD9732. When using
the internal reference, REF OUT (Pin 25) should be connected
to CONTROL AMP IN (Pin 26). CONTROL AMP OUT (Pin
24) should be connected to REF IN (Pin 23). A 0.1 µF ceramic
capacitor connected from Pin 23 to GND improves settling time
by decoupling switching noise from the current sink baseline. A
reference current cell provides feedback to the control amplifier
by sinking current through RSET (Pin 17).
Figure 19. Wideband Multiplying Circuit
Analog Output
The switch network provides complementary current outputs
IOUT and IOUTB. The design of the AD9732 is based on statistical current source matching, which provides a 10-bit linearity
without trim. Current is steered to either IOUT or IOUTB in proportion to the digital input word. The sum of the two currents is
always equal to the full-scale output current. The current can be
converted to a voltage by resistive loading as shown in Figure
20. Both IOUT and IOUTB should be equally loaded for best overall performance. The voltage that is developed is the product of
the output current and the value of the load resistor.
Full-scale current is determined by CONTROL AMP IN and
RSET according to the following equation:
IOUT(FS) = 32 ([CONTROL AMP IN – (+VS)]/RSET)
The internal reference is nominally –1.25 V (referenced to
Analog +VS), with a tolerance of ± 8% and typical drift over
temperature of 150 ppm/°C. If greater accuracy or temperature
stability is required, an external reference can be used. The
AD589 reference features 10 ppm/°C drift over the 0°C to
+70°C temperature range.
EVALUATION BOARD
The performance characteristics of the AD9732 make it ideally
suited for direct digital synthesis (DDS) and other waveform
synthesis applications. The AD9732 evaluation board provides a
platform for analyzing performance under optimum layout conditions. The AD9732 also provides a reference for high speed
circuit board layout techniques.
Two modes of multiplying operation are possible with the
AD9732. Signals with bandwidths up to 2.5 MHz and input
swings from 3.8 V to 4.4 V can be applied to the CONTROL
AMP IN pin as shown in Figure 18. Because the control amplifier is internally compensated, the 0.1 µF capacitor discussed
above can be reduced to maximize the multiplying bandwidth.
REV. A
+VS
–9–
–10–
7
OSC_OUT
R14
390V
CLKB
TB4
TB1
4
3
2
1
+5V
E25
C9
10mF
C2
0.1mF
E10
E12
E14
E16
E18
E20
E22
E24
E26
C3
0.1mF
NOTE:
SERIES 64.9V RESISTORS
CAN BE BYPASSED BY
JUMPING E7 TO E8, ECT.
R12
64.9V
R11
64.9V
R10
64.9V
R9
64.9V
R8
64.9V
R4
64.9V
R3
64.9V
R2
64.9V
E8
1
CMOS CLOCK OSCILLATOR
GND
CR1
R17
1N914 180V
8
E23
1
+5V
E21
1
R13
780V
E19
1
1
+5V
E17
1
1
14
E15
1
1
IN
+V
1
Y1
1
1
1
NO_CONN
1
1
1
1
SW41
1
1
R6
50V
CLK
E13
1
E6
2
4
6
8
10
12
14
16
18
20
E11
R1
64.9V
R18
64.9V
1
E5
1
3
5
7
9
11
13
15
17
19
H1
E5
1
E4
1
E2
SW1
E7
1
E3
E1
1
BNC
J1
1
CLKB
5 = GND PIN FOR EXTERNAL CLOCK
ADD 50V TERMINATION FOR EXTERNAL CLOCK
R5
50V
4 TO 6
BNC EXTERNAL PECL CLOCK (50V)
ON BOARD XTAL OSCILLATOR
3 = INPUT PIN FOR EXTERNAL CLOCK
2 TO 4
1 TO 3
CLOCK MATRIX DESCRIPTION
CONNECTIONS
1
C37DRPF
P1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
SW1
C4
0.1mF
CLK
C5
0.1mF
R7
1960V
1
2
3
4
5
6
7
8
9
10
11
12
13
17
C6
0.1mF
C7
0.1mF
+5V: 14, 15, 18, 19, 28
ANALOG GND 22
DIGITAL GND 16, 27
D9 (MSB)
IOUT
D8
D7
I_OUT
D6
U1
D5
D4 AD9732
D3
REFOUT
D2
D1
C_AMP_IN
D0 (LSB)
CLK
NC1
C_AMP_OUT
NC2
RSET
REF_IN
23
24
26
25
20
21
SINGLE-ENDED RESISTIVE TERMINATED
29 TO 32
31 TO 30
C8
10mF
R16
25V
E30
1
E32
1
E28
1
+
C1
0.1mF
E31
1
E29
1
E27
1
SW2
DIFFERENTIAL TRANSFORMER
COUPLED TERMINATION
OUTPUT DESCRIPTION
27 TO 29
30 TO 28
SW2
T1
6
4
R15
50V
C10
0.1mF
C11
0.1mF
T1–1T
1
2
3
+5V
+5V
DAC_OUT
(SINGLE ENDED)
J2
OUT TO 50V LOAD
J3
OUT TO 50V LOAD
DAC_OUT
(DIFFERENTIAL)
AD9732
Figure 20. Evaluation Board
REV. A
AD9732
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3365a–0–4/99
28-Lead SSOP
(RS-28)
28
15
1
14
0.078 (1.98) PIN 1
0.068 (1.73)
0.07 (1.79)
0.066 (1.67)
88
0.015 (0.38)
SEATING 0.009 (0.229) 08
0.010 (0.25)
PLANE
0.005 (0.127)
0.03 (0.762)
0.022 (0.558)
PRINTED IN U.S.A.
0.008 (0.203) 0.0256
(0.65)
0.002 (0.050) BSC
0.212 (5.38)
0.205 (5.21)
0.311 (7.9)
0.301 (7.64)
0.407 (10.34)
0.397 (10.08)
REV. A
–11–