CS5101 Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters The CS5101 is a bipolar monolithic secondary side post regulator (SSPR) which provides tight regulation of multiple output voltages in AC/DC or DC/DC converters. Leading edge pulse width modulation is used with the CS5101. The CS5101 is designed to operate over an 8.0 V to 45 V supply voltage (VCC) range and up to a 75 V drive voltage (VC). The CS5101 features include a totem pole output with 1.5 A peak output current capability, externally programmable overcurrent protection, an on chip 2.0% precision 5.0 V reference, internally compensated error amplifier, externally synchronized switching frequency, and a power switch drain voltage monitor. It is available in a 14 lead plastic DIP or a 16 lead wide body SOIC package. http://onsemi.com PDIP−14 N SUFFIX CASE 646 14 1 SO−16WB DW SUFFIX CASE 751G 16 1 Features MARKING DIAGRAMS AND PIN ASSIGNMENTS 1.5 A Peak Output (Grounded Totem Pole) 8.0 V to 75 V Gate Drive Voltage 8.0 V to 45 V Supply Voltage 300 ns Propagation Delay 1.0% Error Amplifier Reference Voltage Lossless Turn On and Turn Off Sleep Mode: < 100 mA Overcurrent Protection with Dedicated Differential Amp Synchronization to External Clock External Power Switch Drain Voltage Monitor Pb−Free Packages are Available* 1 SYNC VCC VREF CS5101EN14 AWLYYWWG • • • • • • • • • • • LGND VFB COMP 14 VD VC VG PGND IS COMP IS− IS+ RAMP PDIP−14 1 CS5101 AWLYYWWG SYNC VCC VREF DGND AGND VFB COMP RAMP 16 VD VC VG PGND PGND IS COMP IS− IS+ SO−16WB A WL YY WW G *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 6 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: CS5101/D CS5101 VSY L1 CR4 1 3 4 Q1 VOUT R10 TR 5 R8 6 R11 R13 + CR5 R5 R6 R9 R12 C6 R14 GND CR1 + R1 R2 C5 CR3 R7 R3 VSYNC VD VCC VC CS5101 SSPR VREF CR2 LGND PGND VFB + C1 C2 R4 VG C4 IS COMP COMP IS− RAMP IS+ 2 C3 CR Figure 1. Application Diagram MAXIMUM RATINGS Rating Value Unit Power Supply Voltage, VCC −0.3 to 45 V VSYNC and Output Supply Voltages, VC, VG, VSYNC, VD −0.3 to 75 V VIS+, VIS− (VCC − 4.0 V, up to 24 V) −0.3 to 24 V VREF, VFB, VCOMP, VRAMP, VISCOMP −0.3 to 10 V Operating Junction Temperature, TJ −40 to +150 °C Operating Temperature Range −40 to +85 °C Storage Temperature Range −65 to +150 °C Output Energy (Capacitive Load Per Cycle) 5.0 mJ ESD Human Body 2.0 kV 260 peak 230 peak °C °C Lead Temperature Soldering Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 10 second maximum 2. 60 second maximum above 183°C http://onsemi.com 2 CS5101 ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 85°C, −40°C ≤ TJ ≤ 150°C, 10 V < VCC < 45 V, 8.0 V < VC < 75 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Error Amplifier Input Voltage Initial Accuracy VFB = VCOMP, VCC = 15 V, T = 25°C, Note 3 1.98 2.00 2.02 V Input Voltage VFB = VCOMP, includes line and temp 1.94 2.00 2.06 V Input Bias Current VFB = 0 V, IVFB flows out of pin − − 500 nA Open Loop Gain 1.5 V < VCOMP < 3.0 V 60 70 − dB Unity Gain Bandwidth 1.5 V < VCOMP < 3.0 V, Note 3 0.7 1.0 − MHz Output Sink Current VCOMP = 2.0 V, VFB = 2.2 V 2.0 8.0 − mA Output Source Current VCOMP = 2.0 V, VFB = 1.8 V 2.0 6.0 − mA VCOMP High VFB = 1.8 V 3.3 3.5 3.7 V VCOMP Low VFB = 2.2 V 0.85 1.0 1.15 V PSRR 10 V < VCC < 45 V, VFB = VCOMP, Note 3 60 70 − dB Output Voltage Initial Accuracy VCC = 15 V, T = 25°C, Note 3 4.9 5.0 5.1 V Output Voltage 0 A < IREF < 8.0 mA 4.8 5.0 5.2 V Line Regulation 10 V < VCC < 45 V, IREF = 0 A − 10 60 mV Load Regulation 0 A < IREF < 8.0 mA − 20 60 mV Current Limit VREF = 4.8 V 10 50 − mA VREF−OK FAULT V VSYNC = 5.0 V, VREF = VLOAD 4.10 4.40 4.60 V VREF−OK V VSYNC = 5.0 V, VREF = VLOAD 4.30 4.50 4.80 V 40 100 250 mV Voltage Reference VREF−OK Hysteresis − Current Sense Amplifier IS COMP High V IS+ = 5.0 V, IS− = IS COMP 4.7 5.0 5.3 V IS COMP Low V IS+ = 0 V, IS− = IS COMP 0.5 1.0 1.3 V Source Current IS+ = 5.0 V, IS− = 0 V 2.0 10 − mA Sink Current IS− = 5.0 V, IS+ = 0 V 10 20 − mA Open Loop Gain 1.5 V ≤ VCOMP ≤ 4.5 V, RL = 4.0 kW 60 80 − dB CMRR Note 3 60 80 − dB PSRR 10 V < VCC < 45 V, Note 3 60 80 − dB Unity Gain Bandwidth 1.5 V ≤ VCOMP ≤ 4.5 V, RL = 4.0 kW, Note 3 0.5 0.8 − MHz Input Offset Voltage VIS+ = 2.5 V, VIS− = VISCOMP −8.0 0 8.0 mV Input Bias Currents VIS+ = VIS− = 0 V, IIS flows out of pins − 20 250 nA Input Offset Current (IS+, IS−) −250 0 250 nA Note 3 −0.3 − VCC − 4.0 V RAMP Source Current Initial Accuracy VSYNC = 5.0 V, VRAMP = 2.5 V, T = 25°C, Note 3 0.18 0.20 0.22 mA RAMP Source Current VSYNC = 5.0 V, VRAMP = 2.5 V 0.16 0.20 0.24 mA RAMP Sink Current VSYNC = 0 V, VRAMP = 2.5 V 1.0 4.0 − mA RAMP Peak Voltage VSYNC = 5.0 V 3.3 3.5 3.7 V RAMP Valley Voltage VSYNC = 0 V 1.4 1.5 1.6 V RAMP Dynamic Range VRAMPDR = VRAMPPK − VRAMPVY 1.7 2.0 2.3 V RAMP Sleep Threshold Voltage VRAMP @ VREF < 2.0 V 0.3 0.6 1.0 V SYNC Threshold VSYNC @ VRAMP > 2.5 V 2.3 2.5 2.7 V − 1.0 20 mA Input Signal Voltage Range − RAMP/SYNC Generator SYNC Input Bias Current VSYNC = 0 V, ISYNC flows out of pin 3. Guaranteed by design. Not 100% tested in production. http://onsemi.com 3 CS5101 ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 85°C, −40°C ≤ TJ ≤ 150°C, 10 V < VCC < 45 V, 8.0 V < VC < 75 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Output Stage VG, High VSYNC = 5.0 V, IVG = 200 mA, VC − VG − 1.6 2.5 V VG, Low VSYNC = 0 V, IVG = 200 mA − 0.9 1.5 V VG Rise Time Switch VSYNC High, CG = 1.0 nF, VCC = 15 V, measure 2.0 V to 8.0 V − 30 75 ns VG Fall Time Switch VSYNC Low, CG = 1.0 nF, VCC = 15 V, measure 8.0 V to 2.0 V − 40 100 ns VG Resistance to GND Remove supplies, VG = 10 V − 50 100 kW VD Resistance to GND Remove supplies, VD = 10 V 500 1500 − W General ICC, Operating VSYNC = 5.0 V − 12 18 mA ICC in UVL VCC = 6.0 V − 300 500 mA ICC in Sleep Mode High VRAMP = 0 V, VCC = 45 V − 80 200 mA ICC in Sleep Mode Low VRAMP = 0 V, VCC = 10 V − 20 50 mA IC, Operating High VSYNC = 5.0 V, VFB = VIS− = 0 V, VC = 75 V − 4.0 8.0 mA IC, Operating Low VSYNC = 5.0 V, VFB = VIS− = 0 V, VC = 8.0 V − 3.0 6.0 mA UVLO Start Voltage − 7.4 8.0 9.2 V UVLO Stop Voltage − 6.4 7.0 8.3 V − UVLO Hysteresis 0.8 1.0 1.2 V Leading Edge, tDELAY VSYNC = 2.5 V to VG = 8.0 V − 280 − ns Trailing Edge, tDELAY VSYNC = 2.5 V to VG = 2.0 V − 750 − ns PACKAGE PIN DESCRIPTION PACKAGE LEAD # PDIP−14 SO−16WB LEAD SYMBOL 1 1 SYNC 2 2 VCC Logic supply (10 V to 45 V). 3 3 VREF 5.0 V voltage reference. 4 − LGND Logic level ground (analog and digital ground tied). 5 6 VFB 6 7 COMP Error amplifier output and compensation. 7 8 RAMP RAMP programmable with the external capacitor. 8 9 IS+ Current sense amplifier non−inverting input. 9 10 IS− Current sense amplifier inverting input. 10 11 IS COMP 11 12, 13 PGND 12 14 VG External power switch gate drive. 13 15 VC Output power stage supply voltage (8.0 V to 75 V). 14 16 VD External FET DRAIN voltage monitor. − 5 AGND Analog ground. − 4 DGND Digital ground. FUNCTION Synchronization input. Error amplifier inverting input. Current sense amplifier compensation and output. Power ground. http://onsemi.com 4 CS5101 ORDERING INFORMATION Device Shipping † Package CS5101EN14 PDIP−14 CS5101EN14G PDIP−14 (Pb−Free) CS5101EDW16 SOIC−16WB CS5101EDW16G SOIC−16WB (Pb−Free) CS5101EDWR16 SOIC−16WB CS5101EDWR16G SOIC−16WB (Pb−Free) 25 Units / Rail 47 Units / Rail 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. CIRCUIT DESCRIPTION VCC VD VCC VC REF VREF 5.0 V OK + SLEEP − + UVL + − + − 8.0 V/7.0 V LGND − + VG 0.7 V +− IS EA 10 k − BUF + 10 k VC Q I = 200 mA 5.0 V G1 S Q + IS+ 5.0 V R 0.7 V +− − VCC−OK + + REF_OK − 5.0 V + SYNC − IS− Q3 5.0 V Q4 − LATCH + 1.5 V − + RAMP − + − 1.65 V IS COMP 5.0 V − − + PWM + + 2.4 V − 5.0 V COMP SYNC PGND 5.0 V 24.6 k + 2.0 V − RAMP Q2 VCC 5.0 V VFB Q1 + − 4.5 V/4.4 V G2 + − 2.5 V Figure 2. Block Diagram http://onsemi.com 5 VCC CS5101 Theory of Operation The logic state of the LATCH can be changed only when both the voltage level of the trailing edge of the power pulse at the SYNC pin is less than the threshold voltage of the SYNC comparator (2.5 V) and the RAMP voltage is less than the threshold voltage of the RAMP comparator (1.65 V). On the negative going transition of the secondary side pulse VSY, gate G2 output goes high, resetting the latch at time t3. Capacitor CR is discharged through transistor Q4. CR’s output goes low disabling the output stage, and the external power switch (an N−FET) is turned off. The CS5101 is designed to regulate voltages in multiple output power supplies. Functionally, it is similar to a magnetic amplifier, operating as a switch with a delayed turn−on. It can be used with both single ended and dual ended topologies. The VFB voltage is monitored by the error amplifier EA. It is compared to an internal reference voltage and the amplified differential signal is fed through an inverting amplifier into the buffer, BUF. The buffered signal is compared at the PWM comparator with the ramp voltage generated by capacitor CR. When the ramp voltage VR, exceeds the control voltage VC, the output of the PWM comparator goes high, latching its state through the LATCH, the output stage transistor Q1 turns on, and the external power switch, usually an N−FET, turns on. RAMP Function The value of the ramp capacitor CR is based on the switching frequency of the regulator and the maximum duty cycle of the secondary pulse VSY. If the RAMP pin is pulled externally to 0.3 V or below, the SSPR is disabled. Current drawn by the IC is reduced to less than 100 mA, and the IC is in SLEEP mode. SYNC Function The SYNC circuit is activated at time t1 (Figure 3) when the voltage at the SYNC pin exceeds the threshold level (2.5V) of the SYNC comparator. The external ramp capacitor CR is allowed to charge through the internal current source I (200 mA). At time t2, the ramp voltage intersects with the control voltage VC and the output of the PWM comparator goes high, turning on the output stage and the external power switch. At the same time, the PWM comparator is latched by the RS latch, LATCH. 1 FAULT Function The voltage at the VCC pin is monitored by the undervoltage lockout comparator with hysteresis. When VCC falls below the UVL threshold, the 5.0 V reference and all the circuitry running off of it is disabled. Under this condition the supply current is reduced to less than 500 mA. The VCC supply voltage is further monitored by the VCC_OK comparator. When VCC is reduced below VREF − 0.7 V, a fault signal is sent to gate G1 . This fault signal, which determines if VCC is absent, works in conjunction with the ramp signal to disable the output, but only after the current cycle has finished and the RS latch is reset. Therefore this fault will not cause the output to turn off during the middle of an on pulse, but rather will utilize lossless turn−off. This feature protects the FET from overvoltage stress. This is accomplished through gate G1 by driving transistor Q4 on. An additional fault signal is derived from the REF_OK comparator. VREF is monitored so to disable the output through gate G1 when the VREF voltage falls below the OK threshold. As in the VCC_OK fault, the REF_OK fault disables the output after the current cycle has been completed. The fault logic will operate normally only when VREF voltage is within the specification limits of REF_OK. VSY VSY 0V VC 2 VRAMP VSY + VD 3 VDS 0V VSY 4 VD 0V VSY − VOUT 5 0V VL1 DRAIN Function VG The drain pin, VD monitors the voltage on the drain of the power switch and derives energy from it to keep the output stage in an off state when VC or VCC is below the minimum specified voltage. VOUT + VD VSY + VC 6 VS VD 0V Ground Level (Gate doesn’t go below GND) t1 t2 t3 t4 t1 Figure 3. Waveforms for CS5101. The Number to the Left of Each Curve Refers to a Node On the Application Diagram on Page 2. http://onsemi.com 6 CS5101 S1 C1 1.0 mF R6 10 k R1 100 k VSYNC VD VCC VC CS5101 VREF VG LGND PGND VFB IS COMP COMP IS− RAMP IS+ R3 5.0 k C4 0.1 mF 8.0 V − 45 V R2 100 k V1 100 kHz 0 V to 5.0 V Square Wave C2 0.1 mF SW SPST R7 10 k C5 680 pF C3 1.0 nF R4 2.2 k R5 10 k Figure 4. CS5101 Bench Test on DIP−14 Package http://onsemi.com 7 CS5101 PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F L N C −T− SEATING PLANE H G D 14 PL J K 0.13 (0.005) M M http://onsemi.com 8 DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 _ 0.38 1.01 CS5101 PACKAGE DIMENSIONS SOIC−16WB CASE 751G−03 ISSUE C A D 9 h X 45 _ E 0.25 H 8X M B M 16 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. q 1 MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ 8 16X M 14X e T A S B S A1 L A 0.25 B B SEATING PLANE C T PACKAGE THERMAL DATA Parameter PDIP−14 SOIC−16WB Unit RqJC Typical 23 48 °C/W RqJA Typical 105 85 °C/W ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 9 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CS5101/D