Anpec APL3523A Ultra-low on-resistance, 6a dual load switch with soft start Datasheet

APL3523A
Ultra-Low On-Resistance, 6A Dual Load Switch with Soft Start
Features
General Description
•
16mΩ(Typical) On-resistance per Channel
•
6A Continuous Current
The APL3523A is an ultra-low on-resistance, dual powerdistribution switch with external soft start control. It inte-
•
Soft Start Time Programmable by External
grates two N-channel MOSFETs that can deliver 6A continuous load current each.
Capacitor
The device integrates over-temperature protection. The
over temperature protection function shuts down the N-
•
Wide Input Voltage Range (VIN): 0.8V to 5.5V
•
Supply Voltage Range (VBIAS): 3V to 5.5V
•
Output Discharge when Switch Disabled
•
Reverse Current Blocking when Switch Disabled
•
•
Over-Temperature Protection
on the power switch when the temperature drops by 40oC.
The device is available in lead free TDFN2x3-14
Enable Input
packages.
•
Lead Free and Green Devices Available (RoHS
channel MOSFET power switch when the junction temperature rises beyond 160oC and will automatically turns
Compliant)
Applications
•
Notebook
•
AIO PC
Simplified Application Circuit
Pin Configurations
VBIAS
BIAS
APL3523A
VIN1
VIN1 1
14 VOUT1
VIN1 2
13 VOUT1
EN1 3
12 SS1
BIAS 4
11 GND
EN2 5
10 SS2
VIN2 6
VIN1
VOUT1
APL3523A
VIN2
VIN2
9 VOUT2
VIN2 7
VOUT2
8 VOUT2
TDFN2x3-14
(Top View)
VOUT1
On
Off
EN1
EN2
SS1
= Exposed Pad
VOUT2
SS2
GND
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2013
1
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APL3523A
Ordering and Marking Information
Package Code
QB : TDFN2x3-14
Operating Ambient Temperature Range
I : -40 to 85oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APL3523A
Assembly Material
Handling Code
TemperatureRange
Package Code
APL3523A QB:
3523A
XXXXX
XXXXX-Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant)and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
VBIAS
VIN1, VIN2
VOUT1, VOUT2
VEN1, VEN2
Parameter
Rating
Unit
BAIS to GND Voltage
-0.3 ~ 6
V
VIN1, VIN2 to GND Voltage
-0.3 ~ 6
V
VOUT1, VOUT2 to GND Voltage
-0.3 ~ 6
V
EN1, EN2 to GND Voltage
-0.3 ~ 6
V
Maximum Junction Temperature
-40 ~ 150
o
TSTG
Storage Temperature
-65 ~ 150
o
TSDR
Maximum Lead Soldering Temperature (10 Seconds)
260
o
TJ
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
θJA
Parameter
Typical Value
Junction-to-Ambient Resistance in Free Air (Note 2)
80
Unit
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TDFN2x3-14 is soldered directly on the PCB.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2013
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APL3523A
Recommended Operating Conditions
Symbol
VBIAS
(Note 3)
Parameter
BIAS Input Voltage
VIN1, VIN2 VIN1, VIN2 Input Voltage
IOUT
VOUT1 or VOUT2 Output Current (single channel)
o
(Note4)
Range
Unit
3.0 ~ 5.5
V
0.8 ~ 5.5
V
0~6
A
0.94
W
V
PD
Maximum Power Dissipation, TA=50 C
VIH
EN1, EN2 Logic High Input Voltage
1.2 ~ 5.5
VIL
EN1, EN2 Logic Low Input Voltage
0 ~ 0.4
TA
TJ
Ambient Temperature
Junction Temperature
V
-40 ~ 85
o
-40 ~ 125
o
C
C
Note 3 : Refer to the typical application circuit.
Note 4 : Refer to the thermal consideration on page 15.
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN1= VIN2= 0.8V~5.5V, VEN1= VEN2=VBIAS =5V and TA= -40~85oC.
Typical values are at TA=25oC.
Symbol
Parameter
APL3523A
Test Conditions
Unit
Min.
Typ.
Max.
SUPPLY CURRENT
IBIAS
ISD
IOFF
BIAS Supply Current (both
channels)
No load, VBIAS=5V =VEN1,2=5V
-
60
90
µA
BIAS Supply Current (single
channel)
No load, VBIAS=5V, VEN1=5V, VEN2=0V
-
50
-
µA
BIAS Supply Current at
Shutdown
No load, VBIAS=5V, VEN1,2=0V
-
-
2
µA
No load, VBIAS=5V, VEN1,2=0V, VIN1,2=5V
-
0.1
8
µA
No load, VBIAS=5V, VEN1,2=0V, VIN1,2=3.3V
-
0.1
3
µA
No load, VBIAS=5V, VEN1,2=0V, VIN1,2=1.8V
-
0.1
2
µA
No load, VBIAS=5V, VEN1,2=0V, VIN1,2=0.8V
-
0.1
1
µA
VEN1,2=0V, VIN1,2=0V
-
0.1
16
µA
1.9
2.4
2.9
V
-
0.1
-
V
-
16
18
mΩ
VIN Off-State Supply Current
(per channel)
Reverse Leakage Current (per
channel)
UNDER-VOLTAGE LOCKOUT (UVLO)
Rising BIAS UVLO Threshold
VBIAS rising
BIAS UVLO Hysteresis
POWER SWITCH
IOUT=200mA, TJ= 25oC
RDS(ON)
Power Switch On Resistance
Channel 1
o
IOUT=200mA, TJ= -40~125 C
-
-
24
mΩ
IOUT=200mA, TJ= 25oC
-
16
18
mΩ
IOUT=200mA, TJ= -40~125oC
VOUT Discharge Resistance
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2013
Channel 2
VEN1,2=0V, VOUT1 or VOUT2 force 1V
3
-
-
24
mΩ
-
150
180
Ω
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APL3523A
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN1= VIN2= 0.8V~5.5V, VEN1= VEN2=VBIAS =5V and TA= -40~85oC.
Typical values are at TA=25oC.
Symbol
Parameter
APL3523A
Test Conditions
Unit
Min.
Typ.
Max.
-
560
-
SOFT-START CONTROL PIN
VSS1,2=6V, VEN1,2=0V, EN2=low, measured at
SS1 or SS2
SS Discharge Current
µA
EN INPUT PIN
Input Logic High
1.2
-
-
V
Input Logic Low
-
-
0.4
V
Input Current
-
-
1
µA
-
160
-
°C
-
40
-
°C
OVERT-TEMPERATURE PROTECTION (OTP)
Over-Temperature Threshold
TJ rising
Over-Temperature Hysteresis
Timing Chart
50%
50%
tF
tR
VEN
tON
tOFF
90%
50%
90%
50%
VOUT
VOUT
10%
10%
tD
Figure 1. tON/tOFF, tR/tF Waveforms
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APL3523A
Typical Operating Characteristics
Quiescent Current vs. BIAS
Supply Voltage (Both Channels )
Quiescent Current vs. BIAS Supply
Voltage (Single Channel )
100
90
85
80
125
70
60
50
40
3
3.5
4
4.5
5
25
55
85
50
125
45
40
35
30
5.5
3
BIAS Supply Voltage, V BIAS (V)
4
4.5
5
5.5
Off-Stage Supply Current vs. VIN
Supply Voltage (SINGLE CHANNEL)
0.5
14
Off-Stage Supply Current, IOFF (µA)
-40
V BIAS = VIN
25
Quiescent Current, ISD (µA)
3.5
BIAS Supply Voltage, V BIAS (V)
Shutdown Current vs. BIAS
Supply Voltage (Both Channels)
0.4
85
125
0.3
0.2
0.1
0
-40
V BIAS = 5.5V
25
12
85
10
125
8
6
4
2
0
3.5
4
4.5
5
5.5
3
3.5
4
4.5
5
5.5
BIAS Supply Voltage, V BIAS (V)
VIN Supply Voltage, VIN (V)
Switch On Resistance vs. VIN
Supply Voltage
Switch On Resistance vs. VIN
Supply Voltage
32
24
-40
VBIAS = 3 V
30
0
25
28
50
26
75
24
100
22
125
20
18
16
14
Switch On Resistance, RDS(ON) (mΩ)
3
Switch On Resistance, RDS(ON) (mΩ)
-40
VBIAS = VIN
25
Quiescent Current, IBIAS (µA)
Quiescent Current, IBIAS (µA)
60
-40
VBIAS = V IN
-40
VBIAS = 5.5V
23
0
22
25
21
50
20
75
19
100
18
125
17
16
15
14
13
12
12
0 .5
1
1.5
2
2.5
0
3
VIN Supply Voltage, VIN (V)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2013
0 .5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VIN Supply Voltage, VIN (V)
5
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APL3523A
Typical Operating Characteristics
Switch On Resistance vs. VIN
Supply Voltage
Switch On Resistance vs. Output
Current
TJ =25°C
23
VBIAS=5 V
VBIAS=3 .3V
22
21
20
19
18
17
16
15
20
Switch On Resistance, RDS(ON) (mΩ)
Switch On Resistance, RDS(ON) (mΩ)
24
14
VBIAS = 5V, VIN = 5V , TJ = 25°C
19
18
17
16
15
14
0.5
1.5
2.5
3.5
4.5
5 .5
0
1
2
VIN Supply Voltage, VIN (V)
500
-40
25
400
85
350
125
-40
VBIAS = 5.5V, CSS = 1nF,
ROUT = 10Ω, C OUT = 0.1µF
450
300
250
200
150
100
25
400
85
350
125
300
250
200
150
100
50
50
0 .8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2 .6 2.8 3.0
0.5
1 .5
2.5
3.5
4.5
5.5
VIN Supply Voltage, VIN (V)
VIN Supply Voltage, VIN (V)
Falling Time vs . VIN Supply Voltage
Falling Time vs. VIN Supply Voltage
5
VBIAS = 3V, RL = 10 Ω
C SS = 1nF, C OUT = 0.1µF
4
5
-40
-40
VBIAS = 5.5V, Css = 1nF,
R OUT = 10 Ω, C OUT = 0.1 µF
25
85
Falling Time, tF (µs)
Falling Time, tF (µs)
6
5
Turn On Delay Time vs . VIN Supply
Voltage
Turn On Delay Time, tD (µs)
Turn On Delay Time, tD (µs)
450
VBIAS = 3V, RL = 10 Ω
C SS = 1nF, C OUT = 0.1µF
4
Output Current, IOUT (A)
Turn On Delay Time vs. VIN
Supply Voltage
500
3
125
3
2
25
85
4
125
3
2
1
1
0
0.5
0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
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1.5
2
2 .5
3
3.5
4
4.5
5
5.5
VIN Supply Voltage, VIN (V)
VIN Supply Voltage, VIN (V)
6
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APL3523A
Typical Operating Characteristics
Turn Off Time vs . VIN Supply
Voltage
Turn Off Time vs. VIN Supply
Voltage
5
25
4
85
125
3
2
1
25
4
85
125
3
2
1
0
0
0.8 1.0 1.2 1.4 1 .6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
0.8 1 .0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VIN Supply Voltage, VIN (V)
VIN Supply Voltage, VIN (V)
Turn On Time vs. VIN Supply
Voltage
Turn On Time vs. VIN Supply
Voltage
1200
2000
-40
VBIAS = 3V, R L = 10Ω
CSS = 1nF, C OUT = 0.1µF
Turn On Time, tON (µs)
85
125
800
600
400
200
-40
VBIAS = 5.5V, RL = 10 Ω
CSS = 1nF, C OUT = 0.1 µF
1800
25
1000
Turn On Time, tON (µs)
-40
VBIAS = 5.5V, R L = 10Ω
C SS = 1nF, C OUT = 0.1µF
Turn Off Time, tOFF (µs)
Turn Off Time, tOFF (µs)
5
-40
VBIAS = 3V, R L = 10 Ω
C SS = 1 nF, COUT = 0.1µF
25
1600
85
1400
125
1200
1000
800
600
400
200
0
0
0.5
1.0
1 .5
2.0
2.5
3.0
0.5 1 .0 1.5 2.0
VIN Supply Voltage, VIN (V)
Rising Time vs. VIN Supply Voltage
V BIAS = 5.5V, R L = 10 Ω
C SS = 1nF, C OUT = 0.1µF
-40
VBIAS = 3V, R L = 10Ω
C SS = 1 nF, COUT = 0.1µF
25
85
1000
- 40
25
2500
Rising Time, tR (µs)
Rising Time, tR (µs)
5.5
Rising Time vs. VIN Supply Voltage
3000
1400
1200
2.5 3.0 3 .5 4.0 4.5 5.0
VIN Supply Voltage, VIN (V)
125
800
600
400
85
2000
125
1500
1000
500
200
0
0
0.5
1.0
1.5
2.0
2.5
0.5
3 .0
Copyright  ANPEC Electronics Corp.
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1.0 1 .5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN Supply Voltage, VIN (V)
VIN Supply Voltage, VIN (V)
7
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APL3523A
Typical Operating Characteristics
Rising Time vs. BIAS Supply
Voltage
1600
- 40
Rising Time, tR (µs)
1400
25
85
1200
125
1000
800
600
VIN = 3V, R L = 10 Ω
C SS = 1 nF, COUT = 0.1µF
400
200
3
3.5
4
4.5
5
5.5
BIAS Supply Voltage, V BIAS (V)
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APL3523A
Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.
Shutdown
Enable
V EN
VEN
1
1
2
V OUT
VOUT
2
I OUT
3
3
IOUT
VBIAS=3V, VIN=0.8V
COUT =0.1µF, CSS =1nF, RL=10Ω
CH1: V EN, 2V/Div, DC
CH2: VOUT, 200mV/Div, DC
CH3: IOUT, 50mA/Div, DC
TIME: 1µs/Div
VBIAS=3V, VIN=0.8V
COUT =0.1µF, CSS=1nF, RL=10Ω
CH1: VEN, 2V/Div, DC
CH2: VOUT , 200mV/Div, DC
CH3: IOUT , 50mA/Div, DC
TIME: 200µs/Div
Shutdown
Enable
VEN
VEN
1
1
VOUT
VOUT
2
2
IOUT
I OUT
3
3
VBIAS=3V, VIN=0.8V
COUT=0.1µF, CSS=1nF, RL=10Ω
CH1: VEN, 2V/Div, DC
CH2: VOUT , 200mV/Div, DC
CH3: IOUT , 50mA/Div, DC
TIME: 1µs/Div
VBIAS=3V, VIN=0.8V
COUT =0.1µF, CSS=1nF, RL=10Ω
CH1: V EN, 2V/Div, DC
CH2: V OUT, 200mV/Div, DC
CH3: IOUT , 50mA/Div, DC
TIME: 200µs/Div
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APL3523A
Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.
Shutdown
Enable
VEN
VEN
1
1
VOUT
V OUT
2
2
IOUT
IOUT
3
3
VBIAS=5V, VIN=5V
COUT =0.1µF, CSS=1nF, RL=10Ω
CH1: VEN, 2V/Div, DC
CH2: VOUT , 1V/Div, DC
CH3: IOUT, 200mA/Div, DC
VBIAS=5V, VIN=5V
COUT =0.1µF, CSS=1nF, RL=10Ω
CH1: VEN, 2V/Div, DC
CH2: VOUT , 1V/Div, DC
CH3: IOUT, 200mA/Div, DC
TIME: 500µs/Div
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APL3523A
Pin Description
PIN
FUNCTION
NO.
NAME
1
VIN1
2
VIN1
3
EN1
Enable input of switch 1. Logic high turns on switch 1. The EN1 pin cannot be left floating.
4
BIAS
Bias voltage input pin for internal control circuitry.
5
EN2
Enable input of switch 2. Logic high turns on switch 2. The EN2 pin cannot be left floating.
6
VIN2
7
VIN2
8
VOUT2
9
VOUT2
10
SS2
Soft start control of switch 2. A capacitor from this pin to ground sets the VOUT2’s rise slew
rate.
11
GND
Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
12
SS1
Soft start control of switch 1. A capacitor from this pin to ground sets the VOUT1’s rise slew
rate.
13
VOUT1
14
VOUT1
Exposed Pad
-
Power supply Input of switch 1. Connect this pin to an external DC supply.
Power supply Input of switch 2. Connect this pin to an external DC supply.
Switch 2 output.
Switch 1 output.
Connect the exposed pad to the system ground plan.
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APL3523A
Block Diagram
Bulk
Select
VOUT1
VIN1
BIAS
UVLO
Charge
Pump
SS1
Control
Logic
EN1
OTP1
OTP2
EN2
Bulk
Select
VOUT2
VIN2
Charge
Pump
SS2
GND
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APL3523A
Typical Application Circuit
VBIAS
4
BIAS
C BIAS
0.1µF
V IN1
1, 2
VOUT1 13 , 14
VIN1
C IN1
1µF
C OUT 1
0.1µF
C L1
150µF
RLOAD 1
CL 2
150 µF
R LOAD2
APL3523A
VIN2
6, 7
VIN2
CIN2
1µF
VOUT2
3
On
5
Off
C OUT2
0.1µF
EN1
EN2
SS1
SS2
12
GND
11
10
C SS1
CSS(pF)
8 ,9
C SS2
Soft-Start Time (µs) 10% to 90%, VBIAS=5V, CL=0.1µF, CIN=1µF, RL=10Ω, Typical values are at TA=25°C
VIN=5V
VIN=3.3V
VIN=1.8V
VIN=1.5V
VIN=1.2V
VIN=1.05V
VIN=0.8V
0
112
73
53
49
45
42
38
220
492
322
197
170
146
132
128
330
685
450
270
230
198
180
145
470
911
598
355
307
263
233
188
1000
2030
1280
749
635
538
470
388
2200
4360
2740
1574
1336
1118
1014
797
4700
8780
5540
3218
2696
2289
2037
1624
10000
19060
12011
6862
5700
4806
4301
3410
Note: The table Contains soft-start time values measured on a typical device. The soft-start times shown are only valid for the powerup sequence where VIN and VBIAS are already in steady state condition, and EN pin is asserted high.
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APL3523A
Function Description
VIN Under-voltage Lockout (UVLO)
A under-voltage lockout (UVLO) circuit monitors the VBIAS
pins voltage to prevent wrong logic controls. The UVLO
function initiates a soft-start process after the BIAS supply voltages exceed rising UVLO voltage threshold during powering on.
Power Switch
The power switch is an N-channel MOSFET with a ultralow RDS(ON). When IC is in shutdown state (VEN1,2=0V), the
MOSFET prevents a reverse current flowing from the VOUT
back to VIN. When IC is in UVLO state, the internal parasitic diodes connected from VOUT to VIN will be forward
biased.
Soft-start
The APL3523A Provides an adjustable soft-start circuitry
to control rise rate of the output voltage and limit the current surge during start-up. The soft-start time is set with a
capacitor from the SS pin to the ground.
Enable Control
The APL3523A has a dedicated enable pin (EN). A logic
low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the
output through initiation of a new soft-start cycle.
Over-Temperature Protection (OTP)
When the junction temperature exceeds 160oC, the internal thermal sense circuit turns off the power FET and
allows the device to cool down. When the device’s junction temperature cools by 40 oC, the internal thermal
sense circuit will enable the device, resulting in a pulsed
output during continuous thermal protection. Thermal
protection is designed to protect the IC in the event of
over temperature conditions. For normal operation, the
junction temperature cannot exceed TJ=+125oC.
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APL3523A
Application Information
Power Sequencing
Soft-Start Capacitor
VBIAS
VIN1, VIN2
The soft-start capacitor on SS pin can reduce the inrush
current and overshoot of output voltage. The capacitor is
VEN1, VEN2
charge to VSS with a constant current source. This results
in a linear charge of the soft-start capacitor and thus the
output voltage.
VOUT1, VOUT2
Thermal Consideration
The APL3523A maximum power dissipation depends on
the differences of the thermal resistance and tempera-
VEN1, VEN2
ture between junction and ambient air. The power dissipation PD across the device is:
VOUT1, VOUT2
PD = (TJ - TA) / θJA
VIN1, VIN2
where (TJ-TA) is the temperature difference between the
junction and ambient air. θJA is the thermal resistance
VBIAS
between junction and ambient air. Assuming the TA=25°C
and maximum TJ=160°C (typical thermal limit threshold),
Figure 2. APL3523A Power Sequencing Diagram
The APL3523A has a built-in reverse current blocking circuit to prevent a reverse current flowing through the body
the maximum power dissipation is calculated as:
PD(max)=(160-25)/80
diode of power switch from the VOUT back VIN pin when
power switch disabled. The reverse current blocking cir-
= 1.68(W)
cuit is not active before VBIAS is ready. When IC is in UVLO
state, the internal parasitic diodes of power switch con-
For normal operation, do not exceed the maximum operating junction temperature of TJ = 125°C. The calculated
nected from VOUT to VIN will be forward biased.
Otherwise, VOUT should not be higher than VBIAS, and
power dissipation should be less than:
PD =(125-25)/80
VBIAS must be higher than the voltage of any other input
pin, the reason is that the internal parasitic diodes con-
= 1.25(W)....................................................TA=25oC
PD =(125-85)/80
nected from VOUT to VBIAS will be forward biased.
= 0.5(W)......................................................TA=85oC
The power dissipation depends on operating ambient
temperature for fixed TJ=125oC and thermal resistance
Capacitor Selection
The APL3523A requires proper input capacitors to supply
current surge during stepping load transients to prevent
the input voltage rail from dropping. Because the para-
θJA. For APL3523A packages, the Figure 3 of derating
curves allows the designer to see the effect of rising
sitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge
For normal applications (except OTP or output short circuit has occurred), the recommended input capacitance
of VIN is 1µF and output capacitance of VOUT is 0.1µF at
least. Please place the capacitors near the APL3523A as
1.3
Power Dissipation (W)
currents, more parasitic inductance needs more input
capacitance.
ambient temperature on the maximum power allowed.
close as possible.
A bulk output capacitor, placed close to the load, is rec-
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
-40 -30 -20 -10
ommended to support load transient current.
0
10
20
30
40
50
60
70
80
90
Ambient Temperature (oC)
Figure 3. Derating Curves for APL3523A Package
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2013
15
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APL3523A
Application Information
Layout Consideration
The PCB layout should be carefully performed to maximize thermal dissipation and to minimize voltage drop,
droop and EMI. The following guidelines must be
considered:
1. Please place the input capacitors near the VIN pin as
close as possible.
2. Output decoupling capacitors for load must be placed
near the load as close as possible for decoupling high
frequency ripples.
3. Locate APL3523A and output capacitors near the load
to reduce parasitic resistance and inductance for excellent load transient performance.
4. The negative pins of the input and output capacitors
and the GND pin must be connected to the ground plane
of the load.
5. Keep VIN and VOUT traces as wide and short as
possible.
Recommended Minimum Footprint
The Via Diameter = 0.305, (0.012)
Hole Size = 0.203, (0.008)
1.3
(0.051)
0.48
(0.0192)
0.4
(0.016)
2.5
(0.098)
0.25
(0.01)
0.2
(0.008)
0.9
(0.035)
Unit: mm, (Inch)
TDFN2x3-14
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2013
16
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APL3523A
Package Information
TDFN2x3-14
D
A
E
b
Pin 1
A1
D2
A3
NX
aaa c
E2
e
Pin 1 Cornar
SEATING PLANE
K L
S
Y
M
B
O
L
TDFN2x3-14
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.11 REF
0.004 REF
b
0.15
0.25
0.006
0.010
D
1.90
2.10
0.075
0.083
D2
0.80
1.00
0.031
0.039
E
2.90
3.10
0.114
0.122
E2
2.40
2.60
0.094
0.102
e
0.40 BSC
L
0.30
K
0.20
aaa
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2013
0.016 BSC
0.012
0.40
0.016
0.008
0.08
0.003
17
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APL3523A
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TDFN2x3-14
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.20
1.75±0.10
3.50±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.25±0.05
2.30±0.20
3.30±0.20
1.00±0.20
4.0±0.10
4.0±0.10
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TDFN2x3-14
Tape & Reel
3000
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2013
18
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APL3523A
Taping Direction Information
TDFN2x3-14
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2013
19
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APL3523A
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2013
20
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APL3523A
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2013
21
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