Mitel MT9126AS Cmos quad adpcm transcoder Datasheet

CMOS MT9126
Quad ADPCM Transcoder
Preliminary Information

Features
ISSUE 2
•
Full duplex transcoder with four encode
channels and four decode channels
•
32 kb/s, 24 kb/s and 16 kb/s ADPCM coding
complying with ITU-T (previously CCITT) G.726
(without 40 kb/s), and ANSI T1.303-1989
•
Low power operation, 25 mW typical
•
Asynchronous 4.096 MHz master clock
operation
•
SSI and ST-BUS interface options
•
Transparent PCM bypass
Transparent ADPCM bypass
•
Linear PCM code
•
No microprocessor control required
•
Simple interface to Codec devices
•
Pin selectable µ−Law or A-Law operation
•
Pin selectable ITU-T or signed magnitude PCM
coding
•
Single 5 volt power supply
•
Pair gain
•
Voice mail systems
•
Wireless telephony systems
ADPCMi
ADPCM
I/O
ADPCMo
Ordering Information
MT9126AE
28 Pin Plastic DIP
MT9126AS
28 Pin SOIC
-40 °C to +85 °C
Description
•
Applications
May 1995
The Quad ADPCM Transcoder is a low power,
CMOS device capable of four encode and four
decode functions per frame. Four 64 kbit/s PCM
octets are compressed into four 32, 24 or 16 kbit/s
ADPCM words, and four 32, 24 or 16 kbit/s ADPCM
words are expanded into four 64 kbit/s PCM octets.
The 32, 24 and 16 kbit/s ADPCM transcoding
algorithms
utilized
conform
to
ITU-T
Recommendation G.726 (excluding 40 kbit/s), and
ANSI T1.303 - 1989.
Switching, on-the-fly, between 32 kbit/s and 24 kbit/s
ADPCM, is possible by controlling the appropriate
mode select (MS1 - MS6) control pins. All optional
functions of the device are pin selectable allowing a
simple interface to industry standard codecs, digital
phone devices and Layer 1 transceivers. Linear
coded PCM is provided to facilitate external DSP
functions .
Full Duplex
Quad
Transcoder
PCM
I/O
PCMo1
PCMi1
PCMo2
PCMi2
ENB1
ENB2/F0od
BCLK
F0i
MCLK
C2o
Timing
Control Decode
EN1
EN2
VDD VSS PWRDN IC
MS1 MS2 MS3 A/µ FORMAT MS4 MS5 MS6 LINEAR SEL
Figure 1 - Functional Block Diagram
8-33
MT9126
Preliminary Information
EN1
MCLK
F0i
C2o
BCLK
PCMo1
PCMi1
VSS
LINEAR
ENB2/F0od
ENB1
PCMo2
PCMi2
SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
EN2
MS6
MS5
MS4
ADPCMo
ADPCMi
VDD
MS3
MS2
MS1
IC
PWRDN
FORMAT
A/µ
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
EN1
Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1
PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1.
In SSI mode this output is high impedance.
2
MCLK
Master Clock (input). This is a 4.096 MHz (minimum) input clock utilized by the
transcoder function; it must be supplied in both ST-BUS and SSI modes of operation.
In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is
also used to control the data I/O flow on the PCM and ADPCM input/output pins
according to ST-BUS requirements.
In SSI mode this master clock input is derived from an external source and may be
asynchronous with respect to the 8 kHz frame. MCLK rates greater than 4.096 MHz are
acceptable in this mode since the data I/O rate is governed by BCLK.
3
F0i
Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI
operation is enabled by connecting this pin to VSS.
4
C2o
2.048 MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input
divided by two, inverted, and synchronized to F0i. This output is high-impedance during
SSI operation.
5
BCLK
Bit Clock (Input). 128 kHz to 4096 kHz bit clock input for both PCM and ADPCM ports;
used in SSI mode only. The falling edge of this clock latches data into ADPCMi, PCMi1
and PCMi2. The rising edge clocks data out on ADPCMo, PCMo1 and PCMo2. This input
must be tied to VSS for ST-BUS operation.
6
PCMo1
Serial PCM Stream 1 (Output). 128 kbit/s to 4096 kbit/s serial companded/linear PCM
output stream. Data are clocked out by rising edge of BCLK in SSI mode. Clocked out by
MCLK divided by two in ST-BUS mode. See Figure 14.
7
PCMi1
Serial PCM Stream 1 (Input). 128 kbit/s to 4096 kbit/s serial companded/linear PCM
input stream. Data are clocked in on falling edge of BCLK in SSI mode. Clocked in at the
3/4 bit position of MCLK in ST-BUS mode. See Figure 14.
8
VSS
9
LINEAR
8-34
Digital Ground. Nominally 0 volts.
Linear PCM Select (Input). When tied to VDD the PCM I/O ports (PCM1,PCM2) are 16bit linear PCM. Linear PCM operates only at a bit rate of 2048 kbit/s. Companded PCM is
selected when this pin is tied to VSS. See Figures 5 & 8.
MT9126
Preliminary Information
Pin Description
Pin #
Name
10
ENB2/F0od
Description
PCM B-Channel Enable Strobe 2 (Input) / Delayed Frame Pulse (Output).
SSI operation: ENB2 (Input). An 8-bit wide enable strobe input defining B2 channel
(AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. See
Figures 4 & 6.
ST-BUS operation: F0od (Output). This pin is a delayed frame strobe output. When LINEAR=0, this becomes a delayed frame pulse output occurring 64 C4 clock cycles after
F0i and when LINEAR = 1 at 128 C4 clock cycles after F0i . See Figures 7, 8, 9 & 14.
11
ENB1
PCM B-Channel Enable Strobe 1 (Input).
SSI operation: An 8-bit wide enable strobe input defining B1 channel (AD)PCM data. A
valid 8-bit strobe must be present at this input for SSI operation.
ST-BUS operation: When tied to VSS transparent bypass of the ST-BUS D- and C- channels is enabled. When tied to VDD the ST-BUS D-channel and C-channel output timeslots
are forced to a high-impedance state.
12
PCMo2
Serial PCM Stream 2 (Output). 128 kbit/s to 4096 kbit/s serial companded/linear PCM
output stream. Clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK
divided by two in ST-BUS mode. See Figure 14.
13
PCMi2
Serial PCM Stream 2 (Input). 128 kbit/s to 4096 kbit/s serial companded/linear PCM input
stream. Data bits are clocked in on falling edge of BCLK in SSI mode. Clocked in at the
3/4 bit position of MCLK in ST-BUS mode. See Figure 14.
14
SEL
SELECT (Input).
PCM bypass mode: When SEL=0 the PCM1 port is selected for PCM bypass operation
and when SEL=1 the PCM2 port is selected for PCM bypass operation.
See Figures 6 & 9.
16 kbit/s transcoding mode:
SSI Operation - in 16 kbit/s transcoding mode, the ADPCM words are assigned to the I/O
timeslot defined by ENB2 when SEL=1 and by ENB1 when SEL=0. See Figure 4.
ST-BUS operation- in 16 kbit/s transcoding mode, the ADPCM words are assigned to the
B2 timeslot when SEL=1 and to the B1 timeslot when SEL=0. See Figure 9.
A-Law/µ−Law Select (Input). This input pin selects µ−Law companding when set to
logic 0, and A-Law companding when set to logic 1. This control is for all channels .This
input is ignored in Linear mode during which it may be tied to VSS or VDD.
15
A/µ
16
FORMAT
FORMAT Select (Input). Selects ITU-T PCM coding when high and Sign-Magnitude
PCM coding when low. This control is for all channels.This input is ignored in Linear
mode during which it may be tied to VSS or VDD.
17
PWRDN
Power-down (Input). An active low reset forcing the device into a low power mode
where all outputs are high-impedance and device operation is halted.
18
IC
Internal Connection (Input). Tie to VSS for normal operation.
8-35
MT9126
Preliminary Information
Pin Description
Pin #
Name
19
20
21
MS1
MS2
MS3
Description
Mode Selects 1, 2 and
MS3 MS2 MS1
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
3 (Inputs). Mode selects for all four encoders.
MODE
32 kbit/s ADPCM
24 kbit/s ADPCM
16 kbit/s ADPCM in EN1/ENB1 when SEL=0
in EN2/ENB2 when SEL=1
ADPCM Bypass for 32 kbit/s and 24 kbit/s
ADPCM Bypass for 16 kbit/s
PCM Bypass (64 kbit/s) to PCM1 if SEL=0, PCM2 if SEL=1
Algorithm reset (ITU-T optional reset)
ADPCMo disable
Positive Power Supply. Nominally 5 volts +/-10%
22
VDD
23
ADPCMi
Serial ADPCM Stream ( Input). 128 kbit/s to 4096 kbit/s serial ADPCM word input
stream. Data bits are clocked in on falling edge of BCLK in SSI mode and clocked in on
the 3/4 bit edge of MCLK in ST-BUS mode.
24
ADPCMo
Serial ADPCM Stream (Output). 128 kbit/s to 4096 kbit/s serial ADPCM word output
stream. Data bits are clocked out by rising edge of BCLK in SSI mode and clocked out by
MCLK divided by two in ST-BUS mode.
25
26
27
MS4
MS5
MS6
Mode Selects 4, 5 and
MS6 MS5 MS4
0
0
0
0
0
1
0
1
0
0
1
1
1
1
28
EN2
1
0
0
1
1
1
0
1
0
1
6 (Inputs). Mode selects for all four decoders.
MODE
32 kbit/s ADPCM
24 kbit/s ADPCM
16 kbit/s ADPCM in EN1/ENB1 when SEL=0
in EN2/ENB2 when SEL=1
ADPCM Bypass for 32 kbit/s and 24 kbit/s
ADPCM Bypass for 16 kbit/s
PCM Bypass (64 kbit/s) to PCM1 if SEL=0, PCM2 if SEL=1
Algorithm reset (ITU-T optional reset)
PCMo1/2 disable
Enable Strobe 2 (Output). This 8 bit wide, active high strobe is active during the B2
PCM channel in ST-BUS mode. Forced to high impedance when LINEAR=1.
Notes:
All unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used.
All inputs have TTL compatible logic levels except for MCLK which has CMOS compatible logic levels and PWRDN which has Schmitt
trigger compatible logic levels.
All outputs are CMOS with CMOS logic levels (See DC Electrical Characteristics).
8-36
MT9126
Preliminary Information
Functional Description
Serial (AD)PCM Data I/O
The Quad-channel ADPCM Transcoder is a low
power, CMOS device capable of four encode and
four decode operations per frame. Four 64 kbit/s
channels (PCM octets) are compressed into four 32,
24 or 16 kbit/s ADPCM channels (ADPCM words),
and four 32, 24 or 16 kbit/s ADPCM channels
(ADPCM words) are expanded into four 64 kbit/s
PCM channels (PCM octets). The ADPCM
transcoding algorithm utilized conforms to ITU-T
recommendation G.726 (excluding 40 kb/s), and
ANSI T1.303 - 1989. Switching on-the-fly between
32 and 24 kbit/s transcoding is possible by toggling
the appropriate mode select pins (supports T1
robbed-bit signalling).
Serial data transfer to/from the Quad ADPCM
transcoder is provided through one ADPCM and two
PCM ports (ADPCMi, ADPCMo, PCMi1, PCMo1,
PCMi2, PCMo2). Data is transferred through these
ports according to either ST-BUS or SSI
requirements. The device determines the mode of
operation by monitoring the signal applied to the F0i
pin. When a valid ST-BUS frame pulse (244nSec low
going pulse) is applied to the F0i pin the transcoder
will assume ST-BUS operation. If F0i is tied
continuously to V SS the transcoder will assume SSI
operation. Pin functionality in each of these modes is
described in the following sub-sections.
ST-BUS Mode
All functions supported by the device are pin
selectable. The four encode functions comprise a
common group controlled via Mode Select pins MS1,
MS2 and MS3. Similarily, the four decode functions
form a second group commonly controlled via Mode
Select pins MS4, MS5 and MS6. All other pin
controls are common to the entire transcoder.
The device requires 25 mWatts (MCLK= 4.096 MHz)
typically for four channel transcode operation. A
minimum master clock frequency of 4.096 MHz is
required for the circuit to complete four encode
channels and four decode channels per frame. For
SSI operation a master clock frequency greater than
4.096 MHz and asynchronous, relative to the 8 kHz
frame, is allowed.
The PCM and ADPCM serial busses support both
ST-BUS and Synchronous Serial Interface (SSI)
operation. This allows serial data clock rates from
128 kHz to 4096 kHz, as well as compatibility with
Mitel’s standard Serial Telecom BUS (ST-BUS). For
ST-BUS operation, on chip channel counters provide
channel enable outputs as well as a 2048 kHz bit
clock output which may be used by down-stream
devices utilizing the SSI bus interface.
Linear coded PCM is also supported. In this mode
the encoders compress, four 14-bit, two’s
complement
(S,S,S,12,...,1,0),
uniform
PCM
channels into four 4, 3 or 2 bit ADPCM channels.
Similarly, the decoder expands four 4, 3 or 2 bit
ADPCM channels into four 16-bit, two’s complement
(S,14,...,1,0), uniform PCM channels. The data rate
for both ST-BUS and SSI operation in this mode is
2048 kbit/s.
During ST-BUS operation the C2o, EN1, EN2 and
F0od outputs become active and all serial timing is
derived from the MCLK (C4) and F0i inputs while the
BCLK input is tied to V SS. (See Figures 7, 8 & 9.)
Basic Rate “D” and “C” Channels
In ST-BUS mode, when ENB1 is brought low,
transparent transport of the ST-BUS "Basic Rate Dand C-channels" is supported through the PCMi1
and PCMo1 pins. This allows a microprocessor
controlled device, connected to the PCMi/o1 pins, to
access the "D" and "C" channels of a transmission
device connected to the ADPCMi/o pins. When
ENB1 is brought high, the “D” and “C” channel
outputs are tristated. Basic Rate “D” and “C”
channels are not supported in LINEAR mode.(See
Figure 7.)
SSI Mode
During SSI operation the BCLK, ENB1 and ENB2/
F0od inputs become active. The C2o, EN1, and EN2
outputs are forced to a high-impedance state except
during LINEAR operation during which the EN1
output remains active. (See Figures 4, 5 & 6.)
The SSI port is a serial data interface, including data
input and data output pins, a variable rate bit clock
input and two input strobes providing enables for
data transfers. There are three SSI I/O ports on the
Quad ADPCM; the PCMi/o1 PCM port, the PCMi/o2
PCM port, and the ADPCMi/o port. The two PCM
ports may transport 8-bit companded PCM or 16-bit
linear PCM. The alignment of the channels is
determined by the two input strobe signals ENB1
and ENB2/F0od. The bit clock (BCLK) and input
strobes (ENB1 and ENB2/F0od) are common for all
8-37
MT9126
three of the serial I/O ports. BCLK can be any
frequency between 128 kHz and 4096 kHz
synchronized to the input strobes. BCLK may be
discontinuous outside of the strobe boundaries
except when LINEAR=1. In LINEAR mode, BCLK
must be 2048 kHz and continuous for 64 cycles after
the ENB1 rising edge and for the duration of ENB2/
F0od.
Mode Select Operation (MS1, MS2, MS3,
MS4, MS5, MS6)
Mode Select pins MS1, MS2 and MS3 program
different bit rate ADPCM coding, bypass, algorithmic
reset and disable modes for all four encoder
functions simultaneously. When 24 kbit/s ADPCM
mode is selected bit 4 is unused while in 16 kb/s
ADPCM mode all ADPCM channels are packed
contiguously into one 8-bit octet. Mode Select pins
MS4, MS5 and MS6 operate in the same manner for
the four decode functions. The mode selects must be
set up according to the timing constraints illustrated
in Figures 16 and 17.
32 kbit/s ADPCM Mode
In 32 kbit/s ADPCM mode, the 8-bit PCM octets of
the B1, B2, B3 and B4 channels (PCMi1 and PCMi2)
are compressed into four 4-bit ADPCM words on
ADPCMo. Conversely, the 4-bit ADPCM words of the
B1, B2, B3 and B4 channels from ADPCMi are
expanded into four 8-bit PCM octets on PCMo1 and
PCMo2. The 8-bit PCM octets (A-Law or µ-Law) are
transferred most significant bit first starting with b7
and ending with b0. ADPCM words are transferred
most significant bit first starting with I1 and ending
with I4 (See Figures 4 & 7). Reference ITU-T G.726
for I-bit definitions.
24 kbit/s ADPCM Mode
In 24 kbit/s mode PCM octets are transcoded into 3bit words rather than the 4-bit words utilized in 32
kbit/s ADPCM. This is useful in situations where
lower bandwidth transmission is required. Dynamic
operation of the mode select control pins will allow
switching from 32 kbit/s mode to 24 kbit/s mode on a
frame by frame basis. The 8 bit PCM octets (A-Law
or µ-Law) are transferred most significant bit first
starting with b7 and ending with b0. ADPCM words
are transferred most significant bit first starting with
I1 and ending with I3 (I4 becomes don’t care). (See
Figures 4 & 7.)
8-38
Preliminary Information
16 kbit/s ADPCM Mode
When SEL is set to 0, the 8-bit PCM octets of the B1,
B2, B3 and B4 channels (PCMi1 and PCMi2) are
compressed into four 2-bit ADPCM words on
ADPCMo during the ENB1 timeslot in SSI mode and
during the B1 timeslot in ST-BUS mode. Similarily,
the four 2-bit ADPCM words on ADPCMi are
expanded into four 8-bit PCM octets (on PCMo1 and
PCMo2) during the ENB1/B1 timeslot. (See Figures 4
& 7.)
When SEL is set to 1, The same conversion takes
place as described when SEL = 0 except that the
ENB2/B2 timeslots are utilized.
A-Law or µ-Law 8-bit PCM are received and
transmitted most significant bit first starting with b7
and ending with b0. ADPCM data are most
significant bit first starting with I1 and ending with I2.
ADPCM BYPASS (32 and 24 kbit/s)
In ADPCM bypass mode the B1 and B2 channel
ADPCM words are bypassed (with a two-frame
delay) to/from the ADPCM port and placed into the
most significant nibbles of the PCM1/2 port octets.
Note that the SEL pin performs no function for these
two modes (See Figures 6 & 9). LINEAR, FORMAT
and A/µ pins are ignored in bypass mode.
In 32 kb/s ADPCM bypass mode, Bits 1 to 4 of the
B1, B2, B3 and B4 channels from PCMi1 and PCMi2
are transparently passed, with a two frame delay, to
the same channels on ADPCMo. In the same
manner, the B1, B2, B3 and B4 channels from
ADPCMi are transparently passed, with a two frame
delay, to the same channels on PCMo1 and PCMo2
pins. Bits 5 to 8 are don’t care. This feature allows
two voice terminals, which utilize ADPCM
transcoding, to communicate through a system
without
incurring
unnecessary
transcode
conversions. This arrangement allows byte-wide or
nibble-wide transport through a switching matrix.
24 kb/s ADPCM bypass mode is the same as 32 kb/s
mode bypass excepting that only bits 1 to 3 are
bypassed and bits 4 to 8 are don’t care.
ADPCM BYPASS (16 kbit/s)
When SEL is set to 0, only bits 1 and 2 of the B1, B2,
B3 and B4 PCM octets (on PCMi1 and PCMi2) are
bypassed, with a two frame delay, to the same
channels on ADPCMo during the ENB1 timeslot in
SSI mode and during the B1 timeslot in ST-BUS
MT9126
Preliminary Information
mode. Similarily, the four 2-bit ADPCM words on
ADPCMi are transparently bypassed, with a two
frame delay, to PCMo1 and PCMo2 during the ENB1
or B1 timeslot. Bits 3-8 are don’t care. (See Figures 6
& 9.)
When SEL is set to 1, the same bypass occurs as
described when SEL = 0 except that the ENB2 or B2
timeslots are utilized.
LINEAR, FORMAT and A/µ pins are ignored in
bypass mode.
PCM BYPASS
When SEL is set to 0, the B1 and B2 PCM channels
on PCMi1 are transparently passed, with a twoframe delay, to the same channels on the ADPCMo.
Simiarily, the two 8-bit words which are on ADPCMi
are transparently passed, with a two-frame delay, to
channels B1 and B2 of PCMo1 while PCMo2 is set
to a high-impedance state.(See Figures 6 & 9.)
When SEL is set to 1, the B3 and B4 channels on
PCMi2 are transparently passed, with a two frame
delay, to the same channels on ADPCMo. Similarily,
the two 8-bit words which are on ADPCMi are
transparently passed, with a two-frame delay, to
channels B3 and B4 of PCMo2. In this case PCMo1
is always high-impedance if ENB1 = 0. If ENB1 = 1
during ST-BUS operation then the D and C channels
are active on PCMo1.
LINEAR, FORMAT and A/µ pins are ignored in
bypass mode.
Algorithm Reset Mode
While an algorithmic reset is asserted the device will
incrementally converge its internal variables to the
'Optional reset values' stated in G.726. Algorithmic
reset requires that the master clock (MCLK) and
frame pulse (ENB1/2 or F0i) remain active and that
the reset condition be valid for at least four frames.
Note that this is not a power down mode; see
PWRDN for this function.
ADPCMo & PCMo1/2 Disable
When the encoders are programmed for ADPCMo
disable (MS1 to MS3 set to 1) the ADPCMo output is
set to a high impedance state and the internal
encode
function
remains
active.
Therefore
convergence is maintained. The decode processing
function and data I/O remain active.
When the decoders are programmed for PCMo1/2
disable (MS4 to MS6 set to 1) the PCMo1/2 outputs
are high impedance during the B Channel timeslots
and also, during ST-BUS operation, the D and C
channel timeslots according to the state of ENB1.
Therefore convergence is maintained. The encode
processing function and data I/O remain active.
Whenever any combination of the encoders or
decoders are set to the disable mode the following
outputs remain active. A) ST-BUS mode: ENB2/
F0od, EN1, EN2 and C2o. Also the “D” and “C”
channels from PCMo1 and ADPCMo remain active if
ENB1 is set to 0. If ENB1 is brought high then
PCMo1 and ADPCMo are fully tri-stated. B) SSI
mode: When used in the 16-bit linear mode, only the
EN1 output remains active. For complete chip power
down see PWRDN.
Other Pin Controls
16 Bit Linear PCM
Setting the LINEAR pin to logic one causes the
device to change to 16-bit linear (uniform) PCM
transmission on the PCMi/o1 and PCMi/o2 ports.
The data rate for both ST-BUS and SSI operation in
this mode is 2048 kbit/s and all decode and encode
functions are affected by this pin. In SSI mode, the
input channel strobes ENB1 and ENB2/F0od remain
active for 8 cycles of BCLK for an ADPCM transfer.
The EN1 output is high for one BCLK period at the
end of the frame (i.e., during the 256th BCLK period).
In ST-BUS mode, the output strobes EN1 and ENB2/
F0od are adjusted to accommodate the required
PCM I/O streams. The EN1 output becomes a single
bit high true pulse during the last clock period of the
frame (i.e., the 256th bit period) while ENB2/F0od
becomes a delayed, low true frame-pulse (F0od)
output occuring during the 64 th bit period after the
EN1 rising edge.
Linear PCM on PCMi1 and PCMi2, are received as
14-bit, two’s complement data with three bits of sign
extension in the most significant positions (i.e.,
S,S,S,12,...1,0) for a total of 16 bits. The linear PCM
data transmitted from PCMo1 and PCmo2 are 16-bit,
two’s complement data with one sign bit in the most
significant position (i.e., S,14,13,...1,0)
32 and 24 kbit/s ADPCM mode
In 32 kbit/s and 24 kbit/s linear mode, the 16-bit
uniform PCM dual-octets of the B1, B2, B3 and B4
channels (from PCMi1 and PCMi2) are compressed
into four 4-bit words on ADPCMo. The four 4-bit
ADPCM words of the B1, B2, B3 and B4 channels
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MT9126
Preliminary Information
from ADPCMi are expanded into four 16-bit uniform
PCM dual-octets on PCMo1 and PCMo2. 16-bit
uniform PCM are received and transmitted most
significant bit first starting with b15 and ending with
b0. ADPCM data are transferred most significant bit
first starting with I1 and ending with I4 for 32 kbit/s
and ending with I3 for 24 kbit/s operation (i.e., I4 is
don’t care).(See Figures 5 & 8.)
16 kbit/sADPCM mode
When SEL is set to 0, the four, 2-bit ADPCM words
are transmitted/received on ADPCMo/i during the
ENB1 time-slot in SSI mode and during the B1
timeslot in ST-BUS mode. When SEL is set to 1, the
four, 2-bit ADPCM words are transmitted/received
on ADPCMo/i during the ENB2 timeslot in SSI mode
and during the B2 timeslot in ST-BUS mode. (See
Figures 5 & 8.)
PCM Law Control (A/µ, FORMAT)
The PCM companding/coding law invoked by the
transcoder is controlled via the A/µ and FORMAT
pins. ITU-T G.711 companding curves, µ-Law and
A-Law, are selected by the A/µ pin (0=µ-Law;
1=A-Law). Per sample, digital code assignment can
conform to ITU-T G.711 (when FORMAT=1) or to
Sign-Magnitude coding (when FORMAT=0). Table 1
illustrates these choices.
and assuming that clocks are applied to the MCLK
and BCLK pins, the internal clocks will still not begin
to operate until the first frame alignment is detected
on the ENB1 pin for SSI mode or on the F0i pin for
ST-BUS mode. The C2o clock and EN1, EN2 pins
will not start operation until a valid frame pulse is
applied to the F0i pin. If the F0i pin remains low for
longer than 2 cycles of MCLK then the C2o pin will
top toggling and will stay low. If the F0i pin is held
high then the C2o pin will continue to operate. In STBUS mode the EN1 and EN2 pins will stop toggling if
the frame pulse (F0i) is not applied every frame.
Master Clock (MCLK)
A minimum 4096 kHz master clock is required for
execution of the transcoding algorithm. The
algorithm requires 512 cycles of MCLK during one
frame for proper operation. For SSI operation this
input, at the MCLK pin, may be asynchronous with
the 8 kHz frame provided that the lowest frequency
and deviation due to clock jitter still meets the strobe
period requirement of a minimum of 512 t C4P 25%t C4P (see Figure 3). For example, a system
producing large jitter values can be accommodated
by running an over-speed MCLK that will ensure a
minimum 512 MCLK cycles per frame is obtained.
The minimum MCLK period is 61 nSec, which
translates to a maximum frequency of 16.384 MHz.
Extra MCLK cycles (>512/frame) are acceptable
since the transcoder is aligned by the appropriate
strobe signals each frame.
FORMAT
PCM Code
ENB1
0
1
SignMagnitude
A/µ = 0 or 1
ITU-T (G.711)
MCLK
(A/µ = 0)
(A/µ = 1)
512 tC4P - 25%tC4P Minimum
+ Full Scale
1111 1111
1000 0000 1010 1010
+ Zero
1000 0000
1111 1111 1101 0101
- Zero
0000 0000
0111 1111 0101 0101
- Full Scale
0111 1111
0000 0000 0010 1010
Figure 3 - MCLK Minimum Requirement
Table 1 - Companded PCM
Power Down
Setting the PWRDN pin low will asynchronously
cause all internal operation to halt and the device to
go to a power down condition where no internal
clocks are running. Output pins C2o, EN1, EN2,
PCMo1, PCMo2 and ADPCMo and I/O pin F0od/
ENB2 are forced to a high-impedance state.
Following the reset (i.e., PWRDN pin brought high)
8-40
Bit Clock (BCLK)
For SSI operation the bit rate, for both ADPCM and
PCM ports, is determined by the clock input at BCLK.
BCLK must be eight periods in duration and
synchronous with the 8 kHz frame inputs at ENB1
and ENB2. Data is sampled at PCMi1/2 and at
ADPCMi concurrent with the falling edge of BCLK.
Data is available at PCMo1/2 and ADPCMo
concurrent with the rising edge of BCLK. BCLK may
be any rate between 128 kHz and 4096 kHz. For STBUS operation BCLK is ignored (tie to VSS) and the
bit rate is internally set to 2048 kbit/s.
MT9126
Preliminary Information
BCLK
ENB1
ENB2/F0od
B1
B2
PCMi/o1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
B3
PCMi/o2
B4
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
32 kb/s
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
B1
ADPCM i/o
B3
B2
B4
1 2 3 x 1 2 3 x 1 2 3 x 1 2 3 x
24 kb/s
ADPCM i/o
B1
16 kb/s
B2
B3
1 2 1 2 1 2
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
B4
B1
B2
B3
B4
1 2 1 2 1 2 1 2 1 2
SEL = 0
SEL = 1
SEL for 16 kb/s only
Figure 4 - SSI 8-Bit Companded PCM Relative Timing
Notes: S = 3 bits sign extension
BCLK
µ−Law is 13 bit 2’s complement data (bits 0 -12)
A-Law is 12 bit 2’s complement data (shifted left once and utilizing
bits 1 - 12, bit 0 not defined)
... (2.048 MHz only)
EN1
ENB1
ENB2/F0od
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
B1
PCMi/o1
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
B2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
32 kb/s
ADPCM i/o
24 kb/s
ADPCMi/o
16 kb/s
B4
B3
PCMi/o2
1234 1234 1234 1234
B1
B2
B3
B4
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
1234 1234
B3
B4
123x 123x 123x 123x
123x 123x
12 12 12 12 12 12 12 12
12 12 12 12
B B B B B B B B
B B B B
1 2 3 4 1 2 3 4
AA
AA
SEL = 0 AA
SEL = 1
AA
AA
1 2 3 4
SEL = 1
SEL for 16 kb/s only
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
Figure 5 - SSI 16-Bit Linear PCM Relative Timing
8-41
MT9126
BCLK
ENB1
ENB2/F0od
PCMi/o1
ADPCMo/i
PCMi/o2
PCMi/o1
ADPCMo/i
PCMi/o2
PCMi/o1
ADPCM o/i
PCMi/o2
Preliminary Information
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A7 6 5 4 3 2
A
A
A
A
B1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A7 6 5 4 3 2
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B3
A
A
A
A7 6 5 4 3 2
A
A
A
A
A
A
A
A
A
AA
A
AA
A
A 1 2 3 4AA
AAx x
A
AA
A
AA
A
AA
A
B1 AA
A
AA
A
AA
A
A
A
A
A
A
A
A
A
A1 2 3 4 1 2
A
A
A
A
A
A
A
AA
A
AA
AA
A
A
AA
B3
A
AA
A
AA
AA
A
A
A 1 2 3 4AA
AAx x
A
AA
A
AA
A
A
A
A
A
AA
A
AA
A
A 1 2 AA
AAx x x x
A
AA
A
AA
A
AA
A
B1 AA
A
AA
A
AA
A
AA
A
A
A
SEL = 0
A
A
A
A
A
A
1 2 1 2 1 2
A
A
A
B1 B2 B3
A
A
A
A
AA
A
AA
A
AA
A
AA
B3
A
AA
A
AA
A
AA
A
AA
A
AA
1
2
x x x x
A
AA
A
AA
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
1 0 7 6 5 4 3 2 1 0 AA
AA
AA
AA
AA
B2
AA
AA
AA
AA
AA
AA
AA
AA
SEL = 0
AA
AA
AA
AA
AA
AA
1 0 7 6 5 4 3 2 1 0 AA
AA
AA
AA
AA
AA
AA
AA
SEL = 1
AA
AA
AA
AA
AA
AA
AA
B4
AA
AA
AA
1 0 7 6 5 4 3 2 1 0 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
x x 1 2 3 4AA
x
x
x
x
AA
AA
AA
AA
AA
AA
AA
AA
B2 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
3 4 1 2 3 4 1 2 3 4AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B4 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
x x 1 2 3 4AAx x x x AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
x x 1 2AAx x x x x x AA
AA
AA
AA
AA
AA
AA
B2 AA
AA
AA
AA
AA
AA
AA
AA
AA
AAA SEL = 1
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
1 2 AA
1
2
1
2
1
2
1
2
AA
AA
AA
AA
AA
AA
B4 AAB1 B2 B3 B4 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B4 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
x x 1 2AA
x
x
x
x
x
x
AA
AA
AA
AA
SSI PCM
Bypass
32 kb/s using bits 1 2 3 4
24 kb/s where bit 4 = x
SSI ADPCM
Bypass
16 kb/s
Figure 6 - SSI PCM and ADPCM Bypass Relative Timing
8-42
MT9126
Preliminary Information
MCLK (C4)
F0i
ENB2/F0od
C2o (output)
EN1 (output)
EN2 (output)
PCMi1
PCMo1
PCMi2
PCMo2
ADPCMi
ADPCMo
AA
AA
AA
AA
AA
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAA
AAAA
AAAA
AAAA
A
AA
AA
AA
AAAA
AA
AA
AA
AAAA
AAAA
AAAA
A
0
1
AA
AA7 6 5 4 3 2 1 0AA7 6 5 4 3 2 1 0AA7 6 5 4 3 2 1 0AA
A
AA
AAAA
AAAA
AAAA
AAAA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
D
C
B1
B2
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAA
AAAA
AAAA
AAAA
A
AA
AA
AA0 1AAAAAAAAAAAAAAAAAAA7 6 5 4 3 2 1 0AA7 6 5 4 3 2 1 0AA7 6 5 4 3 2 1 0AA
AA
AA
AAAA
AAAA
AAAA
AA
A
AA
AA
AA
AAAA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AA
AA
AAAA
AA AAAAAAAAAAAAAAAAAAAA
AA AAAAAAAAAAAAAAAAAAAA
AA
AA
AAAA
AA AAAAAAAAAAAAAAAAAAAA
AA AAAAAAAAAAAAAAAAAAAA
AA7 6 5 4 3 2 1 0AA7 6 5 4 3 2 1 0AA
AAAA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA transparent relay of
AA D- and C- channels AA
AA
AA
AA
AA
AA
AA
AA
AA
B3
AA
AA
AA
AA
AA
B4
when
ENB1=0
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA AAAAAAAAAAAAAAAAAAAA
AAAA
AA AAAAAAAAAAAAAAAAAAAA
AA
AA
AA
AA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA7 6 5 4 3 2 1 0AA
AA7 6 5 4 3 2 1 0AA
AA
AA AAAA
AA AAAA
AAAA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAA
AAAA
AAAA
AAAA
A
AA
AA
AA0 1AAAAAAAAAAAAAAAAAAA7 6 5 4
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAA
AAAA
AAAA
AAAA
A
AA
AA
AA
3
2
1
0
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B1
B3
AA
AA
AA
AA
AA
AA
AA
B2
B4
D
C
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAA
AAAA
AAAA
AAAA
A
AA
AA
AA
AA
AA
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
AA0 1AAAAAAAAAAAAAAAAAAA
AA7 6 5 4 3 2 1 0AA
AA
AA
AA
AA
AA
AAAAAAAAAAAAAAAAAA
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
SEL=0
SEL=1
AA
AA
AA
AA
AA
AA
AA
AA
AA
32 kb/s is shown
AA
AA
AA
AA
AA
B1 B2 B3 B4AAB1 B2 B3 B4AA
In 24 kb/s, bit 4 becomes “X”
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
1 2 1 2 1 2 1 2AA1 2 1 2 1 2 1 2AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B1
B2
B3
B4
B1
B2
B3
B4
AA
AA
AA
AA
AA
AA
AA
AA
AA
16 kb/s
AA
AA
AA
AA
AA
1
2
1
2
1
1
2
1
2
1
2
1
2
2
1
2
SEL operates for AA
AA
16 kb/s only
AAAA
AAAA
AAAA
outputs=High impedance
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAA
AAAA inputs = don’t care
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
Two frame delay from data input to data output
Figure 7 - ST-BUS 8-bit Companded PCM Relative Timing
8-43
MT9126
MCLK (C4i)
F0i
C2o
EN1 (output)
F0od/ENB2
PCMi/o1
PCMi/o2
ADPCMi/o
(32/24 kb/s)
bit 4 = x at 24 kbit/s
ADPCMi/o
(16 kb/s)
Preliminary Information
AA
A
AA
A
AA
AA
AA
AA
A
AA
AA
AA
A
A
A
A
AA
A
AA
AA
A
A
AA
AA
A
A
A
AA
A
A
A
AA
AA
A
A
A
AA
A
A
A
A
AA
A
A
A
AA
AA
A
A
A
AA
A
A
A
A
AA
A
A
A
AA
AA
A
A
A
AA
A
A
A
A
AA
A
A
A
AA
AA
A
A
AA
AA
A
A
AA
AA
A
A
A
A
AA
A
A
A
AAA
A
A
A
AA
A
A
A
AAA
AA
A
A
A
A
A
AAA
A
A
A
AA
A
AAA
A
A
A
A
AAA
A
A
AA
A
A
AAA
AA
AA
A
A
A
A
A
AAA
A
AA
AA
A
A
A
AA
A
A
A
A
AA
A
A
A
AA
AA
A
A
A
AA
A
A
A
A
AA
A
A
A
AA
AA SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 A SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 A
A
AA
A
A
A
A
AA
A
A
A
AA
AAAA
AAAAAAAAAAAAAAAA
A AAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAA
A AAAAAAAAAAAAAAAAAAAA
A
A
AA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAA
A AAAAAAAAAAAAAAAAAAAA
B1
B2
AA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAA
AA AAAAAAAAAAAAAAAAAAAAA
AA
A
AA
AAAA
AAAAAAAAAAAAAAAAAAAA
AA
A
A AAAAAAAAAAAAAAAAAAAA
AA
A
A
A
A
AA
A
A
AA
AA
AA
A
AA
AA
A
A SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 A
SSS
12
11
10
9
8
7
6
5
4
3
2
1
0
AA
A
A
A
AA
AA
AA
A
A
AA
A
A
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
A AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAA
AA
AAAA
A
A
AA
AAAA
AAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
B3
B4
AA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAA
AA
A
A
AA
AA
AA
A
AA
A
AA
A
AA
AA
AA
A
A
AA
A
A
AA
A
AA
A
A
AA
A
A
A
AA
A
A
AA
AA
AA
A
A
A
AA
A1234 1234 1234 1234 A
AA
AA
A
A
A
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAA
AA AAAAAAAAAAAAAAAA AA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
A
A
AAA
AA AAAAAAAAAAAAAAAAAAA
A
AAAA
A
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AA
AAAA
AAAAAAAAAAAAAAA
A B1 B2 B3 B4 AAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAA
AAA
AAAAA
AA
AAAA
AAAA
AAAA
AAAA
A
AAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AA
A
A
AA
A
AA
AA
A
AA
AA
A
A
A
AA
A
A
AA
A
A
AA
AA
A
A
AA
AA
A
12 12 12 12 12 12 12 12A
AA
A
A
AAAAAAAAAAAAAAAAAAAAAA
AA
A
A
AA
AA
AAAA
AAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
B
B
B
B
B
B
B
B
AA
AAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA
AA
AAAAA
AAAA
A
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
A 1 2 3 4 1 2 3 4 AAAAA
AAAAAAAAA
AAAA
AA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAAAA
A
AA
AA
A
AA
AA
AA
AA
A
AA
AA
A SEL = 0 AA
SEL operated for
AASEL = 1
AA
AA
AA
16kb/s only
AA
AAAAAAAAAAAA
AAAAAAAA
AAAAAAAA outputs = High impedance
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA inputs = don’t care
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
Two frame delay from data input to data output
Note: D &C channels not supported in this mode.
Figure 8 - ST-BUS 16-bit Linear PCM Relative Timing
8-44
MT9126
Preliminary Information
A
A
AA
AA
A
A
A
A
A
A
A
MCLK
A
AA
AA
A
A
A
A
A
A
A
A
F0i
A
AA
AA
A
A
A
A
A
AA
A
A
A
A
A
A
A
A
ENB2/F0od
A
AA
AA
A
A
A
A
A
A
AA
A
A
A
A
A
A
A
A
A
AA
AA
C2o
A
A
A
A
A
A
A
A
AA
AA
A
EN1 (output)
A
A
A
A
A
AA
A
A
A
A
A
A
A
A
A
A
A
A
EN2 (output)
A
AA
AA
A
A
A
A
A
AA
A
A
A
A
A
A
A
A
A
AA
A
AAAAAAAAAAAAAAAAAAAA
A 0 1AAAAAAAAAAAAAAAAAAA 7 6 5 4 3 2 1 0 A
A
AAAAAAAAAAAAAAAAAAA
A
PCMi1
A
AA
AA
A
A
A
A
A
A
AA
A
A
D
C
A
A
A
A
A
A
P
A
AA
A
AAAAAAAAAAAAAAA
AAAA
A 0 1AAAAAAAAAAAAAAAAAA 7 6 5 4 3 2 1 0 A
C
PCMo1
A
A
AA
AAAA
AAAA
AAAA
AAAA
A
A
A
A
A
A
M
A
A SEL=0
A
A
A
AA
AA
A
A
A
A
A
AAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
A
AAAA
A
PCMi2
B
A
A AAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
A
A
A
AA
AA
y
A
SEL=1
A
A
A
A
A
A
p
A
AA
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
A
A
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
a
A
AAAA
A
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
PCMo2
A
A
A
A
A
A
A
A
s
A
AA
AA
A
A
A
A
s
A
AAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAA
AAAA
AA
AA 7 6 5 4 3 2 1 0 AA
ADPCMi
A 0 1AAAA
AAAA
AAAA
AAAA
AAAA
AA
A
A
A
A
A
AA
AA
D
C
A
A
A
A
A
A
A
A
AA
A
A
ADPCMo
A 0 1AAAAAAAAAAAAAAAAAAA 7 6 5 4 3 2 1 0 A
A
AAAA
AAAA
AAAA
AA
A
AA
AAAA
A
AAAAAAAAAAAAAAAAAAAA
A
A
A
A
A
A
AA
AA
A
A
A
A
A
A
AA
A
AA
A
A
AAAA
AAAA
AAAA
AAAA
A
A
A
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AA 7 6 5 4 3 2 1 0 AA
0 1AAAA
A
AAAA
AAAA
AAAA
AAAA
PCMi/o1
A
A
A
AAAA
AAAA
AAAA
AAAA
A
AA
AA
A
A
A
A
A
A
A
D
C
A
A
AAA
AAA
A
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
PCMi/o2
A
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
A
AAAAAAAAAAAAAAAAAAAAAAAA
AAAAA
A
A
AAAA
AAAA
AAAA
AAAA
A
AAAAAAAAAAAAAAAAAAAA
AA AAAAAAAAAAAAAAAAAAAAA
AAAA
A
AAAA
AAAAAAAAAAAAAAAAAAAA
D
A
AA AAAAAAAAAAAAAAAAAAAAA
A
A
A
AA
P
A
A
AAAA
AAAA
AAAA
AAAAAAA
A
A
AAAA
AAAA
AAAA
AAAA
C
A
AA 7 6 5 4 3 2 1 0 AAA
AAAA
AAAA
AAAA
0 1AAAA
ADPCMi/o
A
AAAA
AAAA
AAAA
AAAA
A
AA
AAAAAAAAAAAAAAAAAA
A
M
32 kb/s
A
AA
AA
D
C
A
24 kb/s bit 4 = X
A
AA
AA
A
A
AA
AA
A
B
A
AA
AA
A
A
y
A
AAA
AAA
A
A
AA
AA
D
C
p
A
A
AA
AA
A
AAAA
AAAA
AAAA
AAAA
a
A
AAAA
AAAA
AAAA
AAAA
AA
AA
ADPCMi/o
A
AAAA
AAAA
AAAA
AAAA
7
6
5
4
3
2
1
0
0
1
A
AAAA
AAAA
AAAA
AAAA
AA
AA
s
A
AAAA
AAAA
AAAA
AAAA
(16 kb/s)
A
AA
AA
A
s
A
AA
AA
A
A
AAAA
AAAA
AAAA
AAAAAA
AA
A
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AA
AA
PCMi/o1
0 1AAAA
A
AAAA
AAAA
AAAA
AAAA
7
6
5
4
3
2
1
0
A
AAAAAAAAAAAAAAAAAA
AA
A
A
AA
AA
A
D
C
A
AA
A
A
PCMi/o2
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAAAAA
A
AAAA
AAAA
AAA AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAA
A
AAAA
AAAA
AA AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAAAAA
AAAA
AAAA
AAAA
A
A
A
AAAA
AAAA
AAAAA
A
A
AAAA
AAAA
A outputs = High impedance A
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAA
A inputs = don’t care
7 6 5 4 3 2 1 0
B1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
B3
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
B1/B3
7 6 5 4 3 2 1 0
AA
AA
AA
AA
AA
AA
x x x x
1 2 3 4 AA
AA
AA
AA
AA
AA
AA
AA
B3
AA
AA
1 2 3 4 AA
AAx x x x
AA
AA
B1
1 2 3 4 1 2 3 4
B1
B2
SEL=0
B1
B2
B3 B4
1 2 1 2 1 2 1 2
AA
AA
AA
B1 AA
AA
AA
1 2AA
x x x x x x
AA
AA
AA
AA
AA
B3 AA
AA
AA
AA
1 2AA
x x x x x x
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA 7 6 5 4 3 2 1 0 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B2
AA
AA
AA
AA
AA
AA
AA
AA
AA 7 6 5 4 3 2 1 0 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA 7 6 5 4 3 2 1 0 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B4
AA
AA
AA
AA
AA
AA
AA 7 6 5 4 3 2 1 0 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
7
6
5
4
3
2
1
0
AA
AA
AA
AA
AA
AA
AA
AA
B2/B4
AA
AA
AA
AA
AA
AA
AA
AA
AA 7 6 5 4 3 2 1 0 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B2
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
1
2
3
4
x
x
x
x
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA B4
AA
AA
AA
AA
AA
AA
AA
AA
AA1 2 3 4 AAx x x xAA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
1 2 3 4 1 2 3 4 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B3
B4
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
SEL=1
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B1
B2
B3
B4
AA
AA
AA
AA
AA
AA
AA
1 2 1 2 1 2 1 2 AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
A
AA
A
AA
B2
AA
A
AA
AA
A
AA
AA
A
AA
1
2
x
x
x
x
x
x
AA
A
AA
AA
A
AA
AA
A
AA
AA
A
AA
AA
A
AA
AA
A
AA
B4
AA
A
AA
AA
A
AA
AA
A
1 2 A x x x x x x AA
AA
AA
AA
A
AA
AA
A
AA
AA
AA
AA
AA
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
Two frame delay from data input to data output
Figure 9 - ST-BUS PCM and ADPCM Bypass Relative Timing
8-45
MT9126
Preliminary Information
Processing Delay Through the Device
Applications
In order to accommodate variable rate PCM and
ADPCM interfaces, the serial input and output
streams require a complete frame to load internal
shift registers. Internal frame alignment of the
encoding/decoding functions are taken from either of
the F0i or ENB1 & ENB2 input strobes depending
upon the device operating mode (i.e., ST-BUS or
SSI). The encoding/decoding of all channels then
takes one frame to complete before the output
buffers are loaded. This results in a two frame
transcoding delay. The two frame delay also applies
to the D and C channels and to the PCM and
ADPCM bypass functions.(See Figure 10.)
Figure 11 depicts an ISDN line card utilizing the
MT8910 ’U’ interface transciever and MT9126
ADPCM transcoder. This central office application
implements the network end of a Pair-Gain system.
Figure 12 shows Mitel devices used to construct the
remote Pair-Gain loop terminator.
Note: When changing the relative positions of the
ENB1 and ENB2 strobes, precaution must be taken
to ensure that two conditions are met. They are:
1) There must be at least 512 master clock cycles
between consecutive rising edges of ENB1. This
condition also holds true for ENB2.
2) The ENB1 strobe must alternate with the ENB2
strobe.
Violation of these requirements may cause noise on
the output channels.
Figure 13 depicts an ADPCM to linear PCM
converter for applications where further, value
added, functions are being performed via digital
signal processor. Access to linear coded PCM
reduces the overhead of the DSP by removing the
need for a companded to linear conversion. The
linear PCM capability of the ADPCM transcoder in
conjunction with the frame alignment signal EN1
allows direct connection to the serial port of both
Motorola and Texas Instruments Digital Signal
Processors. Daisy-chaining via the delayed frame
strobe output ensures that the ADPCM array is
distributed over the complete 2048 kbit bandwidth. If
the DSP has a second serial port then access to the
processed PCM can be had directly. For processors
with only one serial port the MT8920 connected to
the DSP parallel port will provide serial access by
parallel to serial conversion. The same daisychained arrangement of Quad ADPCM transcoders
will provide a general system resource for PCMADPCM conversion by setting the device to nonlinear operation.
frame n-1
frame n
frame n+1
PCM Byte "X" latched into device
during frame n-1
PCM Byte "X" processed according
to MSn input states latched during
frame n
ADPCM Word "X" output from
device during frame n+1
PCMi1/2
Byte "x"
ADPCMo
ENB1 or ENB2
F0i
MS1 or 4
Word "x"
A
A
A
A
A
A
A
A
A
A
A
AA
A
AA
AA
32 kb/s
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
24 kb/s
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
32 kb/s
Where MS2, 3, 5, 6 = 0
This diagram shows the conversion sequence from PCM to ADPCM. The same pipelining occurs in the
reverse ADPCM to PCM direction.
Total delay from data input to data output = 2 frames.
Figure 10 - Data Throughput
8-46
MT9126
Preliminary Information
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AA
AA
AA
AA
A
AA
AA
F0i
AA
AA
A
AA
AA
AA
AA
A
AA
A
AA
A
AA
AA
AA
MT8910
AA
A
MT9126
AA
AA
LIN+
AA
AA
A
PCMi1
LINAA
A
T
AA
2 AA
PCMo1
F0b
F0i
AA
LOUTAA
A
R
AA
AA
MCLK
C4b
LOUT+
AA
AA
A
PCMi2
ADPCMi
AA
A
DSTo
AA
AA
AA
PCMo2
ADPCMo
DSTi
AA
A
AA
AA
AA
AA
A
AA
A
AA
AA
F0od
AA
AA
A
AA
A
AA
AA
AA
AA
A
AA
AA
AA
AA
A
AA
A
AA
AA
AA
AA
A
C4i
AA
AA
AA
AA
A
AA
AA
F0od
AA
AA
AA
AA
AA
AAAA
AAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
1
AAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
8 AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
T RAAAA
T R
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAA
1
2
F0od
C4i
C4i
F0i
PCMi1
PCMo1
PCMi2
PCMo2
F0od
C4i
F0i
PCMi1
PCMo1
PCMi2
PCMo2
F0od
C4i
PCMi1
PCMo1
PCMi2
PCMo2
F0i
8
F0i
F0i
MT8980
DX
ST1i
ST1o
C4i
ST2i
ST2o
Figure 11 - ISDN Line Card with 32 kbit/s ADPCM
8-47
8-48
GND
GND
VBAT
VBAT
VEE
VEE
VDD
VDD
16
25
3
38
5V
-5V
-24VDC
15
26
39
40
14
27
4
37
22
7
34
21
28
30
20
Pair Gain
SLIC 2 19
16
DCRI
DCRI
ESI2
ESTi
RG2
RG1
VX2
VR2
RF3
RF2
RF1
VX1
VR1
13
11
MH88622 18
1
2
Pins
5,8,9,17,23,32,33,36
-24VDC
-5V
5V
RING2
TIP2
RING1
TIP1
MH88622
Pair Gain
SLIC 1
120VDC ring
voltage
meter signal
I/P
120VDC ring
voltage
meter signal
I/P
5V
5V
5V
5V
EN1
EN2 28
8
Reset
A/µ
15
FORMAT 16
10.24 MHz
MT8910
or
MT8972
C4b
DSTi
DSTo
F0b
MicroController
Optional QADPCM
functional control
SLIC Functions
Static Control:
3
3
5V
3
9 control lines for QADPCM, some optional
D-Channel access through CODEC1 Microport as well as CChannel control of MT8910/MT8972
8 signals for microport are:
DATA1, DATA2, SCLK, IRQ, CS1, CS2, CS3, CS4
8
3
16 control/status lines are:
LR1/2, ESE1/2, SHK1/2, RC1/2 - 8 x 2 SLIC’s
16
18
PWRDN 17
IC
MS1 19
MS2 20
Serial Micro-port
Intel MCS-51
Motorola SPI
Nat Semi Microwire
14 SEL
13 PCMi2
12 PCMo2
11 ENB1
10 ENB2/F0od
LINEAR
MS3 21
9
VDD 22
VSS
8
ADPCMi 23
PCMo1
6
PCMi1
ADPCMo 24
BCLK
5
7
MS4 25
C2o
MS6 27
4
1
MT9126
MS5 26
MCLK
F0i
3
2
1
Figure 12 - Pair Gain Remote Terminal utilzing Mitel Components
1
20
2 MT9160 19
3
4
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1
20
2 MT9160 19
3
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1
20
2 MT9160 19
3
2
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
MVSSA
HSPKR+
HSPKRVDD
CLOCKin
STB/F0i
Din
Dout
MT9160
M+
1
VBias
VRef
PWRST
IC
A/µ/IRQ
VSSD
CS
SCLK
DATA1
DATA2
MT9126
Preliminary Information
MT9126
Preliminary Information
System Frame pulse
System 4.096MHz
MT9126
C2o
F0i
MCLK (C4i)
PCMo1
PCMo2
ADPCMo
ADPCMi
PCMi1
PCMi2
LINEAR
ENB2/F0od
EN1
FSR
FSX
IRQ0
MT8920
MT9126
CLKR
C2o
CLKX
PCMo1
PCMo2
S
T
+5v
TI DSP
DR
P
F0i
MCLK (C4i)
PCMi1
PCmi2
LINEAR
ENB2/F0od
EN1
A
DX
ADPCMo
ADPCMi
+5v
MT9126
C2o
F0i
MCLK (C4i)
PCMo1
PCmo2
ADPCMo
ADPCMi
PCMi1
PCMi2
STPA
ST-BUS
port
2nd serial port
if available
EN1
LINEAR
ENB2/F0od
+5v
MT9126
C2o
F0i
MCLK (C4i)
PCMo1
PCMo2
ADPCMo
ADPCMi
PCMi1
PCMi2
EN1
LINEAR
ENB2/F0od
+5v
ADPCM BUS
Figure 13 - ST-BUS to DSP Platform
8-49
MT9126
Preliminary Information
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
VDD-VSS
-0.3
7.0
V
Vi | Vo
VSS-0.3
VDD+ 0.3
V
±20
mA
150
°C
500
mW
1
Supply Voltage
2
Voltage on any I/O pin
3
Continuous Current on any I/O pin
Ii | Io
4
Storage Temperature
TST
5
Package Power Dissipation
PD
-65
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
VDD
4.5
5.0
5.5
V
Test Conditions
1
Supply Voltage
2
TTL Input High Voltage
2.4
VDD
V
400mV noise margin
3
TTL Input Low Voltage
VSS
0.4
V
400mV noise margin
4
CMOS Input High Voltage
4.5
VDD
V
5
CMOS Input Low Voltage
VSS
0.5
V
6
Operating Temperature
-40
+85
°C
TA
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1
Supply Current
Sym
ICC
IDD
2
Input HIGH voltage (TTL)
VIH
3
Input LOW voltage (TTL)
VIL
4
M
C
L
K
Min
Typ‡
Max
Units
Test Conditions
100
µA
mA
PWRDN = 0
PWRDN = 1, clocks active
5
2.0
V
0.8
Input HIGH voltage (CMOS)
VIHC
Input LOW voltage (CMOS)
VILC
6
Input leakage current
IIH/IIL
7
High level output voltage
VOH
8
Low level output voltage
VOL
9
High impedance leakage
IOZ
1
10
Output capacitance
Co
10
pF
11
Input capacitance
Ci
8
pF
Positive Threshold Voltage
Hysteresis
Negative Threshold Voltage
V+
VH
V-
1.0
V
V
V
5
12
P
W
R
D
N
3.5
V
V
0.1
1.5
V
10
µA
VIN=VSS to VDD
V
IOL=5.0mA
0.4
V
IOL=5.0mA
10
µA
VIN=VSS to VDD
2.4
3.7
1.3
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* DC Electrical Characteristics are over recommended temperature and supply voltage.
8-50
MT9126
Preliminary Information
AC Electrical Characteristics† - Serial PCM/ADPCM Interfaces (see Figure 14)
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ†
Max
Units
Test Conditions
1
BCLK Clock High
tBCH
80
ns
2
BCLK Clock Low
tBCL
80
ns
3
BCLK Period
tBCP
200
4
Data Output Delay (excluding first
bit)
tDD
5
Output Active to High Z
tAHZ
6
Strobe Signal Setup
tSSS
80
tBCL80
ns
7
Strobe Signal Hold
tSSH
80
tBCL80
ns
8
Data Input Setup
tDIS
50
ns
9
Data Input Hold
tDIH
50
ns
10
Strobe to Data Delay (first bit)
tSD
11
F0i Setup
tF0iS
50
122
150
ns
12
F0i Hold
tF0iH
50
122
150
ns
13
MCLK (C4i) duty cycle
tH/tL
x100
40
50
60
%
14
F0od Delay
tDFD
60
ns
CL=150pF//RL=1K
15
F0od Pulse Width
tDFW
ns
CL=150pF//RL=1K
16
MCLK (C4i) period
tC4P
17
Data Output delay
tDSD
18
Data in Hold time
tDSH
50
ns
19
Data in Setup time
tDSS
50
ns
7900
60
ns
CL=150pF//RL=1K
60
ns
CL=150pF//RL=1K
60
ns
244
61
ns
244.2
ns
95
ns
CL=150pF//RL=1K
CL=150pF//RL=1K
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
8-51
MT9126
Preliminary Information
tBCH
tBCP
tBCL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
BCLK AAAA
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
tSSH
tSSS
S
S
I
ENB1 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
or
A
A
ENB2 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDIS
tDIH
VIH
VIL
VIH
VIL
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA VIH
PCMi/ADPCMi
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A VIL
tDSS
tAHZ
tDD
tSD
tDSH
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA VOH
PCMo/ADPCMo
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A VOL
tDSD
tH
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAAAA
VIHC
MCLK
VILC
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
tC4P
tL
tF0iH
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA V
IH
F0i
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA VIL
tDFD
tF0iS
tDFD
S
T
B
U
S
F0od
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AA VOH
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA V
OL
tDFW
Figure 14 - Serial Port Timing
AC Electrical Characteristics† - ST-BUS C2o Conversion
Voltages are with respect to ground (VSS) unless otherwise stated.
Sym
1
Delay MCLK falling to C2o rising
tD1
100
ns
150pF//1K Load
2
Delay MCLK falling to Enable
tD2
100
ns
150pF//1K Load
F0i
Min
Typ†
Characteristics
Max
Units
Test Conditions
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
VIH
VIL
AA VIHC
MCLK AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AA
(C4i) AAAA
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA VILC
tD1
C2o
EN1
EN2
AAAA
A
AA
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AA VOH
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA VOL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA VOH
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA VOL
tD2
tD2
Figure 15 - ST-BUS Timing for External Signal Generation
8-52
MT9126
Preliminary Information
AC Electrical Characteristics† - Mode Select Timing (see Figures 16 & 17)
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ†
Max
Units
1
Mode Select Setup
tSU
500
ns
2
Mode Select Hold
tHOLD
500
ns
Test Conditions
MCLK=4096 kHz
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
t
MS1
to
MS6
ENB1 (input)
SU
t
HOLD
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA VIH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA IL
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA VIH
Figure 16 - SSI Mode Select Set-up and Hold Timing
t
SU
MS1
to
MS6
t
HOLD
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIH
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A VIL
MCLK
F0i
Refer to Figure 14 for ST-BUS F0i timing.
Figure 17 - ST-BUS Mode Select Set-up and Hold Timing
8-53
MT9126
Notes:
8-54
Preliminary Information