IDT IDT74FCT88915TT100PY Low skew pll-based cmos clock driver (with 3-state) Datasheet

IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
Integrated Device Technology, Inc.
FEATURES:
IDT54/74FCT88915TT
55/70/100/133
PRELIMINARY
is fed back to the PLL at the FEEDBACK input resulting in
essentially delay across the device. The PLL consists of the
phase/frequency detector, charge pump, loop filter and VCO.
The VCO is designed for a 2Q operating frequency range of
40MHz to f2Q Max.
The IDT54/74FCT88915TT provides 8 outputs with 500ps
skew. The Q5 output is inverted from the Q outputs. The 2Q
runs at twice the Q frequency and Q/2 runs at half the Q
frequency.
The FREQ_SEL control provides an additional ÷ 2 option in
the output path. PLL _EN allows bypassing of the PLL, which
is useful in static test modes. When PLL_EN is low, SYNC
input may be used as a test clock. In this test mode, the input
frequency is not limited to the specified range and the polarity
of outputs is complementary to that in normal operation
(PLL_EN = 1). The LOCK output attains logic HIGH when the
PLL is in steady-state phase and frequency lock. When OE/
RST is low, all the outputs are put in high impedance state and
registers at Q, Q and Q/2 outputs are reset.
The IDT54/74FCT88915TT requires one external loop
filter component as recommended in Figure 1.
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 133MHz
• Pin and function compatible with MC88915T
• 5 non-inverting outputs, one inverting output, one 2x
output, one ÷2 output; all outputs are TTL-compatible
• 3-State outputs
• Output skew < 500ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 1ns (from tPD max. spec)
• TTL level output voltage swing
• 64/–15mA drive at TTL output voltage levels
• Available in 28 pin PLCC, LCC and SSOP packages
DESCRIPTION:
The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input
reference clock. It provides low skew clock distribution for
high performance PCs and workstations. One of the outputs
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
SYNC (0)
SYNC (1)
LOCK
0M
u
1x
Phase/Freq.
Detector
Voltage
Controlled
Oscilator
Charge Pump
LF
REF_SEL
PLL_EN
0
1
Mux
Divide
-By-2
2Q
(÷1)
1 M
u
x
0
(÷2)
D
Q
D
FREQ_SEL
Q0
CP R Q
Q
Q1
Q
Q2
Q
Q3
Q
Q4
Q
Q5
Q
Q/2
CP R
OE/RST
D
CP R
D
CP R
D
CP R
D
CP
R
D
CP R
3072 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1995 Integrated Device Technology, Inc.
9.7
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AUGUST 1995
DSC-4247/1
1
1
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FEEDBK
OE/RST
VCC
Q5
GND
Q4
VCC
2Q
PIN CONFIGURATIONS
4
3
2
1
28
27
26
25
5
6
24
GND
SYNC(0)
7
23
Q3
10
11
12
13
14
15
16
17
18
Q1
GND
PLL_EN
VCC
27
3
26
2Q
OE/RST
4
25
Q/2
FEEDBACK
5
24
GND
REF_SEL
6
23
Q3
SYNC(0)
7
22
VCC
VCC(AN)
8
21
Q2
LF
9
20
GND
GND(AN)
10
19
LOCK
GND
LOCK
19
Q4
2
Q2
20
28
Q5
VCC
21
VCC
SYNC(1)
9
Q0
GND(AN)
22
GND
LF
J28-1,
L28-1
8
FREQ_SEL
VCC(AN)
1
VCC
Q/2
REF_SEL
GND
SO28-7
SYNC(1)
11
18
PLL_EN
FREQ_SEL
12
17
GND
GND
13
14
16
15
Q1
Q0
VCC
3072 drw 03
3072 drw 02
PLCC/LCC
TOP VIEW
SSOP
TOP VIEW
PIN DESCRIPTION
Pin Name
I/O
Description
SYNC(0)
I
Reference clock input.
SYNC(1)
I
Reference clock input.
REF_SEL
I
Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).
FREQ_SEL
I
Selects between ÷1 and ÷2 frequency options. (Refer to functional block diagram).
FEEDBACK
I
Feedback input to phase detector.
LF
I
Input for external loop filter connection.
Q0-Q4
O
Clock output.
Q5
O
Inverted clock output.
2Q
O
Clock output (2 x Q frequency).
Q/2
O
Clock output (Q frequency ÷ 2).
LOCK
O
Indicates phase lock has been achieved (HIGH when locked).
OE/RST
I
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are
enabled. When LOW, outputs are in HIGH impedance.
PLL_EN
I
Disables phase-lock for low frequency testing. (Refer to functional block diagram).
3072 tbl 01
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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
(3)
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
I OUT
DC Output
Current
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
–0.5 to VCC
+0.5
–0.5 to VCC
+0.5
V
0 to +70
–55 to +125
°C
–55 to +125
–65 to +135
°C
–55 to +125
–65 to +150
°C
–60 to +120
–60 to +120
mA
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
Conditions
VIN = 0V
Typ.
4.5
Max.
6.0
Unit
VOUT = 0V
5.5
8.0
pF
NOTE:
1. This parameter is measured at characterization but not tested.
pF
3072 lnk 03
3072 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals.
3. Output and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to 70°C, VCC = 5.0V ± 5%
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2.0
Typ.(2)
—
Max.
—
Unit
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
II H
Input HIGH Current
VCC = Max.
VI = VCC
—
—
±1
µA
II L
Input LOW Current
VI = GND
—
—
±1
µA
I OZH
High Impedance Output Current
VCC = Max.
VO = 2.7V
—
—
±1
µA
VO = 0.5V
—
—
±1
µA
—
–0.7
–1.2
V
—
100
—
mV
2.5
3.5
—
V
2.4
3.5
—
V
2.0
3.0
—
V
—
0.2
0.55
V
—
2.0
4.0
mA
Symbol
VIH
I OZL
VIK
Clamp Diode Voltage
VH
Input Hysteresis
VOH
Output HIGH Voltage
VCC = Min., IIN = –18mA
—
VCC = Min.
IOH = –3mA
VIN = VIH or VIL
VOL
Output LOW Voltage
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOH = –24mA MIL.
IOH = –32mA COM'L.(3)
VCC = Min.
IOL = 48mA MIL.
VIN = VIH or VIL IOL = 64mA COM'L.
VCC = Max., VIN = GND or VCC
(Test mode)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Duration of the condition can not exceed one second.
9.7
3072 tbl 04
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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
—
0.5
1.5
mA
—
0.25
0.4
mA/
MHz
50% Duty Cycle
—
15
40
pF
VCC = Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q/2
—
25
40
mA
—
42
60
mA
Symbol
Parameter
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = VCC –2.1V(3)
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
All Outputs Open
CPD
Power Dissipation Capacitance
IC
Total Power Supply Current (5,6)
VIN = VCC
VIN = GND
SYNC frequency = 20MHz. Q/2 loaded with 50pF
All other outputs open
VCC = Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q/2
SYNC frequency = 20MHz. Q/2 loaded with 50Ω
Thevenin termination. All other outputs open
3072 tbl 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (f) + ILOAD
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q frequency
ILOAD = Dynamic Current due to load.
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
TRISE/FALL Rise/Fall Times,
SYNC inputs
(0.8V to 2.0V)
Frequency Input Frequency,
SYNC Inputs
Duty Cycle Input Duty Cycle,
SYNC Inputs
Min.
—
Max.
3.0
Unit
ns
10(1)
2Q fmax
MHz
25%
75%
—
3053 tbl 06
OUTPUT FREQUENCY SPECIFICATIONS
Max. (2)
Symbol
f2Q
Parameter
Operating frequency 2Q Output
Min.
40
55
55
70
70
100
100
133
133
Unit
MHz
fQ
Operating frequency Q0-Q4, Q5 Outputs
20
27.5
35
50
66.7
MHz
fQ/2
Operating frequency Q/2 Output
10
13.75
17.5
25
33.3
MHz
3072 tbl 07
NOTES:
1. Note 8 in "General AC Specification Notes" and Figure 2 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
tRISE/FALL
All outputs
Rise/Fall Time
(between 0.8V and 2.0V)
tPULSE WIDTH (3)
All outputs(3)
Output Pulse Width
Q0-Q4, Q5, Q/2, 2Q @ 1.5V
SYNC input to FEEDBACK delay
tPD
SYNC-FEEDBACK (3) (measured at SYNC0 or 1 and FEEDBACK
input pins)
Condition(1)
Min.
Max.
Unit
Load = 50Ω to
VCC/2, CL = 20pF
0.2 (2)
1.2
ns
0.5tCYCLE – 0.5(5)
0.5tCYCLE + 0.5(5)
ns
Load = 50Ω to
VCC/2, CL = 20pF
0.1µF from LF to
Analog GND (9)
–0.5
+0.5
ns
Load = 50Ω to
VCC/2, CL = 20pF
—
350
ps
tSKEWr
(rising)(3,4)
Output to Output Skew
between outputs 2Q, Q0-Q4,
Q/2 (rising edges only)
tSKEWf
(falling)(3,4)
Output to Output Skew
between outputs Q0-Q4 (falling edges only)
—
350
ps
Output to Output Skew
2Q, Q/2, Q0-Q4 rising, Q5 falling
—
500
ps
tLOCK (6)
Time required to acquire
Phase-Lock from time
SYNC input signal is received
1(2)
10
ms
tPZH
tPZL
Output Enable Time
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q
3(2)
14
ns
tPHZ
tPLZ
Output Disable Time
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
3(2)
14
ns
tSKEWall
(3,4)
3072 tbl 08
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions, and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF.
(Where C1 is loop filter capacitor shown in Figure 1).
9.7
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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTES:
7. These two specs ( tRISE/FALL and tPULSE WIDTH 2Q output) guarantee that the FCT88915TT meets 68040 P-Clock input specification.
88915TT
Zo (clock trace)
2Q
68040
P-Clock
Output
Rp
Input
Rp = 1.5 Zo
3072 drw 04
8. The wiring diagrams and written explanations of Figure 4 demonstrate the input and output frequency relationships for various possible feedback
configurations. The allowable SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges,
depending on whether FREQ_SEL is HIGH or LOW. Also it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC
input and the Q outputs. The table below summarizes the allowable SYNC frequency range for each possible configuration.
Corresponding 2Q output
Frequency Range
Phase Relationship
of the Q Outputs
to Rising SYNC Edge
10 to (2Q fMAX Spec)/4
40 to (2Q fMAX Spec)
0°
Any Q (Q0-Q4)
20 to (2Q fMAX Spec)/2
40 to (2Q fMAX Spec)
0°
Q5
20 to (2Q fMAX Spec)/2
40 to (2Q fMAX Spec)
180°
2Q
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
0°
FREQ_SEL
Level
Feedback
Output
HIGH
Q/2
HIGH
HIGH
HIGH
Allowable SYNC Input
Frequency Range (MHZ)
LOW
Q/2
5 to (2Q fMAX Spec)/8
20 to (2Q fMAX Spec)/2
0°
LOW
Any Q (Q0-Q4)
10 to (2Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
0°
LOW
Q5
10 to (2Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
180°
LOW
2Q
20 to (2Q fMAX Spec)/2
20 to (2Q fMAX Spec)/2
0°
3072 tbl 09
9. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature
and voltage. Measurements were made with a 10MHz SYNC input and Q/2 output as feedback. The phase measurements were made at 1.5V.
The Q/2 output was terminated at the FEEDBACK input with 100Ω to VCC and 100Ω to ground.
tPD measurements were made with the loop filter connection shown below:
External Loop
Filter
0.1µF
LF
C1
Analog GND
3072 drw 05
9.7
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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BOARD VCC
ANALOG VCC
10µF
Low
Freq.
Bypass
0.1µF
High
Freq.
Bypass
Analog loop filter
LF section of the
FCT88915TT
0.1µF (Loop
Filter Cap)
ANALOG GND
BOARD GND
A separate Analog power supply is not necessary
and should not be used. Following these prescribed
guidelines is all that is necessary to use the
FCT88915TT in a normal digital environment.
3072 drw 06
Figure 1. Recommended Loop Filter and Analog Isolation Scheme for the FCT88915TT
NOTES:
1. Figure 1 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure
stable and jitter-free operation:
a.
All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of
long traces can cause undesirable voltage transients at the LF pin.
b.
The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the
88915TT's sensitivity to voltage transients from the system digital VCC supply and ground planes.
If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should
not occur at the 88915TT's digital VCC supply. The purpose of the bypass filtering scheme shown in figure 1 is to give the 88915TT additional
protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system.
c.
The loop filter capacitor (0.1µF) can be a ceramic chip capacitor, the same as a standard bypass capacitor.
2. In addition to the bypass capacitors used in the analog filter of figure 1 there should be a 0.1µF bypass capacitor between each of the other (digital) four
VCC pins and the board ground plane. This will reduce output switching noise caused by the 88915TT outputs, in addition to reducing potential for noise
in the "analog" section of the chip. These bypass capacitors should also be tied as close to the 88915TT package as possible.
9.7
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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The frequency relationship shown here is applicable to all
Q outputs (Q0, Q1, Q2, Q3 and Q4).
50MHz signal
25MHz feedback signal
HIGH
1:2 INPUT TO "Q" OUTPUT FREQUENCY
RELATIONSHIP
In this application, the Q/2 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q/2 and SYNC, thus the Q/2 frequency will equal the
SYNC frequency. The Q outputs (Q0-Q4, Q5) will always run
at 2X the Q/2 frequency, and the 2Q output will run at 4X the
Q/2 frequency.
RST
Q5
FEEDBACK
LOW
25MHz
input
Q4
2Q
Q/2
REF_SEL
SYNC(0)
VCC(AN)
25MHz
"Q"
Clock
Outputs
Q3
FCT88915TT
Q2
LF
50MHz signal
12.5MHz
signal
GND(AN)
12.5MHz feedback signal
FQ_SEL
Q0
HIGH
RST
Q5
FEEDBACK
LOW
12.5 MHz
input
Q4
2Q
Q/2
3072 drw 08
SYNC(0)
Allowable Input Frequency Range:
20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q FMAX Spec)/4 (for FREQ_SEL LOW)
25MHz
"Q"
Clock
Outputs
Q3
FCT88915TT
Figure 2b. Wiring Diagram and Frequency Relationships With Q4
Output Feedback
Q2
LF
GND(AN)
2:1 INPUT TO "Q" OUTPUT FREQUENCY
RELATIONSHIP
FQ_SEL
Q0
HIGH
PLL_EN
HIGH
HIGH
REF_SEL
VCC(AN)
Q1
Q1
PLL_EN
In this application, the 2Q output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of 2Q and SYNC, thus the 2Q frequency will equal the
SYNC frequency. The Q/2 output will always run at 1/4 the
2Q frequency, and the Q output will run at 1/2 the 2Q
frequency.
HIGH
3072 drw 07
Allowable Input Frequency Range:
10MHz to (f2Q FMAX Spec /4 (for FREQ_SEL HIGH)
5MHz to (f2Q FMAX Spec /8 (for FREQ_SEL LOW)
50MHz feedback signal
HIGH
RST
Q5
FEEDBACK
Figure 2a. Wiring Diagram and Frequency Relationships With Q/2
Output Feedback
LOW
50MHz
input
1:1 INPUT TO "Q" OUTPUT FREQUENCY
RELATIONSHIP
2Q
Q/2
12.5MHz
input
REF_SEL
SYNC(0)
VCC(AN)
In this application, the Q4 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q4 and SYNC, thus the Q4 frequency (and the rest
of the "Q" outputs) will equal the SYNC frequency. The Q/2
output will always run at 1/2 the Q frequency, and the 2Q
output will run at 2X the Q frequency.
Q4
Q3
FCT88915TT
25MHz
"Q"
Clock
Outputs
Q2
LF
GND(AN)
FQ_SEL
Q0
HIGH
Q1
PLL_EN
HIGH
3072 drw 09
Allowable Input Frequency Range:
40MHz to (f2Q FMAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL LOW)
Figure 2c. Wiring Diagram and Frequency Relationships With 2Q
Output Feedback
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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
CLOCK
@f
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FCT88915TT
PLL
2f
SYSTEM
CLOCK
SOURCE
FCT88915TT
PLL
2f
DISTRIBUTE
CLOCK @f
CMMU
CMMU
CPU
CMMU
CMMU
CMMU
CMMU
CMMU
CPU
CMMU
CMMU
CMMU
CPU
CARD
CPU
CARD
CLOCK @2f
at point of use
FCT88915TT
PLL
2f
MEMORY
CONTROL
MEMORY
CARDS
CLOCK @2f
at point of use
3072 drw 10
Figure 3. Multiprocessing Application Using the FCT88915TT for Frequency Multiplication
and Low Board-to-Board skew
FCT88915TT System Level Testing Functionality
When the PLL_EN pin is LOW, the PLL is bypassed and the
FCT88915TT is in low frequency "test mode". In test mode
(with FREQ_SEL HIGH), the 2Q output is inverted from the
selected SYNC input, and the Q outputs are divide-by-2
(negative edge triggered) of the SYNC input, and the Q/2
output is divide-by-4 (negative edge triggered). With
FREQ_SEL LOW the 2Q output is divide-by-2 of the SYNC,
the Q outputs divide-by-4, and the Q/2 output divide-by-8.
These relationships can be seen in the block diagram. A
recommended test configuration would be to use SYNC0 or
SYNC1 as the test clock input, and tie PLL_EN and REF_SEL
together and connect them to the test select logic.
This functionality is needed since most board-level testers
run at 1 MHz or below, and theFCT 88915TT cannot lock onto
that low of an input frequency. In the test mode described
above, any test frequency test can be used.
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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORM
50Ω to VCC/2, CL = 20pF
ENABLE AND DISABLE TEST CIRCUIT
VCC
VCC
VCC
7.0V
100Ω
500Ω
VOUT
VIN
Pulse
Generator
V OUT
VIN
D.U.T.
Pulse
Generator
D.U.T.
50pF
100Ω
RT
RT
20pF
500Ω
CL
3072 drw 11
3072 lnk 12
PROPAGATION DELAY, OUTPUT SKEW
1.5V
SYNC INPUT
(SYNC (1) or
SYNC (0))
t CYCLE SYNC INPUT
tPD
1.5V
FEEDBACK
INPUT
1.5V
Q/2 OUTPUT
t SKEWf
tSKEWALL
t SKEWr
t SKEWf
t SKEWr
1.5V
Q0-Q4
OUTPUTS
t CYCLE "Q" OUTPUTS
1.5V
Q5 OUTPUT
1.5V
2Q OUTPUT
3072 drw 13
(These waveforms represent the hookup of Figure 2a)
NOTES:
1. The FCT88915TT aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the 1.5V crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation
around a center point.
3. If a Q output is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q
output would run at twice the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
ENABLE AND DISABLE TIMES
ENABLE
SWITCH POSITION
DISABLE
Test
Disable Low
Enable Low
Disable High
Enable High
3V
CONTROL
INPUT
1.5V
OUTPUT
NORMALLY SWITCH
LOW CLOSED
t PZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
0V
t PLZ
t PZL
3.5V
Switch
Closed
Open
3072 tbl 10
1.5V
0.3V
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
VOL
t PHZ
0.3V
VOH
1.5V
0V
0V
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NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH
2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns
9.7
10
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXX
XX
FCT
Temp. Range
Device Type
X
Speed
X
Package
X
Process
9.7
Blank
B
Commercial
MIL-STD-883, Class B
J
PY
L
PLCC
SSOP
LCC
55
70
100
133
55MHz Max. frequency
70MHz Max. frequency
100MHz Max. frequency
133MHz Max. frequency
88915TT
Low skew PLL-based CMOS clock driver
54
74
–55°C to +125°C
0°C to +70°C
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11
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