FUJITSU SEMICONDUCTOR DATA SHEET DS04-29119-2E Spread Spectrum Clock Generator MB88155 ■ DESCRIPTION MB88155 is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. For modulation, the MB88155 supports both center-spreading and down-spreading. It has a non-modulated clock output pin (REFOUT) as well as a modulated clock output pin (CKOUT) . ■ FEATURES • Input frequency : • • • • • • • • • 12.5 MHz to 50 MHz (Multiplied by 1) 12.5 MHz to 20 MHz (Multiplied by 4) Output frequency : CKOUT 12.5 MHz to 80 MHz REFOUT The same as input frequency (not multiplied) Modulation rate : ± 0.5%, ± 1.0% (center spread) , − 1.0%, − 2.0% (Down spread) Equipped with oscillation circuit : range of oscillation 12.5 MHz to 40 MHz (Fundamental oscillation) 40 MHz to 48 MHz (3rd overtone) Modulation clock output Duty : 40% to 60% Modulation clock cycle − cycle jitter : MB88155-1xx 12.5 MHz to 20 MHz less than 150 ps MB88155-1xx 20 MHz to 50 MHz less than 100 ps MB88155-4xx less than 200 ps Low current consumption by CMOS process : 5 mA (24 MHz : Typ-sample, no load) Power supply voltage : 3.3 V ± 0.3 V Operating temperature : − 40 °C to + 85 °C Package : 8-pin plastic TSSOP Copyright©2005-2006 FUJITSU LIMITED All rights reserved MB88155 ■ PRODUCT LINEUP The MB88155 is available in different models : 2 models different in multiplier ( × 1 and × 4) , 2 in modulation type (center-spreading and down-spreading) , 2 in input frequency range at a multiplier of 1 (12.5 MHz to 25 MHz and 25 MHz to 50 MHz) , and 1 in input frequency range at a multiplier of 4 (12.5 MHz to 20 MHz) . The MB88155 is also available in two versions : modulation-on/off selectable version (with ENS pin) and powerdown function built-in version (with XPD pin) . MB88155-M T F Input frequency range, With/without ENS/XPD Spread type Multiplication rate setting Multiplied 0 : 12.5 MHz to 25.0 MHz, With ENS, Without XPD by 1 1 : 25.0 MHz to 50.0 MHz, With ENS, Without XPD 2 : 12.5 MHz to 25.0 MHz, Without ENS, With XPD 3 : 25.0 MHz to 50.0 MHz, Without ENS, With XPD Multiplied 0 : 12.5 MHz to 20.0 MHz, With ENS, Without XPD by 4 2 : 12.5 MHz to 20.0 MHz, Without ENS, With XPD → 0 : Down spread, 1 : Center spread → 1 : Multiplied by 1, 4 : Multiplied by 4 → Line-up of MB88155 Product Input frequency MB88155-100 12.5 MHz to 25 MHz MB88155-101 25 MHz to 50 MHz MB88155-102 12.5 MHz to 25 MHz MB88155-103 25 MHz to 50 MHz MB88155-110 Multiplication rate Output frequency 25 MHz to 50 MHz MB88155-112 12.5 MHz to 25 MHz MB88155-113 25 MHz to 50 MHz MB88155-412 2 No No Yes Yes No No Yes Down spread Yes No No Yes Center spread Yes No No Yes Center spread MB88155-400 MB88155-410 Yes Down spread The same as Multiplied by 1 input frequency 12.5 MHz to 25 MHz MB88155-111 MB88155-402 Modulation Modulation Power type enable pin down pin 12.5 MHz to 20 MHz Multiplied by 4 50 MHz to 80 MHz MB88155 ■ PIN ASSIGNMENT XIN 1 8 VDD MB88155 -xx0 -xx1 XOUT 2 ENS 3 XIN 1 7 CKOUT SEL 4 XOUT 2 6 VSS XPD 3 5 REFOUT SEL 4 8 VDD MB88155 -xx2 -xx3 7 CKOUT 6 VSS 5 REFOUT FPT-8P-M07 ■ PIN DESCRIPTION Pin name I/O Pin no. Description XIN I 1 Connection pin of resonator/clock input pin XOUT O 2 Connection pin of resonator ENS/XPD I 3 Modulation enable pin/power down pin SEL I 4 Modulation rate setting pin Down spread, SEL = “L” : Modulation rate − 1.0% Down spread, SEL = “H” : Modulation rate − 2.0% Down spread, SEL = “L” : Modulation rate ± 0.5% Down spread, SEL = “H” : Modulation rate ± 1.0% REFOUT O 5 Non-modulated clock output pin This pin becomes to“L” at power-down. VSS ⎯ 6 GND Pin CKOUT O 7 Modulated clock output pin This pin becomes to“L” at power-down. VDD ⎯ 8 Power supply voltage pin 3 MB88155 ■ I/O CIRCUIT TYPE Pin Circuit type Remarks CMOS hysteresis input SEL, XPD CMOS hysteresis input with pull-up resistor of 50 kΩ (Typ) 50 kΩ ENS • CMOS output • IOL = 3 mA • “L” output at power-down REFOUT (Continued) 4 MB88155 (Continued) Pin Circuit type Remarks • CMOS output • IOL = 4 mA • “L” output at power-down CKOUT Note: For XIN pin and XOUT pin, refer to “■ OSCILLATION CIRCUIT”. 5 MB88155 ■ HANDLING DEVICES Preventing Latch-up A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or (b) a voltage higher than the rating is applied between VDD and VSS. The latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. Handling unused pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pulldown resistor. Unused output pin should be opened. The attention when the external clock is used Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock. Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin. Power supply pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 µF) and the ceramic capacitor (about 0.01 µF) in parallel between VSS and VDD near the device, as a bypass capacitor. Oscillation circuit Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN or XOUT pin and the resonator do not intersect other wiring. Design the printed circuit board that surrounds the XIN and XOUT pins with ground. 6 MB88155 ■ BLOCK DIAGRAM VDD Modulation enable/ power down setting ENS/XPD SEL Modulation rate setting PLL block Clock output CKOUT Reference clock XOUT Reference clock output REFOUT Power down signal Rf = 1 MΩ XIN VSS 1 − M Phase compare Reference clock 1 − N Charge pump V/I conversion IDAC Modulation clock output Loop filter 1 − L Modulation logic MB88155 PLL block ICO Modulation rate setting/ Modulation enable setting A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI. 7 MB88155 ■ PIN SETTING The modulation clock requires stabilization wait time after the PIN setting is changed. For the modulation clock stabilization wait time, assure the maximum value for “Lock-up time” in the AC Characteristics list in “■ ELECTRICAL CHARACTERISTICS”. ENS modulation enable setting ENS Modulation L No modulation H Modulation MB88155-xx0, xx1 Note : Spectrum does not diffuse when “L” is set to ENS pin. MB88155-xx2, xx3 do not have ENS pin. XPD power down XPD Status L Power down status H Operating status MB88155-xx2, xx3 Note : When setting “L” to XPD pin, it becomes power down mode (low power consumption mode) . Both CKOUT and REFOUT of output pins are fixed to “L” output during power down. MB88155-xx0, xx1 do not have XPD pin. SEL modulation rate setting SEL L H Frequency ± 0.5% MB88155-x1x − 1.0% MB88155-x0x ± 1.0% MB88155-x1x − 2.0% MB88155-x0x Note : The modulation rate can be changed at the level of the pin. 8 MB88155 • Center spread Spectrum is spread (modulated) by centering on the non-spread frequency. Modulation width 2.0% Radiation level −1.0% +1.0% Frequency Non-spread frequency Example of center spread at modulation rate ± 1.0% • Down spread Spectrum is spread (modulated) below the non-spread frequency. Modulation width 2.0% Radiation level −2.0% Frequency Non-spread frequency Example of down spread at modulation rate − 2.0% 9 MB88155 ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Unit Min Max VDD − 0.5 + 4.0 V Input voltage* VI VSS − 0.5 VDD + 0.5 V Output voltage* VO VSS − 0.5 VDD + 0.5 V Storage temperature TST − 55 + 125 °C Operation junction temperature TJ − 40 + 125 °C Output current IO − 14 + 14 mA Overshoot VIOVER ⎯ VDD + 1.0 (tOVER ≤ 50 ns) V Undershoot VIUNDER VSS − 1.0 (tUNDER ≤ 50 ns) ⎯ V Power supply voltage* * : The parameter is based on VSS = 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot tUNDER ≤ 50 ns VIOVER ≤ VDD + 1.0 V VDD Input pin VSS tOVER ≤ 50 ns 10 VIUNDER ≤ VSS − 1.0 V MB88155 ■ RECOMMENDED OPERATING CONDITIONS (VSS = 0.0 V) Parameter Symbol Pin Conditions Power supply voltage VDD VDD “H” level input voltage VIH “L” level input voltage Value Unit Min Typ Max ⎯ 3.0 3.3 3.6 V XIN, SEL, ENS, XPD ⎯ VDD × 0.8 ⎯ VDD + 0.3 V VIL XIN, SEL, ENS, XPD ⎯ VSS ⎯ VDD × 0.2 V Input clock duty cycle tDCI XIN 12.5 MHz to 50 MHz 40 50 60 % Operating temperature Ta ⎯ ⎯ − 40 ⎯ + 85 °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Input clock duty cycle (tDCI = tb/ta) ta tb XIN 1.5 V 11 MB88155 ■ ELECTRICAL CHARACTERISTICS • DC Characteristics Parameter (Ta = − 40 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Symbol Pin ICC VDD Value Unit Min Typ Max 24 MHz output No load capacitance ⎯ 5.0 7.0 mA At power-down ⎯ 10 ⎯ µA VDD − 0.5 ⎯ VDD V VSS ⎯ 0.4 V 12.5 MHz to 80 MHz ⎯ 45 ⎯ ZOR REFOUT 12.5 MHz to 50 MHz ⎯ 70 ⎯ Input capacitance CIN Ta = + 25 °C XIN, SEL, VDD = VI = 0.0 V ENS/XPD f = 1 MHz ⎯ ⎯ 16 pF Input pull-up resistor RPU VIL = 0.0 V 25 50 200 kΩ REFOUT 12.5 MHz to 50 MHz ⎯ ⎯ 15 12.5 MHz to 50 MHz ⎯ ⎯ 15 50 MHz to 80 MHz ⎯ ⎯ 7 Power supply current VOHC VOHR Output voltage Output impedance Load capacitance 12 Conditions CKOUT “H” level output IOH = − 4 mA “H” level output REFOUT IOH = − 3 mA VOLC CKOUT “L” level output IOL = 4 mA VOLR REFOUT “L” level output IOL = 3 mA ZOC CKOUT CL ENS CKOUT Ω pF MB88155 • AC Characteristics Parameter Oscillation frequency Input frequency Symbol Pin fx XIN, XOUT fin XIN (Ta = − 40 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Value Conditions Unit Min Typ Max 12.5 ⎯ 40 40 ⎯ 48 MB88155 − 1x0, 1x2 12.5 ⎯ 25 MB88155 − 1x1, 1x3 25 ⎯ 50 MB88155 − 4xx 12.5 ⎯ 20 MB88155 − 1x0, 1x2 12.5 ⎯ 25 25 ⎯ 50 MB88155 − 4xx 12.5 ⎯ 20 MB88155 − 1x0, 1x2 12.5 ⎯ 25 Fundamental oscillation rd 3 overtone REFOUT MB88155 − 1x1, 1x3 Output frequency fOUT CKOUT MB88155 − 1x1, 1x3 SRc Output slew rate SRR Output clock duty cycle Modulation frequency Lock-up time*2 Cycle-cycle jitter tDCC tDCR fMOD tLK tJC 25 ⎯ 50 MB88155 − 4xx 50 ⎯ 80 Load capacitance 15 pF, 0.4 V to 2.4 V 0.4 ⎯ 4.0 Load capacitance 15 pF, REFOUT 0.4 V to 2.4 V 0.3 CKOUT MHz MHz MHz V/ns ⎯ 2.0 ⎯ 60 ⎯ tDCI + 10*1 ⎯ 32.4 ⎯ kHz ⎯ ⎯ 2 5 ms MB88155 − 1xx Input frequency 12.5 MHz to 20 MHz, No load capacitance, Ta = + 25 °C, VDD = 3.3 V, Standard deviation σ ⎯ ⎯ 150 ps MB88155 − 1xx Input frequency CKOUT 20 MHz to 50 MHz, No load capacitance, Ta = + 25 °C, VDD = 3.3 V, Standard deviation σ ⎯ ⎯ 100 ps MB88155 − 4xx No load capacitance, Ta = + 25 °C, VDD = 3.3 V, Standard deviation σ ⎯ ⎯ 200 ps CKOUT 1.5 V reference level 40 REFOUT 1.5 V reference level tDCI − 10* CKOUT Input frequency at 24 MHz CKOUT 1 % *1 : Duty of the REFOUT output is guaranteed only for the following A and B because it depends on tDCI of input clock duty. A. Resonator input : When resonator is connected with XIN pin and XOUT pin, and oscillates normally. B. External clock input : The input level is Full-swing (VSS − VDD). *2 : The modulation clock requires stabilization wait time after the IC is turned on or released from power-down mode, or after SEL (modulation factor) or ENS (modulation enable) setting is changed. For the modulation clock stabilization wait time, assure the maximum value for the lock-up time. 13 MB88155 ■ OUTPUT CLOCK DUTY CYCLE (tDCC, tDCR = tb/ta) ta tb 1.5 V CKOUT, REFOUT ■ INPUT FREQUENCY (fin = 1/tin) tin 0.8 VDD XIN ■ OUTPUT SLEW RATE (SRC, SRR) 2.4 V CKOUT, REFOUT 0.4 V tr tf Note : SRC = (2.4 − 0.4) /tr, SRC = (2.4 − 0.4) /tf SRR = (2.4 − 0.4) /tr, SRR = (2.4 − 0.4) /tf ■ CYCLE-CYCLE JITTER (tJC = |tn − tn + 1| ) CKOUT tn tn+1 Note : Cycle-cycle jitter indicates the difference between a certain cycle and the immediately succeeding (or preceding) cycle. 14 MB88155 ■ MODULATION WAVEFORM • Modulation rate ± 1.0%, example of center spread CKOUT output frequency + 1.0 % Frequency at modulation off Time − 1.0 % fMOD (Typ) = 32.4 kHz (fin = 24 MHz) • Modulation rate − 1.0%, example of down spread CKOUT output frequency Frequency at modulation off Time − 0.5 % − 1.0 % fMOD (Typ) = 32.4 kHz (fin = 24 MHz) 15 MB88155 ■ LOCK-UP TIME VDD 3.0 V External clock stabilization waiting time XIN XPD SEL ENS VIH VIH tLK (Lock-up time) CKOUT If the XPD pin is fixed at the “H” level, the maximum time after the power is turned on until the set clock signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time “tLK”). For the input clock stabilization time, check the characteristics of the resonator or oscillator used. VDD 3.0 V External clock stabilization waiting time XIN VIH XPD SEL ENS VIH tLK (Lock-up time) CKOUT If the XPD pin is used for power-down control, the set clock signal is output from the CKOUT pin at most the lockup time “tLK” after the XPD pin goes “H” level. (Continued) 16 MB88155 (Continued) XIN ENS VIH VIL tLK (Lock-up time) tLK (Lock-up time) CKOUT If the ENS pin is used for modulation enable control during normal operation, the set clock signal is output from the CKOUT pin at most the lock-up time “tLK” after the level at the ENS pin is determined. Note : The wait time for the clock signal output from the CKOUT pin to become stable is required after the IC is released from power-down mode by the XPD pin or after another pin’s setting is changed. During the period until the output clock signal becomes stable, neither of the output frequency, output clock duty cycle, modulation period, and cycle-cycle jitter characteristic cannot be guaranteed. It is therefore advisable to take action, such as cancelling a device reset at the stage after the lock-up time has passed. 17 MB88155 ■ OSCILLATION CIRCUIT The following schematic on the left-hand side shows a sample connection of a general resonator. The oscillation circuit contains a feedback resistor (1 MΩ) . The values of capacitors (C1 and C2) must be adjusted to the optimum constant of the resonator used. The following schematic on the right-hand side shows a sample connection of a 3rd overtone resonator. The values of capacitors (C1, C2, and C3) and inductor (L1) must be adjusted to the optimum constant of the resonator used. The most suitable value is different by individual resonator. Please refer to the resonator manufacturer which you use for the most suitable value. To use an external clock signal (without using the resonator) , input the clock signal to the XIN pin with the XOUT pin connected to nothing . • When using the resonator LSI internal Rf (1 MΩ) Rf (1 MΩ) XIN pin XOUT pin XOUT pin XIN pin LSI external L1 C2 C1 C2 C1 C3 Fundamental resonator 3rd overtone resonator • When using the external clock LSI internal Rf (1 MΩ) XOUT pin XIN pin LSI external External clock OPEN Note : 18 Note that the jitter characteristic of the input clock signal may affect the cycle-cycle jitter characteristic. MB88155 ■ INTERCONNECTION CIRCUIT EXAMPLE 1 8 2 7 R1 MB88155 C1 3 6 4 5 C2 R2 C4 C3 C1, C2 : Oscillation stabilization capacitance (refer to “■ OSCILLATION CIRCUIT”) C3 : Capacitor of 10 µF or higher C4 : Capacitor of about 0.01 µF (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device) R1, R2 : Impedance matching resistor for board pattern 19 MB88155 ■ SPECTRUM EXAMPLE CHARACTERISTICS The condition of the examples of the characteristic is shown as follows : Input frequency = 16 MHz (Output frequency = 64 MHz : Using MB88155-410 (Multiplied by 4) ) Power-supply voltage = 3.3 V, None load capacity. Modulation rate = ± 1.0% (center spread). Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW = 1 kHz (ATT use for −6 dB) . CH B Spectrum 10 dB /REF 0 dBm No modulation −5.64 dBm Avg 4 ±1.0% modulation −26.93 dBm RBW# 1 kHZ VBW 1 kHZ CENTER 64 MHZ 20 ATT 6 dB SWP 8.005 s SPAN 12.8 MHZ MB88155 ■ ORDERING INFORMATION Part number Power Input Multiplica- Output Modulation Modulation enable down tion rate frequency type frequency pin pin MB88155PFTG-100-JNE1 12.5 MHz to 25 MHz MB88155PFTG-101-JNE1 25 MHz to 50 MHz MB88155PFTG-102-JNE1 12.5 MHz to 25 MHz MB88155PFTG-103-JNE1 25 MHz to 50 MHz MB88155PFTG-110-JNE1 The same Multiplied as input by 1 12.5 MHz to frequency 25 MHz MB88155PFTG-111-JNE1 25 MHz to 50 MHz MB88155PFTG-112-JNE1 12.5 MHz to 25 MHz MB88155PFTG-113-JNE1 25 MHz to 50 MHz MB88155PFTG-400-JNE1 MB88155PFTG-402-JNE1 MB88155PFTG-410-JNE1 Center spread MB88155PFT- 12.5 MHz to G-100-JN-EFE1 25 MHz The same Multiplied as input by 1 MB88155PFT- 12.5 MHz to frequency G-102-JN-EFE1 25 MHz MB88155PFT- 25 MHz to G-103-JN-EFE1 50 MHz No Yes Yes No 8-pin plastic TSSOP (FPT-8P-M07) Center spread 12.5 MHz to Multiplied 50 MHz to 20 MHz by 4 80 MHz MB88155PFT- 25 MHz to G-101-JN-EFE1 50 MHz No Remarks Down spread Down spread MB88155PFTG-412-JNE1 Yes Package No Yes Yes No No Yes Yes No No Yes Yes No 8-pin plastic Emboss TSSOP taping (FPT-8P-M07) (EF type) Down spread No Yes 21 MB88155 Part number Power Input Multiplica- Output Modulation Modulation enable down type frequency tion rate frequency pin pin MB88155PFT- 12.5 MHz to G-110-JN-EFE1 25 MHz MB88155PFT- 25 MHz to G-111-JN-EFE1 50 MHz The same Multiplied as input by 1 MB88155PFT- 12.5 MHz to frequency G-112-JN-EFE1 25 MHz Yes MB88155PFTG-400-JN-EFE1 MB88155PFTG-402-JN-EFE1 12.5 MHz to Multiplied 50 MHz to by 4 80 MHz MB88155PFT- 20 MHz G-410-JN-EFE1 MB88155PFTG-412-JN-EFE1 Down spread Center spread MB88155PFT- 12.5 MHz to G-100-JN-ERE1 25 MHz MB88155PFT- 25 MHz to G-101-JN-ERE1 50 MHz MB88155PFT- 12.5 MHz to G-102-JN-ERE1 25 MHz The same Multiplied as input by 1 MB88155PFT- 12.5 MHz to frequency G-110-JN-ERE1 25 MHz MB88155PFT- 12.5 MHz to G-112-JN-ERE1 25 MHz MB88155PFTG-402-JN-ERE1 12.5 MHz to Multiplied 50 MHz to by 4 80 MHz MB88155PFT- 20 MHz G-410-JN-ERE1 MB88155PFTG-412-JN-ERE1 22 No Yes Yes No No Yes Yes No No Yes Yes No No Yes Yes No 8-pin plastic Emboss TSSOP taping (FPT-8P-M07) (EF type) 8-pin plastic Emboss TSSOP taping (FPT-8P-M07) (ER type) Center spread MB88155PFT- 25 MHz to G-113-JN-ERE1 50 MHz MB88155PFTG-400-JN-ERE1 8-pin plastic Emboss TSSOP taping (FPT-8P-M07) (EF type) Down spread MB88155PFT- 25 MHz to G-103-JN-ERE1 50 MHz MB88155PFT- 25 MHz to G-111-JN-ERE1 50 MHz Remarks No Center spread MB88155PFT- 25 MHz to G-113-JN-EFE1 50 MHz Package Down spread Center spread No Yes Yes No No Yes Yes No No Yes MB88155 ■ PACKAGE DIMENSIONS 8-pin plastic TSSOP Lead pitch 0.65 mm Package width × package length 4.40 mm × 3.10 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm Max (FPT-8P-M07) 8-pin plastic TSSOP (FPT-8P-M07) Note) Pins width and pins thickness include plating thickness. 0.127±0.08 (.0050±.003) 3.10±0.10(.122±.004) 8 5 4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part 1.20(.047)MAX 4 1 "A" 0.65(.026) 0.22±0.10 (.009±.004) TYP 0~8˚ 0.50(.020) NOM 0.60±0.10 (.024±.004) 0.10±0.05 (Stand off) (.004±.002) 0.25(.010) 0.10(.004) 1.95(.077) REF C 2006 FUJITSU LIMITED F08015Sc-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 23 MB88155 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0611