ISSI IS27HC010 ISSI IS27HC010 131,072 x 8 HIGH-SPEED CMOS EPROM FEATURES • Fast read access time: 30 ns • Pin compatible with the IS27C010 • High-speed write programming — Typically less than 30 seconds • Industrial and commercial temperature ranges available • ±10% power supply tolerance • JEDEC-approved pinout • Standard 32-pin DIP, PLCC, and TSOP packages ® ® JULY 1997 DESCRIPTION The ISSI IS27HC010 is an ultra-high-speed 1 megabit (128Kword by 8-bit) Ultraviolet Erasable CMOS Programmable Read-Only Memory. It utilizes the standard JEDEC pinout making it functionally compatible with the IS27C010, but with significantly faster access capability. This superior random access capability results from a focused high-speed design. This offers users bipolar speeds with higher density, lower cost, and proven reliability. The device is ideal for use with the faster processors. Designers may take full advantage of high-speed digital signal processors and microprocessors by allowing code to be executed at full speed directly out of EPROM. Typical applications include laser printers, switching networks, graphics, workstations, high-speed modems, and digital signal processing. The IS27HC010 uses ISSI's write programming algorithm which allows the entire chip to be programmed in typically less than 30 seconds. This product is available inOne-Time Programmable (OTP) PDIP, PLCC, and TSOP packages over commercial and industrial temperature ranges. FUNCTIONAL BLOCK DIAGRAM VCC GND VPP DQ0-DQ7 8 OE OUTPUT ENABLE CHIP ENABLE AND PROG LOGIC CE PGM Y DECODER A0-A16 OUTPUT BUFFERS Y GATING 17 X DECODER 1,048,576-BIT CELL MATRIX ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. EP009-1F 07/18/97 1 ISSI IS27HC010 ® PIN CONFIGURATIONS 32-Pin DIP PIN DESCRIPTIONS Address Inputs CE (E) Chip Enable Input DQ0-DQ7 Data Inputs/Outputs 1 32 VCC A16 2 31 PGM (P) A15 3 30 NC A12 4 29 A14 A7 5 28 A13 OE (G) PGM (P) A6 6 27 A8 Vcc Power Supply Voltage A5 7 26 A9 A4 8 25 A11 VPP Program Supply Voltage A3 9 24 OE (G) GND Ground A2 10 23 A10 NC No Internal Connection A1 11 22 CE (E) A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 GND 16 17 DQ3 A12 A15 A16 VPP VCC PGM (P) NC INDEX Output Enable Input Program Enable Input 32-Pin TSOP 32-Pin PLCC 4 3 2 1 32 31 30 A13 A5 7 27 A8 A4 8 26 A9 A3 9 25 A11 A2 10 24 OE (G) A1 11 23 A10 A0 12 22 CE (E) DQ0 13 21 DQ7 14 15 16 17 18 19 20 DQ6 28 DQ5 6 DQ4 A6 DQ3 A14 GND 29 DQ2 5 DQ1 A7 2 A0-A16 VPP A11 A9 A8 A13 A14 NC PGM (P) VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE (G) A10 CE (E) DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 Integrated Silicon Solution, Inc. EP009-1F 07/18/97 IS27HC010 ISSI ® FUNCTIONAL DESCRIPTION Erasing the IS27HC010 In order to clear all locations of their programmed contents, it is necessary to expose the IS27HC010 to an ultraviolet light source. A dosage of 30W - sec/cm2 is required to completely erase the IS27HC010. This dosage can be obtained by exposure to an ultraviolet lamp-wavelength of 2537 Angstroms (Å)—with intensity of 12,000 µW/cm2 for 30 to 40 minutes. The IS27HC010 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the IS27HC010, and similar devices, will erase with light sources having wavelengths shorter than 4000Å. The exposure to fluorescent light and sunlight will eventually erase the IS27HC010 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the IS27HC010 Upon delivery, or after each erasure, the IS27HC010 has 1,048,576 bits in the "ONE", or HIGH state. "ZEROs" are loaded into the IS27HC010 through the procedure of programming. The programming mode is entered when 12.75 ± 0.25V is applied to the VPP pin, VCC = 6.25V, CE and PGM is at VIL, and OE is at VIH. For programming, the data to be programmed is applied eight bits in parallel to the data output pins. The write programming algorithm reduces programming time by using 100 µs programming pulses followed by a byte verification to determine whether the byte has been successfully programmed. If the data does not verify, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the EPROM. The write programming algorithm programs and verifies at VCC = 6.25V and VPP = 12.75V. After the final address is completed, all byte are compared to the original data with VCC = 5.25V. Program Inhibit Programming of multiple IS27HC010s in parallel with different data is also easily accomplished. Except for CE, all like inputs of the parallel IS27HC010 may be common. A TTL low-level program pulse applied to an IS27HC010 CE input with VPP = 12.75 ± 0.25V, PGM LOW and OE HIGH will program that IS27HC010. A high-level CE input inhibits the other IS27HC010 from being programmed. Integrated Silicon Solution, Inc. EP009-1F 07/18/97 Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE and CE at VIL, PGM at VIH, and VPP between 12.5V and 13.0V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the IS27HC010. To activate this mode, the programming equipment must force 12.0 ± 0.5V on address line A9 of the IS27HC010. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto select mode. Byte 0 (A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the IS27HC010, these two identifier bytes are given in the Mode Select table. All identifiers manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The IS27HC010 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Output Enable (OE) is the output control and should be used to get data to the output pins, independent of device selection. Data is available at the outputs tOE after the falling edge of OE assuming that CE has been LOW and addresses have been stable for at least tACC – tOE. Standby Mode The IS27HC010 has a standby mode which reduces the maximum VCC active current. It is placed in standby mode when CE is at VIH. The amount of current drawn in standby mode depends on the frequency and the number of address pins switching. The IS27HC010 is specified with 50% of the address lines toggling at 10 MHz. A reduction of the frequency or quantity of address lines toggling will significantly reduce the actual standby current. 3 ISSI IS27HC010 Output OR-Tieing To accommodate multiple memory connections, a twoline control function is provided to allow for: 1. Low memory power dissipation, and 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. ® System Applications During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device at a minimum, a 0.1 µF ceramic capacitor (high-frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. TRUTH TABLE(1,2) Mode CE OE PGM A0 A9 VPP Outputs Read Output Disable Standby Program Program Verify Program Inhibit Auto Select(3,5) Manufacturer Code Device Code VIL VIL VIH VIL VIL VIH VIL VIL VIL VIH X VIH VIL X VIL VIL X X X VIL VIH X X X X X X X X X VIL VIH X X X X X X VH VH VCC VCC VCC VPP VPP VPP VCC VCC DOUT Hi-Z Hi-Z DIN DOUT Hi-Z D5H 0EH Notes: 1. VH = 12.0V ± 0.5V. 2. X = Either VIH or VIL. 3. A1-A8 = A10-A16 = VIL. 4. See DC Programming Characteristics for VPP voltage during programming. 5. The IS27HC010 can use the same write algorithm during program as other IS27C010 or IS27010 devices. LOGIC SYMBOL 17 A0-A16 8 DQ0-DQ7 CE (E) PGM (P) OE (G) 4 Integrated Silicon Solution, Inc. EP009-1F 07/18/97 ISSI IS27HC010 ® ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TA TSTG TSTG Parameter Terminal Voltage with Respect to GND All pins except A9 and VPP VPP A9 VCC Ambient Temperature with Power Applied Storage Temperature (OTP) Storage Temperature (All others) Value Unit –0.6 to VCC + 0.5(2) VCC – 0.3 to 13.5(2,3) –0.6 to 13.5(2,3) –0.6 to 7.0(2) –65 to +125 –65 to +125 –65 to +150 V V V V °C °C °C Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods less than 10 ns. Maximum DC voltage on output pins is VCC + 0.5V which may overshoot to VCC + 2.0V for periods less than 10 ns. 3. Maximum DC voltage on A9 or VPP may overshoot to +13.5V for periods less than 10 ns. OPERATING RANGE Range Commercial Industrial(1) Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% Note: 1. Operating ranges define those limits between which the functionally of the device is guaranteed. DC ELECTRICAL CHARACTERISTICS(1,2,3) (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 12 mA — 0.45 V 2.0 VCC + 0.5 V –0.3 0.8 V (4) VIH Input HIGH Voltage VIL Input LOW Voltage(4) ILI Input Load Current VIN = 0V to +VCC — 5.0 µA ILO Output Leakage Current VOUT = 0V to +VCC — 10 µA Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. Never try to force VPP LOW to 1V below VCC. Manufacturer suggests to tie VPP and Vcc together during the READ operation. 2. Caution: the IS27HC010 must not be removed from (or inserted into) a socket when VCC or VPP is applied. 3. Minimum DC input voltage is –0.5V. During transitions, the inputs may undershoot to –2.0V for periods less than 10 ns. Maximum DC voltage on output pins is VCC + 0.5V which may overshoot to VCC + 2.0V for periods less than 10 ns. 4. Tested under static DC conditions. Integrated Silicon Solution, Inc. EP009-1F 07/18/97 5 ISSI IS27HC010 ® POWER SUPPLY CHARACTERISTICS(1,2,5) (Over Operating Range) Symbol Parameter Test Conditions ICC1 Vcc Operating Supply Current(3) VCC = Max., CE = VIL IOUT = 0 mA, f = 10 MHz (Open outputs) IPP1 VPP Current During Read(4) VCC = Max., CE = OE = VIL VPP = VCC ICCSB0 Vcc CMOS Standby Current CE ≥ VCC – 0.3V All pins ≥ VCC – 0.3V or ≤ 0.3V toggling f ≤ 10 MHz ICCSB1 Vcc TTL Standby Current CE ≥ VIH All pins = VIH or VIL (TTL Level) toggling f ≤ 10 MHz Commercial Industrial Min. Max. Unit — — 75 90 mA — 1.0 µA — 20 mA — 35 mA Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. Never try to force VPP LOW to 1V below VCC. Manufacturer suggests to tie VPP and Vcc together during the READ operation. 2. Caution: the IS27HC010 must not be removed from (or inserted into) a socket when VCC or VPP is applied. 3. ICC1 is tested with OE = VIH to simulate open outputs. 4. Maximum active power usage is the sum of ICC and IPP. 5. Minimum DC input voltage is –0.5V. During transitions, the inputs may undershoot to –2.0V for periods less than 10 ns. Maximum DC voltage on output pins is VCC + 0.5V which may overshoot to VCC + 2.0V for periods less than 10 ns. CAPACITANCE(1,2,3) DIP Symbol Parameter CIN1 Address Input Capacitance CIN3 OE Input Capacitance CE Input Capacitance COUT Output Capacitance CIN2 PLCC/TSOP Typ. Max. Conditions Typ. Max. Unit VIN = 0V 6 10 6 9 pF VIN = 0V 10 10 7 9 pF VIN = 0V 10 10 7 9 pF VOUT = 0V 8 12 6 9 pF Notes: 1. Typical values are for nominal supply voltage. 2. This parameter is only sampled, but not 100% tested. 3. Test conditions: TA = 25°C, f = 1 MHz. SWITCHING TEST WAVEFORM SWITCHING TEST CIRCUIT 3V Device Under Test CL1 = 30 pF CL2 = 5 pF OUT CL RL = 121Ω 1.5V 0V INPUT TEST POINTS 1.5V OUTPUT VL = 1.9V Notes: AC Testing: 1. Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". 2. Input pulse rise and fall skew rate ≥ 1.5V/ns. 6 Integrated Silicon Solution, Inc. EP009-1F 07/18/97 ISSI IS27HC010 ® SWITCHING CHARACTERISTICS(1,3,4) (Over Operating Range) JEDEC Symbol Std. Symbol tAVQA tACC tELQV tGLQV tCE tOE -30 Parameter Test Conditions Address to Output Delay -45 -70 Min. Max. Min. Max. Min. Max. Unit CE = OE = VIL — 30 — 45 — 70 ns OE = VIL — 30 — 45 — 70 ns CE = VIL — 10 — 20 — 35 ns CL = CL2 0 10 0 20 0 35 ns 0 — 0 — 0 — ns CL = CL1 Chip Enable to Output Delay CL = CL1 Output Enable to Output Delay CL = CL1 tEHOZ, tGHQZ tDF(2) Chip Enable HIGH or Output Enable HIGH, whichever comes first, to Output Float tAVOX tOH Output Hold from Address, CE or OE whichever occured first Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. This parameter is only sampled, not 100% tested. 3. Caution: The IS27HC010 must not be removed from (or inserted into) a socket or board when VPP or VCC applied. 4. Output Load: 1 TTL gate and C = CL. Input Rise and Fall times: 2 ns. Input Pulse Levels: 0 to 3V. Timing Measurement Reference Level: 1.5V for inputs and outputs. SWITCHING WAVEFORMS 3V ADDRESS 1.5V 1.5V ADDRESS VALID 0V CE tCE OE tDF(2) tOE OUTPUT tACC Hi-Z (1) tOH VALID OUTPUT Hi-Z Notes: 1. OE may be delayed up to tACC – tOE after the falling edge of CE without impact on tACC. 2. tDF is specified from OE or CE, whichever occurs first. Integrated Silicon Solution, Inc. EP009-1F 07/18/97 7 ISSI IS27HC010 ® DC PROGRAMMING CHARACTERISTICS(1,2,3,4) (TA = +25°C ± 5°C) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage During Verify IOH = –400 µA 2.4 — V VOL Output LOW Voltage During Verify IOL = 2.1 mA — 0.45 V VIH Input HIGH Voltage 2.0 VCC + 0.5 V VIL Input LOW Voltage (All Inputs) –0.3 0.8 V VH A9 Auto Select Voltage 11.5 12.5 V ILI Input Current (All Inputs) — 10.0 µA ICC VCC Supply Current (Program & Verify) — 50 mA IPP VPP Supply Current — 30 mA VCC Supply Voltage 6.0 6.5 V VPP Programming Voltage 12.5 13.0 V VIN = VIL or VIH CE = VIL, OE = VIH SWITCH PROGRAMMING CHARACTERISTICS(1,2,3,4) (TA = +25°C ± 5°C) JEDEC Symbol Std. Symbol tAVEL tAS tDZGL Parameter Min. Max. Unit Address Setup Time 2 — µs tOES OE Setup Time 2 — µs tDVEL tDS Data Setup Time 2 — µs tGHAX tAH Address Hold Time 0 — µs tEHDX tDH Data Hold Time 2 — µs tGHQZ tDFP OE HIGH to Output Float Delay 0 130 ns tVPS tVPS VPP Setup Time 2 — µs tELEH1 tPW PGM Program Pulse Width 95 105 µs tVCS tVCS VCC Setup Time 2 — µs tELPL tCES CE Setup Time 2 — µs tGLQV tOE — 150 ns Data Valid from OE Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. VPP must be ≥ VCC during the entire programming and verifying procedure. 3. When programming IS27HC010, a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage transients which may damage the device. 4. Programming characteristics are sampled but not 100% tested at worst-case conditions. 8 Integrated Silicon Solution, Inc. EP009-1F 07/18/97 ISSI IS27HC010 ® PROGRAMMING ALGORITHM WAVEFORM(1,2) PROGRAM VERIFY PROGRAM ADDRESS tAS DATA tAH Hi-Z DATAIN STABLE tDS 12.75V tVPS 6.0V-6.5V DATAOUT VALID tDFP tDH VPP ≥Vcc–0.3V VCC 5V±10% tVCS CE tCES PGM OE tPW tOES tOE Max Notes: 1. The timing reference level is 1.5V for inputs and outputs. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. Integrated Silicon Solution, Inc. EP009-1F 07/18/97 9 ISSI IS27HC010 ® PROGRAMMING FLOW CHART Start Address = First Location Vcc = 6.25V VPP = 12.75V X=0 Interactive programming Section Program One 100 µs Pulse Increment X Yes X = 25? No Fail Verify Byte Pass Increment Address No Last Address? Yes Vcc = VPP = 5.25V Verify Section Fail Verify All Bytes Device Failed Pass Device Passed 10 Integrated Silicon Solution, Inc. EP009-1F 07/18/97 ISSI IS27HC010 ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part Number Package 30 IS27HC010-30W IS27HC010-30PL IS27HC010-30T 600-mil Plastic DIP PLCC – Plastic Leaded Chip Carrier TSOP 45 IS27HC010-45W IS27HC010-45PL IS27HC010-45T 600-mil Plastic DIP PLCC – Plastic Leaded Chip Carrier TSOP 70 IS27HC010-70W IS27HC010-70PL IS27HC010-70T 600-mil Plastic DIP PLCC – Plastic Leaded Chip Carrier TSOP ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part Number Package 30 IS27HC010-30PLI IS27HC010-30TI PLCC – Plastic Leaded Chip Carrier TSOP 45 IS27HC010-45PLI IS27HC010-45TI PLCC – Plastic Leaded Chip Carrier TSOP 70 IS27HC010-70PLI IS27HC010-70TI PLCC – Plastic Leaded Chip Carrier TSOP ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Fax: (408) 588-0806 Toll Free: 1-800-379-4774 http://www.issiusa.com Integrated Silicon Solution, Inc. EP009-1F 07/18/97 11