Freescale MC68HC805P18CP Advance information Datasheet

Freescale Semiconductor, Inc.
MC68HC05P18
MC68HC805P18
Advance Information
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Specifications and information herein are subject to change without notice.
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A G R E E M E N T
HC05
N O N - D I S C L O S U R E
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MC68HC805P18/D
Rev. 2.0
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N O N - D I S C L O S U R E
A G R E E M E N T
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R E Q U I R E D
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Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
© Motorola, Inc., 1999
Advance Information
MC68HC(8)05P18 — Rev. 2.0
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Advance Information — MC68HC05P18/MC68HC805P18
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 17
Freescale Semiconductor, Inc...
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Section 3. Central Processing Unit (CPU) . . . . . . . . . . . 35
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Section 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . 53
Section 7. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . 63
Section 8. EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Section 9. Analog-to-Digital (A/D) Converter . . . . . . . . . 79
Section 10. 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Section 11. Serial Input/Output Port (SIOP) . . . . . . . . . . 99
Section 12. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 107
Section 13. Electrical Specifications . . . . . . . . . . . . . . . 123
Section 14. Mechanical Specifications . . . . . . . . . . . . . 133
Section 15. Ordering Information . . . . . . . . . . . . . . . . . 135
Appendix A. Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . 137
MC68HC(8)05P18 — Rev. 2.0
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List of Sections
Advance Information
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MC68HC(8)05P18 — Rev. 2.0
List of Sections
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Advance Information — MC68HC05P18/MC68HC805P18
Table of Contents
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Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.3
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.5.3.1
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.5.3.2
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.5.4
Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.5
Port A (PA0–PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.6
Port B (PB5/SDO, PB6/SDI, and PB7/SCK) . . . . . . . . . . . .24
1.5.7
Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1,
PC6/AD0, and PC7/VREFH) . . . . . . . . . . . . . . . . . . . . . . .24
1.5.8
Port D (PD5/CKOUT and PD7/TCAP) . . . . . . . . . . . . . . . . .24
1.5.9
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.10 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . .25
Section 2. Memory
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3
Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . .27
2.4
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.5
ROM (MC68HC05P18 Only) . . . . . . . . . . . . . . . . . . . . . . . . . .34
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2.6
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.7
User EEPROM (MC68HC805P18 Only). . . . . . . . . . . . . . . . . .34
Section 3. Central Processing Unit (CPU)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
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3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.3.1
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.2
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.3
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .37
3.3.3.1
Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.3.2
Interrupt (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.3.3
Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.3.3.4
Zero (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.3.3.5
Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.3.4
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.3.5
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Section 4. Interrupts
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.3
Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3.1
Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3.2
Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3.3
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3.3.1
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.3.3.2
Optional External Interrupts (PA0–PA7) . . . . . . . . . . . . .46
4.3.3.3
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.3.3.4
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .47
4.3.3.5
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .47
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Section 5. Resets
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.3
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
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5.4
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.4.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.4.2
Computer Operating Properly (COP) Reset . . . . . . . . . . . . .51
5.4.3
Low-Voltage Reset (LVR). . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 6. Operating Modes
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.3
User Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.3.1
User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.3.2
Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6.3.2.1
Bulk Erase/Blank Verify . . . . . . . . . . . . . . . . . . . . . . . . . .55
6.3.2.2
Bulk Erase/Program Verify. . . . . . . . . . . . . . . . . . . . . . . .57
6.4
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6.5
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.5.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.5.2
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.5.3
WAIT Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.6
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .61
Section 7. Input/Output (I/O) Ports
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
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7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
7.7
I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
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Section 8. EEPROM
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
8.3
EEPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . .72
8.4
Programming/Erasing Procedures . . . . . . . . . . . . . . . . . . . . . .74
8.5
Mask Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Section 9. Analog-to-Digital (A/D) Converter
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.3
Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.1
Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.2
VREFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.3
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.4
Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.4
Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
9.4.1
Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
9.4.2
Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . .81
9.4.3
Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.5
A/D Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . .82
9.6
A/D Conversion Data Register . . . . . . . . . . . . . . . . . . . . . . . . .84
9.7
A/D Subsystem During Wait/Halt Modes . . . . . . . . . . . . . . . . .84
9.8
A/D Subsystem Operation During Stop Mode . . . . . . . . . . . . .84
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Section 10. 16-Bit Timer
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
10.3
Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10.4
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
10.5
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
10.6
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
10.7
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.8
Timer Operation During Wait and Halt Modes . . . . . . . . . . . . .97
10.9
Timer Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . .97
Section 11. Serial Input/Output Port (SIOP)
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
11.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . .102
11.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.4.1 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.4.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
11.4.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Section 12. Instruction Set
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
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12.3.4
12.3.5
12.3.6
12.3.7
12.3.8
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
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12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .111
12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .112
12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .112
12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .114
12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
12.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
12.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Section 13. Electrical Specifications
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
13.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
13.4
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .124
13.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
13.6
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
13.7
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .126
13.8
Active Reset Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .127
13.9
A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . .127
13.10 SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
13.11 PD5 Clock Out Timing (PD5 CLKOUT Option Enabled) . . . .129
13.12 Control Timing (MC68HC805P18
and Low-Speed MC68HC05P18) . . . . . . . . . . . . . . . . . . .130
13.13 Control Timing (High-Speed MC68HC05P18 Only) . . . . . . . .130
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Table of Contents
Section 14. Mechanical Specifications
14.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
14.3
28-Pin Dual In-Line Package (Case #710) . . . . . . . . . . . . . . .134
14.4
28-Pin Small Outline Package (Case #751F) . . . . . . . . . . . . .134
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Section 15. Ordering Information
15.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
15.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Appendix A. Emulation
A.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.3
Functional Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.4
Mask Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
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List of Figures
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Figure
Title
1-1
1-2
1-3
MC68HC05P18/MC68HC805P18 Block Diagram . . . . . . . . . .19
User Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2-1
2-2
2-3
2-4
MC68HC05P18 User Mode Memory Map . . . . . . . . . . . . . . . .28
MC68HC805P18 User Mode Memory Map . . . . . . . . . . . . . . .29
I/O and Control Registers Memory Map . . . . . . . . . . . . . . . . . .30
I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3-1
3-2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4-1
4-2
Interrupt Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . .44
IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .45
5-1
5-2
Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Unimplemented Vector and COP Watchdog
Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6-1
6-2
Bootloader Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
STOP/WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
7-1
7-2
7-3
7-4
Port A I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Port C I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Port D I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
8-1
8-2
EEPROM Programming Register (EEPROG) . . . . . . . . . . . . .72
Mask Option Register 1 (MOR1) . . . . . . . . . . . . . . . . . . . . . . .75
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Figure
Title
Page
8-3
Mask Option Register 2 (MOR2) . . . . . . . . . . . . . . . . . . . . . . .75
9-1
9-2
A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . .82
A/D Conversion Data Register (ADC). . . . . . . . . . . . . . . . . . . .84
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
16-Bit Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Timer Registers (TMRH/TMRL) . . . . . . . . . . . . . . . . . . . . . . . .88
Alternate Counter Registers (ACRH/ACRL) . . . . . . . . . . . . . . .88
State Timing Diagram for Timer Overflow . . . . . . . . . . . . . . . .89
State Timing Diagram for Timer Reset . . . . . . . . . . . . . . . . . . .90
Output Compare Registers (OCRH/OCRL) . . . . . . . . . . . . . . .90
Output Compare Software Initialization Example . . . . . . . . . . .92
Input Compare Registers (ICRH/ICRL) . . . . . . . . . . . . . . . . . .93
State Timing Diagram for Input Capture . . . . . . . . . . . . . . . . . .94
Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . .94
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . .96
11-1
11-2
11-3
11-4
11-5
SIOP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . .102
SIOP Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . .104
SIOP Data Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . .105
13-1 SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
13-2 PD5 Clock Out Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
13-3 Power-On Reset and External Reset Timing Diagram . . . . . .131
A-1
A-2
A-3
A-4
A-5
MC68HC705P3 Mask Option Register . . . . . . . . . . . . . . . . . .141
MC68HC705P6 Mask Option Register . . . . . . . . . . . . . . . . . .141
MC68HC705P9 Mask Option Register . . . . . . . . . . . . . . . . . .141
MC68HC805P8 Mask Option Register 1 . . . . . . . . . . . . . . . .142
MC68HC805P8 Mask Option Register 2 . . . . . . . . . . . . . . . .142
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Table
Title
Page
4-1
Vector Addresses for Interrupts and Reset. . . . . . . . . . . . . . . .42
6-1
6-2
6-3
Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
COP Watchdog Timer Recommendations . . . . . . . . . . . . . . . .61
7-1
7-2
7-3
7-4
Port A I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Port B I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Port C I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Port D I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
8-1
8-2
Erase Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SIOP Clock Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .76
9-1
A/D Multiplexer Input Channel Assignments . . . . . . . . . . . . . .83
12-1
12-2
12-3
12-4
12-5
12-6
12-7
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . .111
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .112
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .113
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .114
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
15-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
A-1
A-2
A-3
A-4
Elements of Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Memory Breakdown by Types . . . . . . . . . . . . . . . . . . . . . . . .139
P-Series Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
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List of Tables
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Section 1. General Description
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1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.3
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.5.4
Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.5
Port A (PA0–PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.6
Port B (PB5/SDO, PB6/SDI, and PB7/SCK) . . . . . . . . . . . .24
1.5.7
Port C (PC0–PC2, PC3/AD3, PC4/AD2,
PC5/AD1, PC6/AD0, and PC7/VREFH) . . . . . . . . . . . . . .24
1.5.8
Port D (PD5/CKOUT and PD7/TCAP) . . . . . . . . . . . . . . . . .24
1.5.9
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.10 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . .25
1.2 Introduction
The Motorola MC68HC05P18 and MC68HC805P18 microcontrollers
(MCU) are members of the M68HC05 Family with:
•
4-channel, 8-bit analog-to-digital (A/D) converter
•
16-bit timer with output compare and input capture
•
Serial input/output port (SIOP)
•
Computer operating properly (COP) watchdog timer
•
21 input/output (I/O) pins (20 bidirectional, one input-only)
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1.3 Features
Features include:
•
Low-cost M68HC05 core running at 2-MHz bus speed
•
28-pin dual in-line package (DIP) or small outline (SOIC) package
•
4-MHz on-chip crystal/ceramic resonator oscillator
•
MC68HC05P18:
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– 8064 bytes of user read-only memory (ROM)
– 48 bytes of page zero ROM
– 16 bytes of user vectors
•
MC68HC805P18:
– 8064 bytes of user electrically erasable, programmable
read-only memory (EEPROM)
– 48 bytes of page zero EEPROM
– 16 bytes of user vectors
•
192 bytes of on-chip random-access memory (RAM)
•
128 bytes of EEPROM
•
Low-voltage reset (LVR)
•
4-channel, 8-bit A/D converter
•
SIOP serial communications port
•
COP watchdog timer with active pulldown on RESET
•
16-bit timer with output compare and input capture
•
20 bidirectional I/O lines and one input-only line
•
High current sink and source on two I/O pins (PC0 and PC1)
See Figure 1-1 for a functional block diagram.
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General Description
Features
COP
PH2
CPU CONTROL
ALU
RESET
68HC05 CPU
IRQ
÷2
÷4
OSC 1
OSC
OSC 2
16-BIT TIMER
1 INPUT CAPTURE
1 OUTPUT COMPARE
PORT D LOGIC
PD7/TCAP
TCMP
PD5/CKOUT
ACCUMULATOR
PROGRAM COUNTER
COND CODE REG
1 1 1H I NZC
PC7/VREFH
PC6/AD0
MUX
A/ D CONVERTER
0 0 0 0 0 0 0 0 1 1 STK PNTR
PORT C
PC5/AD1
PC4/AD2
PC3/AD3
PC2
PC1
PC0
SRAM — 192 BYTES
PA7
EEPROM — 128 BYTES
PA6
PA5
PORT A
MC68HC05P18:
USER ROM — 8064 BYTES
MC68HC805P18:
USER EEPROM — 8064 BYTES
DATA DIRECTION REGISTER
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INDEX REGISTER
DATA DIRECTION REGISTER
CPU REGISTERS
PA4
PA3
PA2
PA1
PA0
PB5/SDO
PB6/SDI
PB7/SCK
PORT B AND
SIOP
REGISTERS
AND LOGIC
VDD
VSS
Figure 1-1. MC68HC05P18/MC68HC805P18 Block Diagram
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1.4 Mask Options
There are eight mask options on the MC68HC05P18 that are EEPROM
mask option register (MOR) selectable options for the MC68HC805P18.
For additional information, refer to 8.5 Mask Option Registers.
1. IRQ is edge- and level-sensitive or edge-sensitive only.
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2. SIOP most-significant bit (MSB) first or least-significant bit (LSB)
first
3. SIOP clock rate set to oscillator divided by 2, 4, 8, or 16
4. COP watchdog timer enabled or disabled
5. STOP instruction enabled or converted to halt mode
6. Option to enable clock output pin to replace PD5
7. Option to individually enable pullups/interrupts on each of the
eight port A pins
8. Low-voltage reset (LVR) enabled or disabled
NOTE:
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
Any reference to voltage, current, or frequency specified in the following
sections will refer to the nominal values. The exact values and their
tolerance or limits are specified in Section 13. Electrical
Specifications.
1.5 Functional Pin Description
The following subsections describe the functionality of each pin on the
MC68HC05P18/MC68HC805P18 package. Pins connected to
subsystems described in other sections provide a reference to the
section instead of a detailed functional description.
The pinout is shown in Figure 1-2.
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General Description
Functional Pin Description
RESET
1
28
VDD
IRQ
2
27
OSC1
PA7
3
26
OSC2
PA6
4
25
PD7/TCAP
PA5
5
24
TCMP
PA4
6
23
PD5/CKOUT
PA3
7
22
PC0
PA2
8
21
PC1
PA1
9
20
PC2
PA0
10
19
PC3/AD3
SDO/PB5
11
18
PC4/AD2
SDI/PB6
12
17
PC5/AD1
SCK/PB7
13
16
PC6/AD0
VSS
14
15
PC7/VREFH
Figure 1-2. User Mode Pinout
1.5.1 VDD and VSS
Power is supplied to the MCU through VDD and VSS. VDD is connected
to a regulated positive supply and VSS is connected to ground.
Very fast signal transitions occur on the MCU pins. The short rise and
fall times place very high short-duration current demands on the power
supply. To prevent noise problems, take special care to provide good
power supply bypassing at the MCU. Use bypass capacitors with good
high-frequency characteristics and position them as close to the MCU as
possible. Bypassing requirements vary, depending on how heavily the
MCU pins are loaded.
1.5.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the on-chip
oscillator. The OSC1 and OSC2 pins can accept:
•
A crystal as shown in Figure 1-3(a)
•
A ceramic resonator as shown in Figure 1-3(a)
•
An external clock signal as shown in Figure 1-3(b)
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The frequency, fOSC, of the oscillator or external clock source is divided
by two to produce the internal PH2 bus clock operating frequency, fOP.
The oscillator cannot be turned off by software if the stop-to-halt
conversion is enabled via mask option for the MC68HC05P18 and mask
option register 1 for the MC68HC805P18. Refer to 8.5 Mask Option
Registers.
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1.5.3 Crystal
The circuit in Figure 1-3(a) shows a typical oscillator circuit for an
AT-cut, parallel resonant crystal. Follow the crystal manufacturer’s
recommendations, as the crystal parameters determine the external
component values required to provide maximum stability and reliable
startup. The load capacitance values used in the oscillator circuit design
should include all stray capacitances.
NOTE:
Mount the crystal and components as close as possible to the pins for
startup stabilization and to minimize output distortion.
1.5.3.1 Ceramic Resonator
In cost-sensitive applications, use a ceramic resonator instead of a
crystal. Use the circuit in Figure 1-3(a) for a ceramic resonator and
follow the resonator manufacturer’s recommendations, as the resonator
parameters determine the external component values required for
maximum stability and reliable starting. The load capacitance values
used in the oscillator circuit design should include all stray capacitances.
Mount the resonator and components as close as possible to the pins for
startup stabilization and to minimize output distortion.
1.5.3.2 External Clock
An external clock from another CMOS-compatible device can be
connected to the OSC1 input, with the OSC2 input not connected, as
shown in Figure 1-3(b).
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Functional Pin Description
TO VDD (OR STOP)
OSC1
MCU
OSC2
TO VDD (OR STOP)
OSC1
MCU
OSC2
4.7 MΩ
UNCONNECTED
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EXTERNAL CLOCK
37 pF
37 pF
(a)
Crystal or Ceramic
Resonator Connections
(b)
External Clock Source
Connections
Figure 1-3. Oscillator Connections
1.5.4 Reset (RESET)
Driving this input low will reset the MCU to a known startup state. As an
output, the RESET pin indicates that an internal MCU reset has
occurred. The RESET pin contains an internal Schmitt trigger to improve
its noise immunity. Refer to Section 5. Resets.
1.5.5 Port A (PA0–PA7)
These eight I/O pins comprise port A. The state of any pin is software
programmable and all port A lines are configured as inputs during
power-on or reset. For the MC68HC05P18, eight mask options can be
chosen to enable pullups and interrupts (active low) on the port A pins.
For the MC68HC805P18, the pullups and interrupt options (active low)
on the port A pins can be individually programmed in the mask option
register 2 (MOR2).
For further information, refer to Section 4. Interrupts and Section 7.
Input/Output (I/O) Ports.
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General Description
1.5.6 Port B (PB5/SDO, PB6/SDI, and PB7/SCK)
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These three I/O pins comprise port B and are shared with the SIOP
communications subsystem. The state of any pin is software
programmable and all port B lines are configured as inputs during
power-on or reset. For further information, refer to Section 7.
Input/Output (I/O) Ports and Section 11. Serial Input/Output Port
(SIOP).
1.5.7 Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH)
These eight I/O pins comprise port C and are shared with the A/D
converter subsystem. The state of any pin is software programmable
and all port C lines are configured as inputs during power-on or reset.
Port pins PC0 and PC1 are capable of sourcing and sinking high
currents. For further information, refer to Section 7. Input/Output (I/O)
Ports and Section 9. Analog-to-Digital (A/D) Converter.
1.5.8 Port D (PD5/CKOUT and PD7/TCAP)
These two I/O pins comprise port D, and one of them is shared with the
16-bit timer subsystem. Unless clock output has been selected, the state
of PD5/CKOUT is software programmable and is configured as an input
during power-on or reset. PD7 is always an input; it may be read at any
time, regardless of the mode of operation the 16-bit timer may be in. For
further information, refer to Section 7. Input/Output (I/O) Ports and
Section 10. 16-Bit Timer.
For the MC68HC05P18, there is a mask option to turn the PD5/CKOUT
pin into a clock output. The clock output is a buffered OSC2 signal with
a CMOS output drive. The clock output or the port D function must be
chosen with the mask option and is not alterable in software.
For the MC68HC805P18, the PD5/CKOUT pin can be turned into a clock
output pin by programming mask option register 1 (MOR1). The clock
output is a buffered OSC2 signal with a CMOS output driver.
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General Description
Functional Pin Description
1.5.9 TCMP
This pin is the output from the 16-bit timer’s output compare function. It
is low after reset. For further information, refer to Section 10. 16-Bit
Timer.
1.5.10 Maskable Interrupt Request (IRQ)
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This input pin drives the asynchronous interrupt function of the MCU.
The MCU will complete the current instruction being executed before it
responds to the IRQ interrupt request. When IRQ is driven low, the event
is latched internally to signify an interrupt has been requested. When the
MCU completes its current instruction, the interrupt latch is tested. If the
interrupt latch is set and the interrupt mask bit (I bit) in the condition code
register is clear, the MCU will begin the interrupt sequence.
Depending on the mask option selected for the MC68HC05P18 or the
programming option selected in mask option register 1 (MOR1) for the
MC68HC805P18, the IRQ pin will trigger this interrupt on either a
negative-going edge at the IRQ pin and/or while the IRQ pin is held in
the low state. In either case, the IRQ pin must be held low for at least one
tILIH time period. The IRQ input requires an external resistor connected
to VDD for wired-OR operation if:
•
For the MC68HC05P18, the edge- and level-sensitive mask
option is selected.
•
For the MC68HC805P18, the edge- and level-sensitive edge is
programmed in the MOR1.
If the IRQ pin is not used, it must be tied to the VDD supply. The IRQ pin
contains an internal Schmitt trigger as part of its input circuitry to improve
noise immunity. For further information, refer to Section 4. Interrupts.
NOTE:
For the MC68HC805P18, if the voltage level applied to the IRQ pin
exceeds VDD, it may affect the MCU’s mode of operation. See
Section 6. Operating Modes.
MC68HC(8)05P18 — Rev. 2.0
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General Description
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Section 2. Memory
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2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3
Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . .27
2.4
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.5
ROM (MC68HC05P18 Only) . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.6
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.7
User EEPROM (MC68HC805P18 Only). . . . . . . . . . . . . . . . . .34
2.2 Introduction
The MC68HC05P18 and MC68HC805P18 both utilize 14 address lines
to access an internal memory space covering 16 Kbytes. This memory
space is divided into input/output (I/O), random-access memory (RAM),
electrically erasable, programmable read-only memory (EEPROM),
read-only memory (ROM), and boot ROM areas.
Figure 2-1 and Figure 2-2 show user mode memory maps for the
MC68HC05P18 and MC68HC805P18, respectively.
2.3 Input/Output and Control Registers
Figure 2-3 and Figure 2-4 briefly describe the input/output (I/O) and
control registers at locations $0000–$001F. Reading unimplemented
bits will return unknown states, and writing unimplemented bits will be
ignored.
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Memory
$0000
$001F
$0020
0031
0032
USER ROM
48 BYTES
$004F
$0050
0079
0080
INTERNAL RAM
192 BYTES
$00BF
$00C0
STACK
64 BYTES
$00FF
$0100
$010F
$0140
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0000
I/O
32 BYTES
$01BF
$01C0
0399
0400
UNUSED
77,28 BYTES
$1FBF
$1FC0
8127
8128
USER ROM
8,000 BYTES
$3EFF
$3F00
16127
16128
RESERVED FOR TEST
240 BYTES
$3FEF
$3FF0
$3FFF
16367
16368
USER VECTORS ROM
16 BYTES
I/O REGISTERS
SEE Figure 2-3
0191
0192
0255
0256
0271
0272
EEPROM
128 BYTES
$0000
16383
$001F
COP CONTROL REGISTER
$3FF0
UNIMPLEMENTED
$3FF1
UNIMPLEMENTED
$3FF2
UNIMPLEMENTED
$3FF3
UNIMPLEMENTED
$3FF4
UNIMPLEMENTED
$3FF5
UNIMPLEMENTED
$3FF6
UNIMPLEMENTED
$3FF7
TIMER VECTOR (HIGH BYTE)
$3FF8
TIMER VECTOR (LOW BYTE)
$3FF9
IRQ VECTOR (HIGH BYTE)
$3FFA
IRQ VECTOR (LOW BYTE)
$3FFB
SWI VECTOR (HIGH BYTE)
$3FFC
SWI VECTOR (LOW BYTE)
$3FFD
RESET VECTOR (HIGH BYTE)
$3FFE
RESET VECTOR (LOW BYTE)
$3FFF
Figure 2-1. MC68HC05P18 User Mode Memory Map
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Memory
Input/Output and Control Registers
$0000
$001F
$0020
$004F
$0050
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$00BF
$00C0
$00FF
$010F
$013F
$0140
$01BF
$01C0
0031
0032
USER EEPROM
48 BYTES
0079
0080
INTERNAL RAM
192 BYTES
STACK
64 BYTES
UNUSED
48 BYTES
EEPROM
128 BYTES
0191
0192
0255
0271
0272
0319
0320
0447
0448
UNUSED
77,28 BYTES
$1FBF
$1FC0
8127
8128
USER EEPROM
8,000 BYTES
$3EFF
$3F00
$3F01
$3F02
MASK OPTION REGISTER
16127
16128
16130
UNUSED
238 BYTES
$3FEF
$3FF0
$3FFF
$0000
0000
I/O
32 BYTES
USER VECTORS EEPROM
16 BYTES
16367
16368
16383
I/O REGISTERS
SEE Figure 2-3
$001F
COP CONTROL REGISTER
$3FF0
UNIMPLEMENTED
$3FF1
UNIMPLEMENTED
$3FF2
UNIMPLEMENTED
$3FF3
UNIMPLEMENTED
$3FF4
UNIMPLEMENTED
$3FF5
UNIMPLEMENTED
$3FF6
UNIMPLEMENTED
$3FF7
TIMER VECTOR (HIGH BYTE)
$3FF8
TIMER VECTOR (LOW BYTE)
$3FF9
IRQ VECTOR (HIGH BYTE)
$3FFA
IRQ VECTOR (LOW BYTE)
$3FFB
SWI VECTOR (HIGH BYTE)
$3FFC
SWI VECTOR (LOW BYTE)
$3FFD
RESET VECTOR (HIGH BYTE)
$3FFE
RESET VECTOR (LOW BYTE)
$3FFF
Figure 2-2. MC68HC805P18 User Mode Memory Map
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Memory
PORT A DATA REGISTER
$0000
PORT B DATA REGISTER
$0001
PORT C DATA REGISTER
$0002
PORT D DATA REGISTER
$0003
PORT A DATA DIRECTION REGISTER
$0004
PORT B DATA DIRECTION REGISTER
$0005
PORT C DATA DIRECTION REGISTER
$0006
PORT D DATA DIRECTION REGISTER
$0007
UNIMPLEMENTED
$0008
UNIMPLEMENTED
$0009
SIOP CONTROL REGISTER
$000A
SIOP STATUS REGISTER
$000B
SIOP DATA REGISTER
$000C
UNIMPLEMENTED
$000D
UNIMPLEMENTED
$000E
UNIMPLEMENTED
$000F
UNIMPLEMENTED
$0010
RESERVED
$0011
TIMER CONTROL REGISTER
$0012
TIMER STATUS REGISTER
$0013
INPUT CAPTURE MOST SIGNIFICANT BIT
$0014
INPUT CAPTURE LEAST SIGNIFICANT BIT
$0015
OUTPUT COMPARE MOST SIGNIFICANT BIT
$0016
OUTPUT COMPARE LEAST SIGNIFICANT BIT
$0017
TIMER MOST SIGNIFICANT BIT
$0018
TIMER LEAST SIGNIFICANT BIT
$0019
ALTERNATE COUNTER MOST SIGNIFICANT BIT
$001A
ALTERNATE COUNTER LEAST SIGNIFICANT BIT
$001B
EEPROM PROGRAMMING REGISTER
$001C
A/D CONVERTER DATA REGISTER
$001D
A/D CONVERTER CONTROL AND STATUS REGISTER
$001E
RESERVED
$001F
Figure 2-3. I/O and Control Registers Memory Map
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Memory
Input/Output and Control Registers
Addr.
$0000
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$0001
$0002
$0003
$0004
$0005
$0006
$0007
Register Name
Read:
Port A Data Register
(PORTA) Write:
See page 64.
Reset:
Read:
Port B Data Register
(PORTB) Write:
See page 65.
Reset:
Read:
Port C Data Register
(PORTC) Write:
See page 66.
Reset:
Read:
Port D Data Register
(PORTD) Write:
See page 67.
Reset:
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
0
0
0
PC2
PC1
PC0
0
0
0
Unaffected by reset
PB7
PB6
PC7
PC6
PD7
0
$0009
Unimplemented
Read:
SIOP Control Register
(SCR) Write:
See page 102.
Reset:
0
PC5
PC4
PC3
PD5
1
0
Unaffected by reset
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
DDRB6
DDRB5
1
1
1
1
1
0
0
0
0
0
0
0
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
= Reserved
Read:
Port C Data Direction
DDRC7 DDRC6
(DDRC) Write:
See page 66.
Reset:
0
0
Unimplemented
0
Unaffected by reset
Read:
Port B Data Direction
DDRB7
(DDRB) Write:
See page 65.
Reset:
0
Read:
Port D Data Direction
(DDRD) Write:
See page 67.
Reset:
PB5
Unaffected by reset
Read:
Port A Data Direction
DDRA7
(DDRA) Write:
See page 64.
Reset:
0
$0008
$000A
Bit 7
0
0
0
0
0
0
SPE
0
DDRD5
0
0
0
= Unimplemented
MSTR
U = Unaffected
Figure 2-4. I/O and Control Registers (Sheet 1 of 3)
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Memory
Addr.
$000B
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$000C
Register Name
Read:
SIOP Status Register
(SSR) Write:
See page 104.
Reset:
Unimplemented
$000E
Unimplemented
$000F
Unimplemented
$0010
Unimplemented
$0011
Reserved
$0013
$0014
$0015
$0016
6
5
4
3
2
1
Bit 0
SPIF
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDR6
SDR5
SDR4
SDR3
SDR2
SDR1
SDR0
R
R
IEDG
OLVL
Read:
SIOP Data Register
SDR7
(SDR) Write:
See page 105.
Reset:
$000D
$0012
Bit 7
Unaffected by reset
R
R
R
0
0
0
0
0
0
0
0
0
OCF
TOF
0
0
0
0
0
U
U
0
0
0
0
0
Read: ICRH7
Input Capture MSB Register
(ICRH) Write:
See page 93.
Reset:
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
Read: ICRL7
Input Capture LSB Register
(ICRL) Write:
See page 93.
Reset:
ICRL6
ICRL2
ICRL1
ICRL0
OCRH2
OCRH1 OCRH0
Read:
Timer Control Register
(TCR) Write:
See page 94.
Reset:
Read:
Timer Status Register
(TSR) Write:
See page 96.
Reset:
R
R
R
ICIE
OCIE
TOIE
0
0
ICF
U
Unaffected by reset
ICRL5
ICRL4
ICRL3
Unaffected by reset
Read: OCRH7 OCRH6
Output Compare MSB
Register (OCRH) Write:
See page 90.
Reset:
OCRH5
= Unimplemented
OCRH4
OCRH3
Unaffected by reset
R
= Reserved
U = Unaffected
Figure 2-4. I/O and Control Registers (Sheet 2 of 3)
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Memory
Input/Output and Control Registers
Addr.
$0017
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$0018
$0019
$001A
$001B
$001C
Register Name
Bit 7
Read: OCRL7
Output Compare LSB
Register (OCRL) Write:
See page 90.
Reset:
6
5
4
3
2
1
Bit 0
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
Unaffected by reset
Read: TMRH7 TMRH6
Timer MSB Register
(TMRH) Write:
See page 88.
Reset:
1
1
TMRH5
TMRH4
TMRH3
TMRH2
TMRH1
TMRH0
1
1
1
1
1
1
Read: TMRL7
Timer LSB Register
(TMRL) Write:
See page 88.
Reset:
1
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
1
1
1
1
1
0
0
Read: ACRH7
Alternate Counter MSB
Register (ACRH) Write:
See page 88.
Reset:
1
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
1
1
1
1
1
1
1
Read: ACRL7
Alternate Counter LSB
Register (ACRL) Write:
See page 88.
Reset:
1
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
1
1
1
1
1
0
0
ER1
ER0
LATCH
EERC
EEPGM
Read:
EEPROM Programming
Register (EEPROG) Write:
See page 72.
Reset:
0
CPEN
0
0
0
0
0
0
0
0
0
Read:
A/D Conversion Data Register
$001D
(ADC) Write:
See page 84.
Reset:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Read:
A/D Status and Control
Register (ADSC) Write:
See page 82.
Reset:
CC
CH2
CH1
CH0
$001E
$001F
Reserved
Unaffected by reset
0
0
0
0
0
0
0
0
R
R
R
R
R
R
= Unimplemented
R
= Reserved
R
ADON
0
0
R
R
U = Unaffected
Figure 2-4. I/O and Control Registers (Sheet 3 of 3)
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Memory
2.4 RAM
The user RAM consists of 192 bytes (including the stack) at locations
$0050–$010F. The stack begins at address $00FF. The stack pointer
can access 64 bytes of RAM from $00FF to $00C0.
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NOTE:
Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.
2.5 ROM (MC68HC05P18 Only)
There are 8064 bytes of user ROM available, consisting of 8000 bytes
at locations $1FC0–$3EFF, 48 bytes in page zero locations
$0020–$004F, and 16 additional bytes of user vectors at locations
$3FF0–$3FFF.
NOTE:
Address space $3F00–$3FEF is reserved for test code. Unlike other
M68HC05 devices, the MC68HC05P18 does not contain self-check
code.
2.6 EEPROM
The EEPROM is located at address $0140 and consists of 128 bytes.
Programming the EEPROM can be done by the user on a single byte
basis by manipulating the programming register, located at address
$001C. Refer to Section 8. EEPROM for a discussion of the EEPROM.
2.7 User EEPROM (MC68HC805P18 Only)
There are 8064 bytes of user EEPROM available, consisting of 8000
bytes at locations $1FC0–$3EFF, 48 bytes in page zero locations
$0020–$004F, and 16 additional bytes for user vectors at locations
$3FF0–$3FFF.
This EEPROM can be programmed only in bootloader mode. Refer to
6.3.2 Bootloader Mode for more details.
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Section 3. Central Processing Unit (CPU)
3.1 Contents
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3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.3.1
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.2
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.3
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .37
3.3.3.1
Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.3.2
Interrupt (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.3.3
Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.3.3.4
Zero (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.3.3.5
Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.3.4
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.3.5
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.2 Introduction
This section describes the CPU registers.
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Central Processing Unit (CPU)
3.3 CPU Registers
The five CPU registers are shown in Figure 3-1 and the interrupt
stacking order is shown in Figure 3-2.
7
0
A
ACCUMULATOR
7
0
X
INDEX REGISTER
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12
0
PC
12
0
PROGRAM COUNTER
7
0
0
0
0
1
0
1
SP
STACK POINTER
CCR
H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
7
1
INCREASING
MEMORY
ADDRESSES
R
E
T
U
R
N
0
1
1
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PCH
PCL
STACK
I
N
T
E
R
R
U
P
T
DECREASING
MEMORY
ADDRESSES
UNSTACK
Note: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
Figure 3-2. Stacking Order
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Central Processing Unit (CPU)
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Central Processing Unit (CPU)
CPU Registers
3.3.1 Accumulator (A)
The accumulator is a general-purpose 8-bit register used to hold
operands and results of arithmetic calculations or data manipulations.
7
0
A
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3.3.2 Index Register (X)
The index register is an 8-bit register used for the indexed addressing
value to create an effective address. The index register may also be
used as a temporary storage area.
7
0
X
3.3.3 Condition Code Register (CCR)
The condition code register (CCR) is a 5-bit register in which four bits are
used to indicate the results of the instruction just executed, and the fifth
bit indicates whether interrupts are masked. These bits can be
individually tested by a program, and specific actions can be taken as a
result of their state. Each bit is explained in the following paragraphs.
CCR
H
I
N
Z
C
3.3.3.1 Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
3.3.3.2 Interrupt (I)
When this bit is set, the timer and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the interrupt bit is cleared.
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3.3.3.3 Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
3.3.3.4 Zero (Z)
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When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was 0.
3.3.3.5 Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This bit
is also affected during bit test and branch instructions and during shifts
and rotates.
3.3.4 Stack Pointer (SP)
The stack pointer contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set to location $00FF. The stack pointer is then
decremented as data is pushed onto the stack and incremented as data
is pulled from the stack.
When accessing memory, the seven most significant bits are
permanently set to 0000011. These seven bits are appended to the six
least significant register bits to produce an address within the range of
$00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal)
locations. If 64 locations are exceeded, the stack pointer wraps around
and loses the previously stored information. A subroutine call occupies
two locations on the stack; an interrupt uses five locations.
12
0
0
0
0
0
7
1
0
1
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CPU Registers
3.3.5 Program Counter (PC)
The program counter is a 13-bit register that contains the address of the
next byte to be fetched.
12
0
PC
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NOTE:
The M68HC05 CPU core is capable of addressing a 64-Kbyte memory
map. For this implementation, however, the addressing registers are
limited to an 8-Kbyte memory map.
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Section 4. Interrupts
4.1 Contents
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4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.3
Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3.1
Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3.2
Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3.3
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3.3.1
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.3.3.2
Optional External Interrupts (PA0–PA7) . . . . . . . . . . . . .46
4.3.3.3
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.3.3.4
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .47
4.3.3.5
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .47
4.2 Introduction
The MCUs can be interrupted six different ways:
•
Non-maskable software interrupt instruction (SWI)
•
External asynchronous interrupt (IRQ)
•
Input capture interrupt (TIMER)
•
Output compare interrupt (TIMER)
•
Timer overflow interrupt (TIMER)
•
Port A interrupt (if selected via MOR2, bits 0–7)
Interrupts cause the processor to save the register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
reset, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is
completed.
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When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked (I bit in the
condition code register is clear) and the corresponding interrupt enable
bit is set, the processor proceeds with interrupt processing. Otherwise,
the next instruction is fetched and executed. The software interrupt
(SWI) is executed the same as any other instruction, regardless of the I
bit state.
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When an interrupt is to be processed, the CPU puts the register contents
on the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$3FF0–$3FFF. If more than one interrupt is pending when the interrupt
vector is fetched, the interrupt with the highest vector location shown in
Table 4-1 will be serviced first.
An return-from-interrupt (RTI) instruction is used to signify when the
interrupt software service routine is completed. The RTI instruction
causes the CPU state to be recovered from the stack and normal
processing to resume at the next instruction that was to be executed
when the interrupt took place.
Figure 4-1 shows the sequence of events that occurs during interrupt
processing.
Table 4-1. Vector Addresses for Interrupts and Reset
Register
Flag
Name
CPU
Interrupt
Vector
Address
N/A
N/A
Reset
RESET
$3FF3–$3FFF
N/A
N/A
Software
SWI
$3FFC–$3FFD
N/A
N/A
External interrupt
IRQ
$3FFA–$3FFB
TSR
ICF
Timer input capture
TIMER
$3FF8–$3FF9
TSR
OCF
Timer output compare
TIMER
$3FF8–$3FF9
TSR
TOF
Timer overflow
TIMER
$3FF8–$3FF9
N/A
N/A
Unimplemented
N/A
$3FF6–$3FF7
N/A
N/A
Unimplemented
N/A
$3FF4–$3FF5
N/A
N/A
Unimplemented
N/A
$3FF2–$3FF3
N/A
N/A
Unimplemented
N/A
$3FF0–$3FF1
Interrupts
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Interrupts
Interrupt Types
4.3 Interrupt Types
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The interrupts fall into three categories:
•
Reset
•
Software
•
Hardware
4.3.1 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in Figure 4-1. A low level input
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address which is specified by the
contents of memory locations $3FFE and $3FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as described in Section 5. Resets.
4.3.2 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt
since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction will be
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $3FFC and $3FFD.
4.3.3 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit
is set, all hardware interrupts (internal and external) are disabled.
Clearing the I bit enables the hardware interrupts. Four hardware
interrupts are explained here.
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Interrupts
FROM RESET
Y
IS I BIT
SET?
N
IRQ
INTERRUPT?
Y
CLEAR IRQ
REQUEST
LATCH
N
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TIMER
INTERRUPT?
Y
N
STACK
PC, X, A, CC
SET
I BIT IN CCR
LOAD PC FROM:
SWI: $3FFC, $3FFD
IRQ: $3FFA–$3FFB
TIMER: $3FF8–$3FF9
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
Y
N
RTI
INSTRUCTION?
Y
RESTORE RESISTERS
FROM STACK
CC, A, X, PC
N
EXECUTE INSTRUCTION
Figure 4-1. Interrupt Processing Flowchart
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Interrupts
Interrupt Types
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4.3.3.1 External Interrupt (IRQ)
The IRQ pin drives an asynchronous interrupt to the CPU. An edge
detector flip-flop is latched on the falling edge of IRQ. If either the output
from the internal edge detector flip-flop or the level on the IRQ pin is low,
a request is synchronized to the CPU to generate the IRQ interrupt. If the
edge-sensitive only option is selected, the output of the internal edge
detector flip-flop is sampled and the input level on the IRQ pin is ignored.
If port A interrupts are programmed as an option, a port A interrupt will
use the same vector. The interrupt service routine address is specified
by the contents of memory locations $3FFA and $3FFB.
NOTE:
The internal interrupt latch is cleared nine PH2 clock cycles after the
interrupt is recognized (after location $3FFA is read). Therefore, another
external interrupt pulse could be latched during the IRQ service routine.
When the edge- and level-sensitive option is selected, the voltage
applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed.
The IRQ pin is one source of an IRQ interrupt and a mask option can
also enable the port A pins (PA0–PA7) to act as other IRQ interrupt
sources. These sources are all combined into a single ORing function to
be latched by the IRQ latch.
IRQ PIN
TO BIH & BIL
INSTRUCTION
SENSING
PA0
DDRA0
PA0 IRQ INHIBIT
(MASK OPTION)
:
:
:
:
PA7
DDRA7
PA7 IRQ INHIBIT
(MASK OPTION)
VDD
:
:
:
:
IRQ
LATCH
:
R
TO IRQ
PROCESSING
IN CPU
RST
IRQ VECTOR FETCH
MASK OPTION
(IRQ LEVEL)
Figure 4-2. IRQ Function Block Diagram
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Any enabled IRQ interrupt source sets the IRQ latch on the falling edge
of the IRQ pin or a port A pin if port A interrupts have been enabled. If
edge-only sensitivity is chosen by a mask option, only the IRQ latch
output can activate a request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the:
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1. Falling edge on the IRQ pin with all enabled port A interrupt pins
at a high level
2. Falling edge on any enabled port A interrupt pin with all other
enabled port A interrupt pins and the IRQ pin at a high level
If level sensitivity is chosen, the active high state of the IRQ input can
also activate an IRQ request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the:
1. Low level on the IRQ pin
2. Falling edge on the IRQ pin with all enabled port A interrupt pins
at a high level
3. Low level on any enabled port A interrupt pin
4. Falling edge on any enabled port A interrupt pin with all enabled
port A interrupt pins and the IRQ pin at a high level
This interrupt is serviced by the interrupt service routine located at the
address specified by the contents of $3FFA and $3FFB. The IRQ latch
is cleared automatically by entering the interrupt service routine.
4.3.3.2 Optional External Interrupts (PA0–PA7)
The IRQ interrupt can be triggered by the inputs on the PA0–PA7 port
pins if enabled by individual mask options. With pullup enabled, each
port A pin can activate the IRQ interrupt function and the interrupt
operation will be the same as for inputs to the IRQ pin. Once enabled by
mask option, each individual port A pin can be disabled as an interrupt
source if its corresponding DDR bit is configured for output mode.
NOTE:
The BIH and BIL instructions apply to the output of the logic OR function
of the enabled PA0–PA7 interrupt pins and the IRQ pin. The BIH and BIL
instructions do not test only the state of the IRQ pin.
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Interrupts
Interrupt Types
If enabled, the PA0–PA7 pins will cause an IRQ interrupt only if these
individual pins are configured as inputs.
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4.3.3.3 Input Capture Interrupt
The input capture interrupt is generated by the 16-bit timer as described
in Section 10. 16-Bit Timer. The input capture interrupt flag is located
in register TSR and its corresponding enable bit can be found in register
TCR. The I bit in the CCR must be clear in order for the input capture
interrupt to be enabled. The interrupt service routine address is specified
by the contents of memory locations $3FF8 and $3FF9.
4.3.3.4 Output Compare Interrupt
The output compare interrupt is generated by the 16-bit timer as
described in Section 10. 16-Bit Timer. The output compare interrupt
flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear in order for the
output compare interrupt to be enabled. The interrupt service routine
address is specified by the contents of memory locations $3FF8 and
$3FF9.
4.3.3.5 Timer Overflow Interrupt
The timer overflow interrupt is generated by the 16-bit timer as described
in Section 10. 16-Bit Timer. The timer overflow interrupt flag is located
in register TSR and its corresponding enable bit can be found in register
TCR. The I bit in the CCR must be clear in order for the timer overflow
interrupt to be enabled. This internal interrupt will vector to the interrupt
service routine located at the address specified by the contents of
memory locations $3FF8 and $3FF9.
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Section 5. Resets
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5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.3
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.4
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.4.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.4.2
Computer Operating Properly (COP) Reset . . . . . . . . . . . . .51
5.4.3
Low-Voltage Reset (LVR). . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.2 Introduction
The MCU can be reset from four sources: one external input and three
internal reset conditions. The RESET pin is an input with a Schmitt
trigger as shown in Figure 5-1. The CPU and all peripheral modules will
be reset by the RST signal which is the logical OR of internal reset
functions and is clocked by PH2.
5.3 External Reset (RESET)
The RESET input is the only external reset and is connected to an
internal Schmitt trigger. The external reset occurs whenever the RESET
input is driven below the lower threshold and remains in reset until the
RESET pin rises above the upper threshold. The upper and lower
thresholds are given in Section 13. Electrical Specifications.
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Resets
TO IRQ
LOGIC
IRQ
D
LATCH
MODE
SELECT
RESET
R
(PULSE WIDTH = 4 x E-CLK)
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PH2
OSC
DATA
ADDRESS
COP WATCHDOG
(COPR)
VDD
LOW-VOLTAGE
RESET (LVR)
VDD
POWER-ON RESET
(POR)
CLOCKED
ONE-SHOT
CPU
S
D
LATCH
RST
TO OTHER
PERIPHERALS
PH2
Figure 5-1. Reset Block Diagram
5.4 Internal Resets
The three internally generated resets are:
•
Initial power-on reset (POR)
•
Computer operating properly (COP) watchdog timer
•
Low-voltage reset (LVR) functions
5.4.1 Power-On Reset (POR)
The internal POR is generated at power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
PH2 clock cycle oscillator stabilization delay after the oscillator becomes
active.
The POR will generate the RST signal and reset the MCU. The POR will
also pull the RESET pin low at the same time, allowing external devices
to be reset with the MCU. If any other reset function is active at the end
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Resets
Internal Resets
of this 4064 PH2 clock cycle delay, the RST signal will remain active until
the other reset condition(s) end.
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5.4.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled (by MOR1, bit 0), the internal
COP reset is generated automatically by a timeout of the COP watchdog
timer. This timer is implemented with an 18-stage ripple counter that
provides a timeout period of 65.5 ms when a 4-MHz oscillator is used.
The COP watchdog counter is cleared by writing a logical 0 to bit zero at
location $3FF0.
The COP register is shared with the most significant bit (MSB) of an
unimplemented user interrupt vector as shown in Figure 5-2. Reading
this location will return the MSB of the unimplemented user interrupt
vector. Writing to this location will clear the COP watchdog timer.
Address:
$3FF0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
0
Write:
R
Reset:
—
COPR
—
—
= Unimplemented
—
—
—
—
R
= Reserved
—
Figure 5-2. Unimplemented Vector and COP
Watchdog Timer Register
5.4.3 Low-Voltage Reset (LVR)
If the LVR has been enabled via MOR1, the internal LVR reset is
generated when the supply voltage to the VDD pin falls below a nominal
3.80 Vdc. The LVR threshold is not intended to be an accurate and
stable trip point, but is intended to ensure that the CPU will be held in
reset when the VDD supply voltage is below reasonable operating limits.
If the LVR is tripped for a short time, the LVR reset signal will last at least
two cycles of the CPU bus clock, PH2.
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Resets
The LVR will generate the RST signal which will reset the CPU and other
peripherals. Also, the LVR will establish the mode of operation based on
the state of the IRQ pin at the time the LVR signal ends. If any other reset
function is active at the end of the LVR reset signal, the RST signal will
remain in the reset condition until the other reset condition(s) end.
The voltage of the IRQ pin must be between 0–VDD volts to stay in the
normal operation mode.
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NOTE:
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Section 6. Operating Modes
6.1 Contents
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6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.3
User Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.3.1
User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.3.2
Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6.3.2.1
Bulk Erase/Blank Verify . . . . . . . . . . . . . . . . . . . . . . . . . .55
6.3.2.2
Bulk Erase/Program Verify. . . . . . . . . . . . . . . . . . . . . . . .57
6.4
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6.5
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.5.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.5.2
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.5.3
WAIT Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.6
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .61
6.2 Introduction
This section describes the user, bootloader, and low-power operating
modes. In addition the computer operating properly (COP) timer
considerations are discussed.
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Operating Modes
6.3 User Modes
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The MC68HC(8)05P18 has two modes of operation available to the
user:
•
User mode
•
Bootloader mode
The mode of operation is determined by the voltages on the IRQ and
PD7/TCAP pins on the rising edge of the external RESET pin. Table 6-1
shows the condition required to go into each mode.
Table 6-1. Operating Mode Conditions
RESET
IRQ
TCAP
Mode
0–5 V
0–5 V
User
2 x VDD
5V
Bootloader
6.3.1 User Mode
The user mode allows the MCU to function as a self-contained
microcontroller with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU and is not
available externally. User mode is entered on the rising edge of RESET,
if the IRQ pin is within the normal operating voltage range. In the user
mode, there is an 8-bit input/output (I/O) port, a second 8-bit I/O port
shared with the analog-to-digital (A/D) subsystem, one 3-bit I/O port
shared with the serial input/output port (SIOP), and a 2-bit I/O port
shared with the16-bit timer subsystem.
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Operating Modes
User Modes
6.3.2 Bootloader Mode
Bootloader mode is entered upon the rising edge of RESET if the IRQ
pin is twice the VDD voltage and the TCAP/PD7 pin is at logic 1. In
bootloader mode, the user EEPROM and mask option register (MOR)
bytes can be erased and programmed. Figure 6-1 shows the bootloader
circuit. PTC4 determines whether erasing or programming will occur as
shown in Table 6-2.
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Table 6-2. Bootloader Functions
PTC4
Function
0
Bulk erase/blank verify
1
Bulk erase/program/verify
6.3.2.1 Bulk Erase/Blank Verify
To use the bootloader circuit to bulk erase the user EEPROM, follow this
sequence:
1. Close RESET switch and PTC4 switch so these pins are held low.
2. Apply 12-V power to IRQ.
3. Release RESET.
4. Programming LED will turn on while bulk erase is occurring.
5. When bulk erase is finished, programming LED will turn off.
6. When blank verify is finished, verify LED will turn on.
7. Close RESET switch.
8. Remove 12 V from IRQ, then remove power.
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12 V
27C128
MC14040B
1 kΩ
IRQ
OSC1
PA0
DQ1
A11
Q12
PA1
DQ2
A10
Q11
PA2
DQ3
A9
Q10
PA3
DQ4
A8
Q9
PA4
DQ5
A7
Q8
PA5
DQ6
A6
Q7
PA6
DQ7
A5
Q6
PA7
DQ8
A4
Q5
CE
A3
Q4
OE
A2
Q3
A1
Q2
A0
Q1
4 MHz
OSC2
10 MΩ
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20 pF
20 pF
VDD
10 kΩ
RESET
PC6
PC7
1 µF
A12
A13
RST
PC5 (SYNC)
VDD
CLK
VDD
4.7 kΩ
4.7 kΩ
PROG
TCAP
PB7
390 Ω
PC1
PC2
VDD
VERF
PB6
10 KΩ
390 Ω
PC4
VDD = 5.0 V
PC3
4.7 kΩ
Figure 6-1. Bootloader Circuit
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Low-Power Modes
6.3.2.2 Bulk Erase/Program Verify
To use the bootloader circuit to bulk erase, program, and verify the user
EEPROM, follow this sequence:
1. Close RESET switch so RESET is low upon power up.
2. Open PTC4 switch so PTC4 remains high during reset sequence.
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3. Make sure code to be loaded into user EEPROM is in the external
EPROM (shown as 27C128).
4. Apply 12 V power to IRQ.
5. Release RESET.
6. Programming LED will be on during bulk erase and programming.
(The code in the 27C128 will be loaded into the user EEPROM
and MOR.)
7. When programming is finished, the programming LED will turn off.
8. When the verify is finished, verify LED will turn on.
9. Close RESET switch.
10. Remove 12 V from IRQ, then remove power.
NOTE:
Bootloader mode is the only mode in which the user can program the 8-K
user EEPROM and MOR. The 128-byte EEPROM can be programmed
in user mode.
6.4 Low-Power Modes
The MC68HC(8)05P18 is capable of running in a low-power mode in
each of its configurations. The WAIT and STOP instructions provide
modes that reduce the power required for the MCU by stopping various
internal clocks and/or the on-chip oscillator. The STOP and WAIT
instructions are not normally used if the COP watchdog timer is enabled
(MOR1, bit 0). The stop conversion to halt option (MOR1, bit 5) is used
to modify the behavior of the STOP instruction from stop mode to halt
mode. The flow of the stop, halt, and wait modes is shown in
Figure 6-2.
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STOP
STOP
TO HALT
OPTION?
HALT
WAIT
EXTERNAL OSCILLATOR ACTIVE
AND
INTERNAL TIMER CLOCK ACTIVE
Y
N
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
RESET START-UP DELAY
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STOP RC OSCILLATOR
STOP INTERNAL PROCESSOR
CLOCK, CLEAR I-BIT IN CCR
STOP RC OSCILLATOR
STOP INTERNAL PROCESSOR
CLOCK, CLEAR I BIT IN CCR
EXTERNAL OSCILLATOR ACTIVE
AND
INTERNAL TIMER CLOCK ACTIVE
LVR OR
EXTERNAL
RESET?
STOP INTERNAL PROCESSOR
CLOCK,
CLEAR I BIT IN CCR
Y
N
LVR OR
EXTERNAL
RESET?
Y
Y
N
IRQ
EXTERNAL
INTERRUPT?
N
IRQ
EXTERNAL
INTERRUPT?
Y
N
N
Y
Y
RESTART EXTERNAL OSCILLATOR,
START STABILIZATION DELAY
Y
COP
INTERNAL
RESET?
2.
Y
TIMER
INTERNAL
INTERRUPT?
N
Y
RESTART INTERNAL
PROCESSOR CLOCK
IRQ
EXTERNAL
INTERRUPT?
N
N
N
1.
Y
N
Y
END
OF STABILIZATION
DELAY?
TIMER
INTERNAL
INTERRUPT?
LVR OR
EXTERNAL
RESET?
COP
INTERNAL
RESET?
N
FETCH RESET VECTOR
OR
SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO INTERRUPT ROUTINE
Figure 6-2. STOP/WAIT Flowcharts
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STOP Instruction
6.5 STOP Instruction
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The STOP instruction can result in one of two modes of operation
depending on the option programmed in the mask option register 1. If the
stop conversion to halt option (MOR1, bit 5) is not chosen, the STOP
instruction will behave like a normal STOP instruction in the M68HC805
Family and place the MCU in stop mode. If the stop conversion to halt
option is chosen, the STOP instruction will behave like a WAIT
instruction (with the exception of a brief delay at startup) and place the
MCU in halt mode.
6.5.1 Stop Mode
Execution of the STOP instruction (without conversion to halt) places the
MCU in its lowest power-consumption mode. In stop mode, the internal
oscillator is turned off, stopping all internal processing including the COP
watchdog timer. The RC oscillator that feeds the EEPROM and the A/D
converter is also stopped. Execution of the STOP instruction
automatically clears the I bit in the condition code register so that the
IRQ external interrupt is enabled. All other registers and memory remain
unaltered. All input/output lines remain unchanged.
The MCU can be brought out of the stop mode only by an IRQ external
interrupt (or port A, if selected as an option in the MOR2) or an externally
generated reset. When exiting stop mode, the internal oscillator will
resume after a 4064 PH2 clock cycle oscillator stabilization delay.
NOTE:
Execution of the STOP instruction without conversion to halt (via MOR1)
will cause the oscillator to stop, and therefore disable the COP watchdog
timer. If the COP watchdog timer is to be used, stop mode should be
changed to halt mode by programming the appropriate option in MOR1.
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6.5.2 Halt Mode
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Execution of the STOP instruction with the conversion to halt places the
MCU in this low-power mode. Halt mode consumes the same amount of
power as wait mode (both halt and wait modes consume more power
than stop mode).
In halt mode the PH2 clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register
enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit
halt mode and resume normal operation. Halt mode also can be exited
when an IRQ external interrupt (or port A, if selected as an option in the
MOR2) or external RESET occurs. When exiting halt mode, the PH2
clock will resume after a delay of one to 4064 PH2 clock cycles. This
varied delay time is the result of the halt mode exit circuitry testing the
oscillator stabilization delay timer (a feature of the stop mode), which has
been free-running (a feature of the wait mode).
NOTE:
Halt mode is not intended for normal use. This feature is provided to
keep the COP watchdog timer active in the event a STOP instruction is
executed inadvertently.
6.5.3 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode which
consumes more power than stop mode. In wait mode, the PH2 clock is
halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the
16-bit timer and reset to be generated from the COP watchdog timer.
Execution of the WAIT instruction automatically clears the I bit in the
condition code register enabling the IRQ external interrupt. All other
registers, memory, and input/output lines remain in their previous state.
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COP Watchdog Timer Considerations
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If the 16-bit timer interrupt is enabled, it will cause the processor to exit
wait mode and resume normal operation. The 16-bit timer may be used
to generate a periodic exit from wait mode. Wait mode may also be
exited when an IRQ or RESET occurs. Note that if port A interrupts (if
programmed as an option in the mask option register 1) will also exit wait
mode. However, when exiting wait mode, the internal oscillator will not
need to wait for 4064 PH2 clock cycles to stabilize as in the stop and halt
modes.
6.6 COP Watchdog Timer Considerations
The COP watchdog timer is active in user mode of operation when
programmed as an option in MOR1. Executing the STOP instruction
without conversion to halt (via mask option register1) will cause the COP
to be disabled. Therefore, it is recommended that the STOP instruction
be modified to produce halt mode (via MOR1) if the COP watchdog timer
will be enabled.
Furthermore, it is recommended that the COP watchdog timer be
disabled for applications that will use the halt or wait modes for time
periods that will exceed the COP timeout period.
COP watchdog timer interactions are summarized in Table 6-3.
Table 6-3. COP Watchdog Timer Recommendations
IF these conditions exist:
STOP Instruction Mode
Wait Period
THEN the COP
Watchdog Timer Should Be:
Halt mode selected
via MOR1, bit 5
WAIT period less than
COP timeout
Enable or disable COP
via MOR1, bit 0
Halt mode selected
via MOR1, bit 5
WAIT period more than
COP timeout
Disable COP
via MOR1, bit 0
Stop mode selected
via MOR1, bit 5
Any length wait period
Disable COP
via MOR1, bit 0
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Section 7. Input/Output (I/O) Ports
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7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
7.7
I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.2 Introduction
In user mode, 20 bidirectional input/output (I/O) lines are arranged as
two 8-bit I/O ports (ports A and C), one 3-bit I/O port (port B), and one
1-bit I/O port (port D). These ports are programmable as either inputs or
outputs under software control of the data direction registers (DDRs). An
input-only pin is associated with port D.
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Input/Output (I/O) Ports
7.3 Port A
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Port A is an 8-bit bidirectional port which can share its pins with the IRQ
interrupt system as shown in Figure 7-1. Each port A pin is controlled by
the corresponding bits in a data direction register and a data register.
The port A data register is located at address $0000. The port A data
direction register (DDRA) is located at address $0004. Reset clears the
DDRA, thereby initializing port A as an input port. The port A data
register is unaffected by reset.
VDD
MOR 2
(PULLUP INHIBIT)
READ $0004
WRITE $0004
DATA DIRECTION
REGISTER BIT
WRITE $0000
OUTPUT
DATA
REGISTER BIT
I/O
PIN
READ $0000
INTERNAL
HC05
DATA BUS
100 µA
PULLUP
RESET
(RST)
TO IRQ INTERRUPT
SYSTEM
Figure 7-1. Port A I/O Circuitry
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Port B
7.4 Port B
Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with
the serial input/output port (SIOP) communications subsystem. The port
B data register is located at address $0001 and its data direction register
(DDR) is located at address $0005. Reset does not affect the data
registers, but clears the DDRs, thereby setting all of the port pins to input
mode. Writing a logic 1 to a DDR bit sets the corresponding port pin to
output mode (see Figure 7-2).
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Port B may be used for general I/O applications when the SIOP
subsystem is disabled. The SPE bit in register SPCR is used to
enable/disable the SIOP subsystem. When the SIOP subsystem is
enabled, port B registers are still accessible to software. Writing to either
of the port B registers while a data transfer is under way could corrupt
the data. See Section 11. Serial Input/Output Port (SIOP) for a
discussion of the SIOP subsystem.
READ $0005
WRITE $0005
WRITE $0001
RESET
(RST)
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0001
INTERNAL
HC05
DATA BUS
Figure 7-2. Port B I/O Circuitry
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7.5 Port C
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Port C is an 8-bit bidirectional port which can share pins PC3–PC7 with
the A/D subsystem. The port C data register is located at address $0002
and its data direction register (DDR) is located at address $0006. Reset
does not affect the data registers, but clears the DDRs, thereby setting
all of the port pins to input mode. Writing a logic 1 to a DDR bit sets the
corresponding port pin to output mode (see Figure 7-3). Two port C
pins, PC0 and PC1, can source and sink a higher current than a typical
I/O pin. See Section 13. Electrical Specifications regarding current
specifications.
Port C may be used for general I/O applications when the A/D
subsystem is disabled. The ADON bit in register ADSC is used to
enable/disable the A/D subsystem. Care must be exercised when using
pins PC0–PC2 while the A/D subsystem is enabled. Accidental changes
to bits that affect pins PC3–PC7 in the data or DDR registers will produce
unpredictable results in the A/D subsystem. See Section 9.
Analog-to-Digital (A/D) Converter.
READ $0006
WRITE $0006
WRITE $0002
RESET
(RST)
HIGH CURRENT
CAPABILITY, PC0
AND PC1 ONLY
DATA DIRECTION
REGISTER BIT
OUTPUT
DATA
REGISTER BIT
I/O
PIN
READ $0002
INTERNAL
HC05
DATA BUS
Figure 7-3. Port C I/O Circuitry
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Port D
7.6 Port D
Port D is a 2-bit port with one bidirectional pin (PD5/CKOUT) and one
input-only pin (PD7). Pin PD7 is shared with the 16-bit timer. PD5 can be
replaced with a buffered OSC2 clock output via MOR1. The port D data
register is located at address $0003 and its data direction register (DDR)
is located at address $0007. Reset does not affect the data registers, but
clears the DDRs, thereby setting PD5/CKOUT to input mode. Writing a
1 to DDR bit 5 sets PD5/CKOUT to output mode (see Figure 7-4).
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Port D may be used for general I/O applications regardless of the state
of the 16-bit timer. Since PD7 is an input-only line, its state can be read
from the port D data register at any time.
READ $0007
WRITE $0007
WRITE $0003
RESET
(RST)
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0003
INTERNAL
HC05
DATA BUS
Figure 7-4. Port D I/O Circuitry
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Input/Output (I/O) Ports
7.7 I/O Port Programming
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Each pin on port A through port D (except pin 7 of port D) may be
programmed as an input or an output under software control as shown
in Table 7-1, Table 7-2, Table 7-3, and Table 7-4. The direction of a pin
is determined by the state of its corresponding bit in the associated port
data direction register (DDR). A pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.
Table 7-1. Port A I/O Functions
DDRA
I/O Pin Mode
Access to DDRA
@ $0004
Access to Data
Register @ $0000
Read/Write
Read
Write
0
Input, high impedance
DDRA0–DDRA7
I/O pin
*
1
Output
DDRA0–DDRA157
PA0–PA7
PA0–PA7
*Does not affect input, but stored to data register
Table 7-2. Port B I/O Functions
DDRB
I/O Pin Mode
Access to DDRA
@ $0005
Access to Data
Register @ $0001
Read/Write
Read
Write
0
Input, high impedance
DDRB5–DDRB7
I/O pin
*
1
Output
DDRB5–DDRB7
PB5–PB7
PB5–PB7
*Does not affect input, but stored to data register
Table 7-3. Port C I/O Functions
DDRA
I/O Pin Mode
Access to DDRA
@ $0006
Accesses to Data
Register @ $0002
Read/Write
Read
Write
0
Input, high impedance
DDRC0–DDRC7
I/O pin
*
1
Output
DDRC0–DDRC7
PC0–PC7
PC0–PC7
*Does not affect input, but stored to data register
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I/O Port Programming
Table 7-4. Port D I/O Functions
DDRA
I/O Pin Mode
Access to DDRA
@ $0007
Accesses to Data
Register @ $0003
Read/Write
Read
Write
0
Input, high impedance
DDRD5
I/O pin
*
1
Output
DDRD5
PD5/CKOUT
PD5/CKOUT
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*Does not affect input, but stored to data register
**PD7 is input-only
NOTE:
To avoid generating a glitch on an I/O port pin, data should be written to
the I/O port data register before writing a logical 1 to the corresponding
data direction register.
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Section 8. EEPROM
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8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
8.3
EEPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . .72
8.4
Programming/Erasing Procedures . . . . . . . . . . . . . . . . . . . . . .74
8.5
Mask Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8.2 Introduction
This section describes the electrically erasable, programmable
read-only memory (EEPROM) which is located at address $0140 and
consists of 128 bytes. Programming the EEPROM can be done by the
user on a single byte basis by manipulating the programming register
located at address $001C.
Also, the mask option register (MOR), which consists of two additional
EEPROM bytes, is discussed.
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EEPROM
8.3 EEPROM Programming Register
The contents and use of the programming register are discussed here.
Address:
$001C
Bit 7
Read:
6
0
5
4
3
2
1
Bit 0
ER1
ER0
LATCH
EERC
EEPGM
0
0
0
0
0
0
CPEN
Write:
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Reset:
0
0
0
= Unimplemented
Figure 8-1. EEPROM Programming Register (EEPROG)
CPEN — Charge Pump Enable Bit
When set, CPEN enables the charge pump which produces the
internal EEPROM programming voltage. This bit should be set
concurrently with the LATCH bit. The programming voltage will not be
available until EEPGM is set. The charge pump should be disabled
when not in use. CPEN is readable and writable and is cleared by
reset.
ER1 and ER0 — Erase Select Bits
ER1 and ER0 form a 2-bit field which is used to select one of three
erase modes: byte, block, or bulk. Table 8-1 shows the modes
selected for each bit configuration. These bits are readable and
writable and are cleared by reset.
Table 8-1. Erase Mode Select
ER1
ER0
Mode
0
0
Program (no erase)
0
1
Byte erase
1
0
Block erase
1
1
Bulk erase
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EEPROM
EEPROM Programming Register
In byte erase mode, only the selected byte is erased. In block mode,
a 32-byte block of EEPROM is erased. The EEPROM memory space
is divided into four 32-byte blocks ($140–$15F, $160–$17F,
$180–$19F and $1A0–$1BF) and doing a block erase to any address
within a block will erase the entire block. In bulk erase mode, the
entire 128-byte EEPROM section is erased.
LATCH — Latch Bit
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When set, LATCH configures the EEPROM address and data bus for
programming. Writes to the EEPROM array cause the data bus and
the address bus to be latched. This bit is readable and writable, but
reads from the array are inhibited if the LATCH bit is set and a write
to the EEPROM space has taken place.
When clear, address and data buses are configured for normal
operation. Reset clears this bit.
EERC — EEPROM RC Oscillator Control Bit
When this bit is set, the EEPROM section uses the internal RC
oscillator instead of the CPU clock. The RC oscillator is shared with
the A/D converter, so this bit should be set by the user when the
internal bus frequency is below 1.5 MHz to guarantee reliable
operation of the EEPROM or A/D converter. After setting the EERC
bit, delay a time, tRCON, to allow the RC oscillator to stabilize. This bit
is readable and writable. The EERC bit is cleared by reset. The RC
oscillator is disabled while the MCU is in stop mode.
EEPGM — EEPROM Programming Power Enable Bit
EEPGM must be written to enable (or disable) the EEPGM function.
When set, EEPGM turns on the charge pump and enables the
programming (or erasing) power to the EEPROM array. When clear,
this power is switched off. This will enable pulsing of the programming
voltage to be controlled internally. This bit can be read at any time, but
can only be written to if LATCH = 1. If LATCH is not set, then EEPGM
cannot be set. LATCH and EEPGM cannot both be set with one write
if LATCH is cleared. EEPGM is cleared automatically when LATCH is
cleared. Reset clears this bit.
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EEPROM
8.4 Programming/Erasing Procedures
To program a byte of EEPROM, set LATCH = CPEN = 1,
set ER1 = ER0 = 0, write data to the desired address, and then set
EEPGM for a time, tEPGM.
NOTE:
Any bit should be erased before it is programmed. However, if
write/erase cycling is a concern, the following procedure will minimize
the cycling of each bit in each EEPROM byte.
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If PB • EB = 0, then program the new data over the existing data without
erasing it first. If PB • EB ≠ 0, then erase the byte before programming
where PB = byte data to be programmed and
EB = existing EEPROM byte data.
To erase a byte of EEPROM, set LATCH = 1, CPEN = 1, ER1 = 0, and
ER0 = 1, write to the address to be erased and set EEPGM for a time,
tEBYT.
To erase a block of EEPROM, set LATCH = 1, CPEN = 1, ER1 = 1, and
ER0 = 0, write to any address in the block, and set EEPGM for a time,
tEBLOCK.
For a bulk erase, set LATCH = 1, CPEN = 1, ER1 = 1, and ER0 = 1, write
to any address in the array, and set EEPGM for a time, tEBULK.
To terminate the programming or erase sequence, clear EEPGM, delay
for a time tFPV to allow the program voltage to fall, and then clear LATCH
and CPEN to free up the buses. Following each erase or programming
sequence, clear all programming control bits.
NOTE:
Erased/programmed state of the programming EEPROM (128 bytes)
and the user EEPROM (8064 bytes) is opposite. An erased EEPROM
memory location is a logic 0 for user EEPROM, while it is a logic 1 for
programming EEPROM.
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EEPROM
Mask Option Registers
8.5 Mask Option Registers
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The mask option registers (MOR) consist of two EEPROM bytes located
at $3F00 and $3F01. The MORs hold the 16 option bits for:
•
The SIOP data format, interrupt sensitivity
•
COP enable/disable
•
SIOP clock rate
•
LVR enable/disable
•
Stop conversion to halt, pullup/interrupt enable on port A
•
Clock output option to replace PD5
When in the erased state, the EEPROM cells will read as logic 0s. These
registers are refreshed every 256 µs during power-on reset and every
16 ms after the part is out of reset (assuming fOSC = 4 MHz).
Address:
$3F00
Bit 7
Read: CLKOUT
6
5
4
3
2
1
Bit 0
LVRE
SWAIT
SPR1
SPR0
LSBF
LEVIRQ
COPEN
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 8-2. Mask Option Register 1 (MOR1)
Address:
Read:
$3F01
Bit 7
6
5
4
3
2
1
Bit 0
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 8-3. Mask Option Register 2 (MOR2)
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EEPROM
COPEN — COP Enable/Disable Bit
COPEN may be read at any time. In user mode, writing has no effect.
It has to be programmed in bootloader mode.
0 = The COP is disabled (erased state).
1 = The COP is enabled.
LEVIRQ — Interrupt Request Option Bit
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LEVIRQ may be read at any time. In user mode, writing has no effect.
It has to be programmed in bootloader mode.
0 = The IRQ pin is edge-sensitive (erased state).
1 = The IRQ pin is edge- and level-sensitive.
LSBF — SIOP MSB or LSB First Bit
LSBF may be read at any time. In user mode, writing has no effect. It
has to be programmed in bootloader mode.
0 = The SIOP sends/receives MSB (bit 7) first (erased state).
1 = The SIOP sends/receives LSB (bit 0) first.
SPR1 and SPR0 — SIOP Rate Select Bits
These bits may be read at any time. In user mode, writing has no
effect. It has to be programmed in bootloader mode.
Table 8-2. SIOP Clock Rate Selection
SPR1
SPR0
Frequency
0
0
fOSC divided by 16
0
1
fOSC divided by 8
1
0
fOSC divided by 4
1
1
fOSC divided by 2
SWAIT — STOP Conversion to WAIT Bit
SWAIT may be read at any time. In user mode, writing has no effect.
It has to be programmed in bootloader mode.
0 = STOP instruction puts MCU in stop mode.
1 = STOP instruction puts MCU in halt mode.
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EEPROM
Mask Option Registers
LVRE — LVR Enable/Disable Bit
LVRE may be read at any time. In user mode, writing has no effect. It
has to be programmed in bootloader mode.
0 = The LVR is disabled (erased state).
1 = The LVR is enabled.
CLKOUT — CLKOUT Enable/Disable Bit
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CLKOUT may be read at any time. In user mode, writing has no effect.
It has to be programmed in bootloader mode.
0 = The CLKOUT is disabled (erased state).
1 = The CLKOUT is enabled.
PA7PU–PA0PU — Port A Pullups/Interrupt Enable/Disable Bits
These bits may be read at any time. In user mode, writing has no
effect. It has to be programmed in bootloader mode.
0 = Port A (bits 0–7) pullups/interrupt is disabled (erased state).
1 = Port A (bits 0–7) pullups/interrupt is enabled.
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EEPROM
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Section 9. Analog-to-Digital (A/D) Converter
9.1 Contents
Freescale Semiconductor, Inc...
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.3
Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.1
Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.2
VREFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.3
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.4
Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.4
Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
9.4.1
Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
9.4.2
Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . .81
9.4.3
Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.5
A/D Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . .82
9.6
A/D Conversion Data Register . . . . . . . . . . . . . . . . . . . . . . . . .84
9.7
A/D Subsystem During Wait/Halt Modes . . . . . . . . . . . . . . . . .84
9.8
A/D Subsystem Operation During Stop Mode . . . . . . . . . . . . .84
9.2 Introduction
The MC68HC(8)05P18 includes a 4-channel, multiplexed input, 8-bit
successive approximation analog-to-digital (A/D) converter. The A/D
subsystem shares its inputs with port C pins PC3–PC7.
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Analog-to-Digital (A/D) Converter
9.3 Analog Section
This section describes the operation and performance of analog
modules within the analog subsystem.
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9.3.1 Ratiometric Conversion
The A/D converter is ratiometric, with pin VREFH supplying the high
reference voltage. Applying an input voltage equal to VREFH produces a
conversion result of $FF (full scale). Applying an input voltage equal to
VSS produces a conversion result of $00. An input voltage greater than
VREFH will convert to $FF with no overflow indication. For ratiometric
conversions, VREFH should be at the same potential as the supply
voltage being used by the analog signal being measured and referenced
to VSS.
9.3.2 VREFH
The reference supply for the A/D converter shares pin PC7 with port C.
The low reference is tied to the VSS pin internally. VREFH can be any
voltage between VSS and VDD; however, the accuracy of conversions is
tested and guaranteed only for VREFH = VDD.
9.3.3 Accuracy and Precision
The 8-bit conversion result is accurate to within ± 1 1/2 LSB (least
significant bit), including quantization; however, the accuracy of
conversions is tested and guaranteed only with external oscillator
operation.
9.3.4 Conversion Process
The A/D reference inputs are applied to a precision digital-to-analog
converter. Control logic drives the D/A and the analog output is
successively compared to the selected analog input which was sampled
at the beginning of the conversion cycle. The conversion process is
monotonic and has no missing codes.
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Analog-to-Digital (A/D) Converter
Digital Section
9.4 Digital Section
This section describes the operation and performance of digital modules
within the analog subsystem.
9.4.1 Conversion Times
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Each input conversion requires 32 PH2 clock cycles, which must be at a
frequency equal to or greater than 1 MHz.
9.4.2 Internal versus External Oscillator
If the MCU PH2 clock frequency is less than 1 MHz (2 MHz external
oscillator), the internal RC oscillator (approximately 1.5 MHz) must be
used for the A/D converter clock. The internal RC clock is selected by
setting the EERC bit in the EEPROM programming register (EEPROG).
NOTE:
The RC oscillator is shared with the EEPROM module. The RC oscillator
is disabled while the MCU is in stop mode.
When the internal RC oscillator is being used, these limitations apply:
1. Since the internal RC oscillator is running asynchronously with
respect to the PH2 clock, the conversion complete bit (CC) in the
A/D status and control register must be used to determine when a
conversion sequence has been completed.
2. Electrical noise will slightly degrade the accuracy of the A/D
converter. The A/D converter is synchronized to read voltages
during the quiet period of the clock driving it. Since the internal and
external clocks are not synchronized, the A/D converter
occasionally will measure an input when the external clock is
making a transition.
3. If the PH2 clock is 1 MHz or greater (for instance, external
oscillator 2 MHz or greater), the internal RC oscillator should be
turned off and the external oscillator used as the conversion clock.
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Analog-to-Digital (A/D) Converter
9.4.3 Multi-Channel Operation
An input multiplexer allows the A/D converter to select from one of four
external analog signals. Port C pins PC3–PC6 are shared with the inputs
to the multiplexer.
9.5 A/D Status and Control Register
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The ADSC register reports the completion of A/D conversion and
provides control over oscillator selection, analog subsystem power, and
input channel selection. See Figure 9-1.
Address:
$001E
Bit 7
Read:
6
5
R
ADON
0
0
0
0
= Unimplemented
R
= Reserved
CC
4
3
0
0
2
1
Bit 0
CH2
CH1
CH0
0
0
0
Write:
Reset:
0
Figure 9-1. A/D Status and Control Register (ADSC)
CC — Conversion Complete Bit
This read-only status bit is set when a conversion sequence has
completed and data is ready to be read from the ADC register. CC is
cleared when a channel is selected for conversion, when data is read
from the ADC register, or when the A/D subsystem is turned off. Once
a conversion has been started, conversions of the selected channel
will continue every 32 PH2 clock cycles until the ADSC register is
written to again. During continuous conversion operation, the ADC
register will be updated with new data and the CC bit set every 32
PH2 clock cycles. Also, data from the previous conversion will be
overwritten regardless of the state of the CC bit.
Reserved
This bit is not used currently. It can be read or written, but does not
control anything.
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Analog-to-Digital (A/D) Converter
A/D Status and Control Register
ADON — A/D Subsystem On But
When the A/D subsystem is turned on (ADON = 1), it requires a time,
tADON, to stabilize before accurate conversion results can be attained.
CH2-CH0 — Channel Select Bits
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CH2, CH1, and CH0 form a 3-bit field which is used to select an input
to the A/D converter. Channels 0–3 correspond to port C input pins
PC6–PC3. Channels 4–6 are used for reference measurements. In
user mode channel 7 is reserved. If a conversion is attempted with
channel 7 selected the result will be $00. Table 9-1 lists the inputs
selected by bits CH0–CH3.
If the ADON bit is set and an input from channels 0–4 is selected, the
corresponding port C pin’s DDR bit will be cleared (making that port C
pin an input). If the port C data register is read while the A/D is on and
one of the shared input channels is selected using bit CH0–CH2, the
corresponding port C pin will read as a logic 0. The remaining port C pins
will read normally. To digitally read a port C pin, the A/D subsystem must
be disabled (ADON = 0) or input channels 5–7 must be selected.
Table 9-1. A/D Multiplexer Input
Channel Assignments
Channel
Signal
0
AD0 — port C, bit 6
1
AD1 — port C, bit 5
2
AD2 — port C, bit 4
3
AD3 — port C, bit 3
4
VREFH — port C, bit 7
5
(VREFH + VSS)/2
6
VSS
7
Reserved
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Analog-to-Digital (A/D) Converter
9.6 A/D Conversion Data Register
This register contains the output of the A/D converter. See Figure 9-2.
Address:
Read:
$001D
Bit 7
6
5
4
3
2
1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
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Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 9-2. A/D Conversion Data Register (ADC)
9.7 A/D Subsystem During Wait/Halt Modes
The A/D subsystem continues normal operation during wait mode and
halt mode. To decrease power consumption during wait or halt, the
ADON bit in the ADSC register and the EERC bit in the EEPROG
register should be cleared if the A/D subsystem is not being used.
9.8 A/D Subsystem Operation During Stop Mode
When stop mode is enabled, execution of the STOP instruction will
terminate all A/D subsystem functions. Any pending conversion is
aborted. When the oscillator resumes operation upon leaving stop
mode, a finite amount of time passes before the A/D subsystem
stabilizes sufficiently to provide conversions at its rated accuracy. The
delays built into the MC68HC805P18 when coming out of stop mode are
sufficient for this purpose. No explicit delays need to be added to the
application software.
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Section 10. 16-Bit Timer
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10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
10.3
Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10.4
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
10.5
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
10.6
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
10.7
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.8
Timer Operation During Wait/Halt Modes. . . . . . . . . . . . . . . . .97
10.9
Timer Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . .97
10.2 Introduction
The MC68HC(8)05P18 MCU contains a single 16-bit programmable
timer with an input capture function and an output compare function. The
16-bit timer is driven by the output of a fixed divide-by-four prescaler
operating from the PH2 clock. The 16-bit timer may be used for many
applications including input waveform measurement, while
simultaneously generating an output waveform. Pulse widths can vary
from microseconds to seconds depending on the oscillator frequency
selected. The 16-bit timer is also capable of generating periodic
interrupts. See Figure 10-1.
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16-Bit Timer
INTERNAL HC05 BUS
OUTPUT
COMPARE
OCRH
BUFFER
FREERUNNING
COUNTER
OCRL
TMRH/
ACRH
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INPUT
CAPTURE
PH2
CLOCK
COMPARE
DETECTOR
ICRH
TMRL/
ACRL
ICRL
÷4
OVERFLOW
DETECTOR
EDGE
DETECTOR
R
R
TCAP
TCMP
>
R
TIMER
STATUS
REGISTER
OCF
TOF
RESET
ICF
INTERRUPT
GENERATOR
OCIE
TOIE
TIMER INTERRUPT
ICIE
IEDG
OLVL
TIMER
CONTROL
REGISTER
Figure 10-1. 16-Bit Timer Block Diagram
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16-Bit Timer
Timer
Because the timer has a 16-bit architecture, each function is represented
by two registers. Each register pair contains the high and low byte of that
function. Generally, accessing the low byte of a specific timer function
allows full control of that function; however, an access of the high byte
inhibits that specific timer function until the low byte is also accessed.
Freescale Semiconductor, Inc...
NOTE:
The I bit in the condition code register (CCR) should be set while
manipulating both the high and low byte registers of a specific timer
function. This prevents interrupts from occurring between the time the
high and low bytes are accessed.
10.3 Timer
The key element of the programmable timer is a 16-bit free-running
counter, or timer registers, preceded by a prescaler which divides the
PH2 clock by four. The prescaler gives the timer a resolution of 2.0
microseconds when a 4-MHz crystal is used. The counter is incremented
to increasing values during the low portion of the PH2 clock cycle.
The double byte free-running counter can be read from either of two
locations: the timer registers (TMRH and TMRL) or the alternate counter
registers (ACRH and ACRL). Both locations will contain identical values.
A read sequence containing only a read of the LSB of the counter
(TMRL/ACRL) will return the count value at the time of the read. If a read
of the counter accesses the MSB first (TMRH/ACRH), it causes the LSB
(TMRL/ACRL) to be transferred to a buffer. This buffer value remains
fixed after the first MSB byte read, even if the MSB is read several times.
The buffer is accessed when reading the counter LSB (TMRL/ACRL)
and thus completes a read sequence of the total counter value. When
reading either the timer or alternate counter registers, if the MSB is read,
the LSB must also be read to complete the read sequence. See
Figure 10-2 and Figure 10-3.
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16-Bit Timer
Register name and address: TMRH — $0018
Read:
Bit 7
6
5
4
3
2
1
Bit 0
TMRH7
TMRH6
TMRH5
TMRH4
TMRH3
TMRH2
TMRH1
TMRH0
1
1
1
1
1
1
1
1
Write:
Reset:
Freescale Semiconductor, Inc...
Register name and address: TMRL — $0019
Read:
Bit 7
6
5
4
3
2
1
Bit 0
TMRL7
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
1
1
1
1
1
1
0
0
Write:
Reset:
= Unimplemented
Figure 10-2. Timer Registers (TMRH/TMRL)
Register name and address: ACRH — $001A
Read:
Bit 7
6
5
4
3
2
1
Bit 0
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
1
1
1
1
1
1
1
1
Write:
Reset:
Register name and address: ACRL — $001B
Read:
Bit 7
6
5
4
3
2
1
Bit 0
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
1
1
1
1
1
1
0
0
Write:
Reset:
= Unimplemented
Figure 10-3. Alternate Counter Registers (ACRH/ACRL)
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16-Bit Timer
Timer
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The timer registers and alternate counter registers can be read at any
time without affecting their value. However, the alternate counter
registers differ from the timer registers in one respect: A read of the timer
register most significant bit (MSB) can clear the timer overflow flag
(TOF). Therefore, the alternate counter registers can be read at any time
without the possibility of missing timer overflow interrupts due to clearing
of the TOF. See Figure 10-4.
The free-running counter is initialized to $FFFC during reset and is a
read-only register. During power-on-reset (POR), the counter is
initialized to $FFFC and begins counting after the oscillator startup
delay. Because the counter is 16 bits preceded by a fixed divide-by-four
prescaler, the value in the counter repeats every 262,144 PH2 clock
cycles (524,288 oscillator cycles). When the free-running counter rolls
over from $FFFF to $0000, the timer overflow flag bit (TOF) in register
TSR is set. An interrupt can also be enabled when counter rollover
occurs by setting the timer overflow interrupt enable bit (TOIE) in register
TCR. See Figure 10-5.
PH2
CLOCK
16-BIT
FREE-RUNNING
COUNTER
$FFFE
$FFFF
$0000
$0001
$0002
TIMER
OVERFLOW
FLAG (TOF)
Note: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer status
register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register pair (TCRL).
Figure 10-4. State Timing Diagram for Timer Overflow
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16-Bit Timer
PH2
CLOCK
INTERNAL
RESET
16-BIT
FREE-RUNNING
COUNTER
$FFFC
$FFFD
$FFFE
$FFFF
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RESET
(EXTERNAL
OR OTHER)
NOTE: The counter and control registers are the only 16-bit timer registers affected by reset.
Figure 10-5. State Timing Diagram for Timer Reset
10.4 Output Compare
The output compare function may be used to generate an output
waveform and/or as an elapsed time indicator. All of the bits in the output
compare register pair OCRH/OCRL are readable and writable and are
not altered by the 16-bit timer’s control logic. Reset does not affect the
contents of these registers. If the output compare function is not utilized,
its registers can be used for data storage. See Figure 10-6.
Register name and address: OCRH — $0016
Read:
Bit 7
6
5
4
3
2
1
Bit 0
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
Write:
Reset:
Unaffected by reset
Register name and address: OCRL — $0017
Read:
Bit 7
6
5
4
3
2
1
Bit 0
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 10-6. Output Compare Registers (OCRH/OCRL)
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Output Compare
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The contents of the output compare registers are compared with the
contents of the free-running counter once every four PH2 clock cycles.
If a match is found, the output compare flag bit (OCF) is set and the
output level bit (OLVL) is clocked to the output latch. The values in the
output compare registers and output level bit should be changed after
each successful comparison to control an output waveform or to
establish a new elapsed timeout. An interrupt can also accompany a
successful output compare if the output compare interrupt enable bit
(OCIE) is set.
After a CPU write cycle to the MSB of the output compare register pair
(OCRH), the output compare function is inhibited until the least
significant bit (LSB) (OCRL) is written. Both bytes must be written if the
MSB is written. A write made only to the LSB will not inhibit the compare
function. The free-running counter increments every four PH2 clock
cycles. The minimum time required to update the output compare
registers is a function of software rather than hardware.
The output compare output level bit (OLVL) will be clocked to its output
latch regardless of the state of the output compare flag bit (OCF). A valid
output compare must occur before the OLVL bit is clocked to its output
latch (TCMP).
Since neither the output compare flag (OCF) nor the output compare
registers are affected by reset, care must be exercised when initializing
the output compare function. The following procedure is recommended:
1. Block interrupts by setting the I bit in the condition code register
(CCR).
2. Write the MSB of the output compare register pair (OCRH) to
inhibit further compares until the LSB is written.
3. Read the timer status register (TSR) to arm the output compare
flag (OCF).
4. Write the LSB of the output compare register pair (OCRL) to
enable the output compare function and to clear its flag (and
interrupt).
5. Unblock interrupts by clearing the I bit in the CCR.
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This procedure prevents the output compare flag bit (OCF) from being
set between the time it is read and the time the output compare registers
are updated. A software example is shown in Figure 10-7.
9B
.
.
B6
BE
B7
B6
BF
.
.
.
XX
XX
16
13
17
.
SEI
.
.
LDA
LDX
STA
LDA
STX
.
.
.
DATAH
DATAL
OCRH
TSR
OCRL
.
BLOCK INTERRUPTS
.
.
HI BYTE FOR COMPARE
LO BYTE FOR COMPARE
INHIBIT OUTPUT COMPARE
ARM OCF BIT TO CLEAR
READY FOR NEXT COMPARE
.
Figure 10-7. Output Compare Software Initialization Example
10.5 Input Capture
Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input
capture. They are used to latch the value of the free-running counter
after a defined transition is sensed by the input capture edge detector.
See Figure 10-8.
NOTE:
The input capture edge detector contains a Schmitt trigger to improve
noise immunity.
The edge that triggers the counter transfer is defined by the input edge
bit (IEDG) in register TCR. Reset does not affect the contents of the
input capture registers. See Figure 10-10.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the PH2 clock preceding
the external transition (see Figure 10-9). This delay is required for
internal synchronization. Resolution is affected by the prescaler,
allowing the free-running counter to increment once every four PH2
clock cycles.
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Input Capture
Register name and address: ICRH — $0014
Read:
Bit 7
6
5
4
3
2
1
Bit 0
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
Write:
Reset:
Unaffected by reset
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Register name and address: ICRL — $0015
Read:
Bit 7
6
5
4
3
2
1
Bit 0
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 10-8. Input Capture Registers (ICRH/ICRL)
The contents of the free-running counter are transferred to the input
capture registers on each proper signal transition regardless of the state
of the input capture flag bit (ICF) in register TSR. The input capture
registers always contain the free-running counter value which
corresponds to the most recent input capture.
After a read of the MSB of the input capture register pair (ICRH), counter
transfers are inhibited until the LSB of the register pair (ICRL) is also
read. This characteristic forces the minimum pulse period attainable to
be determined by the time required to execute an input capture software
routine in an application.
Reading the LSB of the input capture register pair (ICRL) does not inhibit
transfer of the free-running counter. Again, minimum pulse periods are
ones which allow software to read the LSB of the register pair (ICRL) and
perform needed operations. There is no conflict between reading the
LSB (ICRL) and the free-running counter transfer, since they occur on
opposite edges of the PH2 clock.
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16-Bit Timer
PH2
CLOCK
16-BIT
FREE-RUNNING
COUNTER
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
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TCAP
PIN
INPUT
CAPTURE
LATCH
INPUT
CAPTURE
REGISTER
(SEE NOTE)
$????
$FFED
INPUT
CAPTURE
FLAG
Note: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture
flag is set during the next T11 timer state.
Figure 10-9. State Timing Diagram for Input Capture
10.6 Timer Control Register
The timer control (TCR) shown in Figure 10-10 and free-running counter
(TMRH, TMRL, ACRH, and ACRL) registers are the only registers of the
16-bit timer affected by reset. The output compare port (TCMP) is forced
low after reset and remains low until OLVL is set and a valid output
compare occurs.
Address:
$0012
Bit 7
6
5
ICIE
OCIE
TOIE
0
0
0
Read:
4
3
2
0
0
0
1
Bit 0
IEDG
OLVL
0
0
Write:
Reset:
0
0
0
= Unimplemented
Figure 10-10. Timer Control Register (TCR)
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16-Bit Timer
Timer Status Register
ICIE — Input Capture Interrupt Enable Bit
Bit 7, when set, enables input capture interrupts to the CPU. The
interrupt will occur at the same time bit 7 (ICF) in the TSR register is
set.
OCIE —Output Compare Interrupt Enable Bit
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Bit 6, when set, enables output compare interrupts to the CPU. The
interrupt will occur at the same time bit 6 (OCF) in the TSR register is
set.
TOIE — Timer Overflow Interrupt Enable Bit
Bit 5, when set, enables timer overflow (rollover) interrupts to the
CPU. The interrupt will occur at the same time bit 5 (TOF) in the TSR
register is set.
IEDG — Input Capture Edge Select Bit
Bit 1 selects which edge of the input capture signal will trigger a
transfer of the contents of the free-running counter registers to the
input capture registers. Clearing this bit will select the falling edge;
setting it selects the rising edge.
OLVL — Output Compare Output Level Select Bit
Bit 0 selects the output level (high or low) that is clocked into the
output compare output latch at the next successful output compare.
10.7 Timer Status Register
Reading the timer status register (TSR) satisfies the first condition
required to clear status flags and interrupts. See Figure 10-11. The only
remaining step is to read (or write) the register associated with the active
status flag (and/or interrupt). This method does not present any
problems for input capture or output compare functions.
However, a problem can occur when using a timer interrupt function and
reading the free-running counter at random times to, for example,
measure an elapsed time. If the proper precautions are not designed into
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the application software, a timer interrupt flag (TOF) could
unintentionally be cleared if:
1. The TSR is read when bit 5 (TOF) is set.
2. The LSB of the free-running counter is read, but not for the
purpose of servicing the flag or interrupt.
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The alternate counter registers (ACRH and ACRL) contain the same
values as the timer registers (TMRH and TMRL). Registers ACRH and
ACRL can be read at any time without affecting the timer overflow flag
(TOF) or interrupt.
Address:
Read:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
Write:
Reset:
= Unimplemented
U = Unaffected
Figure 10-11. Timer Status Register (TSR)
ICF — Input Capture Flag
Bit 7 is set when the edge specified by IEDG in register TCR has been
sensed by the input capture edge detector fed by pin TCAP. This flag
and the input capture interrupt can be cleared by reading register TSR
followed by reading the LSB of the input capture register pair (ICRL).
OCF — Output Compare Flag
Bit 6 is set when the contents of the output compare registers match
the contents of the free-running counter. This flag and the output
compare interrupt can be cleared by reading register TSR followed by
writing the LSB of the output compare register pair (OCRL).
TOF — Timer Overflow Flag
Bit 5 is set by a rollover of the free-running counter from $FFFF to
$0000. This flag and the timer overflow interrupt can be cleared by
reading register TSR followed by reading the LSB of the timer register
pair (TMRL).
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16-Bit Timer
Timer Operation During Wait and Halt Modes
10.8 Timer Operation During Wait and Halt Modes
During wait and halt modes, the 16-bit timer continues to operate
normally and may generate an interrupt to trigger the MCU out of wait
and halt modes.
10.9 Timer Operation During Stop Mode
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When the MCU enters stop mode, the free-running counter stops
counting (the PH2 clock is stopped). It remains at that particular count
value until the stop mode is exited by applying a low signal to the IRQ
pin, at which time the counter resumes from its stopped value as if
nothing had happened. If stop mode is exited via an external RESET
(logic low applied to the RESET pin), the counter is forced to $FFFC.
If a valid input capture edge occurs at the TCAP pin during stop mode,
the input capture detect circuitry will be armed. This action does not set
any flags or “wake up” the MCU, but when the MCU does “wake up”
there will be an active input capture flag (and data) from the first valid
edge. If stop mode is exited by an external RESET, no input capture flag
or data will be present even if a valid input capture edge was detected
during stop mode.
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16-Bit Timer
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Section 11. Serial Input/Output Port (SIOP)
11.1 Contents
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11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
11.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . .102
11.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.4.1 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.4.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
11.4.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.2 Introduction
The simple synchronous serial input/output port (SIOP) subsystem is
designed to provide efficient serial communications between peripheral
devices or other MCUs. The SIOP is implemented as a 3-wire
master/slave system with serial clock (SCK), serial data Input (SDI), and
serial data output (SDO). A block diagram of the SIOP is shown in
Figure 11-1.
The SIOP subsystem shares its input/output pins with port B. When the
SIOP is enabled (SPE bit set in register SCR), port B data direction
registers (DDR) and data registers are modified by the SIOP. Although
port B DDR and data registers can be altered by application software,
these actions could affect the transmitted or received data.
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Serial Input/Output Port (SIOP)
HCO5 INTERNAL BUS
SPE
76543210
76543210
76543210
STATUS
8-BIT
BAUD
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CONTROL
RATE
SHIFT
REGISTER
$0A
SDO
GENERATOR
REGISTER
$0B
REGISTER
$0C
I/O
SDO/PB5
CONTROL
SDI
LOGIC
SCK
SDI/PB6
SCK/PB7
PH2 CLOCK
Figure 11-1. SIOP Block Diagram
11.3 SIOP Signal Format
The SIOP subsystem is software configurable for master or slave
operation. No external mode selection inputs are available (such as the
slave select pin).
11.3.1 Serial Clock (SCK)
The state of the serial clock (SCK) output normally remains a logic 1
during idle periods between data transfers. The first falling edge of SCK
signals the beginning of a data transfer. At this time, the first bit of
received data is accepted at the SDI pin and the first bit of transmitted
data is presented at the SDO pin (see Figure 11-2). Data is captured at
the SDI pin on the rising edge of SCK, and the first bit of transmitted data
is presented at the SDO pin. The transfer is terminated upon the eighth
rising edge of SCK.
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Serial Input/Output Port (SIOP)
SIOP Signal Format
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 6
BIT 7
SDO
SCK
100 ns
100 ns
SDI
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
Freescale Semiconductor, Inc...
Figure 11-2. SIOP Timing Diagram
The master and slave modes of operation differ only by the sourcing of
SCK. In master mode, SCK is driven from an internal source within the
MCU. In slave mode, SCK is driven from a source external to the MCU.
The SCK frequency is programmable via the mask option register 1
(MOR1). Available rates are OSC divided by 2, 4, 8, or 16.
NOTE:
OSC divided by 2 is four times faster than the standard rate available on
the 68HC05P6.
Refer to 8.5 Mask Option Registers for a description of available mask
option registers.
11.3.2 Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SIOP subsystem is
enabled. New data is presented to the SDI pin on the falling edge of
SCK. Valid data must be present at least 100 nanoseconds before the
rising edge of SCK and remain valid for 100 nanoseconds after the rising
edge of SCK. See Figure 11-2.
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Serial Input/Output Port (SIOP)
11.3.3 Serial Data Output (SDO)
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The SDO pin becomes an output as soon as the SIOP subsystem is
enabled. Prior to enabling the SIOP, PB5 can be initialized to determine
the beginning state. While the SIOP is enabled, PB5 cannot be used as
a standard output since that pin is connected to the last stage of the
SIOP serial shift register. The data can be transmitted in either MSB first
format or the LSB format by programming the MOR1.
On the first falling edge of SCK, the first data bit will be shifted out to the
SDO pin. The remaining data bits will be shifted out to the SDI pin on
subsequent falling edges of SCK. The SDO pin will present valid data at
least 100 nanoseconds before the rising edge of the SCK and remain
valid for 100 nanoseconds after the rising edge of SCK. See
Figure 11-2.
11.4 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register
(SCR) located at address $000A, the SIOP status register (SSR) located
at address $000B, and the SIOP data register (SDR) located at address
$000C.
11.4.1 SIOP Control Register
This register is located at address $000A and contains two bits.
Figure 11-3 shows the position of each bit in the register and indicates
the value of each bit after reset.
Address:
$000A
BIt 7
Read:
6
0
5
4
0
SPE
3
2
1
Bit 0
0
0
0
0
0
0
0
0
MSTR
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 11-3. SIOP Control Register (SCR)
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Serial Input/Output Port (SIOP)
SIOP Registers
SPE — Serial Peripheral Enable Bit
When set, the SPE bit enables the SIOP subsystem such that
SDO/PB5 is the serial data output, SDI/PB6 is the serial data input,
and SCK/PB7 is a serial clock input in slave mode or a serial clock
output in master mode. Port B DDR and data registers can be
manipulated as usual (except for PB5); however, these actions could
affect the transmitted or received data.
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The SPE bit is readable and writable at any time. Clearing the SPE bit
while a transmission is in progress will:
1. Abort the transmission
2. Reset the serial bit counter
3. Convert the port B/SIOP port to a general-purpose I/O port
Reset clears the SPE bit.
MSTR — Master Mode Select Bit
When set, the MSTR bit configures the serial I/O port for master
mode. A transfer is initiated by writing to the SDR. Also, the SCK pin
becomes an output providing a synchronous data clock dependent
upon the oscillator frequency. When the device is in slave mode, the
SDO and SDI pins do not change function. These pins behave exactly
the same in both the master and slave modes.
The MSTR bit is readable and writable at any time regardless of the
state of the SPE bit. Clearing the MSTR bit will abort any transfers that
may have been in progress. Reset clears the MSTR bit, placing the
SIOP subsystem in slave mode.
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Serial Input/Output Port (SIOP)
11.4.2 SIOP Status Register
This register is located at address $000B and contains two bits.
Figure 11-4 shows the position of each bit in the register and indicates
the value of each bit after reset.
Address:
Freescale Semiconductor, Inc...
Read:
$000B
BIt 7
6
5
4
3
2
1
Bit 0
SPIF
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 11-4. SIOP Status Register (SSR)
SPIF — Serial Port Interface Flag
SPIF is a read-only status bit that is set on the last rising edge of SCK
and indicates that a data transfer has been completed. It has no effect
on any future data transfers and can be ignored. The SPIF bit is
cleared by reading the SSR followed by a read or write of the SDR. If
the SPIF is cleared before the last rising edge of SCK, it will be set
again on the last rising edge of SCK. Reset clears the SPIF bit.
DCOL — Data Collision Bit
DCOL is a read-only status bit which indicates that an illegal access
of the SDR has occurred. The DCOL bit will be set when reading or
writing the SDR after the first falling edge of SCK and before SPIF is
set. Reading or writing the SDR during this time will result in invalid
data being transmitted or received.
The DCOL bit is cleared by reading the SSR (when the SPIF bit is set)
followed by a read or write of the SDR. If the last part of the clearing
sequence is done after another transfer has started, the DCOL bit will
be set again. Reset clears the DCOL bit.
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Serial Input/Output Port (SIOP)
SIOP Registers
11.4.3 SIOP Data Register
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This register is located at address $000C and serves as both the
transmit and receive data register. Writing to this register will initiate a
message transmission if the SIOP is in master mode. The SIOP
subsystem is not double buffered and any write to this register will
destroy the previous contents. The SDR can be read at any time;
however, if a transfer is in progress, the results may be ambiguous and
the DCOL bit will be set. Writing to the SDR while a transfer is in
progress can cause invalid data to be transmitted and/or received.
Figure 11-5 shows the position of each bit in the register. This register
is not affected by reset.
Address:
$000C
BIt 7
6
5
4
3
2
1
Bit 0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Read:
Write:
Reset:
Unaffected by reset
Figure 11-5. SIOP Data Register (SDR)
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Serial Input/Output Port (SIOP)
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Advance Information — MC68HC05P18/MC68HC805P18
Section 12. Instruction Set
12.1 Contents
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12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
12.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .111
12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .112
12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .112
12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .114
12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
12.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
12.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
12.2 Introduction
This section describes the addressing modes and instruction types.
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12.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes define the manner in which the CPU finds the
data required to execute an instruction.
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The eight addressing modes are:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
12.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no memory
address and are one byte long.
12.3.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no memory address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
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Addressing Modes
12.3.3 Direct
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Direct instructions can access any of the first 256 memory addresses
with two bytes. The first byte is the opcode, and the second is the low
byte of the operand address. In direct addressing, the CPU automatically
uses $00 as the high byte of the operand address. BRSET and BRCLR
are 3-byte instructions that use direct addressing to access the operand
and relative addressing to specify a branch destination.
12.3.4 Extended
Extended instructions use only three bytes to access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
12.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the conditional
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
12.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the conditional address of the operand.
These instructions can access locations $0000–$01FE.
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Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
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12.3.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the conditional address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset. These instructions can address
any location in memory.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
12.3.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the conditional branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset because the assembler determines the proper offset
and verifies that it is within the span of the branch.
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Instruction Types
12.4 Instruction Types
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The MCU instructions fall into five categories:
•
Register/memory instructions
•
Read-modify-write instructions
•
Jump/Branch instructions
•
Bit manipulation instructions
•
Control instructions
12.4.1 Register/Memory Instructions
Most of these instructions use two operands. One operand is in either
the accumulator or the index register. The CPU finds the other operand
in memory. Table 12-1 lists the register/memory instructions.
Table 12-1. Register/Memory Instructions
Instruction
Add memory byte and carry bit to accumulator
ADC
Add memory byte to accumulator
ADD
AND memory byte with accumulator
AND
Bit test accumulator
BIT
Compare accumulator
CMP
Compare index register with memory byte
CPX
EXCLUSIVE OR accumulator with memory byte
EOR
Load accumulator with memory byte
LDA
Load index register with memory byte
LDX
Multiply
MUL
OR accumulator with memory byte
ORA
Subtract memory byte and carry bit from accumulator
SBC
Store accumulator in memory
STA
Store index register in memory
STX
Subtract memory byte from accumulator
SUB
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12.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register. The test for negative or zero instruction (TST) is an
exception to the read-modify-write sequence because it does not write a
replacement value. Table 12-2 lists the read-modify-write instructions.
Table 12-2. Read-Modify-Write Instructions
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Instruction
Mnemonic
Arithmetic shift left
ASL
Arithmetic shift right
ASR
Clear bit in memory
BCLR
Set bit in memory
BSET
Clear
CLR
Complement (one’s complement)
COM
Decrement
DEC
Increment
INC
Logical shift left
LSL
Logical shift right
LSR
Negate (two’s complement)
NEG
Rotate left through carry bit
ROL
Rotate right through carry bit
ROR
Test for negative or zero
TST
12.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump- to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed. All branch instructions use relative
addressing.
Bit test and branch instructions cause a branch based on the state of any
readable bit in the first 256 memory locations. These 3-byte instructions
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Instruction Types
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use a combination of direct addressing and relative addressing. The
direct address of the byte to be tested is in the byte following the opcode.
The third byte is the signed offset byte. The CPU finds the conditional
branch destination by adding the third byte to the program counter if the
specified bit tests true. The bit to be tested and its condition (set or clear)
is part of the opcode. The span of branching is from –128 to +127 from
the address of the next location after the branch instruction. The CPU
also transfers the tested bit to the carry/borrow bit of the condition code
register. Table 12-3 lists the jump and branch instructions.
Table 12-3. Jump and Branch Instructions
Instruction
Branch if carry bit clear
BCC
Branch if carry bit set
BCS
Branch if equal
BEQ
Branch if half-carry bit clear
BHCC
Branch if half-carry bit set
BHCS
Branch if higher
BHI
Branch if higher or same
BHS
Branch if IRQ pin high
BIH
Branch if IRQ pin low
BIL
Branch if lower
BLO
Branch if lower or same
BLS
Branch if interrupt mask clear
BMC
Branch if minus
BMI
Branch if interrupt mask set
BMS
Branch if not equal
BNE
Branch if plus
BPL
Branch always
BRA
Branch if bit clear
Branch never
Branch if bit set
BRCLR
BRN
BRSET
Branch to subroutine
BSR
Unconditional jump
JMP
Jump to subroutine
JSR
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12.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory. Port registers, port data direction registers, timer registers, and
on-chip RAM locations are in the first 256 bytes of memory. The CPU
can also test and branch based on the state of any bit in any of the first
256 memory locations. Bit manipulation instructions use direct
addressing. Table 12-4 lists these instructions.
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Table 12-4. Bit Manipulation Instructions
Instruction
Mnemonic
Clear bit
BCLR
Branch if bit clear
BRCLR
Branch if bit set
BRSET
Set bit
BSET
12.4.5 Control Instructions
These register reference instructions control CPU operation during
program execution. Control instructions, listed in Table 12-5, use
inherent addressing.
Table 12-5. Control Instructions
Instruction
Mnemonic
Clear carry bit
CLC
Clear interrupt mask
CLI
No operation
NOP
Reset stack pointer
RSP
Return from interrupt
RTI
Return from subroutine
RTS
Set carry bit
SEC
Set interrupt mask
SEI
Stop oscillator and enable IRQ pin
STOP
Software interrupt
SWI
Transfer accumulator to index register
TAX
Transfer index register to accumulator
TXA
Stop CPU clock and enable interrupts
WAIT
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Instruction Set
Instruction Set Summary
12.5 Instruction Set Summary
Table 12-6 is an alphabetical list of all M68HC05 instructions
and shows the effect of each instruction on the condition code
register.
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ii
A9
B9 dd
C9 hh ll
D9 ee ff
ff
E9
F9
2
3
4
5
4
3
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
AB
BB dd
CB hh ll
DB ee ff
ff
EB
FB
2
3
4
5
4
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
ii
A4
B4 dd
C4 hh ll
D4 ee ff
ff
E4
F4
2
3
4
5
4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
↕ — ↕
A ← (A) + (M)
Add without Carry
↕ — ↕
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left
(Same as LSL)
Arithmetic Shift Right
BCC rel
Branch if Carry Bit
Clear
C
— — ↕
0
b7
↕
↕
b0
C
b7
— — ↕
↕
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
— — — — —
MC68HC(8)05P18 — Rev. 2.0
ff
ff
Cycles
↕
IMM
DIR
EXT
IX2
IX1
IX
Effect
on CCR
Description
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
MOTOROLA
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Address
Mode
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Source
Form
Operand
Table 12-6. Instruction Set Summary (Sheet 1 of 7)
5
3
3
6
5
5
3
3
6
5
3
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Cycles
Description
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
Effect
on CCR
H I N Z C
Mn ← 0
Address
Mode
Operation
Operand
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Source
Form
Opcode
Table 12-6. Instruction Set Summary (Sheet 2 of 7)
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set
(Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry
Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry
Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0
— — — — —
REL
22
rr
3
BHS rel
Branch if Higher or
Same
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
ii
A5
B5 dd
C5 hh ll
D5 ee ff
ff
E5
p
F5
2
3
4
5
4
3
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test
Accumulator with
Memory Byte
BLO rel
Branch if Lower
(Same as BCS)
BLS rel
Branch if Lower or
Same
PC ← (PC) + 2 + rel ? C ∨ Z = 1
— — — — —
REL
23
rr
3
BMC rel
Branch if Interrupt
Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt
Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
(A) ∧ (M)
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Instruction Set Summary
Operand
Cycles
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BRCLR n opr rel
Operation
PC ← (PC) + 2 + rel ? Mn = 0
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
21
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
Description
Effect
on CCR
H I N Z C
Branch if bit n clear
BRSET n opr rel
Branch if Bit n Set
BRN rel
Branch Never
PC ← (PC) + 2 + rel ? 1 = 0
Mn ← 1
Address
Mode
Source
Form
Opcode
Table 12-6. Instruction Set Summary (Sheet 3 of 7)
REL
BSET n opr
Set Bit n
BSR rel
Branch to
Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
— — 0
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
IMM
DIR
EXT
IX2
IX1
IX
ii
A1
B1 dd
C1 hh ll
D1 ee ff
ff
E1
F1
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
Clear Byte
Compare
Accumulator with
Memory Byte
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
(A) – (M)
— — ↕
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
1 —
↕
↕
dd
ff
5
3
3
6
5
2
3
4
5
4
3
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DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
Cycles
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
Description
Operand
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COM opr
COMA
COMX
COM opr,X
COM ,X
Operation
Opcode
Source
Form
Address
Mode
Table 12-6. Instruction Set Summary (Sheet 4 of 7)
DIR
INH
INH
IX1
IX
33
43
53
63
73
dd
5
3
3
6
5
1
IMM
DIR
EXT
IX2
IX1
IX
ii
A3
B3 dd
C3 hh ll
D3 ee ff
ff
E3
F3
↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
↕ —
IMM
DIR
EXT
IX2
IX1
IX
ii
A8
B8 dd
C8 hh ll
D8 ee ff
ff
E8
F8
↕ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
— — — — —
DIR
EXT
IX2
IX1
IX
BC dd
CC hh ll
DC ee ff
EC ff
FC
2
3
4
3
2
— — — — —
DIR
EXT
IX2
IX1
IX
BD dd
CD hh ll
DD ee ff
ED ff
FD
5
6
7
6
5
— — ↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A6
B6 dd
C6 hh ll
D6 ee ff
ff
E6
F6
2
3
4
5
4
3
Effect
on CCR
H I N Z C
Complement Byte
(One’s Complement)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
Compare Index
Register with
Memory Byte
(X) – (M)
Decrement Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
EXCLUSIVE OR
Accumulator with
Memory Byte
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
Increment Byte
Unconditional Jump
PC ← Jump Address
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
Load Accumulator with
Memory Byte
A ← (M)
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
Advance Information
118
↕
↕
1
↕ —
ff
dd
ff
dd
ff
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
MC68HC(8)05P18 — Rev. 2.0
Instruction Set
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MOTOROLA
Freescale Semiconductor, Inc.
Instruction Set
Instruction Set Summary
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
ii
AE
BE dd
CE hh ll
DE ee ff
ff
EE
FE
Logical Shift Left
(Same as ASL)
MUL
Unsigned Multiply
X ← (M)
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
0 — — — 0
INH
42
— — ↕
DIR
INH
INH
IX1
IX
30
40
50
60
70
— — — — —
INH
9D
2
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
ii
AA
BA dd
CA hh ll
DA ee ff
ff
EA
FA
2
3
4
5
4
3
39
49
59
69
79
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
INH
9C
— — ↕
C
0
b7
Negate Byte
(Two’s Complement)
NOP
No Operation
C
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
Logical OR
Accumulator with
Memory
A ← (A) ∨ (M)
Rotate Byte Left
through Carry Bit
b7
Rotate Byte Right
through Carry Bit
RSP
Reset Stack Pointer
↕
↕
↕
↕
— — ↕
↕
↕
b0
SP ← $00FF
— — — — —
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
↕
b0
C
b7
— — 0
— — ↕
C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
⋅
b0
X : A ← (X) × (A)
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
↕
b0
0
b7
— — ↕
↕ —
ff
ff
Cycles
Description
Load Index Register
with Memory Byte
Logical Shift Right
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
IMM
DIR
EXT
IX2
IX1
IX
Effect
on CCR
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Opcode
Freescale Semiconductor, Inc...
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Sheet 5 of 7)
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
11
ii
ff
ff
ff
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
2
Advance Information
Instruction Set
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119
Freescale Semiconductor, Inc.
Instruction Set
INH
80
6
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A2
B2 dd
C2 hh ll
D2 ee ff
ff
E2
F2
2
3
4
5
4
3
Effect
on CCR
Description
H I N Z C
↕
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
INH
A ← (A) – (M) – (C)
↕
↕
↕
↕
Cycles
Opcode
Operation
Address
Mode
Freescale Semiconductor, Inc...
Source
Form
Operand
Table 12-6. Instruction Set Summary (Sheet 6 of 7)
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte
and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
B7 dd
C7 hh ll
D7 ee ff
ff
E7
F7
4
5
6
5
4
— 0 — — —
INH
8E
2
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
BF dd
CF hh ll
DF ee ff
ff
EF
FF
4
5
6
5
4
↕
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A0
B0 dd
C0 hh ll
D0 ee ff
ff
E0
F0
2
3
4
5
4
3
— 1 — — —
INH
83
10
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in
Memory
STOP
Stop Oscillator and
Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SWI
Store Index
Register In Memory
Subtract Memory Byte
from
Accumulator
Software Interrupt
M ← (A)
M ← (X)
A ← (A) – (M)
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
— — ↕
— — ↕
Advance Information
120
↕
MC68HC(8)05P18 — Rev. 2.0
Instruction Set
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MOTOROLA
Freescale Semiconductor, Inc.
Instruction Set
Opcode Map
Test Memory Byte for
Negative or Zero
TXA
Transfer Index
Register to
Accumulator
WAIT
Stop CPU Clock and
Enable
Interrupts
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
X ← (A)
(M) – $00
A ← (X)
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
— — — — —
INH
97
— — — — —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
— — — — —
INH
9F
2
— ↕ — — —
INH
8F
2
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
Cycles
Opcode
TST opr
TSTA
TSTX
TST opr,X
TST ,X
H I N Z C
Effect
on CCR
Description
Transfer
Accumulator to Index
Register
TAX
Freescale Semiconductor, Inc...
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Sheet 7 of 7)
2
dd
ff
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
12.6 Opcode Map
The opcode map is provided in Table 12-7.
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
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121
122
5
Advance Information
Instruction Set
For More Information On This Product,
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F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
BCLR7
DIR 2
5
BSET7
DIR 2
5
BCLR6
DIR 2
5
BSET6
DIR 2
5
BCLR5
DIR 2
5
BSET5
DIR 2
5
BCLR4
DIR 2
5
BSET4
DIR 2
5
BCLR3
DIR 2
5
BSET3
3
REL 2
3
BCC
REL 2
3
BLS
REL
3
BHI
REL
3
BRN
REL 2
3
BRA
2
REL
5
5
DIR 1
5
ASR
DIR 1
5
ROR
DIR 1
LSR
DIR 1
5
COM
1
3
11
3
INH 1
3
ASRA
INH 1
3
RORA
INH 1
LSRA
INH 1
3
COMA
INH
3
MUL
INH 1
NEGA
4
3
3
3
INH 2
3
ASRX
INH 2
3
RORX
INH 2
LSRX
INH 2
3
COMX
INH 2
NEGX
5
INH
6
6
5
DIR 1
CLR
DIR 1
TST
DIR 1
4
INC
5
DIR 1
DEC
DIR 1
5
ROL
DIR 1
5
3
INH 1
CLRA
INH 1
TSTA
INH 1
3
INCA
3
INH 1
DECA
INH 1
3
ROLA
INH 1
3
3
INH 2
CLRX
INH 2
TSTX
INH 2
3
INCX
3
INH 2
DECX
INH 2
3
ROLX
INH 2
3
IX1 1
6
IX1 1
6
IX1 1
IX1 1
5
CLR
TST
INC
6
IX1 1
DEC
IX1 1
6
ROL
ASR
ROR
LSR
COM
NEG
7
IX
5
5
IX
5
IX
5
5
IX
IX 1
5
IX
IX
4
5
IX
IX
5
9
10
2
1
1
1
1
1
1
1
INH 1
WAIT
INH
2
STOP
INH
SWI
INH
RTS
INH
6
RTI
8
2
2
2
2
2
2
2
2
INH
TXA
2
2
MSB
0
4
EXT 3
STX
EXT 3
5
LDX
EXT 3
4
JSR
EXT 3
6
JMP
EXT 3
3
ADD
EXT 3
4
ORA
EXT 3
4
ADC
EXT 3
4
EOR
EXT 3
4
STA
EXT 3
5
LDA
EXT 3
4
BIT
EXT 3
4
AND
EXT 3
4
CPX
EXT 3
4
SBC
EXT 3
4
CMP
EXT 3
4
SUB
3
IX2 2
5
IX2 2
6
STX
LDX
JSR
IX2 2
IX2 2
6
IX2 2
5
IX2 2
7
JMP
IX2 2
4
ADD
IX2 2
5
ORA
IX2 2
5
ADC
IX2 2
5
EOR
STA
LDA
IX2 2
5
IX2 2
5
AND
IX2 2
5
CPX
IX2 2
5
SBC
IX2 2
5
CMP
BIT
5
IX2 2
5
SUB
D
IX2
IX1 1
4
IX1 1
5
STX
LDX
JSR
IX1 1
IX1 1
5
IX1 1
4
IX1 1
6
JMP
IX1 1
3
ADD
IX1 1
4
ORA
IX1 1
4
ADC
IX1 1
4
EOR
STA
LDA
IX1 1
4
IX1 1
4
AND
IX1 1
4
CPX
IX1 1
4
SBC
IX1 1
4
CMP
BIT
5 Number of Cycles
DIR Number of Bytes/Addressing Mode
4
IX1 1
4
SUB
E
IX1
MSB of Opcode in Hexadecimal
DIR 3
STX
DIR 3
4
LDX
DIR 3
3
JSR
DIR 3
5
JMP
DIR 3
2
ADD
DIR 3
3
ORA
DIR 3
3
ADC
DIR 3
3
EOR
DIR 3
3
STA
DIR 3
4
LDA
DIR 3
3
DIR 3
3
AND
DIR 3
3
CPX
DIR 3
3
SBC
DIR 3
3
CMP
BIT
3
C
EXT
Register/Memory
DIR 3
3
SUB
B
DIR
BRSET0 Opcode Mnemonic
2
IMM 2
LDX
REL 2
2
BSR
6
IMM 2
ADD
IMM 2
2
ORA
IMM 2
2
ADC
0
2
IMM 2
2
EOR
2
IMM 2
LDA
IMM 2
2
BIT
IMM 2
2
AND
IMM 2
2
CPX
IMM 2
2
SBC
IMM 2
2
CMP
IMM 2
2
SUB
A
IMM
LSB
2
INH 2
NOP
INH
2
RSP
INH 2
2
SEI
INH 2
2
INH 2
2
SEC
INH 2
2
CLC
CLI
2
INH
2
TAX
9
INH
Control
INH
LSB of Opcode in Hexadecimal
CLR
TST
INC
DEC
ROL
IX
5
1
IX 1
5
1
IX 1
ASL/LSL
IX1 1
6
ASR
IX1 1
6
ROR
IX1 1
IX1 1
6
COM
LSR
6
IX1 1
NEG
6
IX1
Read-Modify-Write
INH
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
REL 2
BIH
REL
3
BIL
REL 2
3
BMS
REL 2
3
BMC
REL
3
BMI
REL 2
3
BPL
REL 2
3
BHCS
5
DIR 1
NEG
3
DIR
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL
REL 2
3
BHCC
REL 2
3
BEQ
REL 2
3
BNE
REL
3
BCS/BLO
DIR 2
5
BCLR2
DIR 2
5
BSET2
DIR 2
5
BCLR1
DIR 2
5
BSET1
DIR 2
5
BCLR0
DIR 2
5
BSET0
1
DIR
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
3
BRCLR7
3
BRSET7
3
BRCLR6
3
BRSET6
3
BRCLR5
3
BRSET5
3
BRCLR4
3
BRSET4
3
BRCLR3
3
BRSET3
3
BRCLR2
3
BRSET2
3
BRCLR1
3
BRSET1
3
BRCLR0
DIR 2
5
BRSET0
0
3
0
MSB
LSB
DIR
Bit Manipulation Branch
Table 12-7. Opcode Map
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
3
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
Instruction Set
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
Freescale Semiconductor, Inc.
Advance Information — MC68HC05P18/MC68HC805P18
Section 13. Electrical Specifications
Freescale Semiconductor, Inc...
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
13.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
13.4
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .124
13.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
13.6
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
13.7
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .126
13.8
Active Reset Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .127
13.9
A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . .127
13.10 SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
13.11 PD5 Clock Out Timing (PD5 CLKOUT Option Enabled) . . . .129
13.12 Control Timing (MC68HC805P18
and Low-Speed MC68HC05P18) . . . . . . . . . . . . . . . . . . .130
13.13 Control Timing (High-Speed MC68HC05P18 Only) . . . . . . . .130
13.2 Introduction
This section contains electrical and timing specifications.
MC68HC(8)05P18 — Rev. 2.0
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Electrical Specifications
13.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
Freescale Semiconductor, Inc...
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to + 7.0
V
Input voltage
VIn
VSS –0.3
to VDD + 0.3
V
Factory mode (IRQ pin only)
VIn
VSS –0.3
to 2 x VDD
V
I
25
mA
TSTG
–65 to +150
°C
Current drain per pin excluding VDD and VSS
Storage temperature range
Note: Voltages referenced to VSS
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 13.7 DC Electrical Characteristics for guaranteed
operating conditions.
13.4 Operating Temperature Range
Rating
Symbol
Value
Unit
TA
TL to TH
0 to +70
–40 to +85
–40 to +125
°C
Operating temperature range
MC68HC805P18 (standard)
MC68HC805P18 (extended)
MC68HC805P18 (automotive)
Advance Information
124
MC68HC(8)05P18 — Rev. 2.0
Electrical Specifications
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Electrical Specifications
Thermal Characteristics
13.5 Thermal Characteristics
Characteristic
Symbol
Value
Unit
θJA
60
60
°C/W
Thermal resistance
Plastic
SOIC
13.6 Power Considerations
Freescale Semiconductor, Inc...
The average chip-junction temperature, TJ, in °C, can be obtained from:
TJ = TA + (PD × θJA)
(1)
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction to ambient, °C/W
PD = PINT + PI/O
PINT = IDD × VDD watts (chip internal power)
PI/O = Power dissipation on input and output pins (user-determined)
For most applications, PI/O « PINT and can be neglected.
The following is an approximate relationship between PD and TJ
(neglecting PI/O):
PD = K ÷ (TJ + 273°C)
(2)
Solving equations (1) and (2) for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
MC68HC(8)05P18 — Rev. 2.0
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Electrical Specifications
13.7 DC Electrical Characteristics
Characteristic(1)
Freescale Semiconductor, Inc...
Output voltage
ILoad = 10.0 µA
Output high voltage
ILoad = –0.8 mA: PA0–PA7, PB5–PB7, PC2–PC7, PD5/CKOUT
ILoad = –5 mA: PC0, PC1
Output low voltage
ILoad = 1.6 mA: PA0–PA7, PB5–PB7, PC2–PC7, PD5/CKOUT
ILoad = 10 mA: PC0, PC1
Input high voltage
PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT, TCAP/PD7, IRQ,
RESET, OSC1
Input low voltage
PA0–PA7, PB5–PB7, PC0–PC7, PD5, TCAP/PD7, IRQ, RESET,
OSC1
Supply current(2) (3) (4) (5) (6) (7)
Low frequency (2-MHz bus)
Run
Wait (A2D on)
Wait (A2D off)
High frequency (4-MHz bus) MC68HC05P18 only
Run
Wait (A2D on)
Wait (A2D off)
Stop (–40°C to +132°C)
Stop LVR disabled
Stop LVR enabled
I/O ports hi-z leakage current
PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT, TCAP/PD7
I/O ports switch resistance (pullup enabled PA0–PA7)
A/D ports hi-z leakage current
PC3–PC7
Input current
RESET, IRQ, OSC1
Capacitance
Ports (as input or output)
RESET, IRQ
EEPROM program/erase time (128 byte array)
Byte
Block (erase only)
Bulk (erase only)
Low-voltage reset voltage
Symbol
VOL
VOH
Min
Max
Unit
—
VDD –0.1
0.1
—
V
VOH
VDD –0.8
—
V
VOL
—
0.4
V
VIH
0.7 x VDD
VDD
V
VIL
VSS
0.2 x VDD
V
—
—
—
4
3.5
2.5
mA
mA
mA
—
—
—
6
4.5
3.5
mA
mA
mA
—
—
50
200
µA
µA
IIL
—
±10
µA
RPTA
7
30
k
IIL
—
±1
µA
IIN
—
±1
µA
COut
CIn
—
—
12
8
pF
—
—
—
3.5
5
15
50
4.3
IDD
—
—
ms
V
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, all values shown reflect average measurements.
2. Run (operating) IDD, wait IDD: Measured using external square wave clock source (fosc = 4.2 MHz), all inputs
0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2
3. Wait IDD with active systems: timer, SIOP, and A/D. Wait IDD is affected linearly by the OSC2 capacitance.
4. Wait, stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V
5. Stop IDD measured with OSC1 = VSS. Stop IDD maximum values given with LVR option enabled.
6. Run and wait IDD limit values are with no load on PD5 clock out, when PD5 is enabled.
7. Run and wait IDD values are for both PD5 enabled and disabled and LVR enabled and disabled.
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Electrical Specifications
Active Reset Characteristics
13.8 Active Reset Characteristics
Rise Time(1)
Fall Time
Pulse Width
CLoad
Pullup
0.5 µs
13 ns
2.4 µs
50 pF
10 K
1.0 µs
20 ns
2.7 µs
100 pF
10 K
2.5 µs
20 ns
2.7 µs
250 pF
10 K
Freescale Semiconductor, Inc...
1. VDD = 4.5 Vdc, VSS = 0 Vdc, TA = 125°C
13.9 A/D Converter Characteristics
Characteristic(1)
Min
Max
Unit
Resolution
8
8
Bits
Absolute accuracy
(VDD ≥ VREFH > 4.5)
—
± 1 1/2
LSB
VSS
VSS
VREFH
VDD
V
—
—
±1
±1
µA
32
32
tAD(2)
Conversion range, VREFH
Input leakage
AD0, AD1, AD2, AD3
VREFH
Conversion time
(includes sampling time)
Monotonicity
Comments
Including quantization
A/D accuracy may decrease
proportionately as VREFH is reduced
below 4.5
Inherent (within total error)
Zero input reading
00
00
01
03
Hex
VIn = 0 V (external)
VIn = 0 V (internal)
Full-scale reading
FE
FF
Hex
VIn = VREFH
Sample time
12
12
tAD*
Input capacitance
—
12
pF
VSS
VREFH
V
Analog input voltage
1. VDD = 4.5 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted
2. tAD = tCYC if clock source equals MCU
MC68HC(8)05P18 — Rev. 2.0
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13.10 SIOP Timing
Characteristic(1)
Freescale Semiconductor, Inc...
Number
Symbol
Min
Max
Unit
Operating frequency(2)
Master
Slave
fSIOP(M)
fSIOP(S)
1
dc
1
1
fOP
1
Cycle time
Master
Slave
tSCK(M)
tSCK(S)
1
—
1
1
tCYC
2
SCK low time(3)
tCYC
238
—
ns
3
SDO data valid time
tv
—
200
ns
4
SDO hold time
tHO
0
—
ns
5
SDI setup time
tS
100
—
ns
6
SDI hold time
tH
100
—
ns
1. VDD = 4.5 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted
2. fOP = fOSC ÷ 2; tCYC = 1 ÷ fOP
3. In master mode, the SCK rate is determined by the programmable option in MOR1.
t2
t1
SCK
t5
SDI
SDI
SDI
t3
SDI
t6
SDI
t4
SDI
SDI
BIT 7
Figure 13-1. SIOP Timing Diagram
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Electrical Specifications
PD5 Clock Out Timing (PD5 CLKOUT Option Enabled)
13.11 PD5 Clock Out Timing (PD5 CLKOUT Option Enabled)
Symbol(1)
Min
Max
Unit
Cycle time
1(1)
tCYC
—
ns
Rise time
4(1)
3.5
12
ns
Fall time
5(1)
7.5
27.5
ns
2 and 3(1)
tOH, tOL
—
ns
Characteristic
Freescale Semiconductor, Inc...
Pulse width
1. The numbers shown in the symbol column correspond to those shown in Figure 13-2.
(1)
(2)
(3)
PD5 CLOCK OUT
(4)
(5)
Figure 13-2. PD5 Clock Out Timing
NOTE:
All timing is shown with respect to 20% and 70% VDD. Maximum rise and
fall times assume 44% duty cycle. Minimum rise and fall times assume
55% duty cycle.
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13.12 Control Timing (MC68HC805P18 and Low-Speed MC68HC05P18)
Freescale Semiconductor, Inc...
Characteristic(1)
Frequency of operation
Crystal option
External clock option
Internal operating frequency
Crystal (fOSC ÷ 2)
External clock (fOSC ÷ 2)
Symbol
Min
Max
Unit
fOSC
—
dc
4.2
4.2
MHz
fOP
—
dc
2.1
2.1
MHz
Cycle time
tCYC
476
—
ns
Crystal oscillator startup time
tOXOV
—
100
ms
Stop recovery startup time (crystal oscillator)
tILCH
—
100
ms
RESET pulse width
tRL
1.5
—
tCYC
Interrupt pulse width low (edge-triggered)
tILIH
125
—
ns
tILIL
(2)
—
tCYC
tOH, tOL
200
—
ns
A/D on current stabilization time
tADON
—
100
µs
RC oscillator stabilization time (A/D)
tRCON
—
5.0
µs
Interrupt pulse period
OSC1 pulse width
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted
2. The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine
plus 21 tCYC.
13.13 Control Timing (High-Speed MC68HC05P18 Only)
Characteristic(1)
Frequency of operation
Crystal option
External clock option
Internal operating frequency
Crystal (fOSC ÷ 2)
External clock (fOSC ÷ 2)
Symbol
Min
Max
Unit
fOSC
—
dc
4.2
8.4
MHz
fOP
—
dc
2.1
4.2
MHz
Cycle time
tCYC
238
—
ns
Crystal oscillator startup time
tOXOV
—
100
ms
Stop recovery startup time (crystal oscillator)
tILCH
—
100
ms
RESET pulse width
tRL
1.5
—
tCYC
Interrupt pulse width low (edge-triggered)
tILIH
125
—
ns
tILIL
(2)
—
tCYC
tOH, tOL
100
—
ns
A/D on current stabilization time
tADON
—
100
µs
RC oscillator stabilization time (A/D)
tRCON
—
5.0
µs
Interrupt pulse period
OSC1 pulse width
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted
2. The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine
plus 21 tCYC.
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Electrical Specifications
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MOTOROLA
NEW
PCH
INTERNAL
DATA
BUS1
NEW
PCL
3FFF
tCYC
NEW PC
OP
CODE
NEW PC
NOTE 3
tRL
3FFE
3FFE
MC68HC(8)05P18 — Rev. 2.0
Electrical Specifications
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3FFE
PCH
3FFE
PCL
3FFF
Figure 13-3. Power-On Reset and External Reset Timing Diagram
Notes:
1. Internal timing signal and bus information not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the PH2 clock following the rising edge of RESET initiates the reset sequence.
RESET
3FFE
4064 tCYC
VDD THRESHOLD (1–2 V TYPICAL)
INTERNAL
ADDRESS
BUS1
INTERNAL
PROCESSOR
CLOCK1
OSC12
VDD
tVDDR
Freescale Semiconductor, Inc...
NEW PC
OP
CODE
NEW PC
Freescale Semiconductor, Inc.
Electrical Specifications
Control Timing (High-Speed MC68HC05P18 Only)
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Electrical Specifications
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Freescale Semiconductor, Inc.
Advance Information — MC68HC05P18/MC68HC805P18
Section 14. Mechanical Specifications
Freescale Semiconductor, Inc...
14.1 Contents
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
14.3
28-Pin Dual In-Line Package (Case #710) . . . . . . . . . . . . . . .134
14.4
28-Pin Small Outline Package (Case #751F) . . . . . . . . . . . . .134
14.2 Introduction
This section provides package dimension drawings for the 28-pin dual
in-line (DIP) or 28-pin small outline (SOIC) packages.
To make sure that you have the latest case outline specifications,
contact one of the following:
•
Local Motorola Sales Office
•
Motorola Mfax
– Phone 602-244-6609
– EMAIL [email protected]
•
Worldwide Web (wwweb) at http://design-net.com
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
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Mechanical Specifications
14.3 28-Pin Dual In-Line Package (Case #710)
28
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
15
B
1
14
Freescale Semiconductor, Inc...
A
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
N
H
G
F
D
M
K
J
SEATING
PLANE
MILLIMETERS
MIN
MAX
36.45 37.21
13.72 14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
0°
15°
0.51
1.02
INCHES
MIN
MAX
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 BSC
0.065 0.085
0.008 0.015
0.115 0.135
0.600 BSC
0°
15°
0.020 0.040
14.4 28-Pin Small Outline Package (Case #751F)
-A28
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
15
14X
-B1
P
0.010 (0.25)
M
B
M
14
28X D
0.010 (0.25)
M
T
A
S
B
M
S
R X 45°
C
-T26X
-T-
G
K
SEATING
PLANE
F
J
Advance Information
134
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
17.80 18.05
7.60
7.40
2.65
2.35
0.49
0.35
0.90
0.41
1.27 BSC
0.32
0.23
0.29
0.13
8°
0°
10.05 10.55
0.75
0.25
INCHES
MIN
MAX
0.701 0.711
0.292 0.299
0.093 0.104
0.014 0.019
0.016 0.035
0.050 BSC
0.009 0.013
0.005 0.011
8°
0°
0.395 0.415
0.010 0.029
MC68HC(8)05P18 — Rev. 2.0
Mechanical Specifications
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Advance Information — MC68HC05P18/MC68HC805P18
Section 15. Ordering Information
Freescale Semiconductor, Inc...
15.1 Contents
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
15.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
15.2 Introduction
This section contains instructions for ordering the MC68HC05P18 and
the MC68HC805P18.
15.3 MC Order Numbers
Table 15-1 shows the MC order numbers for the available package
types.
Table 15-1. MC Order Numbers
MC Order Number(1)
Operating
Temperature Range
MC68HC805P18P (standard)
0°C to 70°C
MC68HC805P18DW (standard)
0°C to 70°C
MC68HC805P18CP (extended)
–40°C to +85°C
MC68HC805P18CDW (extended)
–40°C to +85°C
MC68HC805P18MP (automotive)
–40°C to +125°C
MC68HC805P18MDW (automotive)
–40°C to +125°C
1. P = Plastic dual in-line package
DW = Small outline (wide body) package
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Ordering Information
Advance Information
136
MC68HC(8)05P18 — Rev. 2.0
Ordering Information
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Appendix A. Emulation
Freescale Semiconductor, Inc...
A.1 Contents
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.3
Functional Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.4
Mask Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
A.2 Introduction
This appendix discusses the functional differences between the P-series
devices. The MC68HC805P18 can be used to emulate these devices:
MC68HC05P1A
MC68HC05P7
MC68HC05P2
MC68HC05P7A
MC68HC05P3
MC68HC05P8
MC68HC05P4
MC68HC05P9
MC68HC05P4A
MC68HC705P9
MC68HC05P6
MC68HC05P10
MC68HC705P6
MC68HC05P18
A.3 Functional Differences
The functional differences will be summarized in:
Table A-1. Elements of Memory
Table A-2. Memory Breakdown by Types
Table A-3. P-Series Features
Table A-4. Mask Options
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Emulation
Freescale Semiconductor, Inc...
Table A-1. Elements of Memory
Device
RAM
User ROM
EPROM
EEPROM
User
EEPROM
ROM
Security
P1A
128 b
0080-00FF
R 2320 b
0020-004F
0100-08FF*
N
N
N
N
P2
96 b
00A0-00FF
R 3088 b
0020-004F
1300-1EFF
N
N
N
N
P3
128 b
0080-00FF
R 3072 b
0020-004F
0300-0EFF
N
128 b
0100-017F
N
N
705P3
128 b
0080-00FF
N
3072 b
0020-004F
0300-0EFF
128 b
0100-017F
N
N
P4/P4A
176 b
0050-00FF
R 4160 b
0020-004F
0100-10FF
N
N
N
N/Y
P6
176 b
0050-00FF
R 4672 b
0020-004F
0100-10FF*
N
N
N
N
705P6
176 b
0050-00FF
N
4672 b
0020-004F
0100-12FF*
N
N
N
P7/P7A
128 b
0080-00FF
R 2112 b
0020-004F
0100-08FF*
N
N
N
N/Y
P8
112 b
0090-00FF
R 2064 b
1680-1E7F
N
32 b
0030-004F
N
N
P9/P9A
128 b
0080-00FF
R 2112 b
0020-004F
0100-08FF
N
N
N
N/Y
705P9
128 b
0080-00FF
N
2112 b
0020-004F
0100-08FF*
N
N
N
P10
128 b
0080-00FF
R 4160 b
0020-004F
0100-10FF
N
N
N
N
P18
192 b
0050-010F
R 8064 b
0020-004F
1FC0-3EFF
N
128 b
0140-01BF
N
N
805P18
192 b
0050-010F
N
N
128 b
0140-01BF
8064 b
0020-004F
1FC0-3EFF
Y
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Emulation
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Emulation
Functional Differences
Table A-2. Memory Breakdown by Types
Range
P1A
P2
P3/
705P3
P4/
P4A
P6
705
P6
P7/
P7A
0020–004F
ROM
ROM
ROM/E
ROM
ROM
ROM
ROM
0030–004F
P10
P18
805
P18
ROM/E
ROM
ROM
UEE
RAM
RAM
EE
0050–007F
Freescale Semiconductor, Inc...
P9/
705P9
P8
RAM
RAM
RAM
0080–008F
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
0090–009F
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
00A0–00FF
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
0100–010F
ROM
EE
ROM
ROM
E
ROM
ROME
ROM
RAM
RAM
0110–013F
ROM
EE
ROM
ROM
E
ROM
ROME
ROM
0140–017F
ROM
EE
ROM
ROM
E
ROM
ROME
ROM
EE
EE
0180–01BF
ROM
ROM
ROM
E
ROM
ROME
ROM
EE
EE
01C0–02D1
ROM
ROM
ROM
E
ROM
ROME
ROM
02D2–02FF
ROM
ROM
ROM
E
ROM
ROME
ROM
0300–08FF
ROM
ROME
ROM
ROM
E
ROM
ROME
ROM
0900–0EFF
ROME
RON
ROM
E
ROM
0F00–0FEF
ROM
ROM
ROM
E
ROM
ROM
ROM
E
ROM
ROM
E
RAM
0FF0–10FF
1100–12FF
1300–167F
ROM
1680–1EFF
ROM
1F00
ROM
ROM
1F01–1FBF
ROM
ROM
ROM
1FC0–1FEF
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
1FF0–3EFF
ROM
UEE
ROM
UEE
3F00–3F01
UEE
3F02–3FEF
ROM
NOTE: I/O registers are common to all parts so they are not included in the table. There are an additional 16 bytes
of user vectors in the memory map for each device.
E = EPROM
EE = EEPROM
PEE = User EEPROM
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Table A-3. P-Series Features
Devices
Mask Option
MOR
A/D
LVR
High Current
P1A
Y
N
N
N
Y
P2
Y
N
N
N
N
P3/705P3
Y/N
N/Y
N
N
N
P4/P4A
Y
N
N
N
N/Y
P6/705P6
Y/N
N/Y
Y
N
N
P7/P7A
Y
N
N
N
N/Y
P8
Y
N
Y
N
N
P9/705P9/P9A
Y/N/Y
N/Y/N
Y
N
N/N/Y
P10
Y
N
N
N
N
P18/805P18
Y/N
N/Y
Y
Y
Y
Table A-4. Mask Options
Devices
XTAL/RC
SIOP
Clock Rate
SIOP
MSB/LSB
Port A
PU/INT
STOP
to HALT
P1A
Y
N
N
Y
Y
P2
Y
N
N
N
N
P3
N
N
N
N
N
P4/P4A
Y
N
Y
N/Y
N/Y
P6
Y
Y
Y
N
Y
P7/P7A
Y
N
Y
N/Y
N/Y
P8
N
N
N
N
N
P9/P9A
N
N
Y
N/Y
N/Y
P10
Y
N
Y
Y
N
P18
N
Y(1)
Y
Y
Y
1. The MC68HC05P18 and MC68HC805P18 have selectable clock rates that are four times as fast as the MC68HC05P6
selectable rates.
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140
MC68HC(8)05P18 — Rev. 2.0
Emulation
For More Information On This Product,
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MOTOROLA
Freescale Semiconductor, Inc.
Emulation
Mask Option Registers
A.4 Mask Option Registers
Address:
Read:
$0F
Bit 7
6
5
4
3
2
1
Bit 0
0
1
0
0
1
0
OPTCOP
OPTIRQ
Write:
Reset:
Unaffected by reset
Freescale Semiconductor, Inc...
= Unimplemented
Figure A-1. MC68HC705P3 Mask Option Register
Address:
Read:
$900
Bit 7
6
5
4
3
2
1
Bit 0
—
RC
SWAIT
SPR1
SPR0
LSBF
IRQ
COP
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure A-2. MC68HC705P6 Mask Option Register
Address:
Read:
$900
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
SIOP
IRQ
COP
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure A-3. MC68HC705P9 Mask Option Register
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
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Emulation
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Freescale Semiconductor, Inc.
Emulation
Address:
$3F00
Bit 7
Read: CLKOUT
6
5
4
3
2
1
Bit 0
LVRE
SWAIT
SPR1
SPR0
LSBF
LEVIRQ
COPEN
Write:
Reset:
Unaffected by reset
= Unimplemented
Freescale Semiconductor, Inc...
Figure A-4. MC68HC805P8 Mask Option Register 1
Address:
Read:
$3F01
Bit 7
6
5
4
3
2
1
Bit 0
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure A-5. MC68HC805P8 Mask Option Register 2
Advance Information
142
MC68HC(8)05P18 — Rev. 2.0
Emulation
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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