MC74HCT04A Hex Inverter With LSTTL–Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT04A may be used as a level converter for interfacing TTL or NMOS outputs to High–Speed CMOS inputs. The HCT04A is identical in pinout to the LS04. • • • • • • • http://onsemi.com MARKING DIAGRAMS Output Drive Capability: 10 LSTTL Loads TTL/NMOS–Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5V Low Input Current: 1µA In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 48 FETs or 12 Equivalent Gates 14 PDIP–14 N SUFFIX CASE 646 MC74HCT04AN AWLYYWW 1 14 SOIC–14 D SUFFIX CASE 751A HCT04A AWLYWW LOGIC DIAGRAM 1 14 A1 A2 A3 1 2 3 4 5 6 9 8 Y2 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week Y3 Y=A A4 A5 A6 11 10 13 12 HCT 04A ALYW TSSOP–14 DT SUFFIX CASE 948G Y1 Pin 14 = VCC Pin 7 = GND Y4 FUNCTION TABLE Inputs Outputs A Y L H H L Y5 Y6 Pinout: 14–Lead Packages (Top View) VCC A6 Y6 A5 Y5 A4 Y4 14 13 12 11 10 9 8 ORDERING INFORMATION Device 1 A1 2 Y1 3 A2 4 Y2 Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 7 5 A3 6 Y3 7 GND 1 Package Shipping MC74HCT04AN PDIP–14 2000 / Box MC74HCT04AD SOIC–14 55 / Rail MC74HCT04ADR2 SOIC–14 2500 / Reel MC74HCT04ADT TSSOP–14 96 / Rail MC74HCT04ADTR2 TSSOP–14 2500 / Reel Publication Order Number: MC74HCT04A/D MC74HCT04A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit – 0.5 to + 7.0 V Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 50 mA PD Power Dissipation in Still Air 750 500 450 mW Tstg Storage Temperature Range – 65 to + 150 _C Iin TL Plastic DIP† SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package 260 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Figure 1) Max Unit 4.5 5.5 V 0 VCC V – 55 + 125 _C 0 500 ns http://onsemi.com 2 MC74HCT04A DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Guaranteed Limit VCC V –55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High–Level Input Voltage Vout = 0.1V |Iout| ≤ 20µA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low–Level Input Voltage Vout = VCC – 0.1V |Iout| ≤ 20µA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum High–Level Output Voltage Vin = VIL |Iout| ≤ 20µA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V 4.5 3.98 3.84 3.70 VOL Maximum Low–Level Output Voltage 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 4.5 0.26 0.33 0.40 |Iout| ≤ 4.0mA Vin = VIL Vin = VIH |Iout| ≤ 20µA |Iout| ≤ 4.0mA Vin = VIH V Maximum Input Leakage Current Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0µA 5.5 1 10 40 µA ∆ICC Additional Quiescent Supply Current Vin = 2.4V, Any One Input Vin GND Other Inputs i = VCC or GND, Iout = 0µA Iin 5.5 ≥ –55°C 25 to 125°C 2.9 2.4 mA 1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). 2. Total Supply Current = ICC + Σ∆ICC. AC CHARACTERISTICS (VCC = 5.0V ±10%, CL = 50pF, Input tr = tf = 6ns) Guaranteed Limit Symbol Parameter –55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2) 15 17 19 21 22 26 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 15 19 22 ns Maximum Input Capacitance 10 10 10 pF Cin NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Inverter)* 22 pF * Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). http://onsemi.com 3 MC74HCT04A tf INPUT A tr 3.0V 2.7V 1.3V 0.3V GND tPLH tPHL 90% 1.3V 10% OUTPUT Y tTLH tTHL Figure 1. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance Figure 2. Test Circuit A Y Figure 3. Expanded Logic Diagram (1/6 of the Device Shown) http://onsemi.com 4 MC74HCT04A PACKAGE DIMENSIONS PDIP–14 N SUFFIX CASE 646–06 ISSUE L 14 8 1 7 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. B A F DIM A B C D F G H J K L M N L C J N H G D SEATING PLANE K M INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 SOIC–14 D SUFFIX CASE 751A–03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 14 8 –B– 1 P 7 PL 0.25 (0.010) 7 G B M M R X 45 _ C F –T– SEATING PLANE D 14 PL 0.25 (0.010) M K M T B S A S http://onsemi.com 5 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC74HCT04A PACKAGE DIMENSIONS TSSOP–14 DT SUFFIX CASE 948G–01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. S S N 2X 14 L/2 0.25 (0.010) 8 M B –U– L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K ÉÉ ÇÇ ÇÇ ÉÉ A –V– K1 J J1 SECTION N–N –W– C 0.10 (0.004) –T– SEATING PLANE D G H DETAIL E http://onsemi.com 6 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HCT04A Notes http://onsemi.com 7 MC74HCT04A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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