Cypress CY7C68013-56PVC Ez-usb fx usb microcontroller high-speed usb peripheral controller Datasheet

68013
CY7C68013
CY7C68013
EZ-USB® FX2™ USB Microcontroller
High-Speed USB Peripheral Controller
Cypress Semiconductor Corporation
Document #: 38-08012 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised June 21, 2002
CY7C68013
TABLE OF CONTENTS
1.0 EZ-USB® FX2™ FEATURES ........................................................................................................... 5
2.0 APPLICATIONS ............................................................................................................................... 6
3.0 FUNCTIONAL OVERVIEW .............................................................................................................. 6
3.1 USB Signaling Speed ..................................................................................................................... 6
3.2 8051 Microprocessor ...................................................................................................................... 6
3.3 I2C-compatible Bus ......................................................................................................................... 7
3.4 Buses ............................................................................................................................................... 7
3.5 USB Boot Methods ......................................................................................................................... 8
3.6 ReNumeration™ .............................................................................................................................. 8
3.7 Interrupt System ............................................................................................................................. 9
3.8 Reset and Wakeup ........................................................................................................................ 10
3.9 Program/Data RAM ....................................................................................................................... 10
3.10 Register Addresses .................................................................................................................... 13
3.11 Endpoint RAM ............................................................................................................................. 13
3.12 External FIFO interface .............................................................................................................. 15
3.13 GPIF ............................................................................................................................................. 15
3.14 USB Uploads and Downloads ................................................................................................... 16
3.15 Autopointer Access .................................................................................................................... 16
3.16 I2C-compatible Controller .......................................................................................................... 16
4.0 PIN ASSIGNMENTS ...................................................................................................................... 17
4.1 CY7C68013 Pin Descriptions ....................................................................................................... 23
5.0 REGISTER SUMMARY .................................................................................................................. 30
6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 36
7.0 OPERATING CONDITIONS ........................................................................................................... 36
8.0 DC CHARACTERISTICS ............................................................................................................... 36
8.1 USB Transceiver ........................................................................................................................... 36
9.0 AC ELECTRICAL CHARACTERISTICS ....................................................................................... 37
9.1 USB Transceiver ........................................................................................................................... 37
9.2 Program Memory Read ................................................................................................................ 37
9.3 Data Memory Read ....................................................................................................................... 38
9.4 Data Memory Write ....................................................................................................................... 39
9.5 GPIF Synchronous Signals .......................................................................................................... 40
9.6 Slave FIFO Synchronous Read ................................................................................................... 41
9.7 Slave FIFO Asynchronous Read ................................................................................................. 42
9.8 Slave FIFO Synchronous Write ................................................................................................... 42
9.9 Slave FIFO Asynchronous Write ................................................................................................. 43
9.10 Slave FIFO Synchronous Packet End Strobe .......................................................................... 43
9.11 Slave FIFO Asynchronous Packet End Strobe ........................................................................ 44
9.12 Slave FIFO Output Enable .......................................................................................................... 44
9.13 Slave FIFO Address to Flags/Data ............................................................................................ 44
9.14 Slave FIFO Synchronous Address ............................................................................................ 45
9.15 Slave FIFO Asynchronous Address .......................................................................................... 45
10.0 ORDERING INFORMATION ........................................................................................................ 45
11.0 PACKAGE DIAGRAMS ............................................................................................................... 46
Document #: 38-08012 Rev. *B
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CY7C68013
LIST OF FIGURES
Figure 1-1. Block Diagram .................................................................................................................... 5
Figure 3-1. Internal Code Memory, EA = 0......................................................................................... 11
Figure 3-2. External Code Memory, EA = 1........................................................................................ 12
Figure 3-3. Endpoint Configuration ................................................................................................... 14
Figure 4-1. Signals ............................................................................................................................... 18
Figure 4-2. CY7C68013 128-pin TQFP Pin Assignment.................................................................... 19
Figure 4-3. CY7C68013 100-pin TQFP Pin Assignment.................................................................... 20
Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment ..................................................................... 21
Figure 4-5. CY7C68013 56-pin QFN Pin Assignment........................................................................ 22
Figure 9-1. Program Memory Read Timing Diagram ........................................................................ 37
Figure 9-2. Data Memory Read Timing Diagram ............................................................................... 38
Figure 9-3. Data Memory Write Timing Diagram ............................................................................... 39
Figure 9-4. GPIF Synchronous Signals Timing Diagram ................................................................. 40
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram ........................................................... 41
Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram ......................................................... 42
Figure 9-7. Slave FIFO Synchronous Write Timing Diagram ........................................................... 42
Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram......................................................... 43
Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram .................................... 43
Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram ................................ 44
Figure 9-11. Slave FIFO Output Enable Timing Diagram ................................................................. 44
Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram .................................................... 44
Figure 9-13. Slave FIFO Synchronous Address Timing Diagram ................................................... 45
Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram ................................................. 45
Figure 11-1. 56-lead Shrunk Small Outline Package O56 ................................................................ 46
Figure 11-2. 56-lead QFN Package ..................................................................................................... 47
Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 .................................... 48
Figure 11-4. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128.................................. 49
Document #: 38-08012 Rev. *B
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CY7C68013
LIST OF TABLES
Table 3-1. Special Function Registers ................................................................................................ 8
Table 3-2. Default ID Values for FX2 ................................................................................................... 8
Table 3-3. INT2 USB Interrupts ............................................................................................................ 9
Table 3-4. Individual FIFO/GPIF Interrupt Sources .......................................................................... 10
Table 3-5. Default Full-Speed Alternate Settings .............................................................................. 14
Table 3-6. Default High-Speed Alternate Settings ............................................................................ 15
Table 3-7. Strap Boot EEPROM Address Lines to These Values ................................................... 17
Table 4-1. FX2 Pin Descriptions ......................................................................................................... 23
Table 5-1. FX2 Register Summary ..................................................................................................... 30
Table 8-1. DC Characteristics ............................................................................................................ 36
Table 9-1. Program Memory Read Parameters ................................................................................ 37
Table 9-2. Data Memory Read Parameters ....................................................................................... 38
Table 9-3. Data Memory Write Parameters .......................................................................................39
Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK ...................... 40
Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK ..................... 40
Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK ............... 41
Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK ............... 41
Table 9-8. Slave FIFO Asynchronous Read Parameters .................................................................. 42
Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK ............... 42
Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK ............ 43
Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK ........... 43
Table 9-12. Slave FIFO Sync. Packet End Strobe Parameters with Internally Sourced IFCLK ... 43
Table 9-13. Slave FIFO Sync. Packet End Strobe Parameters with Externally Sourced IFCLK .. 44
Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters ........................................ 44
Table 9-15. Slave FIFO Output Enable Parameters ......................................................................... 44
Table 9-16. Slave FIFO Address to Flags/Data Parameters ............................................................ 45
Table 9-17. Slave FIFO Synchronous Address Parameters ............................................................ 45
Table 9-18. Slave FIFO Asynchronous Address Parameters .......................................................... 45
Table 10-1. Ordering Information ...................................................................................................... 45
Document #: 38-08012 Rev. *B
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CY7C68013
1.0
EZ-USB® FX2™ Features
Cypress’s EZ-USB® FX2™ is the world’s first USB 2.0 integrated microcontroller. By integrating the USB 2.0 transceiver, SIE,
enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very costeffective solution that provides superior time-to-market advantages. The ingenious architecture of FX2 results in data transfer
rates of 56 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low-cost 8051 microcontroller in
a package as small as a 56 SSOP. Because it incorporates the USB 2.0 transceiver, the FX2 is more economical, providing a
smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2, the Cypress Smart SIE
handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions
and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8- or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP,
PCMCIA, and most DSP/processors.
Four packages are defined for the family: 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.
High-performance micro
using standard tools
with lower-power options
x20
PLL
VCC
/0.5
/1.0
/2.0
Data (8)
Address (16)
FX2
8051 Core
12/24/48 MHz,
four clocks/cycle
1.5k
connected for
full speed
D+
D–
USB
2.0
XCVR
Integrated
full- and high-speed
XCVR
CY
Smart
USB
1.1/2.0
Engine
8.5 kB
RAM
Address (16) / Data Bus (8)
24 MHz
Ext. XTAL
I 2C
Compatible
Master
ADDR (9)
GPIF
RDY (6)
CTL (6)
4 kB
FIFO
Enhanced USB core
Simplifies 8051 core
“Soft Configuration”
Easy firmware changes
Abundant I/O
including two USARTS
Additional I/Os (24)
8/16
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
Up to 96 MBytes/s
burst rate
FIFO and endpoint memory
(master or slave operation)
Figure 1-1. Block Diagram
• Single-chip integrated USB 2.0 Transceiver, Serial Interface Engine (SIE), and Enhanced 8051 Microprocessor
• Software: 8051 runs from internal RAM, which is:
— Downloaded via USB, or
— Loaded from EEPROM
— External memory device (128-pin configuration only)
• Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints
— Buffering options: double, triple and quad
• 8- or 16-bit external data interface
• General Programmable Interface (GPIF)
— Allows direct connection to most parallel interfaces; 8- and 16-bit
— Programmable waveform descriptors and configuration registers to define waveforms
— Supports multiple Ready (RDY) inputs and Control (CTL) outputs
• Integrated, industry standard 8051 with enhanced features:
— Up to 48-MHz clock rate
— Four clocks per instruction cycle
— Two USARTS
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CY7C68013
— Three counter/timers
— Expanded interrupt system
•
•
•
•
•
•
•
— Two data pointers
3.3V operation
Smart Serial Interface Engine
Vectored USB interrupts
Separate data buffers for the SETUP and DATA portions of a CONTROL transfer
Integrated I2C-compatible controller, runs at 100 or 400 kHz
48-MHz, 24-MHz, or 12-MHz 8051 operation
Four integrated FIFOs
— Brings glue and FIFOs inside for lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— FIFOs can use externally supplied clock or asynchronous strobes
— Easy interface to ASIC and DSP ICs
• Special autovectors for FIFO and GPIF interrupts
• Up to 40 general purpose I/Os
• Four package options—128-pin TQFP, 100-pin TQFP, 56-pin QFN and 56-pin SSOP.
2.0
Applications
• DSL modems
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Home PNA
• Wireless LAN
• MP3 players
• Networking.
The “Reference Designs” section of the cypress website provides additional tools for typical USB 2.0 applications. Each reference
design comes complete with firmware source and object code, schematics, and documentation. Please visit
http://www.cypress.com for more information.
3.0
3.1
Functional Overview
USB Signaling Speed
FX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0, dated April 27, 2000:
• Full speed, with a signaling bit rate of 12 Mbps
• High speed, with a signaling bit rate of 480 Mbps
FX2 does not support the low-speed signaling mode of 1.5 Mbps.
3.2
8051 Microprocessor
The 8051 microprocessor embedded in the FX2 family has 256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
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CY7C68013
3.2.1
8051 Clock Frequency
FX2 has an on-chip oscillator circuit that uses an external 24-MHz (±100 ppm) crystal with the following characteristics:
• Parallel resonant
• Fundamental mode
• 500-µW drive level
• 27–33 pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz, as required by the transceiver/PHY, and internal counters divide
it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed
by the 8051 through the CPUCS register, dynamically.
The CLKOUT pin, which can be tri-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the
selected 8051 clock frequency—48, 24, or 12 MHz.
3.2.2
USARTS
FX2 contains two standard 8051 USARTs, addressed via Special Function Register (SFR) bits. The USART interface pins are
available on separate I/O pins, and are not multiplexed with port pins.
UART0 and UART1 can operate using an internal clock at 230 KBaud with no more than 1% baud rate error. 230-KBaud operation
is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal clock adjusts
for the 8051 clock rate (48, 24, 12 MHz) such that it always presents the correct frequency for 230-KBaud operation.
Note. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1,
respectively.
3.2.3
Special Function Registers (SFR)
Certain 8051 SFR addresses are populated to provide fast access to critical FX2 functions. These SFR additions are shown in
Table 3-1. Bold type indicates non-standard, enhanced 8051 registers.
The two SFR rows that end with “0” and “8” contain bit-addressable registers. The four I/O ports A–D use the SFR addresses
used in the standard 8051 for ports 0–3, which are not implemented in FX2.
Because of the faster and more efficient SFR addressing, the FX2 I/O ports are not addressable in external RAM space (using
the MOVX instruction).
3.3
I2C-compatible Bus
FX2 supports the I2C-compatible bus as a master only at 100/400 kbps. SCL and SDA pins have open-drain outputs and
hysteresis inputs. These signals must be pulled up to 3.3V, even if no I2C compatible device is connected.
3.4
Buses
All packages: 8- or 16-bit “FIFO” bidirectional data bus, multiplexed on I/O ports B and D.
128-pin package: adds 16-bit output-only 8051 address bus, 8-bit bidirectional data bus.
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CY7C68013
Table 3-1. Special Function Registers
x
8x
9x
Ax
Bx
Cx
Dx
Ex
Fx
PSW
ACC
B
EICON
EIE
EIP
0
IOA
IOB
IOC
IOD
SCON1
1
SP
EXIF
INT2CLR
IOE
SBUF1
2
DPL0
MPAGE
INT4CLR
OEA
3
DPH0
OEB
4
DPL1
OEC
5
DPH1
OED
6
DPS
OEE
7
PCON
8
TCON
SCON0
9
TMOD
SBUF0
IE
IP
T2CON
A
TL0
AUTOPTRH1
EP2468STAT
EP01STAT
RCAP2L
B
TL1
AUTOPTRL1
EP24FIFOFLGS
GPIFTRIG
RCAP2H
EP68FIFOFLGS
TH2
C
TH0
reserved
D
TH1
AUTOPTRH2
GPIFSGLDATH
E
CKCON
AUTOPTRL2
GPIFSGLDATLX
F
3.5
reserved
AUTOPTRSETUP
TL2
GPIFSGLDATLNOX
USB Boot Methods
During the power-up sequence, internal logic checks the I2C-compatible port for the connection of an EEPROM whose first byte
is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0),
or it boot-loads the EEPROM contents into internal RAM (0xC2). If no EEPROM is detected, FX2 enumerates using internally
stored descriptors. The default ID values for FX2 are VID/PID/DID (0x04B4, 0x8613, 0xxxyy).
Table 3-2. Default ID Values for FX2
Default VID/PID/DID
Vendor ID
0x04B4
Cypress Semiconductor
Prod ID
0x8613
EZ-USB FX2
Device release
0xXXYY
Depends on revision (0x04 for Rev E)
Note. The I2C-compatible bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this
detection method does not work properly.
3.6
ReNumeration™
Because the FX2’s configuration is soft, one chip can take on the identities of multiple distinct USB devices.
When first plugged into USB, the FX2 enumerates automatically and downloads firmware and USB descriptor tables over the
USB cable. Next, the FX2 enumerates again, this time as a device defined by the downloaded information. This patented twostep process, called ReNumeration™, happens instantly when the device is plugged in, with no hint that the initial download step
has occurred.
Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device will
handle device requests over endpoint zero: if RENUM = 0, the Default USB Device will handle device requests; if RENUM = 1,
the firmware will.
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CY7C68013
3.7
Interrupt System
3.7.1
INT2 Interrupt Request and Enable Registers
FX2 implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors.
See FX2 TRM for more details.
3.7.2
USB-Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that normally would be required
to identify the individual USB interrupt source, the FX2 provides a second level of interrupt vectoring, called Autovectoring. When
a USB interrupt is asserted, the FX2 pushes the program counter onto its stack then jumps to address 0x0043, where it expects
to find a “jump” instruction to the USB Interrupt service routine.
The FX2 jump instruction is encoded as follows.
Table 3-3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Priority
INT2VEC Value Source
1
00
2
3
4
5
Notes
SUDAV
SETUP Data Available
04
SOF
Start of Frame (or microframe)
08
SUTOK
Setup Token Received
0C
SUSPEND
USB Suspend request
10
USB RESET
Bus reset
6
14
HISPEED
Entered high speed operation
7
18
EP0ACK
FX2 ACK’d the CONTROL Handshake
8
1C
9
20
EP0-IN
EP0-IN ready to be loaded with data
10
24
EP0-OUT
EP0-OUT has USB data
11
28
EP1-IN
EP1-IN ready to be loaded with data
12
2C
EP1-OUT
EP1-OUT has USB data
13
30
EP2
IN: buffer available. OUT: buffer has data
14
34
EP4
IN: buffer available. OUT: buffer has data
15
38
EP6
IN: buffer available. OUT: buffer has data
16
3C
EP8
IN: buffer available. OUT: buffer has data
17
40
IBN
IN-Bulk-NAK (any IN endpoint)
18
44
19
48
EP0PING
EP0 OUT was Pinged and it NAK’d
20
4C
EP1PING
EP1 OUT was Pinged and it NAK’d
21
50
EP2PING
EP2 OUT was Pinged and it NAK’d
22
54
EP4PING
EP4 OUT was Pinged and it NAK’d
23
58
EP6PING
EP6 OUT was Pinged and it NAK’d
24
5C
EP8PING
EP8 OUT was Pinged and it NAK’d
25
60
ERRLIMIT
Bus errors exceeded the programmed limit
26
64
reserved
27
68
reserved
28
6C
29
70
EP2ISOERR
ISO EP2 OUT PID sequence error
30
74
EP4ISOERR
ISO EP4 OUT PID sequence error
31
78
EP6ISOERR
ISO EP6 OUT PID sequence error
32
7C
EP8ISOERR
ISO EP8 OUT PID sequence error
Document #: 38-08012 Rev. *B
reserved
reserved
reserved
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CY7C68013
If Autovectoring is enabled (AV2EN = 1 in the INTSETUP register), the FX2 substitutes its INT2VEC byte. Therefore, if the high
byte (“page”) of a jump-table address is preloaded at location 0x0044, the automatically-inserted INT2VEC byte at 0x0045 will
direct the jump to the correct address out of the 27 addresses within the page.
3.7.3
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual USB-interrupt sources, the FIFO/GPIF interrupt is shared among 14
individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 3-4 shows the
priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources
Table 3-4. Individual FIFO/GPIF Interrupt Sources
Priority
INT4VEC Value
Source
1
80
EP2PF
Endpoint 2 Programmable Flag
Notes
2
84
EP4PF
Endpoint 4 Programmable Flag
3
88
EP6PF
Endpoint 6 Programmable Flag
4
8C
EP8PF
Endpoint 8 Programmable Flag
5
90
EP2EF
Endpoint 2 Empty Flag
6
94
EP4EF
Endpoint 4 Empty Flag
7
98
EP6EF
Endpoint 6 Empty Flag
8
9C
EP8EF
Endpoint 8 Empty Flag
9
A0
EP2FF
Endpoint 2 Full Flag
10
A4
EP4FF
Endpoint 4 Full Flag
11
A8
EP6FF
Endpoint 6 Full Flag
12
AC
EP8FF
Endpoint 8 Full Flag
13
B0
GPIFDONE
14
B4
GPIFWF
GPIF Operation Complete
GPIF Waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSETUP register), the FX2 substitutes its INT4VEC byte. Therefore, if the high
byte (“page”) of a jump-table address is preloaded at location 0x0054, the automatically-inserted INT4VEC byte at 0x0055 will
direct the jump to the correct address out of the 14 addresses within the page. When the ISR occurs, the FX2 pushes the program
counter onto its stack then jumps to address 0x0053, where it expects to find a “jump” instruction to the ISR Interrupt service
routine.
3.8
Reset and Wakeup
3.8.1
Reset Pin
An input pin (RESET#) resets the chip. This pin has hysteresis and is active LOW. The internal PLL stabilizes approximately 200
µs after VCC has reached 3.3V. Typically, an external RC network (R = 100k, C = 0.1 µF) is used to provide the RESET# signal.
3.8.2
Wakeup Pins
The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator restarts and after the PLL stabilizes, and the 8051 receives a wakeup
interrupt. This applies whether or not FX2 is connected to the USB.
The FX2 exits the power down (USB suspend) state using one of the following methods:
• USB bus signals resume
• External logic asserts the WAKEUP pin
• External logic asserts the PA3/WU2 pin.
The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This allows a simple external R-C network
to be used as a periodic wakeup source.
3.9
Program/Data RAM
3.9.1
Size
The FX2 has eight kbytes of internal program/data RAM, where PSEN#/RD# signals are internally ORed to allow the 8051 to
access it as both program and data memory. No USB control registers appear in this space.
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CY7C68013
Two memory maps are shown in the following diagrams:
Figure 3-1 Internal Code Memory, EA = 0
Figure 3-2 External Code Memory, EA = 1.
3.9.2
Internal Code Memory, EA = 0
This mode implements the internal eight-kbyte block of RAM (starting at 0) as combined code and data memory. When external
RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This
allows the user to connect a 64-kbyte memory without requiring address decodes to keep clear of internal memory spaces.
Only the internal eight kbytes and scratch pad 0.5 kbytes RAM spaces have the following access:
• USB download
• USB upload
• Setup data pointer
• I2C-compatible interface boot load.
Inside FX2
Outside FX2
FFFF
7.5 kbytes
US B regs and
4k EP buffers
(RD#,WR#)
E200
E1FF
0.5 kbytes RAM
E000 Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
48 kbytes
External
Data
Memory
(RD#,WR#)
56 kbytes
External
Code
Memory
(PSEN#)
1FFF
Eight kbytes RAM
Code and Data
(PSEN#,RD#,WR#)*
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
0000
Data
Code
*SUDPTR, USB upload/download, I2C-compatible interface boot access
Figure 3-1. Internal Code Memory, EA = 0
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CY7C68013
3.9.3
External Code Memory, EA = 1
The bottom eight kbytes of program memory is external, and therefore the bottom eight kbytes of internal RAM is accessible only
as data memory.
Inside FX2
Outside FX2
FFFF
7.5 kbytes
USB regs and
4k EP buffers
(RD#,WR#)
E200
E1FF
0.5 kbytes RAM
E000 Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
48 kbytes
External
Data
Memory
(RD#,WR#)
64 kbytes
External
Code
Memory
(PSEN#)
1FFF
Eight kbytes
RAM
Data
(RD#,WR#)*
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
0000
Data
Code
*SUDPTR, USB upload/download, I2C-compatible interface boot access
Figure 3-2. External Code Memory, EA = 1
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CY7C68013
3.10
Register Addresses
FFFF
4 kbytes EP2-EP8 buffers
(8 × 512)
F000
EFFF
2 kbytes RESERVED
E800
E7FF
E7C0
E7BF
E780
E77F
E740
E73F
E700
E6FF
E600
E5FF
E480
E47F
E400
E3FF
64 bytes EP1IN
64 bytes EP1OUT
64 bytes EP0 IN/OUT
64 bytes RESERVED
256 bytes Registers
384 bytes RESERVED
128 bytes GPIF Waveforms
512 bytes RESERVED
E200
E1FF
E000
3.11
512 bytes
8051 xdata RAM
Endpoint RAM
3.11.1 Size
• 3 × 64 bytes
• 8 × 512 bytes
(Endpoints 0 and 1)
(Endpoints 2, 4, 6, 8)
3.11.2 Organization
• EP0
Bidirectional endpoint zero, 64-byte buffer
• EP1IN, EP1OUT
64-byte buffers, bulk or interrupt
• EP2,4,6,8
Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2 and 6 can be either double, triple, or quad
buffered. For high-speed endpoint configuration options, see Figure 3-3.
3.11.3
Setup Data Buffer
A separate eight-byte buffer at 0xE6B8-0xE6BF holds the SETUP data from a CONTROL transfer.
Document #: 38-08012 Rev. *B
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CY7C68013
3.11.4
Endpoint Configurations (High-speed Mode)
EP0 IN&OUT
64
64
64
64
64
64
EP1 IN
64
64
64
64
64
64
EP1 OUT
64
64
64
64
64
64
512
512
512
EP2
512
1024
512
EP2
EP2
EP2
512
512
512
512
512
1024
1024
1024
512
1024
EP4
1024
512
EP2
EP2
512
EP6
512
EP6
512
1024
512
EP6
512
1024
512
1024
EP6
512
1024
EP8
512
512
512
512
EP8
EP8
1024
512
512
512
Figure 3-3. Endpoint Configuration
Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either
BULK or INTERRUPT. To the left of the vertical line, the user may pick different configurations for EP2&4 and EP6&8, since none
of the 512-byte buffers are combined between these endpoint groups. An example endpoint configuration would be:
EP2—1024 double buffered; EP6—512 quad buffered.
To the right of the vertical line, buffers are shared between EP2–8, and therefore only entire columns may be chosen.
3.11.5
Default Full-Speed Alternate Settings
Table 3-5. Default Full-Speed Alternate Settings[1, 2]
Alternate Setting
0
1
2
3
ep0
64
64
64
64
ep1out
0
64 bulk
64 int
64 int
ep1in
0
64 bulk
64 int
64 int
ep2
0
64 bulk out (2×)
64 int out (2×)
64 iso out (2×)
ep4
0
64 bulk out (2×)
64 bulk out (2×)
64 bulk out (2×)
ep6
0
64 bulk in (2×)
64 int in (2×)
64 iso in (2×)
ep8
0
64 bulk in (2×)
64 bulk in (2×)
64 bulk in (2×)
Notes:
1. “0” means “not implemented.”
2. “2x” means “double buffered.”
Document #: 38-08012 Rev. *B
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CY7C68013
3.11.6 Default High-Speed Alternate Settings
Table 3-6. Default High-Speed Alternate Settings[1, 2]
Alternate Setting
0
1
ep0
64
64
ep1out
0
ep1in
0
ep2
ep4
2
3
64
64
512 bulk[3]
64 int
64 int
[3]
512 bulk
64 int
64 int
0
512 bulk out (2×)
512 int out (2×)
512 iso out (2×)
0
512 bulk out (2×)
512 bulk out (2×)
512 bulk out (2×)
ep6
0
512 bulk in (2×)
512 int in (2×)
512 iso in (2×)
ep8
0
512 bulk in (2×)
512 bulk in (2×)
512 bulk in (2×)
Note:
3. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
3.12
External FIFO interface
3.12.1
Architecture
The FX2 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories, and are
controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the I/O transfer logic.
The transfer logic takes two forms, the GPIF for internally generated control signals, or the slave FIFO interface for externally
controlled transfers.
3.12.2
Master/Slave Control Signals
The FX2 endpoint FIFOS are implemented as eight physically distinct 256x16 RAM blocks. The 8051/SIE can switch any of the
RAM blocks between two domains, the USB (SIE) domain and the 8051-I/O Unit domain. This switching is done virtually instantaneously, giving essentially zero transfer time between “USB FIFOS” and “Slave FIFOS.” Since they are physically the same
memory, no bytes are actually transferred between buffers.
At any given time, some RAM blocks are filling/emptying with USB data under SIE control, while other RAM blocks are available
to the 8051 and/or the I/O control unit. The RAM blocks operate as single-port in the USB domain, and dual-port in the 8051-I/O
domain. The blocks can be configured as single, double, triple, or quad buffered as previously shown.
The I/O control unit implements either an internal-master (M for master) or external-master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-pin package, six
in the 100-pin and 128-pin packages) can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can
be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96
Megabytes/s (48 MHz).
In Slave (S) mode, the FX2 accepts either an internally derived clock or externally supplied clock (IFCLK, max. frequency 48
MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. Each endpoint can individually be selected for byte
or word operation by an internal configuration bit, and a Slave FIFO Output Enable signal SLOE enables data of the selected
width. External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface
can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in
synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#.
3.12.3
GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alternatively,
an externally supplied clock of 5 MHz – 48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured
to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register
turns this clock output off, if desired. Another bit within the IFCONFIG register will invert the IFCLK signal whether internally or
externally sourced.
3.13
GPIF
The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. It allows the CY7C68013
to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and
Utopia.
Document #: 38-08012 Rev. *B
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CY7C68013
The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs
(RDY). The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, and determines what
state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to
the next data value, advance an address, etc. A sequence of the GPIF vectors make up a single waveform that will be executed
to perform the desired data move between the CY7C68013 and the external design.
3.13.1
Six Control OUT Signals
The 100- and 128-pin packages bring out all six Control Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to define
the CTL waveforms. The 56-pin package brings out three of these signals, CTL0–CTL2. CTLx waveform edges can be
programmed to make transitions as fast as once per clock (20.8 ns using a 48-MHz clock).
3.13.2
Six Ready IN Signals
The 100- and 128-pin packages bring out all six Ready inputs (RDY0–RDY5). The 8051 programs the GPIF unit to test the RDY
pins for GPIF branching. The 56-pin package brings out two of these signals, RDY0–1.
3.13.3
Nine GPIF Address OUT signals
Nine GPIF address lines are available in the 100- and 128-pin packages, GPIFADR[8..0]. The GPIF address lines allow indexing
through up to a 512-byte block of RAM. If more address lines are needed, I/O port pins can be used.
3.13.4
Long Transfer Mode
In master mode, the 8051 appropriately sets GPIF transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended transfers of up to 4,294,967,296 bytes. The GPIF automatically throttles data flow to prevent under
or overflow until the full number of requested transactions complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
3.14
USB Uploads and Downloads
The core has the ability to directly edit the data contents of the internal 8-kbyte RAM and of the internal 512-byte scratch pad
RAM via a vendor-specific command. This capability is normally used when “soft” downloading user code and is available only
to and from internal RAM, whether the 8051 is held in reset or running. The available RAM spaces are 8 kbytes from
0x0000–0x1FFF (code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad RAM).
Note: A “loader” running in internal RAM can be used to transfer downloaded data to external memory.
3.15
Autopointer Access
FX2 provides two identical autopointers. They are similar to the internal 8051 data pointers, but with an additional feature: they
can optionally increment a pointer address after every memory access. This capability is available to and from both internal and
external RAM. The autopointers are available in external FX2 registers, under control of a mode bit (AUTOPTRSETUP.0). Using
the external FX2 autopointer access (at 0xE67B – 0xE67C) allows the autopointer to access all RAM, internal and external to
the part. Also, the autopointers can point to any FX2 register or endpoint buffer space. When autopointer access to external
memory is enabled, location 0xE67B and 0xE67C in XDATA and PDATA space cannot be used.
3.16
I2C-compatible Controller
FX2 has one I2C-compatible port that is driven by two internal controllers, one that automatically operates at boot time to load
VID/PID/DID and configuration information, and another that the 8051, once running, uses to control external I2C-compatible
devices. The I2C-compatible port operates in master mode only.
3.16.1
I2C-compatible Port Pins
The I2C-compatible pins SCL and SDA must have external 2.2-kΩ pull-up resistors. External EEPROM device address pins must
be configured properly. See Table 3-7 for configuring the device address pins.
Document #: 38-08012 Rev. *B
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CY7C68013
Table 3-7. Strap Boot EEPROM Address Lines to These Values
Bytes
Example EEPROM
[4]
A2
A1
A0
16
24LC00
N/A
N/A
N/A
128
24LC01
0
0
0
256
24LC02
0
0
0
4K
24LC32
0
0
1
8K
24LC64
0
0
1
3.16.2
I2C-compatible Interface Boot Load Access
At power-on reset the I2C-compatible interface boot loader will load the VID/PID/DID/a configuration byte and up to 8 kbytes of
program/data. The available RAM spaces are 8 kbytes from 0x0000–0x1FFF and 512 bytes from 0xE000–0xE1FF. The 8051 will
be in reset. I2C-compatible interface boot loads only occur after power-on reset.
3.16.3
I2C-compatible Interface General Purpose Access
The 8051 can control peripherals connected to the I2C-compatible bus using the I2CTL and I2DAT registers. FX2 provides I2C
compatible master control only, it is never an I2C-compatible slave.
4.0
Pin Assignments
Figure 4-1 identifies all signals for the four package types. The following pages illustrate the individual pin diagrams, plus a
combination diagram showing which of the full set of signals are available in the 128-, 100-, and 56-pin packages.
The 56-pin package is the lowest-cost version. The signals on the left edge of the 56-pin package in Figure 4-1 are common to
all versions in the FX2 family. Three modes are available in all package versions: Port, GPIF master, and Slave FIFO. These
modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register
bits. Port mode is the power-on default configuration.
The 100-pin package adds functionality to the 56-pin package by adding these pins:
• PORTC or alternate GPIFADR[7...0] address signals
• PORTE or alternate GPIFADR8 address signals and 7 more 8051 signals
• 3 GPIF Control signals
• 4 GPIF Ready signals
• Nine 8051 signals (two USARTs, three timer inputs, INT4,and INT5#)
• BKPT, RD#, WR#
The 128-pin package is the full version, adding the 8051 address and data buses plus control signals. Note that two of the required
signals, RD# and WR#, are present in the 100-pin version. In the 100-pin and 128-pin versions, an 8051 control bit can be set to
pulse the RD# and WR# pins when the 8051 reads from/writes to PORTC.
Note:
4.
This EEPROM does not have address pins.
Document #: 38-08012 Rev. *B
Page 17 of 50
CY7C68013
Port
XTALIN
XTALOUT
RESET#
WAKEUP#
GPIF Master
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
56
SCL
SDA
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
IFCLK
CLKOUT
DPLUS
DMINUS
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
Slave FIFO
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
RDY0
RDY1
SLRD
SLWR
CTL0
CTL1
CTL2
FLAGA
FLAGB
FLAGC
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
100
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
RD#
WR#
CS#
OE#
PSEN#
D7
D6
D5
D4
D3
D2
D1
D0
128
EA
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
TIMER2
TIMER1
TIMER0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Figure 4-1. Signals
Document #: 38-08012 Rev. *B
Page 18 of 50
CY7C68013
27
28
29
30
31
32
33
34
35
36
37
38
103
26
104
25
105
24
106
23
107
22
108
21
109
20
110
19
111
18
112
17
113
16
114
15
115
14
116
13
117
12
118
11
119
10
120
9
121
8
122
7
123
6
124
5
125
4
126
3
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
A4
A5
A6
A7
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
A8
A9
A10
2
127
128
1
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
VCC
DPLUS
DMINUS
GND
A11
A12
A13
A14
A15
VCC
GND
INT4
T0
T1
T2
IFCLK
RESERVED
BKPT
EA
SCL
SDA
OE#
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
A3
A2
A1
A0
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
D7
D6
D5
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
GND
CY7C68013
128-pin TQFP
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
D4
D3
D2
D1
D0
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RxD1
TxD1
RxD0
TxD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
CS#
WR#
RD#
PSEN#
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
Figure 4-2. CY7C68013 128-pin TQFP Pin Assignment
* denotes programmable polarity
Document #: 38-08012 Rev. *B
Page 19 of 50
CY7C68013
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
VCC
DPLUS
DMINUS
GND
VCC
GND
INT4
T0
T1
T2
IFCLK
RESERVED
BKPT
SCL
SDA
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
CY7C68013
100-pin TQFP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RxD1
TxD1
RxD0
TxD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
WR#
RD#
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
Figure 4-3. CY7C68013 100-pin TQFP Pin Assignment
* denotes programmable polarity
Document #: 38-08012 Rev. *B
Page 20 of 50
CY7C68013
CY7C68013
56-pin SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD5/FD13
PD4/FD12
PD6/FD14
PD3/FD11
PD7/FD15
PD2/FD10
GND
PD1/FD9
CLKOUT
PD0/FD8
VCC
*WAKEUP
GND
VCC
RDY0/*SLRD
RESET#
RDY1/*SLWR
GND
AVCC
PA7/*FLAGD/SLCS#
XTALOUT
PA6/PKTEND
XTALIN
PA5/FIFOADR1
AGND
PA4/FIFOADR0
VCC
PA3/*WU2
DPLUS
PA2/*SLOE
DMINUS
PA1/INT1#
GND
PA0/INT0#
VCC
VCC
GND
CTL2/*FLAGC
IFCLK
CTL1/*FLAGB
RESERVED
CTL0/*FLAGA
SCL
GND
SDA
VCC
VCC
GND
PB0/FD0
PB7/FD7
PB1/FD1
PB6/FD6
PB2/FD2
PB5/FD5
PB3/FD3
PB4/FD4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment
* denotes programmable polarity
Document #: 38-08012 Rev. *B
Page 21 of 50
CY7C68013
GND
VCC
CLKOUT
GND
PD7/FD15
PD6/FD14
PD5/FD13
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
RDY0/*SLRD
1
42
RESET#
RDY1/*SLWR
2
41
GND
AVCC
3
40
PA7/*FLAGD/SLCS#
XTALOUT
4
39
PA6/*PKTEND
XTALIN
5
38
PA5/FIFOADR1
AGND
6
37
PA4/FIFOADR0
36
PA3/*WU2
CY7C68013
VCC
7
DPLUS
8
35
PA2/*SLOE
DMINUS
9
34
PA1/INT1#
GND
10
33
PA0/INT0#
VCC
11
32
VCC
GND
12
31
CTL2/*FLAGC
*IFCLK
13
30
CTL1/*FLAGB
RESERVED
14
29
CTL0/*FLAGA
56-pin QFN
21
22
23
24
25
26
27
28
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
GND
VCC
GND
PB0/FD0
PB2/FD2
18
VCC
20
17
SDA
PB1/FD1
16
SCL
19
15
Figure 4-5. CY7C68013 56-pin QFN Pin Assignment
* denotes programmable polarity
Document #: 38-08012 Rev. *B
Page 22 of 50
CY7C68013
4.1
CY7C68013 Pin Descriptions
Table 4-1. FX2 Pin Descriptions[5]
128
100
56
56
TQFP TQFP SSOP QFN
Type
Default
Description
10
9
10
3
AVCC
Name
Power
N/A
Analog VCC. This signal provides power to the analog section of
the chip.
13
12
13
6
AGND
Power
N/A
Analog Ground. Connect to ground with as short a path as possible.
19
18
16
9
DMINUS
I/O/Z
Z
18
17
15
8
DPLUS
USB D– Signal. Connect to the USB D– signal.
I/O/Z
Z
USB D+ Signal. Connect to the USB D+ signal.
94
A0
Output
L
95
A1
Output
L
8051 Address Bus. This bus is driven at all times. When the 8051
is addressing internal RAM it reflects the internal address.
96
A2
Output
L
97
A3
Output
L
117
A4
Output
L
118
A5
Output
L
119
A6
Output
L
120
A7
Output
L
126
A8
Output
L
127
A9
Output
L
128
A10
Output
L
21
A11
Output
L
22
A12
Output
L
23
A13
Output
L
24
A14
Output
L
25
A15
Output
L
59
D0
I/O/Z
Z
60
D1
I/O/Z
Z
61
D2
I/O/Z
Z
62
D3
I/O/Z
Z
63
D4
I/O/Z
Z
86
D5
I/O/Z
Z
87
D6
I/O/Z
Z
8051 Data Bus. This bidirectional bus is high-impedance when
inactive, input for bus reads, and output for bus writes. The data
bus is used for external 8051 program and data memory. The data
bus is active only for external bus accesses, and is driven LOW in
suspend.
88
D7
I/O/Z
Z
39
PSEN#
Output
H
Program Store Enable. This active-LOW signal indicates an 8051
code fetch from external memory. It is active for program memory
fetches from 0x2000–0xFFFF when the EA pin is LOW, or from
0x0000–0xFFFF when the EA pin is HIGH.
BKPT
Output
L
Breakpoint. This pin goes active (HIGH) when the 8051 address
bus matches the BPADDRH/L registers and breakpoints are enabled in the BREAKPT register (BPEN = 1). If the BPPULSE bit in
the BREAKPT register is HIGH, this signal pulses HIGH for eight
12-/24-/48-MHz clocks. If the BPPULSE bit is LOW, the signal remains HIGH until the 8051 clears the BREAK bit (by writing 1 to it)
in the BREAKPT register.
Input
N/A
Active LOW Reset. Resets the entire chip. This pin is normally tied
to VCC through a 100K resistor, and to GND through a 0.1-µF capacitor.
34
28
99
77
49
42 RESET#
Note:
5. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power-up and
in standby.
Document #: 38-08012 Rev. *B
Page 23 of 50
CY7C68013
Table 4-1. FX2 Pin Descriptions[5] (continued)
128
100
56
56
TQFP TQFP SSOP QFN
35
Name
Type
Default
Description
EA
Input
N/A
External Access. This pin determines where the 8051 fetches
code between addresses 0x0000 and 0x1FFF. If EA = 0 the 8051
fetches this code from its internal RAM. IF EA = 1 the 8051 fetches
this code from external memory.
Input
N/A
Crystal Input. Connect this signal to a 24-MHz parallel-resonant,
fundamental mode crystal and 20-pF capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square
wave derived from another clock source.
Output
N/A
Crystal Output. Connect this signal to a 24-MHz parallel-resonant,
fundamental mode crystal and 20-pF capacitor to GND.
If an external clock is used to drive XTALIN, leave this pin open.
12
11
12
5
XTALIN
11
10
11
4
XTALOUT
1
100
5
54 CLKOUT
O/Z
12 MHz 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input clock.
The 8051 defaults to 12-MHz operation. The 8051 may tri-state this
output by setting CPUCS.1 = 1.
82
67
40
33 PA0 or
INT0#
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA0) PORTACFG.0
PA0 is a bidirectional IO port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is
either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
83
68
41
34 PA1 or
INT1#
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA1) PORTACFG.1
PA1 is a bidirectional IO port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is
either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
84
69
42
35 PA2 or
SLOE
I/O/Z
I
Multiplexed pin whose function is selected by two bits:
(PA2) IFCONFIG[1:0].
PA2 is a bidirectional IO port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPOLAR.4) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
85
70
43
36 PA3 or
WU2
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA3) WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN
bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the
8051 is in suspend and WU2EN = 1, a transition on this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Asserting this pin inhibits the chip from suspending, if
WU2EN=1.
89
71
44
37 PA4 or
FIFOADR0
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA4) IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0].
90
72
45
38 PA5 or
FIFOADR1
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA5) IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0].
91
73
46
39 PA6 or
PKTEND
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
(PA6) bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input-only packet end with programmable polarity
(FIFOPOLAR.5) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
Port A
Document #: 38-08012 Rev. *B
Page 24 of 50
CY7C68013
Table 4-1. FX2 Pin Descriptions[5] (continued)
128
100
56
56
TQFP TQFP SSOP QFN
92
Name
Type
Default
Description
74
47
40 PA7 or
FLAGD or
SLCS#
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
(PA7) and PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
44
34
25
18 PB0 or
FD[0]
I/O/Z
I
Multiplexed pin whose function is selected by the following bits:
(PB0) IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
45
35
26
19 PB1 or
FD[1]
I/O/Z
I
Multiplexed pin whose function is selected by the following bits:
(PB1) IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
46
36
27
20 PB2 or
FD[2]
I/O/Z
I
Multiplexed pin whose function is selected by the following bits:
(PB2) IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
47
37
28
21 PB3 or
TXD1 or
FD[3]
I/O/Z
I
Multiplexed pin whose function is selected by the following bits:
(PB3) IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
54
44
29
22 PB4 or
FD[4]
I/O/Z
I
Multiplexed pin whose function is selected by the following bits:
(PB4) IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
55
45
30
23 PB5 or
FD[5]
I/O/Z
I
Multiplexed pin whose function is selected by the following bits:
(PB5) IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
56
46
31
24 PB6 or
FD[6]
I/O/Z
I
Multiplexed pin whose function is selected by the following bits:
(PB6) IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
57
47
32
25 PB7 or
FD[7]
I/O/Z
I
Multiplexed pin whose function is selected by the following bits:
(PB7) IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
Port B
PORT C
72
57
PC0 or
GPIFADR0
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.0
(PC0) PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
73
58
PC1 or
GPIFADR1
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.1
(PC1) PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
74
59
PC2 or
GPIFADR2
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.2
(PC2) PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
75
60
PC3 or
GPIFADR3
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.3
(PC3) PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
76
61
PC4 or
GPIFADR4
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.4
(PC4) PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
Document #: 38-08012 Rev. *B
Page 25 of 50
CY7C68013
Table 4-1. FX2 Pin Descriptions[5] (continued)
128
100
56
56
TQFP TQFP SSOP QFN
Name
Type
Default
Description
77
62
PC5 or
GPIFADR5
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.5
(PC5) PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
78
63
PC6 or
GPIFADR6
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.6
(PC6) PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
79
64
PC7 or
GPIFADR7
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.7
(PC7) PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
PORT D
102
80
52
45 PD0 or
FD[8]
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD0) and EPxFIFCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
103
81
53
46 PD1 or
FD[9]
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD1) and EPxFIFCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
104
82
54
47 PD2 or
FD[10]
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD2) and EPxFIFCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
105
83
55
48 PD3 or
FD[11]
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD3) and EPxFIFCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
121
95
56
49 PD4 or
FD[12]
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD4) and EPxFIFCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
122
96
1
50 PD5 or
FD[13]
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD5) and EPxFIFCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
123
97
2
51 PD6 or
FD[14]
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD6) and EPxFIFCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
124
98
3
52 PD7 or
FD[15]
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD7) and EPxFIFCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Port E
108
86
PE0 or
T0OUT
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.0 bit.
(PE0) PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051 Timer-counter0.
T0OUT outputs a high level for one CLKOUT clock cycle when
Timer0 overflows. If Timer0 is operated in Mode 3 (two separate
timer/counters), T0OUT is active when the low byte timer/counter
overflows.
109
87
PE1 or
T1OUT
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.1 bit.
(PE1) PE1 is a bidirectional I/O port pin.
T1OUT is an active-HIGH signal from 8051 Timer-counter1.
T1OUT outputs a high level for one CLKOUT clock cycle when
Timer1 overflows. If Timer1 is operated in Mode 3 (two separate
timer/counters), T1OUT is active when the low byte timer/counter
overflows.
110
88
PE2 or
T2OUT
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.2 bit.
(PE2) PE2 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signal from 8051 Timer2. T2OUT
is active (HIGH) for one clock cycle when Timer/Counter 2 overflows.
Document #: 38-08012 Rev. *B
Page 26 of 50
CY7C68013
Table 4-1. FX2 Pin Descriptions[5] (continued)
128
100
56
56
TQFP TQFP SSOP QFN
Name
Type
Default
Description
111
89
PE3 or
RXD0OUT
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.3 bit.
(PE3) PE3 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0. If
RXD0OUT is selected and UART0 is in Mode 0, this pin provides
the output data for UART0 only when it is in sync mode. Otherwise
it is a 1.
112
90
PE4 or
RXD1OUT
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.4 bit.
(PE4) PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1. When
RXD1OUT is selected and UART1 is in Mode 0, this pin provides
the output data for UART1 only when it is in sync mode. In Modes
1, 2, and 3, this pin is HIGH.
113
91
PE5 or
INT6
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.5 bit.
(PE5) PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT5 interrupt request input signal. The INT6 pin
is edge-sensitive, active HIGH.
114
92
PE6 or
T2EX
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.6 bit.
(PE6) PE6 is a bidirectional I/O port pin.
T2EX is an active-high input signal to the 8051 Timer2. T2EX reloads timer 2 on its falling edge. T2EX is active only if the EXEN2
bit is set in T2CON.
115
93
PE7 or
GPIFADR8
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.7 bit.
(PE7) PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
4
3
8
1
RDY0 or
SLRD
Input
N/A
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity
(FIFOPOLAR.3) for the slave FIFOs connected to FDI[7..0] or
FDI[15..0].
5
4
9
2
RDY1 or
SLWR
Input
N/A
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity
(FIFOPOLAR.2) for the slave FIFOs connected to FDI[7..0] or
FDI[15..0].
6
5
RDY2
Input
N/A
RDY2 is a GPIF input signal.
7
6
RDY3
Input
N/A
RDY3 is a GPIF input signal.
8
7
RDY4
Input
N/A
RDY4 is a GPIF input signal.
9
8
RDY5
Input
N/A
RDY5 is a GPIF input signal.
69
54
36
29 CTL0 or
FLAGA
Output
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the
FIFOADR[1:0] pins.
70
55
37
30 CTL1 or
FLAGB
Output
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
Document #: 38-08012 Rev. *B
Page 27 of 50
CY7C68013
Table 4-1. FX2 Pin Descriptions[5] (continued)
128
100
56
56
TQFP TQFP SSOP QFN
38
Name
Default
Description
Output
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0]
pins.
71
56
66
51
CTL3
Output
H
CTL3 is a GPIF control output.
67
52
CTL4
Output
H
CTL4 is a GPIF control output.
98
76
CTL5
Output
H
CTL5 is a GPIF control output.
32
26
I/O/Z
Z
Interface Clock, used for synchronously clocking data into or out of
the slave FIFOs. IFCLK also serves as a timing reference for all
slave FIFO control signals and GPIF. When internal clocking,
IFCONFIG.7 = 1, is used the IFCLK pin can be configured to output
30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be
inverted, whether internally or externally sourced, by setting the bit
IFCONFIG.4 =1.
28
22
INT4
Input
N/A
INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin
is edge-sensitive, active HIGH.
106
84
INT5#
Input
N/A
INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin
is edge-sensitive, active LOW.
31
25
T2
Input
N/A
T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides the input to Timer2 when C/T2 = 1. When C/T2 = 0, Timer2
does not use this pin.
30
24
T1
Input
N/A
T1 is the active-HIGH T1 signal for 8051 Timer1, which provides
the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does
not use this bit.
29
23
T0
Input
N/A
T0 is the active-HIGH T0 signal for 8051 Timer0, which provides
the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does
not use this bit.
53
43
RXD1
Input
N/A
RXD1is an active-HIGH input signal for 8051 UART1, which provides data to the UART in all modes.
52
42
TXD1
Output
H
TXD1is an active-HIGH output pin from 8051 UART1, which provides the output clock in sync mode, and the output data in async
mode.
51
41
RXD0
Input
N/A
RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides data to the UART in all modes.
50
40
TXD0
Output
H
TXD0 is the active-HIGH TXD0 output from 8051 UART0, which
provides the output clock in sync mode, and the output data in
async mode.
CS#
Output
H
CS# is the active-LOW chip select for external memory.
20
42
31 CTL2 or
FLAGC
Type
13 IFCLK
41
32
WR#
Output
H
WR# is the active-LOW write strobe output for external memory.
40
31
RD#
Output
H
RD# is the active-LOW read strobe output for external memory.
OE#
Output
H
OE# is the active-LOW output enable for external memory.
38
33
27
21
14 Reserved
Input
N/A
Reserved. Connect to ground.
101
79
51
44 WAKEUP
Input
N/A
USB Wakeup. If the 8051 is in suspend, asserting this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Holding WAKEUP asserted inhibits the EZ-USB chip
from suspending. This pin has programmable polarity (WAKEUP.4).
Document #: 38-08012 Rev. *B
Page 28 of 50
CY7C68013
Table 4-1. FX2 Pin Descriptions[5] (continued)
128
100
56
56
TQFP TQFP SSOP QFN
Name
Type
Default
Description
2
36
29
22
15 SCL
OD
Z
Clock for the I C-compatible interface. Connect to VCC with a
2.2K resistor, even if no I2C-compatible peripheral is attached.
37
30
23
16 SDA
OD
Z
Data for I2C-compatible interface. Connect to VCC with a 2.2K
resistor, even if no I2C-compatible peripheral is attached.
2
1
6
55 VCC
Power
N/A
VCC. Connect to 3.3V power source.
17
16
14
7
VCC
Power
N/A
VCC. Connect to 3.3V power source.
26
20
18
11
VCC
Power
N/A
VCC. Connect to 3.3V power source.
43
33
24
17 VCC
Power
N/A
VCC. Connect to 3.3V power source.
48
38
34
27 VCC
Power
N/A
VCC. Connect to 3.3V power source.
64
49
39
32 VCC
Power
N/A
VCC. Connect to 3.3V power source.
68
53
50
43 VCC
Power
N/A
VCC. Connect to 3.3V power source.
81
66
VCC
Power
N/A
VCC. Connect to 3.3V power source.
100
78
VCC
Power
N/A
VCC. Connect to 3.3V power source.
107
85
VCC
Power
N/A
VCC. Connect to 3.3V power source.
3
2
4
53 GND
Ground
N/A
Ground.
20
19
7
56 GND
Ground
N/A
Ground.
27
21
17
10 GND
Ground
N/A
Ground.
49
39
19
12 GND
Ground
N/A
Ground.
58
48
33
26 GND
Ground
N/A
Ground.
65
50
35
28 GND
Ground
N/A
Ground.
80
65
48
41 GND
Ground
N/A
Ground.
93
75
GND
Ground
N/A
Ground.
116
94
GND
Ground
N/A
Ground.
125
99
GND
Ground
N/A
Ground.
14
13
NC
N/A
N/A
No-connect. This pin must be left open.
15
14
NC
N/A
N/A
No-connect. This pin must be left open.
16
15
NC
N/A
N/A
No-connect. This pin must be left open.
Document #: 38-08012 Rev. *B
Page 29 of 50
CY7C68013
5.0
Register Summary
FX2 register bit definitions are described in the FX2 TRM in greater detail.
Table 5-1. FX2 Register Summary
Hex Size Name
Description
GPIF Waveform Memories
E400 128 WAVEDATA
GPIF Waveform Descriptor
0, 1, 2, 3 data
E480 384 reserved
GENERAL CONFIGURATION
E600 1 CPUCS
CPU Control & Status
E601 1 IFCONFIG
Interface Configuration
(Ports, GPIF, slave FIFOs)
[6]
E602 1 PINFLAGSAB
Slave FIFO FLAGA and
FLAGB Pin Configuration
[6]
E603 1 PINFLAGSCD
Slave FIFO FLAGC and
FLAGD Pin Configuration
E604 1 FIFORESET[6]
Restore FIFOS to default
state
E605 1 BREAKPT
Breakpoint Control
E606 1 BPADDRH
Breakpoint Address H
E607 1 BPADDRL
Breakpoint Address L
E608 1 UART230
230 Kbaud internally
generated ref. clock
[6]
E609 1 FIFOPINPOLAR Slave FIFO Interface pins
polarity
E60A 1 REVID
Chip Revision
E60B
1
E60C
1
3
E610
1
E611
E612
E613
E614
E615
E618
1
1
1
1
1
2
1
E619
1
E61A
1
E61B
1
E620
4
1
E621
1
E622
1
E623
1
E624
1
E625
1
E626
1
E627
1
E630
H.S.
E630
F.S.
E631
H.S.
8
1
1
1
REVCTL[6]
UDMA
GPIFHOLDTIME
reserved
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
0
IFCLKSRC
0
3048MHZ
PORTCSTB
IFCLKOE
CLKSPD1
IFCLKPOL
CLKSPD0
ASYNC
CLKINV
GSTATE
CLKOE
IFCFG1
8051RES
IFCFG0
00000010 rrbbbbbr
11000000
RW
FLAGB3
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0
00000000
RW
FLAGD3
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
01000000
RW
NAKALL
0
0
0
EP3
EP2
EP1
EP0
xxxxxxxx
W
0
A15
A7
0
0
A14
A6
0
0
A13
A5
0
0
A12
A4
0
BREAK
A11
A3
0
BPPULSE
A10
A2
0
BPEN
A9
A1
230UART1
0
00000000 rrrrbbbr
A8
xxxxxxxx
RW
A0
xxxxxxxx
RW
230UART0 00000000 rrrrrrbb
0
0
PKTEND
SLOE
SLRD
SLWR
EF
FF
00000000 rrbbbbbb
rv7
rv6
rv5
rv4
rv3
rv2
rv1
rv0
Chip Revision Control
0
0
0
0
0
0
dyn_out
enh_pkt
Rev A, B 00000000
Rev C, D 00000010
Rev E 00000100
00000000
rrrrrrbb
MSTB Hold Time (for UDMA)
0
0
0
0
0
0
HOLDTIME1 HOLDTIME0 00000000
rrrrrrbb
VALID
0
TYPE1
TYPE0
0
0
0
0
VALID
VALID
VALID
VALID
VALID
0
DIR
DIR
DIR
DIR
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE0
TYPE0
TYPE0
TYPE0
TYPE0
0
SIZE
0
SIZE
0
0
0
0
0
0
0
BUF1
0
BUF1
0
0
BUF0
0
BUF0
0
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
RW
0
0
0
0
0
0
PL9
PL8
00000010
rrrrrrbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
RW
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
RW
0
0
0
0
0
0
PL9
PL8
00000010
rrrrrrbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
RW
DECIS
PKTSTAT
0
PFC9
DECIS
PKTSTAT
0
PFC9
PFC7
PFC6
PFC2
PFC1
ENDPOINT CONFIGURATION
EP1OUTCFG
Endpoint 1-OUT Configuration
EP1INCFG
Endpoint 1-IN Configuration
EP2CFG
Endpoint 2 Configuration
EP4CFG
Endpoint 4 Configuration
EP6CFG
Endpoint 6 Configuration
EP8CFG
Endpoint 8 Configuration
reserved
[6]
EP2FIFOCFG
Endpoint 2 / slave FIFO configuration
[6]
EP4FIFOCFG
Endpoint 4 / slave FIFO configuration
[6]
EP6FIFOCFG
Endpoint 6 / slave FIFO configuration
EP8FIFOCFG[6] Endpoint 8 / slave FIFO configuration
reserved
EP2AUTOINLENH Endpoint 2 AUTOIN Packet
[6]
Length H
EP2AUTOINLENL Endpoint 2 AUTOIN Packet
[6]
Length L
EP4AUTOINLENH Endpoint 4 AUTOIN Packet
[6]
Length H
EP4AUTOINLENL Endpoint 4 AUTOIN Packet
[6]
Length L
EP6AUTOINLENH Endpoint 6 AUTOIN Packet
[6]
Length H
EP6AUTOINLENL Endpoint 6 AUTOIN Packet
[6]
Length L
EP8AUTOINLENH Endpoint 8 AUTOIN Packet
[6]
Length H
EP8AUTOINLENL Endpoint 8 AUTOIN Packet
[6]
Length L
reserved
EP2FIFOPFH[6]
Endpoint 2 / slave FIFO Programmable Flag H
EP2FIFOPFH[6]
Endpoint 2 / slave FIFO Programmable Flag H
[6]
EP2FIFOPFL
Endpoint 2 / slave FIFO Programmable Flag L
IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
OUT:PFC12 OUT:PFC11 OUT:PFC10
PFC5
PFC4
PFC3
PFC8
R
10100000 brbbrrrr
10100000
10100010
10100000
11100010
11100000
brbbrrrr
bbbbbrbb
bbbbrrrr
bbbbbrbb
bbbbrrrr
10001000 bbbbbrbb
IN:PKTS[2] 10001000 bbbbbrbb
OUT:PFC8
PFC0
00000000
RW
Note:
6. Read and writes to these register may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
Document #: 38-08012 Rev. *B
Page 30 of 50
CY7C68013
Table 5-1. FX2 Register Summary (continued)
Hex Size Name
E631 1 EP2FIFOPFL[6]
F.S
E632 1 EP4FIFOPFH[6]
H.S.
E632 1 EP4FIFOPFH[6]
F.S
E633 1 EP4FIFOPFL[6]
H.S.
E633 1 EP4FIFOPFL[6]
F.S
E634 1 EP6FIFOPFH[6]
H.S.
E634 1 EP6FIFOPFH[6]
F.S
E635 1 EP6FIFOPFL[6]
H.S.
E635 1 EP6FIFOPFL[6]
F.S
E636 1 EP8FIFOPFH[6]
H.S.
E636 1 EP8FIFOPFH[6]
F.S
E637
H.S.
E637
F.S
[6]
1
EP8FIFOPFL
1
EP8FIFOPFL[6]
E640
8
1
reserved
EP2ISOINPKTS
E641
1
EP4ISOINPKTS
E642
1
EP6ISOINPKTS
E643
1
EP8ISOINPKTS
4
reserved
E648
E649
1
7
E650
1
INPKTEND[6]
OUTPKTEND[6]
INTERRUPTS
EP2FIFOIE[6]
E651
1
EP2FIFOIRQ[6]
E652
1
EP4FIFOIE[6]
E653
1
EP4FIFOIRQ[6]
1
EP6FIFOIE[6]
E655
1
EP6FIFOIRQ[6]
E656
1
EP8FIFOIE[6]
E657
1
EP8FIFOIRQ[6]
E658
1
IBNIE
E654
E659
1
IBNIRQ
E65A
1
NAKIE
E65B
1
NAKIRQ
E65C
E65D
E65E
E65F
E660
E661
E662
E663
1
1
1
1
1
1
1
1
USBIE
USBIRQ
EPIE
EPIRQ
GPIFIE[6]
GPIFIRQ[6]
USBERRIE
USBERRIRQ
E664
E665
E666
E667
1
1
1
1
ERRCNTLIM
CLRERRCNT
INT2IVEC
INT4IVEC
E668
1
INTSETUP
Description
Endpoint 2 / slave FIFO Programmable Flag L
Endpoint 4 / slave FIFO Programmable Flag H
Endpoint 4 / slave FIFO Programmable Flag H
Endpoint 4 / slave FIFO Programmable Flag L
Endpoint 4 / slave FIFO Programmable Flag L
Endpoint 6 / slave FIFO Programmable Flag H
Endpoint 6 / slave FIFO Programmable Flag H
Endpoint 6 / slave FIFO Programmable Flag L
Endpoint 6 / slave FIFO Programmable Flag L
Endpoint 8 / slave FIFO Programmable Flag H
Endpoint 8 / slave FIFO Programmable Flag H
b7
IN:PKTS[1]
OUT:PFC7
DECIS
b6
IN:PKTS[0]
OUT:PFC6
PKTSTAT
b5
PFC5
DECIS
PKTSTAT
0
PFC7
PFC6
PFC5
PFC4
PFC5
PFC4
IN: PKTS[1] IN: PKTS[0]
OUT:PFC7 OUT:PFC6
DECIS
PKTSTAT
Force IN Packet End
Force OUT Packet End
Endpoint 2 slave FIFO Flag
Interrupt Enable
Endpoint 2 slave FIFO Flag
Interrupt Request
Endpoint 4 slave FIFO Flag
Interrupt Enable
Endpoint 4 slave FIFO Flag
Interrupt Request
Endpoint 6 slave FIFO Flag
Interrupt Enable
Endpoint 6 slave FIFO Flag
Interrupt Request
Endpoint 8 slave FIFO Flag
Interrupt Enable
Endpoint 8 slave FIFO Flag
Interrupt Request
IN-BULK-NAK Interrupt Enable
IN-BULK-NAK interrupt Request
Endpoint Ping-NAK / IBN Interrupt Enable
Endpoint Ping-NAK / IBN Interrupt Request
USB Int Enables
USB Interrupt Requests
Endpoint Interrupt Enables
Endpoint Interrupt Requests
GPIF Interrupt Enable
GPIF Interrupt Request
USB Error Interrupt Enables
USB Error Interrupt Requests
USB Error counter and limit
Clear Error Counter EC3:0
Interrupt 2 (USB) Autovector
Interrupt 4 (slave FIFO &
GPIF) Autovector
Interrupt 2&4 Setup
Document #: 38-08012 Rev. *B
b3
PFC3
b2
PFC2
b1
PFC1
b0
PFC0
Default Access
00000000
RW
0
0
PFC8
10001000 bbrbbrrb
0
0
PFC8
10001000 bbrbbrrb
PFC3
PFC2
PFC1
PFC0
00000000
RW
PFC3
PFC2
PFC1
PFC0
00000000
RW
0
PFC9
PFC8
00001000 bbbbbrbb
0
PFC9
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
OUT:PFC10 OUT:PFC9
IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
OUT:PFC12 OUT:PFC11 OUT:PFC10
DECIS
PKTSTAT
PFC7
PFC6
PFC5
IN:PKTS[1]
OUT:PFC7
DECIS
IN:PKTS[0]
OUT:PFC6
PKTSTAT
PFC5
DECIS
PKTSTAT
0
Endpoint 8 / slave FIFO ProPFC7
PFC6
grammable Flag L
Endpoint 8 / slave FIFO Pro- IN: PKTS[1] IN: PKTS[0]
grammable Flag L
OUT:PFC7 OUT:PFC6
EP2 (if ISO) IN Packets per
frame (1-3)
EP4 (if ISO) IN Packets per
frame (1-3)
EP6 (if ISO) IN Packets per
frame (1-3)
EP8 (if ISO) IN Packets per
frame (1-3)
0
b4
PFC4
0
IN:PKTS[2] 00001000 bbbbbrbb
OUT:PFC8
PFC0
00000000
RW
PFC4
PFC3
PFC2
PFC1
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
0
0
PFC8
00001000 bbrbbrrb
0
0
PFC8
00001000 bbrbbrrb
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
OUT:PFC10 OUT:PFC9
RW
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
RW
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
RW
0
0
0
0
0
0
INPPF1
INPPF0
00000001
rrrrrrbb
0
0
0
0
0
0
INPPF1
INPPF0
00000001
rrrrrrbb
0
0
0
0
0
0
INPPF1
INPPF0
00000001
rrrrrrbb
0
0
0
0
0
0
INPPF1
INPPF0
00000001
rrrrrrbb
Skip
Skip
0
0
0
0
0
0
EP3
EP3
EP2
EP2
EP1
EP1
EP0
EP0
xxxxxxxx
xxxxxxxx
R/W
W
0
0
0
0
EDGEPF
PF
EF
FF
00000000
RW
0
0
0
0
0
PF
EF
FF
00000xxx
RW
0
0
0
0
EDGEPF
PF
EF
FF
00000000
RW
0
0
0
0
0
PF
EF
FF
00000xxx
RW
0
0
0
0
EDGEPF
PF
EF
FF
00000000
RW
0
0
0
0
0
PF
EF
FF
00000xxx
RW
0
0
0
0
EDGEPF
PF
EF
FF
00000000
RW
0
0
0
0
0
PF
EF
FF
00000xxx
RW
0
0
EP8
EP6
EP4
EP2
EP1
EP0
00000000
RW
0
0
EP8
EP6
EP4
EP2
EP1
EP0
00xxxxxx
RW
EP8
EP6
EP4
EP2
EP1
EP0
0
IBN
00000000
RW
EP8
EP6
EP4
EP2
EP1
EP0
0
IBN
xxxxxxxx
RW
0
0
EP8
EP8
0
0
ISOEP8
ISOEP8
EP0ACK
EP0ACK
EP6
EP6
0
0
ISOEP6
ISOEP6
HSGRANT
HSGRANT
EP4
EP4
0
0
ISOEP4
ISOEP4
URES
URES
EP2
EP2
0
0
ISOEP2
ISOEP2
SUSP
SUSP
EP1OUT
EP1OUT
0
0
0
0
SUTOK
SUTOK
EP1IN
EP1IN
0
0
0
0
SOF
SOF
EP0OUT
EP0OUT
GPIFWF
GPIFWF
0
0
SUDAV
SUDAV
EP0IN
EP0IN
GPIFDONE
GPIFDONE
ERRLIMIT
ERRLIMIT
00000000
0xxxxxxx
00000000
xxxxxxxx
00000000
000000xx
00000000
xxxx000x
RW
RW
RW
RW
RW
RW
RW
RW
EC3
x
0
1
EC2
x
I2V4
0
EC1
x
I2V3
I4V3
EC0
x
I2V2
I4V2
LIMIT3
x
I2V1
I4V1
LIMIT2
x
I2V0
I4V0
LIMIT1
x
0
0
LIMIT0
x
0
0
xxxx0100 rrrrbbbb
xxxxxxxx
W
00000000
R
10000000
R
0
0
0
0
AV2EN
0
INT4SRC
AV4EN
00000000
RW
Page 31 of 50
CY7C68013
Table 5-1. FX2 Register Summary (continued)
Hex Size Name
Description
E669 7 reserved
INPUT / OUTPUT
E670 1 PORTACFG
I/O PORTA Alternate Configuration
E671 1 PORTCCFG
I/O PORTC Alternate Configuration
E672 1 PORTECFG
I/O PORTE Alternate Configuration
E673 5 reserved
E678 1 I2CS
I²C-Compatible Bus
Control & Status
E679 1 I2DAT
I²C-Compatible Bus
Data
E67A 1 I2CTL
I²C-Compatible Bus
Control
E67B 1 XAUTODAT1
Autoptr1 MOVX access,
when APTREN=1
E67C 1 XAUTODAT2
Autoptr2 MOVX access,
when APTREN=1
UDMA CRC
E67D 1 UDMACRCH[6]
UDMA CRC MSB
E67E
E67F
1
1
E680
E681
E682
E683
E684
E685
E686
E687
E688
1
1
1
1
1
1
1
1
2
UDMACRCL[6]
UDMACRCQUALIFIER
USB CONTROL
USBCS
SUSPEND
WAKEUPCS
TOGCTL
USBFRAMEH
USBFRAMEL
MICROFRAME
FNADDR
reserved
E68A
E68B
E68C
E68D
E68E
E68F
E690
E691
E692
E694
E695
E696
E698
E699
E69A
E69C
E69D
E69E
E6A0
1
1
1
1
1
1
1
1
2
1
1
2
1
1
2
1
1
2
1
ENDPOINTS
EP0BCH[6]
EP0BCL[6]
reserved
EP1OUTBC
reserved
EP1INBC
EP2BCH[6]
EP2BCL[6]
reserved
EP4BCH[6]
EP4BCL[6]
reserved
EP6BCH[6]
EP6BCL[6]
reserved
EP8BCH[6]
EP8BCL[6]
reserved
EP0CS
E6A1
1
EP1OUTCS
E6A2
1
EP1INCS
E6A3
1
EP2CS
E6A4
1
EP4CS
E6A5
1
EP6CS
E6A6
1
EP8CS
E6A7
E6A8
E6A9
E6AA
E6AB
1
1
1
1
1
EP2FIFOFLGS
EP4FIFOFLGS
EP6FIFOFLGS
EP8FIFOFLGS
EP2FIFOBCH
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
FLAGD
SLCS
0
0
0
0
INT1
INT0
00000000
RW
GPIFA7
GPIFA6
GPIFA5
GPIFA4
GPIFA3
GPIFA2
GPIFA1
GPIFA0
00000000
RW
GPIFA8
T2EX
INT6
RXD1OUT
RXD0OUT
T2OUT
T1OUT
T0OUT
00000000
RW
START
STOP
LASTRD
ID1
ID0
BERR
ACK
DONE
000xx000
bbbrrrrr
d7
d6
d5
d4
d3
d2
d1
d0
xxxxxxxx
RW
0
0
0
0
0
0
STOPIE
400KHZ
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
CRC15
CRC14
CRC13
CRC12
CRC11
CRC10
CRC9
CRC8
01001010
RW
CRC7
QENABLE
CRC6
0
CRC5
0
CRC4
0
CRC3
QSTATE
CRC2
QSIGNAL2
CRC1
QSIGNAL1
USB Control & Status
Put chip into suspend
Wakeup Control & Status
Toggle Control
USB Frame count H
USB Frame count L
Microframe count, 0-7
USB Function address
HSM
x
WU2
Q
0
FC7
0
0
0
x
WU
S
0
FC6
0
FA6
0
x
WU2POL
R
0
FC5
0
FA5
0
x
WUPOL
IO
0
FC4
0
FA4
DISCON
x
0
EP3
0
FC3
0
FA3
NOSYNSOF
x
DPEN
EP2
FC10
FC2
MF2
FA2
RENUM
x
WU2EN
EP1
FC9
FC1
MF1
FA1
SIGRSUME
x
WUEN
EP0
FC8
FC0
MF0
FA0
Endpoint 0 Byte Count H
Endpoint 0 Byte Count L
(BC15)
(BC7)
(BC14)
BC6
(BC13)
BC5
(BC12)
BC4
(BC11)
BC3
(BC10)
BC2
(BC9)
BC1
(BC8)
BC0
xxxxxxxx
xxxxxxxx
RW
RW
0
BC6
BC5
BC4
BC3
BC2
BC1
BC0
0xxxxxxx
RW
Endpoint 1 IN Byte Count
Endpoint 2 Byte Count H
Endpoint 2 Byte Count L
0
0
BC7/SKIP
BC6
0
BC6
BC5
0
BC5
BC4
0
BC4
BC3
0
BC3
BC2
BC10
BC2
BC1
BC9
BC1
BC0
BC8
BC0
0xxxxxxx
00000xxx
xxxxxxxx
RW
RW
RW
Endpoint 4 Byte Count H
Endpoint 4 Byte Count L
0
BC7/SKIP
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC9
BC1
BC8
BC0
000000xx
xxxxxxxx
RW
RW
Endpoint 6 Byte Count H
Endpoint 6 Byte Count L
0
BC7/SKIP
0
BC6
0
BC5
0
BC4
0
BC3
BC10
BC2
BC9
BC1
BC8
BC0
00000xxx
xxxxxxxx
RW
RW
Endpoint 8 Byte Count H
Endpoint 8 Byte Count L
0
BC7/SKIP
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC9
BC1
BC8
BC0
000000xx
xxxxxxxx
RW
RW
HSNAK
0
0
0
0
0
BUSY
STALL
10000000 bbbbbbrb
0
0
0
0
0
0
BUSY
STALL
00000000 bbbbbbrb
0
0
0
0
0
0
BUSY
STALL
00000000 bbbbbbrb
0
NPAK2
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00101000
rrrrrrrb
0
0
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00101000
rrrrrrrb
0
NPAK2
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00000100
rrrrrrrb
0
0
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00000100
rrrrrrrb
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BC12
0
0
0
0
BC11
PF
PF
PF
PF
BC10
EF
EF
EF
EF
BC9
FF
FF
FF
FF
BC8
00000010
00000010
00000110
00000110
00000000
R
R
R
R
R
UDMA CRC LSB
UDMA CRC Qualifier
Endpoint 1 OUT Byte Count
Endpoint 0 Control and Status
Endpoint 1 OUT Control and
Status
Endpoint 1 IN Control and
Status
Endpoint 2 Control and Status
Endpoint 4 Control and Status
Endpoint 6 Control and Status
Endpoint 8 Control and Status
Endpoint 2 slave FIFO Flags
Endpoint 4 slave FIFO Flags
Endpoint 6 slave FIFO Flags
Endpoint 8 slave FIFO Flags
Endpoint 2 slave FIFO total
byte count H
Document #: 38-08012 Rev. *B
CRC0
10111010
RW
QSIGNAL0 00000000 brrrbbbb
x0000000 rrrrbbbb
xxxxxxxx
W
xx000101 bbbbrbbb
xxxxxxxx rbbbbbbb
00000xxx
R
xxxxxxxx
R
00000xxx
R
0xxxxxxx
R
Page 32 of 50
CY7C68013
Table 5-1. FX2 Register Summary (continued)
Hex Size Name
E6A 1 EP2FIFOBCL
C
E6A 1 EP4FIFOBCH
D
E6AE 1 EP4FIFOBCL
E6AF
1
EP6FIFOBCH
E6B0
1
EP6FIFOBCL
E6B1
1
EP8FIFOBCH
E6B2
1
EP8FIFOBCL
E6B3
1
SUDPTRH
E6B4
1
SUDPTRL
E6B5
1
SUDPTRCTL
E6B8
2
8
reserved
SETUPDAT
Description
Endpoint 2 slave FIFO total
byte count L
Endpoint 4 slave FIFO total
byte count H
Endpoint 4 slave FIFO total
byte count L
Endpoint 6 slave FIFO total
byte count H
Endpoint 6 slave FIFO total
byte count L
Endpoint 8 slave FIFO total
byte count H
Endpoint 8 slave FIFO total
byte count L
Setup Data Pointer high address byte
Setup Data Pointer low address byte
Setup Data Pointer Auto
Mode
8 bytes of SETUP data
b7
BC7
b6
BC6
b5
BC5
b4
BC4
b3
BC3
b2
BC2
b1
BC1
b0
BC0
Default Access
00000000
R
0
0
0
0
0
BC10
BC9
BC8
00000000
R
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
R
0
0
0
0
BC11
BC10
BC9
BC8
00000000
R
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
R
0
0
0
0
0
BC10
BC9
BC8
00000000
R
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
R
A15
A14
A13
A12
A11
A10
A9
A8
xxxxxxxx
RW
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
SDPAUTO
00000001
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
R
FIFOWR0
0
FIFORD1
0
FIFORD0
IDLEDRV
11100100
10000000
RW
RW
CTL2
CTL2
0
GPIFA2
CTL1
CTL1
0
GPIFA1
CTL0
CTL0
GPIFA8
GPIFA0
11111111
00000000
00000000
00000000
RW
RW
RW
RW
FS2
FS1
FS0
TERMB2
CTL2
TERMB1
CTL1
TERMB0
CTL0
00000000
00000000
RW
RW
xxxxxxx0 bbbbbbbr
SETUPDAT[0] =
bmRequestType
SETUPDAT[1] = bmRequest
SETUPDAT[2:3] = wValue
SETUPDAT[4:5] = wIndex
SETUPDAT[6:7] = wLength
E6C0
E6C1
1
1
E6C2
E6C3
E6C4
E6C5
1
1
1
1
E6C6
1
E6C7
E6C8
1
1
E6C9
1
E6C
A
E6C
B
E6C
C
E6C
D
E6C
E
E6CF
1
GPIF
GPIFWFSELECT Waveform Selector
SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1
GPIFIDLECS
GPIF Done, GPIF IDLE drive
DONE
0
0
0
0
mode
GPIFIDLECTL
Inactive Bus, CTL states
0
0
CTL5
CTL4
CTL3
GPIFCTLCFG
CTL Drive Type
TRICTL
0
CTL5
CTL4
CTL3
GPIFADRH[6]
GPIF Address H
0
0
0
0
0
GPIFADRL[6]
GPIF Address L
GPIFA7
GPIFA6
GPIFA5
GPIFA4
GPIFA3
FLOWSTATE
FLOWSTATE
Flowstate Enable and SelecFSE
0
0
0
0
tor
FLOWLOGIC
Flowstate Logic
LFUNC1
LFUNC0
TERMA2
TERMA1
TERMA0
FLOWEQ0CTL
CTL-Pin States in Flowstate
CTL0E3
CTL0E2
CTL0E1/
CTL0E0/
CTL3
(when Logic = 0)
CTL5
CTL4
FLOWEQ1CTL
CTL-Pin States in Flowstate
CTL0E3
CTL0E2
CTL0E1/
CTL0E0/
CTL3
(when Logic = 1)
CTL5
CTL4
FLOWHOLDOFF Holdoff Configuration
HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 HOSTATE
1
FLOWSTB
E6D0
1
E6D1
1
00000000 brrrrbbb
CTL2
CTL1
CTL0
00000000
RW
HOCTL2
HOCTL1
HOCTL0
00010010
RW
Flowstate Strobe Configuration
FLOWSTBEDGE Flowstate Rising/Falling
Edge Configuration
FLOWSTBPERI- Master-Strobe Half-Period
OD
GPIFTCB3[6]
GPIF Transaction Count
Byte 3
GPIFTCB2[6]
GPIF Transaction Count
Byte 2
[6]
GPIFTCB1
GPIF Transaction Count
Byte 1
[6]
GPIFTCB0
GPIF Transaction Count
Byte 0
reserved
reserved
reserved
EP2GPIFFLGSEL Endpoint 2 GPIF Flag select
[6]
EP2GPIFPFSTOP Endpoint 2 GPIF stop transaction on prog. flag
EP2GPIFTRIG[6] Endpoint 2 GPIF Trigger
reserved
reserved
reserved
EP4GPIFFLGSEL Endpoint 4 GPIF Flag select
SLAVE
RDYASYNC
CTLTOGL
SUSTAIN
0
MSTB2
MSTB1
MSTB0
00100000
RW
0
0
0
0
0
0
FALLING
RISING
00000001
rrrrrrbb
1
EP4GPIFPFSTOP Endpoint 4 GPIF stop transaction on GPIF Flag
EP4GPIFTRIG[6] Endpoint 4 GPIF Trigger
3
reserved
1
1
1
1
2
E6D2
1
E6D3
1
E6D4
1
3
E6D
A
E6D
B
E6D
C
1
1
[6]
Document #: 38-08012 Rev. *B
D7
D6
D5
D4
D3
D2
D1
D0
00000010
RW
TC31
TC30
TC29
TC28
TC27
TC26
TC25
TC24
00000000
RW
TC23
TC22
TC21
TC20
TC19
TC18
TC17
TC16
00000000
RW
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
00000000
RW
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
00000001
RW
00000000
RW
00000000
RW
FIFO2FLAG 00000000
RW
0
0
0
0
0
0
FS1
0
0
0
0
0
0
0
x
x
x
x
x
x
x
0
0
0
0
0
0
FS1
0
0
0
0
0
0
0
x
x
x
x
x
x
x
FS0
x
xxxxxxxx
W
FS0
00000000
RW
FIFO4FLAG 00000000
RW
x
xxxxxxxx
W
Page 33 of 50
CY7C68013
Table 5-1. FX2 Register Summary (continued)
Hex Size Name
Description
reserved
reserved
E6E2 1 EP6GPIFFLGSEL Endpoint 6 GPIF Flag select
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
0
0
0
0
0
0
FS1
FS0
00000000
RW
EP6GPIFPFSTOP Endpoint 6 GPIF stop transaction on prog. flag
EP6GPIFTRIG[6] Endpoint 6 GPIF Trigger
reserved
reserved
reserved
EP8GPIFFLGSEL Endpoint 8 GPIF Flag select
0
0
0
0
0
0
0
FIFO6FLAG 00000000
RW
x
x
x
x
x
x
x
0
0
0
0
0
0
FS1
EP8GPIFPFSTOP Endpoint 8 GPIF stop transaction on prog. flag
EP8GPIFTRIG[6] Endpoint 8 GPIF Trigger
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
xxxxxxxx
W
D15
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
xxxxxxxx
R
[6]
E6E3
1
E6E4
1
3
E6EA
1
E6EB
1
E6E
C
1
E6F0
3
1
E6F1
1
E6F2
1
E6F3
1
E6F4
E6F5
E6F6
1
1
2
E740
E780
E7C0
F000
F400
F600
F800
FC00
FE00
xxxx
[6]
reserved
XGPIFSGLDATH GPIF Data H (16-bit mode
only)
XGPIFSGLDATLX Read/Write GPIF Data L &
trigger transaction
XGPIFSGLDATL- Read GPIF Data L, no transNOX
action trigger
GPIFREADYCFG Internal RDY, Sync/Async,
RDY pin states
GPIFREADYSTAT GPIF Ready Status
GPIFABORT
Abort GPIF Waveforms
reserved
ENDPOINT BUFFERS
64 EP0BUF
EP0-IN/-OUT buffer
64 EP10UTBUF
EP1-OUT buffer
64 EP1INBUF
EP1-IN buffer
2048 reserved
1024 EP2FIFOBUF
512/1024-byte EP 2 / slave
FIFO buffer (IN or OUT)
512 EP4FIFOBUF
512 byte EP 4 / slave FIFO
buffer (IN or OUT)
512 reserved
1024 EP6FIFOBUF
512/1024-byte EP 6 / slave
FIFO buffer (IN or OUT)
512 EP8FIFOBUF
512 byte EP 8 / slave FIFO
buffer (IN or OUT)
512 reserved
I²C Compatible Configuration Byte
80
81
82
83
84
85
86
87
88
1
1
1
1
1
1
1
1
1
89
8A
8B
8C
8D
8E
8F
90
91
92
1
1
1
1
1
1
1
1
1
1
93
98
5
1
99
1
Special Function Registers (SFRs)
IOA[7]
Port A (bit addressable)
SP
Stack Pointer
DPL0
Data Pointer 0 L
DPH0
Data Pointer 0 H
DPL1[7]
Data Pointer 1 L
DPH1[7]
Data Pointer 1 H
DPS[7]
Data Pointer 0/1 select
PCON
Power Control
TCON
Timer/Counter Control (bit
addressable)
TMOD
Timer/Counter Mode Control
TL0
Timer 0 reload L
TL1
Timer 1 reload L
TH0
Timer 0 reload H
TH1
Timer 1 reload H
CKCON[7]
Clock Control
reserved
IOB[7]
Port B (bit addressable)
EXIF[7]
External Interrupt Flag(s)
MPAGE[7]
Upper Addr Byte of MOVX
using @R0 / @R1
reserved
SCON0
Serial Port 0 Control (bit addressable)
SBUF0
Serial Port 0 Data Buffer
x
xxxxxxxx
W
FS0
00000000
RW
FIFO8FLAG 00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
INTRDY
SAS
TCXRDY5
0
0
0
0
0
0
x
0
x
RDY5
x
RDY4
x
RDY3
x
RDY2
x
RDY1
x
RDY0
x
00xxxxxx
xxxxxxxx
R
W
D7
D7
D7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
xxxxxxxx
xxxxxxxx
xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
RW
RW
RW
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
0
DISCON
0
0
0
0
0
400KHZ
xxxxxxxx
n/a
D7
D7
A7
A15
A7
A15
0
SMOD0
TF1
D6
D6
A6
A14
A6
A14
0
x
TR1
D5
D5
A5
A13
A5
A13
0
1
TF0
D4
D4
A4
A12
A4
A12
0
1
TR0
D3
D3
A3
A11
A3
A11
0
GF1
IE1
D2
D2
A2
A10
A2
A10
0
GF0
IT1
D1
D1
A1
A9
A1
A9
0
STOP
IE0
D0
D0
A0
A8
A0
A8
SEL
IDLE
IT0
xxxxxxxx
00000111
00000000
00000000
00000000
00000000
00000000
00110000
00000000
RW
RW
RW
RW
RW
RW
RW
RW
RW
GATE
D7
D7
D15
D15
x
CT
D6
D6
D14
D14
x
M1
D5
D5
D13
D13
T2M
M0
D4
D4
D12
D12
T1M
GATE
D3
D3
D11
D11
T0M
CT
D2
D2
D10
D10
MD2
M1
D1
D1
D9
D9
MD1
M0
D0
D0
D8
D8
MD0
00000000
00000000
00000000
00000000
00000000
00000001
RW
RW
RW
RW
RW
RW
D7
IE5
A15
D6
IE4
A14
D5
I²CINT
A13
D4
USBNT
A12
D3
1
A11
D2
0
A10
D1
0
A9
D0
0
A8
xxxxxxxx
00001000
00000000
RW
RW
RW
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
00000000 bbbrrrrr
[8]
Notes:
7. SFRs not part of the standard 8051 architecture.
8. If no EEPROM is detected by the SIE then the default is 00000000.
Document #: 38-08012 Rev. *B
Page 34 of 50
CY7C68013
Table 5-1. FX2 Register Summary (continued)
Hex Size Name
9A
1 AUTOPTRH1[7]
9B
1 AUTOPTRL1[7]
9C
1 reserved
9D
1 AUTOPTRH2[7]
9E
1 AUTOPTRL2[7]
9F
1 reserved
A0
1 IOC[7]
A1
1 INT2CLR[7]
A2
1 INT4CLR[7]
A3
5 reserved
A8
1 IE
A9
AA
AB
1
1
1
AC
1
AD
AF
2
1
Description
Autopointer 1 Address H
Autopointer 1 Address L
b7
A15
A7
b6
A14
A6
b5
A13
A5
b4
A12
A4
b3
A11
A3
b2
A10
A2
b1
A9
A1
b0
A8
A0
Default Access
00000000
RW
00000000
RW
Autopointer 2 Address H
Autopointer 2 Address L
A15
A7
A14
A6
A13
A5
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
00000000
00000000
RW
RW
Port C (bit addressable)
Interrupt 2 clear
Interrupt 4 clear
D7
x
x
D6
x
x
D5
x
x
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
xxxxxxxx
xxxxxxxx
xxxxxxxx
RW
W
W
Interrupt Enable (bit addressable)
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
00000000
RW
EP8F
0
EP8E
EP4PF
EP6F
EP4EF
EP6E
EP4FF
EP4F
0
EP4E
EP2PF
EP2F
EP2EF
EP2E
EP2FF
01011010
00100010
R
R
0
EP8PF
EP8EF
EP8FF
0
EP6PF
EP6EF
EP6FF
01100110
R
0
0
0
0
0
APTR2INC
APTR1INC
APTREN
00000110
RW
Port D (bit addressable)
Port E (NOT bit addressable)
Port A Output Enable
Port B Output Enable
Port C Output Enable
Port D Output Enable
Port E Output Enable
D7
D7
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
D0
xxxxxxxx
xxxxxxxx
00000000
00000000
00000000
00000000
00000000
RW
RW
RW
RW
RW
RW
RW
Interrupt Priority (bit addressable)
1
PS1
PT2
PS0
PT1
PX1
PT0
PX0
10000000
RW
Endpoint 0&1 Status
Endpoint 2,4,6,8 GPIF slave
FIFO Trigger
0
DONE
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx
RW
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx
xxxxxxxx
RW
R
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CT2
CPRL2
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
D7
D15
D6
D14
D5
D13
D4
D12
D3
D11
D2
D10
D1
D9
D0
D8
00000000
00000000
RW
RW
CY
AC
F0
RS1
RS0
OV
F1
P
00000000
RW
SMOD1
1
ERESI
RESI
INT6
0
0
0
01000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
1
1
1
EX6
EX5
EX4
EI²C
EUSB
11100000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
1
1
1
PX6
PX5
PX4
PI²C
PUSB
11100000
RW
reserved
EP2468STAT[7]
Endpoint 2,4,6,8 status flags
EP24FIFOFLGS[7] Endpoint 2,4 slave FIFO status flags
EP68FIFOFLGS[7] Endpoint 6,8 slave FIFO status flags
reserved
AUTOPTRSETAutopointer 1&2 Setup
UP[7]
B0
B1
B2
B3
B4
B5
B6
B7
B8
1
1
1
1
1
1
1
1
1
IOD[7]
B9
BA
BB
1
1
1
reserved
EP01STAT[7]
GPIFTRIG[7] [6]
BC
BD
1
1
BE
BF
1
1
C0
1
C1
C2
C8
1
6
1
C9
CA
1
1
CB
1
CC
CD
CE
D0
1
1
2
1
D1
D8
D9
E0
7
1
7
1
E1
E8
E9
F0
F1
F8
7
1
7
1
7
1
F9
7
reserved
GPIFSGLDATH[7] GPIF Data H (16-bit mode
only)
GPIFSGLDATLX[7] GPIF Data L w/ Trigger
GPIFSGLDATL- GPIF Data L w/ No Trigger
NOX[7]
SCON1[7]
Serial Port 1 Control (bit addressable)
[7]
SBUF1
Serial Port 1 Data Buffer
reserved
T2CON
Timer/Counter 2 Control (bit
addressable)
reserved
RCAP2L
Capture for Timer 2, auto-reload, up-counter
RCAP2H
Capture for Timer 2, auto-reload, up-counter
TL2
Timer 2 reload L
TH2
Timer 2 reload H
reserved
PSW
Program Status Word (bit addressable)
reserved
EICON[7]
External Interrupt Control
reserved
ACC
Accumulator (bit addressable)
reserved
EIE[7]
External Interrupt Enable(s)
reserved
B
B (bit addressable)
reserved
EIP[7]
External Interrupt Priority
Control
reserved
IOE[7]
OEA[7]
OEB[7]
OEC[7]
OED[7]
OEE[7]
reserved
IP
EP1INBSY EP1OUTBSY
RW
EP1
EP0BSY
EP0
00000000
R
10000xxx brrrrbbb
R = all bits read-only
W = all bits write-only
r = read-only bit
w = write-only bit
b = both read/write bit
Document #: 38-08012 Rev. *B
Page 35 of 50
CY7C68013
6.0
Absolute Maximum Ratings
Storage Temperature .................................................................................................................................... –65°C to +150°C
Ambient Temperature with Power Supplied ........................................................................................................ 0°C to +70°C
Supply Voltage to Ground Potential ..................................................................................................................–0.5V to +4.0V
DC Input Voltage to Any Input Pin ................................................................................................................................. 5.25V
DC Voltage Applied to Outputs in High Z State....................................................................................... –0.5V to VCC + 0.5V
Power Dissipation ...................................................................................................................................................... 936 mW
Static Discharge Voltage ............................................................................................................................................ > 2000V
Max Output Current, per I/O port .................................................................................................................................. 10 mA
Max Output Current, all five I/O ports (128- and 100-pin packages) ............................................................................ 50 mA
7.0
Operating Conditions
TA (Ambient Temperature Under Bias) ............................................................................................................... 0°C to +70°C
Supply Voltage ..................................................................................................................................................+3.0V to +3.6V
Ground Voltage .................................................................................................................................................................... 0V
FOSC (Oscillator or Crystal Frequency) ...................................................................................................... 24 MHz ± 100 ppm
Parallel Resonant
8.0
DC Characteristics
Table 8-1. DC Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
VCC
Supply Voltage
VIH
Input HIGH Voltage
2
5.25
V
VIL
Input LOW Voltage
–0.5
0.8
V
II
Input Leakage Current
0< VIN < VCC
±10
µA
0.4
V
VOH
Output Voltage HIGH
IOUT = 4 mA
VOL
Output LOW Voltage
IOUT = –4 mA
IOH
Output Current HIGH
4
mA
IOL
Output Current LOW
4
mA
CIN
Input Pin Capacitance
Except D+/D–
10
pF
D+/D–
15
pF
400
µA
ISUSP
Suspend Current
ICC
Supply Current
8.1
2.4
V
Includes 1.5k internal pull-up
250
8051 running, connected to USB HS
200
260
mA
8051 running, connected to USB FS
90
150
mA
USB Transceiver
USB 2.0-certified in full- and high-speed modes.
Document #: 38-08012 Rev. *B
Page 36 of 50
CY7C68013
9.0
AC Electrical Characteristics
9.1
USB Transceiver
USB 2.0-certified in full- and high-speed modes.
9.2
Program Memory Read
tCL
CLKOUT
[9]
tAV
tAV
A[15..0]
tSTBH
tSTBL
PSEN#
[10]
tACC1
D[7..0]
tDH
data in
tSOEL
OE#
tSCSL
CS#
Figure 9-1. Program Memory Read Timing Diagram
Table 9-1. Program Memory Read Parameters
Parameter
tCL
Description
Min.
1/CLKOUT Frequency
Typ.
Max.
Unit
Notes
20.83
ns
48 MHz
41.66
ns
24 MHz
83.2
ns
12 MHz
tAV
Delay from Clock to Valid Address
0
10.7
ns
tSTBL
Clock to PSEN Low
0
8
ns
tSTBH
Clock to PSEN High
0
8
ns
tSOEL
Clock to OE Low
11.1
ns
tSCSL
Clock to CS Low
13
ns
tDSU
Data Set-up to Clock
tDH
Data Hold Time
9.6
ns
0
ns
Notes:
9. CLKOUT is shown with positive polarity.
10. tACC1 is computed from the above parameters as follows:
tACC1(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC1(48 MHz) = 3*tCL – tAV – tDSU = 43 ns.
Document #: 38-08012 Rev. *B
Page 37 of 50
CY7C68013
9.3
Data Memory Read
tCL
CLKOUT
Stretch = 0
[9]
tAV
tAV
A[15..0]
tSTBH
tSTBL
RD#
tSCSL
CS#
tSOEL
OE#
tDSU
[11]
tDH
tACC1
D[7..0]
data in
Stretch = 1
tCL
[9]
CLKOUT
tAV
A[15..0]
RD#
CS#
tDSU
[11]
tACC1
D[7..0]
tDH
data in
Figure 9-2. Data Memory Read Timing Diagram
Note:
11. tACC2 and tACC3 are computed from the above parameters as follows:
tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC2(48 MHz) = 3*tCL – tAV – tDSU = 43 ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 190 ns
tACC3(48 MHz) = 5*tCL – tAV – tDSU = 86 ns.
Table 9-2. Data Memory Read Parameters
Parameter
tCL
Description
Min.
1/CLKOUT Frequency
Typ.
Max.
Unit
20.83
ns
48 MHz
41.66
ns
24 MHz
83.2
ns
12 MHz
tAV
Delay from Clock to Valid Address
tSTBL
Clock to RD LOW
11
ns
tSTBH
Clock to RD HIGH
11
ns
tSCSL
Clock to CS LOW
13
ns
tSOEL
Clock to OE LOW
11.1
ns
tDSU
Data Set-up to Clock
tDH
Data Hold Time
Document #: 38-08012 Rev. *B
Notes
10.7
ns
9.6
ns
0
ns
Page 38 of 50
CY7C68013
9.4
Data Memory Write
tCL
CLKOUT
tAV
tSTBL
tSTBH
tAV
A[15..0]
WR#
tSCSL
CS#
tON1
tOFF1
data out
D[7..0]
Stretch = 1
tCL
CLKOUT
tAV
A[15..0]
WR#
CS#
tON1
tOFF1
data out
D[7..0]
Figure 9-3. Data Memory Write Timing Diagram
Table 9-3. Data Memory Write Parameters
Min.
Max.
Unit
tAV
Parameter
Delay from Clock to Valid Address
Description
0
10.7
ns
tSTBL
Clock to WR Pulse LOW
0
11.2
ns
tSTBH
Clock to WR Pulse HIGH
0
11.2
ns
tSCSL
Clock to CS Pulse LOW
13.0
ns
tON1
Clock to Data Turn-on
0
13.1
ns
tOFF1
Clock to Data Hold Time
0
13.1
ns
Document #: 38-08012 Rev. *B
Notes
Page 39 of 50
CY7C68013
9.5
GPIF Synchronous Signals
tIFCLK
IFCLK
tSGA
GPIFADR[8:0]
RDYX
tSRY
tRYH
DATA(input)
valid
tSGD
tDAH
CTLX
tXCTL
DATA(output)
N
N+1
tXGD
Figure 9-4. GPIF Synchronous Signals Timing Diagram[12]
Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[13, 14]
Parameter
Description
Min.
Max.
20.83
Unit
tIFCLK
IFCLK Period
ns
tSRY
RDYX to Clock Set-up Time
tRYH
Clock to RDYX
tSGD
GPIF Data to Clock Set-up Time
tDAH
GPIF Data Hold Time
tSGA
Clock to GPIF Address Propagation Delay
7.5
ns
tXGD
Clock to GPIF Data Output Propagation Delay
11
ns
tXCTL
Clock to CTLX Output Propagation Delay
6.7
ns
Min.
Max.
Unit
20.83
200
ns
8.9
ns
0
ns
9.2
ns
0
ns
Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[14]
Parameter
Description
tIFCLK
IFCLK Period
tSRY
RDYX to Clock Set-up Time
2.9
ns
tRYH
Clock to RDYX
3.7
ns
tSGD
GPIF Data to Clock Set-up Time
3.2
ns
tDAH
GPIF Data Hold Time
4.5
ns
tSGA
Clock to GPIF Address Propagation Delay
tXGD
Clock to GPIF Data Output Propagation Delay
tXCTL
Clock to CTLX Output Propagation Delay
11.5
ns
15
ns
10.7
ns
Notes:
12. Dashed lines denote signals with programmable polarity
13. GPIF asynchronous RDYx signals have a minimum set-up time of 50 ns when using internal 48-MHz IFCLK.
14. IFCLK must not exceed 48 MHz.
Document #: 38-08012 Rev. *B
Page 40 of 50
CY7C68013
9.6
Slave FIFO Synchronous Read
tIFCLK
IFCLK
tSRD
tRDH
SLRD
tXFLG
FLAGS
DATA
N
tOEon
N+1
tXFD
tOEoff
SLOE
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram[12]
Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[14]
Parameter
Description
Min.
Max.
Unit
tIFCLK
IFCLK Period
20.83
ns
tSRD
SLRD to Clock Set-up Time
18.7
ns
tRDH
Clock to SLRD Hold Time
0
ns
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
tXFLG
Clock to FLAGS Output Propagation Delay
9.5
ns
tXFD
Clock to FIFO Data Output Propagation Delay
11
ns
Min.
Max.
Unit
200
ns
Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[14]
Parameter
Description
tIFCLK
IFCLK Period
20.83
tSRD
SLRD to Clock Set-up Time
12.7
tRDH
Clock to SLRD Hold Time
3.7
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
tXFLG
Clock to FLAGS Output Propagation Delay
13.5
ns
tXFD
Clock to FIFO Data Output Propagation Delay
15
ns
Document #: 38-08012 Rev. *B
ns
ns
Page 41 of 50
CY7C68013
9.7
Slave FIFO Asynchronous Read
tRDpwh
SLRD
tRDpwl
FLAGS
tXFD
tXFLG
DATA
N+1
N
tOEon
tOEoff
SLOE
Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram[12]
Table 9-8. Slave FIFO Asynchronous Read Parameters[15]
Parameter
Description
Min.
Max.
Unit
tRDpwl
SLRD Pulse Width LOW
50
ns
tRDpwh
SLRD Pulse Width HIGH
50
ns
tXFLG
SLRD to FLAGS Output Propagation Delay
70
ns
tXFD
SLRD to FIFO Data Output Propagation Delay
15
ns
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
10.5
ns
Max.
Unit
SLOE Turn-off to FIFO Data Hold
tOEoff
Note:
15. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
9.8
Slave FIFO Synchronous Write
tIFCLK
IFCLK
SLWR
DATA
tSWR
tWRH
N
Z
tSFD
Z
tFDH
FLAGS
tXFLG
Figure 9-7. Slave FIFO Synchronous Write Timing Diagram[12]
Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK [14]
Parameter
Description
Min.
tIFCLK
IFCLK Period
20.83
ns
tSWR
SLWR to Clock Set-up Time
18.1
ns
tWRH
Clock to SLWR Hold Time
tSFD
FIFO Data to Clock Set-up Time
tFDH
Clock to FIFO Data Hold Time
tXFLG
Clock to FLAGS Output Propagation Time
Document #: 38-08012 Rev. *B
0
ns
9.2
ns
0
ns
9.5
ns
Page 42 of 50
CY7C68013
Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK [14]
Parameter
Description
Min.
Max.
Unit
200
ns
tIFCLK
IFCLK Period
20.83
tSWR
SLWR to Clock Set-up Time
12.1
ns
tWRH
Clock to SLWR Hold Time
3.6
ns
tSFD
FIFO Data to Clock Set-up Time
3.2
ns
tFDH
Clock to FIFO Data Hold Time
4.5
tXFLG
Clock to FLAGS Output Propagation Time
9.9
ns
13.5
ns
Max.
Unit
Slave FIFO Asynchronous Write
tWRpwh
SLWR/SLCS#
tWRpwl
tSFD
tFDH
DATA
tXFD
FLAGS
Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram[12]
Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [15]
Parameter
Description
Min.
tWRpwl
SLWR Pulse LOW
50
ns
tWRpwh
SLWR Pulse HIGH
70
ns
tSFD
SLWR to FIFO DATA Set-up Time
10
ns
tFDH
FIFO DATA to SLWR Hold Time
10
ns
tXFD
SLWR to FLAGS Output Propagation Delay
9.10
70
ns
Slave FIFO Synchronous Packet End Strobe
IFCLK
tPEH
PKTEND
tSPE
FLAGS
tXFLG
Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram[12]
Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK [14]
Parameter
Description
Min.
Max.
Unit
tIFCLK
IFCLK Period
20.83
tSPE
PKTEND to Clock Set-up Time
14.6
ns
tPEH
Clock to PKTEND Hold Time
0
ns
tXFLG
Clock to FLAGS Output Propagation Delay
Document #: 38-08012 Rev. *B
ns
9.5
ns
Page 43 of 50
CY7C68013
Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK [14]
Parameter
Description
Min.
Max.
Unit
20.83
200
ns
tIFCLK
IFCLK Period
tSPE
PKTEND to Clock Set-up Time
8.6
ns
tPEH
Clock to PKTEND Hold Time
2.5
ns
tXFLG
Clock to FLAGS Output Propagation Delay
9.11
13.5
ns
Slave FIFO Asynchronous Packet End Strobe
tPEpwh
PKTEND
tPEpwl
FLAGS
tXFLG
Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[12]
Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters[15]
Parameter
Description
Min.
Max.
Unit
tPEpwl
PKTEND Pulse Width LOW
50
ns
tPWpwh
PKTEND Pulse Width HIGH
50
ns
tXFLG
PKTEND to FLAGS Output Propagation Delay
9.12
70
ns
Max.
Unit
Slave FIFO Output Enable
SLOE
tOEon
DATA
tOEoff
Figure 9-11. Slave FIFO Output Enable Timing Diagram[12]
Table 9-15. Slave FIFO Output Enable Parameters
Parameter
Description
Min.
tOEon
SLOE Assert to FIFO DATA Output
10.5
ns
tOEoff
SLOE Deassert to FIFO DATA Hold
10.5
ns
9.13
Slave FIFO Address to Flags/Data
FIFOADR [1.0]
tXFLG
FLAGS
tXFD
DATA
N
N+1
Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram[12]
Document #: 38-08012 Rev. *B
Page 44 of 50
CY7C68013
Table 9-16. Slave FIFO Address to Flags/Data Parameters
Parameter
Description
Min.
Max.
Unit
tXFLG
FIFOADR[1:0] to FLAGS Output Propagation Delay
10.7
ns
tXFD
FIFOADR[1:0] to FIFODATA Output Propagation Delay
14.3
ns
Min.
Max.
Unit
20.83
200
ns
9.14
Slave FIFO Synchronous Address
IFCLK
SLCS/FIFOADR [1:0]
tSFA
tFAH
Figure 9-13. Slave FIFO Synchronous Address Timing Diagram
Table 9-17. Slave FIFO Synchronous Address Parameters [14]
Parameter
Description
tIFCLK
Interface Clock Period
tSFA
FIFOADR[1:0] to Clock Set-up Time
25
ns
tFAH
Clock to FIFOADR[1:0] Hold Time
10
ns
9.15
Slave FIFO Asynchronous Address
SLCS/FIFOADR [1:0]
tSFA
tFAH
RD/WR/PKTEND
Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram[12]
Table 9-18. Slave FIFO Asynchronous Address Parameters[15]
Parameter
Description
Min.
Max.
Unit
tSFA
FIFOADR[1:0] to RD/WR/PKTEND Set-up Time
10
ns
tFAH
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
10
ns
RAM Size
8051
Address
/Data Busses
10.0
Ordering Information
Table 10-1. Ordering Information
Ordering Code
Package Type
# Prog I/Os
CY7C68013-128AC
128 TQFP
8K
40
16/8 bit
CY7C68013-100AC
100 TQFP
8K
40
-
CY7C68013-56PVC
56 SSOP
8K
24
-
CY7C68013-56LFC
56 QFN
8K
24
-
CY3681
EZ-USB FX2 Xcelerator Development Kit
Document #: 38-08012 Rev. *B
Page 45 of 50
CY7C68013
11.0
Package Diagrams
The FX2 is available in four packages:
• 56-pin SSOP
• 56-pin QFN
• 100-pin TQFP
• 128-pin TQFP.
51-85062-*C
Figure 11-1. 56-lead Shrunk Small Outline Package O56
Document #: 38-08012 Rev. *B
Page 46 of 50
CY7C68013
51-85144-*A
Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 X 8 mm) LF56
Document #: 38-08012 Rev. *B
Page 47 of 50
CY7C68013
51-85050-*A
Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
Document #: 38-08012 Rev. *B
Page 48 of 50
CY7C68013
51-85101-*B
Figure 11-4. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
EZ-USB is a registered trademark, and FX2 and ReNumeration are trademarks of Cypress Semiconductor Corporation. Purchase
of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-08012 Rev. *B
Page 49 of 50
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C68013
Document Title: CY7C68013 EZ USB® FX2™ USB Microcontroller, High-Speed USB Peripheral Controller
Document Number: 38-08012
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
111753
11/15/01
DSG
Change from Spec number: 38-00929 to 38-08012
*A
111802
02/20/02
KKU
Update functional changes between revision D part and revision E part
Changed timing data from simulation data to revision E characterization data
*B
115480
06/26/02
KKU
Added new 56 pin Quad Flatpack No Lead package and pinout
Revised pin description table to reflect new package
Corrected Figure 9-8 by moving tsfd parameter location
Corrected labels on Dplus and Dminus in Table 4-1
Removed Preliminary from spec title
Document #: 38-08012 Rev. *B
Page 50 of 50