LE25S161 Serial Flash Memory 16 Mb (2048K x 8) www.onsemi.com 1. Overview The LE25S161 is a SPI bus flash memory device with a 16M bit (2048K 8-bit) configuration. It uses a single power supply. While making the most of the features inherent to a serial flash memory device, the LE25S161 is housed in an 8-pin ultra-miniature package. All these features make this device ideally suited to storing program in applications such as portable information devices, which are required to have increasingly more compact dimensions. The LE25S161 also has a small sector erase capability which makes the device ideal for storing parameters or data that have fewer rewrite cycles and conventional EEPROMs cannot handle due to insufficient capacity. SOIC 8, 150mils VSOIC8 NB WLCSP8, 2.92x1.53 UDFN8 4x3, 0.8P 2. Features Operations power supply : 1.65 to 1.95V supply voltage range Operating frequency : 70MHz (max) Temperature range : –40 to +90C Serial interface : SPI mode 0, mode 3 supported Electronic Identification : JDEC ID, Device ID, Serial Flash Discoverable Parameter (SFDP) Sector size : 4K bytes/small sector, 64K bytes/sector Erase functions : small sector erase (SSE), sector erase (SE), chip erase (CHE) Page program function : 256 bytes/page Status functions : Ready/Busy information, protect information Low operation current : 5.0mA (Low-power program mode, typ), 3.5mA (Low-Power Read mode, typ) Erase time : 10ms (SSE, typ), 15ms (SE, typ), 210ms (CHE, typ) Page program time (tPP) : 0.4ms/256 bytes (typ.), 0.7ms/256 bytes (max.) Emergency shutdown of the current consumption : transition to a standby state in less than 20s from the active by Write Suspend : transition to a standby state in less than 40s from the active by Software Reset High reliability : 100,000 erase/program cycles : 20 years data retention period Package : LE25S161MDTWG SOIC 8, 150 mils CASE 751BD : LE25S161FDTWG VSOIC8 NB CASE 753AA : LE25S161XATAG WLCSP8, 2.921.53 CASE 567LC : LE25S161PCTXG UDFN8 43, 0.8P CASE 506DC : KGD N/A * This product is licensed from Silicon Storage Technology, Inc. (USA). ORDERING INFORMATION See detailed ordering and shipping information on page 54 of this data sheet. © Semiconductor Components Industries, LLC, 2015 November 2015 - Rev. 0 1 Publication Order Number : LE25S161/D LE25S161 3. Package Types and Pin Configurations CS 1 8 V DD SO (SIO1) 2 7 HOLD WP 3 6 SCK V SS 4 5 SI (SIO0) Top view SOIC8 (LE25S161MDTWG) VSOIC8 NB (LE25S161FDTWG) CS 1 8 V DD SO (SIO1) 2 7 HOLD WP 3 6 SCK V SS 4 5 SI (SIO0) Top view UDFN8 (LE25S161PCTXG) www.onsemi.com 2 LE25S161 A VDD CS B HOLD SO/SIO1 C SCK WP D SI/SIO0 VSS 1 2 Top View WLCSP8 (LE25S161XATAG) 3 2 1 5 6 7 8 KGD Name 1 CS 2 SO (SIO1) 3 WP 4 VSS 5 SI (SIO0) 6 SCK 7 HOLD 8 VDD A SO/SIO1 HOLD B WP SCK C VSS SI/SIO0 D 2 1 Ball side View WLCSP8 (LE25S161XATAG) 4 Pad No. VDD CS www.onsemi.com 3 LE25S161 4. Package Dimensions unit : mm LE25S161MDTWG SOIC 8, 150 mils CASE 751BD-01 ISSUE O E1 SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 E MAX 4.00 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 0º 8º TOP VIEW D h A1 A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. www.onsemi.com 4 LE25S161 Package Dimensions unit : mm LE25S161FDTWG VSOIC8 NB CASE 753AA ISSUE O D A 8 NOTE 5 2X 0.10 C D 5 F NOTE 6 E E1 A1 NOTE 4 L2 2X 4 TIPS 0.20 C L 4 1 NOTE 5 8X B b 0.25 C DETAIL A M C A-B D TOP VIEW 2X NOTE 4 D 0.10 C A-B 0.10 C A DETAIL A 8X 0.10 C e SIDE VIEW C SEATING PLANE END VIEW SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.10mm IN EXCESS OF MAXIMUM MATERIAL CONDITION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. DIMENSION E DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25mm PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F. 5. DATUMS A AND B ARE TO BE DETERMINED AT DATUM F. 6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. DIM A A1 b c D E E1 e L L2 MILLIMETERS MIN MAX 0.65 0.85 0.05 0.31 0.51 0.17 0.25 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.40 1.27 0.25 BSC GENERIC MARKING DIAGRAM* 8 RECOMMENDED SOLDERING FOOTPRINT* XXXXXXXXX ALYWX 1 8X 1.52 7.00 XXXXX A L Y W = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) 1 8X 1.27 PITCH 0.60 DIMENSION: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 5 *This information is generic. Please refer to device data sheet for actual part LE25S161 Package Dimensions unit : mm LE25S161XATAG WLCSP8, 2.92x1.53 CASE 567LC ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE SPHERICAL CROWNS OF THE SOLDER BALLS. A B E PIN A1 REFERENCE DIM A A1 b D E e D MILLIMETERS MIN MAX 0.50 0.03 0.13 0.25 0.35 2.92 BSC 1.53 BSC 0.50 BSC 0.10 C 2X 0.10 C 2X TOP VIEW A 0.10 C 0.08 C A1 SIDE VIEW NOTE 3 C RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE A1 PACKAGE OUTLINE e e/2 b 0.05 C A B 8X 0.03 C 0.50 PITCH 8X e D 0.30 e/2 C B 0.50 PITCH A 1 2 BOTTOM VIEW DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 6 LE25S161 Package Dimensions unit : mm LE25S161PCTXG UDFN8, 4x3, 0.8P CASE 506DC ISSUE O A B D L L1 PIN ONE REFERENCE E DETAIL A 0.15 C 2X ALTERNATE TERMINAL CONSTRUCTIONS NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e G L L1 0.15 C TOP VIEW 2X EXPOSED Cu DETAIL B MOLD CMPD A 0.10 C 10X L 0.08 C (A3) DETAIL B A1 NOTE 4 C SIDE VIEW ALTERNATE CONSTRUCTIONS SEATING PLANE GENERIC MARKING DIAGRAM* G DETAIL A 2X 1 D2 0.10 M E2 0.10 L 8 XXXXX XXXXX AYWW C A B 4 2X 8X MILLIMETERS MIN MAX 0.50 0.60 0.00 0.05 0.152 REF 0.25 0.35 4.00 BSC 0.70 0.90 3.00 BSC 0.10 0.30 0.80 BSC 1.60 BSC 0.55 0.65 0.15 5 8X e e/2 C A B M b 0.10 M C A B 0.05 M C NOTE 3 BOTTOM VIEW 2.60 *This information is generic. Please refer to device data sheet for actual part marking. 8X 0.83 1.00 3.30 PACKAGE OUTLINE 2X 0.40 1 0.80 PITCH = Specific Device Code = Assembly Location = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) RECOMMENDED SOLDERING FOOTPRINT* 2X XXXXX A Y WW 8X 0.40 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 7 LE25S161 5. Pin Description Sy mbol Pin Name IO CS Chip select I SCK Serial clock I Description The dev ice becomes activ e when the logic lev el of this pin is low; it is deselected and placed in standby status when the logic lev el of the pin is high. This pin controls the data input/output timing. The input data and addresses are latched sy nchronized to the rising edge of the serial clock, and the data is output sy nchronized to the f alling edge of the serial clock. SI (SIO0) SO (SIO1) WP HOLD Serial data input (Serial data input output) Serial data output (Serial data input output) The data and addresses are input f rom this pin, and latched internally sy nchronized to the rising I/O edge of the serial clock. (It changes into input/output pin during the Dual operation.) The data stored inside the dev ice is output f rom this pin sy nchronized to the f alling edge of the I/O serial clock. ( It changes into input/output pin during the Dual operation.) Write protect I The Write Status Register Protect (SRWP) takes ef f ect when the logic lev el of this pin is low. Hold I Serial communication is suspended when the logic lev el of this pin is low. VDD Power supply This pin supplies the 1.65 to 1.95V supply v oltage. VSS Ground This pin supplies the 0V supply v oltage. www.onsemi.com 8 LE25S161 6. Block Diagram 16M Bit Flash EEPROM Cell Array Power Circuit Energyconsumption Control Unit Memory Control Logic Decoder Logic & Serial-parallel conversion Logic Command Logic Serial interface CS SCK SI (SIO0) SO (SIO1) www.onsemi.com 9 WP HOLD LE25S161 7. Device Operation 7-1. Standard SPI Modes The read, erase, program and other required functions of the device are executed through the command registers. The serial I/ O corrugate is shown in "Figure 1. SPI Modes" and the command list are shown in "Table.1-1. Co mmand Settings (Standard SPI)". At the falling CS edge the device is selected, and serial input is enabled for the co mmands, addresses, etc. These inputs are normalized in 8 b it units and taken into the device interior in synchronization with the rising edge of SCK, which causes the device to execute operation according to the command that is input. The LE25S161 supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of SCK is high. Figure 1. SPI Modes CS Mode3 SCK Mode0 8CLK SI 1st byte MSB (Bit7) 2nd byte Nth byte LSB (Bit0) High Impedance SO DATA DATA 7-2. Dual SPI Modes The LE25S161 supports Dual SPI operations when using "Dual Output Read (RDDO: 3Bh)", "Dual I/O Read (RDIO: BBh)". The SI and SO p ins change into the input/output pin (SIOx) during the Dual SPI modes. The command list is shown in "Table.1-2. Command Settings (Dual SPI)". Pin Configurations at Dual SPI Mode Standard SPI Dual SPI SI SIO0 SO SIO1 www.onsemi.com 10 LE25S161 Table 1-1. Command Settings (Standard SPI) --- Max: 70MHz (except RDLP) Command WREN Description 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte Nth byte (clock number) (0 - 7) (8 - 15) (16- 23) (24 - 31) (32 - 39) (40 - 47) (8N-8 to 8N-1) Write enable 06h WRDI Write disable 04h RDSR Read Status Register 05h WRSR Write Status Register 01h DATA 03h A23-A16 A15-A8 A7-A0 RD 0Bh A23-A16 A15-A8 A7-A0 X 20h / D7h A23-A16 A15-A8 A7-A0 D8h A23-A16 A15-A8 A7-A0 A23-A16 A15-A8 A7-A0 Manufacture Memory Capacity (62h) Ty pe (16h) (15h) ABh X X X Read SFDP 5Ah A23-A16 A15-A8 A7-A0 X Deep Power down B9h RDLP RDHS SSE SE Low -Power Read (Max: 33.33MHz) High-Speed Read Small Sector Erase (4KB) Sector Erase (64KB) CHE Chip Erase (16M bits) 60h / C7h PP Normal Page Program 02h PPL Low-Power Page Program 0Ah WSUS Write Suspend B0h RESM Resume 30h RJID Read JEDEC ID 9Fh RID RSFDP DP EDP RSTEN RST Read Dev ice ID (Exit power down mode) Exit Deep Power down PD (5) (7) RD (5) RD (5) RD (5) RD (5) PD (7) PD (7) RD (5) RD (5) Dev ice ID (88h) ABh Reset Enable 66h Reset 99h Table 1-2. Command Settings (Dual SPI) --- Max: 50MHz Command RDDO Description 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte Nth byte (clock number) (0 - 7) (8 - 15) (16- 23) (24 - 31) (32 - 39) (40 - 47) (8N-8 to 8N-1) 3Bh A23-A16 A15-A8 A7-A0 Z Dual Output Read RDD (6) RDD (6) RDD (6) RDD (6) (8) RDIO Dual I/O Read BBh A23-A8(8) A7-A0 , X, Z RDD (6) Note: 1. "X" signifies "don’t care" (that is to say, any value may be input). 2. "Z" signifies "high-impedance". 3. The "h" follow ing each code indicates that the number given is in hexadecimal notation. 4. Addresses A23 to A21 for all commands are "Don't care". 5. "RD" Read data on SO. 6. "RDD" Dual Read data: SIO0=(Bit6, Bit4, Bit2, Bit0) 7. "PD" SIO1=(Bit7, Bit5, Bit3, Bit1) Page Program data on SO. 8. Dual SPI address input from SIO0 and SIO1: SIO0=(A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0) SIO1=(A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1) www.onsemi.com 11 RDD (6) LE25S161 8. Memory Organization Table 2. Memory Organization 16M bits Sector (64KB) Symbol :SE 31 30 to 6 5 4 3 2 1 small sector (4KB) Symbol :SSE SSE[511] to SSE[496] SSE[495] to SSE[96] SSE[95] to SSE[80] SSE[79] to SSE[64] SSE[63] to SSE[48] SSE[47] to SSE[32] SSE[31] to SSE[16] SSE[15] to SSE[4] SSE[3] 0 SSE[2] SSE[1] SSE[0] address space (A23 to A0) 1FF000h 1FFFFFh 1F0000h 1EF000h 1F0FFFh 1EFFFFh 060000h 05F000h 060FFFh 05FFFFh 050000h 04F000h 050FFFh 04FFFFh 040000h 03F000h 040FFFh 03FFFFh 030000h 02F000h 030FFFh 02FFFFh 020000h 01F000h 020FFFh 01FFFFh 010000h 00F000h 010FFFh 00FFFFh 004000h 003800h 003000h 002800h 002000h 001800h 001000h 000800h 000000h 004FFFh 003FFFh 0037FFh 002FFFh 0027FFh 001FFFh 0017FFh 000FFFh 0007FFh www.onsemi.com 12 LE25S161 9. Status Registers The status registers hold the operating and setting statuses inside the device, and this information can be read by Read Status Register (RDSR) and the protect informat ion can be rewritten by Write Status Register (WRSR). There are 8 b its in total, and "Table 3. Status registers" gives the significance of each bit. Table 3. Status Registers Bit Name Bit0 RDY Bit1 Bit2 Logic Function 0 Ready 1 Erase/Program 0 Write disabled 1 Write enabled 0 WEN BP0 Power-on Time Inf ormation 0 0 1 Bit3 0 Block protect inf ormation 1 Protected area switch BP1 Nonv olatile inf ormation 0 Bit4 BP2 1 Bit5 TB Bit6 SUS Bit7 SRWP 0 Block protect 1 Upper side/Lower side switch 0 Erase/Program is not suspended 1 Erase/Program suspended 0 Write Status Register enabled 1 Write Status Register disabled Nonv olatile inf ormation 0 Nonv olatile inf ormation Note: All non-v olatile bits of the status registers-1 are set "0" in the f actory . www.onsemi.com 13 LE25S161 9-1. Contents of each status register 9-1-1. RDY (bit 0) The RDY register is for detecting the write (Program, Erase and Write Status Register) end. When it is " 1", the device is in a busy state, and when it is "0", it means that write is completed. 9-1-2. WEN (bit 1) The WEN reg ister is for detecting whether the device can perform write operations. If it is set to "0", the device will not perform the write operation even if the write command is input. If it is set to "1", the device can perform write operations in any area that is not block-protected. WEN can be controlled using the write enable (WREN) and write d isable (W RDI). By inputting the write enable (WREN: 06h), WEN can be set to "1" by inputting the write disable (WRDI: 04h ), it can be set to "0." In the following states, WEN is automatically set to "0" in order to protect against unintentional writing. • At power-on • Upon completion of Erase (SSE, SE, or CHE) • Upon completion of Page Program (PP or PPL) • Upon completion of Write Status Register (WRSR) * If a write operation has not been performed inside the LE25S161 because, for instance, the command input for any of the write operations (SSE, SE, CHE, PP, PPL or W RSR) has failed or a write operation has been performed for a protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermo re, its state will not be changed by a read operation. 9-1-3. BP0, BP1, BP2, TB (bits 2, 3, 4, 5) Block Protect: BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. For the setting conditions, refer to "Table 4. Protected Level Setting Conditions". BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order address area or lower-order address area. Table 4. Protection Level Setting Conditions Status Register Bits Protected Lev el Protected Block TB BP2 BP1 BP0 Protected Area 0 Whole area unprotected X 0 0 0 None T1 Upper side 1/32 protected 0 0 0 1 1F0000h to 1FFFFFh T2 Upper side 1/16 protected 0 0 1 0 1E0000h to 1FFFFFh T3 Upper side 1/8 protected 0 0 1 1 1C0000h to 1FFFFFh T4 Upper side 1/4 protected 0 1 0 0 180000h to 1FFFFFh T5 Upper side 1/2 protected 0 1 0 1 100000h to 1FFFFFh B1 Lower side 1/32 protected 1 0 0 1 000000h to 00FFFFh B2 Lower side 1/16 protected 1 0 1 0 000000h to 01FFFFh B3 Lower side 1/8 protected 1 0 1 1 000000h to 03FFFFh B4 Lower side 1/4 protected 1 1 0 0 000000h to 07FFFFh B5 Lower side 1/2 protected 1 1 0 1 000000h to 0FFFFFh 6 Whole area protected X 1 1 X 000000h to 1FFFFFh Note: Chip Erase is enabled only when the protection level is 0. www.onsemi.com 14 LE25S161 9-1-4. SUS (bit 6) The SUS reg ister indicates when Erase/Program operation has been suspended. The SUS beco mes "1" when the Erase/Program operation has been suspended (WSUS: B0h). The SUS is cleared to"0" by Resume (RESM :30h) or re-erase/program (SSE, SE, CHE, PP, PPL). 9-1-5. SRWP (bit 7) Write Status Register protect SRWP is the bit for protecting the status registers, and its informat ion can be rewritten. When SRWP is "1" and the logic level of the WP pin is low, the Write Status Register (WRSR: 01h) is ignored, and status registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5. SRWP Sett ing Conditions". Table 5. SRWP Setting Conditions WP Pin SRWP Status Register Protect State 0 Unprotected 0 1 1 Protected 0 Unprotected 1 Unprotected www.onsemi.com 15 LE25S161 10. Description of Commands and Operations A detailed description of the functions and operations corresponding to each command is presented below. 10-1. Read Status Register (RDSR) The contents of the status registers can be read using the Read Status Register (RDSR). This command can be executed even during the following operations. • Erase (SSE, SE or CHE) • Page Program (PP or PPL) • Write Status Register (WRSR) "Figure 2. Read Status Register (RDSR)" shows the timing waveforms. The sequence of RDSR operation : CS goes to low input RDSR command (05h) Status Register data (SRWP, SUS, TB, BP2, BP1, BP0,WEN, RDY) out on SO completed by CS =high * The data output starts from the falling edge of SCK(7th clock) This command outputs the contents of the status registers synchronized to the falling edge of the clock (SCK). If the clock input is continued after bit0 ( RDY) has been output, the data is output by returning to bit7 (SRWP) that was first output, after which the output is repeated for as long as the clock input is continued. The data can be read by this command at any time (even during a program, erase cycle). By setting CS to high, the device is deselected, and Read JEDEC ID cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state Figure 2. Read Status Register (RDSR) CS Mode 3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 Mode 0 8CLK SI 05h MSB SO High Impedance DATA MSB DATA MSB ● DATA: Status Resister, "Table 3 Status Register" www.onsemi.com 16 DATA MSB LE25S161 10-2. Write Status Register (WRSR) The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using this co mmand. bit0 ( RDY), bit 1 (WEN) and bit6 (SUS) are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2, TB and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at power-down. "Figure 3. Write Status Register (WRSR)" shows the timing waveforms. "Figure 31. Write Status Register Flowcharts" shows the flowcharts. The sequence of WRSR operation : CS goes to low input WRSR command (01h) Status Register data input on SI CS goes to high (be executed by the rising CS edge) Erase and program are performed automatically inside the device by Write Status Register. So that erasing or other processing is unnecessary before executing the command. By the operation of this command, the informat ion in bits BP0, BP1, BP2, TB and SRWP can be rewritten. Since bits bit0 ( RDY), b it1 (W EN), b it 6 (SUS) of the status register cannot be written, no problem will arise if an attempt is made to set them to any value when rewrit ing the status register. Write Status Register ends can be detected by RDY of Read Status Register (RDSR). To init iate Write Status Register, the logic level of the WP pin must be set high and status register WEN must be set to "1". Self-timed Write Cycle Figure 3. Write Status Register (WRSR) tWRSR CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 Mode0 8CLK SI 01h DATA MSB SO High Impedance www.onsemi.com 17 LE25S161 10-3. Write Enable (WREN) Before performing any of the operations listed below, the device must be placed in the write enable state. • Erase (SSE, SE, CHE or CHE) • Page Program (PP or PPL) • Write Status Register (WRSR) Operation is the same as for setting status register WEN to "1", and the state is enabled by this command. "Figure 4. Write Enable (WREN)" shows the timing waveforms. The sequence of WREN operation : CS goes to low input WREN command (06h) CS goes to high (be executed by the rising CS edge) Figure 4. Write Enable (WREN) CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI 06h MSB SO High Impedance www.onsemi.com 18 LE25S161 10-4. Write Disable (WRDI) This command sets status register WEN to "0" to prohibit unintentional writing. The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable (WREN: 06h). "Figure 5. Write Disable (WRDI)" shows the timing waveforms. The sequence of WRDI operation : CS goes to low input WRDI command (04h) CS goes to high (be executed by the rising CS edge) Figure 5. Write Disable (WRDI) CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI 04h MSB SO High Impedance www.onsemi.com 19 LE25S161 Standard SPI Read There are two Read commands, "Low-Power Read (RDLP: 03h)" and "High-Speed Read (RDHS: 0Bh)". 10-5. Standard SPI Read There are two Read commands, Low-Power Read (RDLP) and High-Speed Read (RDHS). 10-5-1. Low-Power Read command (RDLP) Maximum Clock frequency: 33.33MHz This command is for reading data out. "Figure 6. Low-Power Read (RDLP)" shows the timing waveforms. The sequence of RDLP operation : CS goes to low input RDLP command (03h) 3 Byte address (A23-A0) input on SI the corresponding data out on SO continuous data out (n-byte) completed by CS =high * The data output starts from the falling edge of SCK(31th clock) The Address is latched on rising edge of SCK, and the corresponding data is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data is shifted out. If the SCK input is continued after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device is deselected, and the read cycle is co mpleted. While the device is deselected, the output pin SO is in a high-impedance state. Figure 6. Low-Power Read (RDLP) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 Mode0 8CLK SI 03h Add (A23-A16) Add (A15-A8) Add (A7-A0) Byte 1 SO High Impedance DATA MSB ● Address A23 to A21 are "Don't care". www.onsemi.com 20 Byte 2 DATA MSB Byte 3 DATA MSB LE25S161 10-5-2. High-Speed Read command (RDHS) Maximum Clock frequency: 70MHz This command is for reading data out at the high frequency operation. "Figure 7. High-Speed Read (RDHS)" shows the timing waveforms. The sequence of RDHS operation : CS goes to low input RDHS command (0Bh) 3 Byte address (A23-A0) input on SI 1 byte dummy cycle the corresponding data out on SO continuous data out (n-byte) completed by CS =high * The data output starts from the falling edge of SCK(39th clock) The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the corresponding data is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data is shifted out. If the SCK input is continued after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device is deselected, and the read cycle is co mpleted. While the device is deselected, the output pin SO is in a high-impedance state. Figure 7. High-Speed Read (RDHS) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 Mode0 8CLK SI 0Bh Add Add Add (A23-A16) (A15-A8) (A7-A0) X MSB Byte 1 Byte 2 Byte 3 SO High Impedance DATA MSB ● Address A23 to A21 are "Don't care". www.onsemi.com 21 DATA MSB DATA MSB LE25S161 10-6. Dual read There are two Dual read commands, the Dual Output Read (RDDO) and the Dual I/O Read (RDIO). They achieve the twice speed-up from "High-Speed Read (RDHS: 0Bh)". The command list is shown in "Table.1-2. Command Settings (Dual SPI)" Pin Configurations at Dual SPI Mode Standard SPI Dual SPI SI SIO0 SO SIO1 10-6-1. Dual Output Read command (RDDO) Maximum Clock frequency: 50MHz The SI and SO pins change into the input/output pin (SIOx) during this operation. It makes the data output x2 b it and has achieved a high-speed output. bit7, 5, 3 and bit1are output from SIO0. bit6, 4, 2 and bit0 are output from SIO1. "Figure 8. Dual Output Read (RDDO)" shows the timing waveforms. The sequence of RDDO operation : CS goes to low input RDDO command (3Bh) 3 Byte address (A23-A0) input on SI 1 byte dummy cycle the corresponding data out on SI/SIO0 and SO/SIO1 continuous data out (n-byte) per 4clock completed by CS =high * The data output starts from the falling edge of SCK(39th clock) Output Data SI/SIO0 bit6,4,2,0 SO/SIO1 bit7,5,3,1 The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the corresponding data is shifted out on SI/SIO0 and SO/SIO1 by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data (4 clock cycles) is shifted out. If the SCK input is continued after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address (000000h ). By setting CS to high, the device is deselected, and the read cycle is co mpleted. While the device is deselected, the output pin SO is in a high-impedance state. Figure 8. Dual Output Read (RDDO) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 43 44 47 Mode0 8CLK 3Bh SIO0 Add Add Add (A23-A16) (A15-A8) (A7-A0) MSB SIO1 dummy bit Byte 1 Byte 3 DATA0 DATA0 DATA0 4CLK High Impedance Byte 2 4CLK DATA1 DATA1 DATA1 MSB MSB MSB DATA0: bit6,bit4,bit2,bit0 DATA1: bit7,bit5,bit3,bit1 ● Address A23 to A21 are "Don't care". www.onsemi.com 22 LE25S161 10-6-2. Dual I/O Read command (RDIO) Maximum Clock frequency: 50MHz The SI and SO p ins change into the input/output pin (SIOx) during this operation. It makes the address input and data output x2 b it and has achieved a high-speed output. Add1 (A23, A 21, -, A3 and A1) is input fro m SIO1 and Add0 (A22, A20, -, A2 and A0) is input from SIO0. b it7, 5, 3 and bit1are output from SIO0. b it6, 4, 2 and bit0 are output from SIO1. "Figure 9. Dual I/O Read (RDIO)" shows the timing waveforms. The sequence of RDIO operation : CS goes to low input RDIO command (BBh) 3 Byte address (A23-A0) input on SI/SIO0 and SO/SIO1 by 12 clock cycle 2 dummy clock (SI/SIO0 and SO/SIO1 are don’t care) + 2 dummy clock (must set SI/SIO0 and SO/SIO1 high impedance) the corresponding data out on SI/SIO0 and SO/SIO continuous data out (n-byte) per 4clock completed by CS =high * The data output starts from the falling edge of SCK(23th clock) Input Address Output Data SI/SIO0 A22,20,18 --,A2,A0 bit6,4,2,0 SO/SIO1 A23,21,19 --,A3,A1 bit7,5,3,1 The Address is latched on rising edge of SCK. It is necessary to add 4 dummy clocks after address is latched, 2CLK of the latter half of the dummy clock is in the state of high impedance, the controller can switch I/ O for this period. The corresponding data is shifted out on SI/SIO0 and SO/SIO1 by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data (4 clock cycles) is shifted out. If the SCK input is continued after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address (000000h ). By setting CS to high, the device is deselected, and the read cycle is co mpleted. While the device is deselected, the output pin SO is in a high-impedance state. Figure 9. Dual I/O Read (RDIO) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 19 20 21 22 23 24 31 Mode0 dummy bit 8CLK BBh SIO0 MSB SIO1 27 28 High Impedance Add1:A22,A20-A2,A0 12CLK Add2:A23,A21-A3,A1 X Byte 1 Byte3 DATA0 DATA0 DATA0 2CLK 2CLK X Byte2 4CLK DATA1 DATA1 DATA1 MSB MSB MSB DATA0: bit6,bit4,bit2,bit0 DATA1: bit7,bit5,bit3,bit1 ● Address A23 to A21 are "Don't care". www.onsemi.com 23 LE25S161 10-7. Small Sector Erase (SSE) Small Sector Erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of 4Kbytes. "Figure 10. Small Sector Erase (SSE)" shows the timing waveforms. "Figure 32. Small Sector Erase Flowcharts" shows the flowcharts. The sequence of SSE operation : CS goes to low input SSE command (20h or D7h) 3 Byte address (A23-A0) input on SI CS goes to high (be executed by the rising CS edge) * A20 to A12 are valid address After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (tSSE). The end of erase operation can also be detected by status register (RDY). Figure 10. Small Sector Erase (SSE) Self-timed Erase Cycle tSSE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 Mode0 8CLK SI 20h / D7h Add Add Add (A23-A16) (A15-A8) (A7-A0) MSB SO High Impedance ● Address A23 to A21, A11 to A0 are "Don't care". www.onsemi.com 24 LE25S161 10-8. Sector Erase (SE) Sector Erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes. "Figure 11. Sector Erase (SE)" shows the timing waveforms. "Figure 33. Sector Erase Flowcharts" shows the flowcharts. The sequence of SE operation : CS goes to low input SE command (D8h) 3 Byte address (A23-A0) input on SI CS goes to high (be executed by the rising CS edge) * A20 to A16 are valid address After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (tSE). The end of erase operation can also be detected by status register (RDY). Figure 11. Sector Erase (SE) Self-timed Erase Cycle tSE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 Mode0 8CLK SI D8h Add Add Add (A23-A16) (A15-A8) (A7-A0) MSB SO High Impedance ● Address A23 to A21 , A15 to A0 are "Don't care. www.onsemi.com 25 LE25S161 10-9. Chip Erase (CHE) Chip Erase is an operation that sets the memory cell data in all sectors to "1". "Figure 12. Chip Erase (CHE)" shows the timing waveforms. "Figure 34. Chip Erase Flowcharts" shows the flowcharts. The sequence of CHE operation : CS goes to low input CHE command (60h or C7h) CS goes to high (be executed by the rising CS edge) After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (tSE). The end of erase operation can also be detected by status register (RDY). Figure 12. Chip Erase (CHE) Self-timed Erase Cycle tCHE CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI 60h / C7h MSB SO High Impedance www.onsemi.com 26 LE25S161 10-10. Page Program 10-10-1. Normal Page Program (PP) 10-10-2. Low-Power Page Program (PPL) There are two Page Program co mmands, Normal program (PP: 02h ) and Low-Power program (PPL: 0Ah) These two commands are comp letely functionally the same. By selecting the Low-Power p rogram (PPL), the operating current is reduced, but the program cycle time is extended. (Iccpp > Iccppl , tPPL > tPP) Page Program is an operation that programs any number of bytes fro m 1 to 256 bytes within the same sector page (page addresses: A20 to A8). Before init iating Page Program, the data on the page concerned must be erased using Small Sector Erase, Sector Erase, or Chip Erase. Page Program (PP, PPL) allows only previous erased data (FFh). "Figure 13. Normal Page Program (PP)". "Figure 14. Low-power Page Program (PPL)" shows the timing waveforms. "Figure 35. Page Program Flowcharts" shows the flowcharts. The sequence of PP or PPL operation : CS goes to low input PP command (02h) or PPL command (0Ah) 3 Byte address (A23-A0) input on SI n-Byte data input on SI CS goes to high (be executed by the rising CS edge) The program data must be loaded in 1-byte increments. If the data loaded has exceeded 256 bytes, the 256 bytes loaded last are programmed. After the correct input sequence the internal program operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (t PP or t PPL). The end of program operation can also be detected by status register (RDY). Self -timed Figure 13. Normal Page Program (PP) Program Cy cle tPP CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 2079 Mode0 8CLK SI 02h Byte 1 Add (A23-A16) Add (A15-A8) Add (A7-A0) PD Byte 2 PD Byte 256 PD MSB High Impedance SO ● Address A23 to A21 are "Don't care". Self -timed Program Cy cle Figure 14. Low-Power Page Program (PPL) tPPL CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 2079 Mode0 8CLK SI 0Ah Byte 1 Add Add Add (A23-A16) (A15-A8) (A7-A0) MSB SO High Impedance ● Address A23 to A21 are "Don't care". www.onsemi.com 27 PD Byte 2 PD Byte 256 PD LE25S161 10-11. Write Suspend (WSUS) The Write Suspend (WSUS) allo w the system to interrupt Small Sector Erase (SSE), Sector Erase (SE), Ch ip Erase (CHE) or Page Program (PP, PPL). "Figure 15. Write Suspend (WSUS)" shows the timing waveforms. The sequence of WSUS operation : CS goes to low input WSUS command (B0h) CS goes to high (be executed by the rising CS edge) After the command has been input, the device becomes consumption current equivalent to standby within 20 us. The recovery time (t RSUS) is needed before next co mmand fro m suspend. The internal operation status could be checked by using status register RDY bit or SUS bit, but the device will not accept another command until it is ready. • The Write Suspend is valid Erase cycle (SSE, SE and CHE) or Program cycle (PP, PPL). • If the Erase (SSE, SE, CHE) or Program (PP, PPL) entry during the suspension, the suspension will be canceled automatically. And a new Erase (SSE, SE, CHE), Program (PP, PPL) will be executed. In this case, it is necessary to erase/program the suspended area again. • During Write Suspend, Read (RDSR, RDLP, RDHS, RDDO, RDIO) and Resume (RESM) can be accepted. • If the Software Reset is executed during the suspension, the suspension will be canceled automatically. Figure 15. Write Suspend (WSUS) Recovery time from Suspend tRSUS CS Mode3 SCK 20us 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Mode0 8CLK SI Next Command (Read or Resume) MSB B0h MSB SO High Impedance Operation Current = Isb www.onsemi.com 28 LE25S161 10-12. Resume (RESM) This command (RESM) restarts erase cycle (SSE, SE, CHE) or program cycle (PP, PPL) that was suspended. "Figure 16. Resume (RESM)" shows the timing waveforms. The sequence of RESM operation : CS goes to low input RESM command (30h) CS goes to high (be executed by the rising CS edge) The internal operation status could be checked by using status register RDY bit or SUS bit. This command will be ignored if the previous Write Suspend operation was interrupted by unexpected power off or re-erase/program (cancel of suspend) or Software Reset(RST). To execute Write Suspend (WSUS) again after Resume, it is necessary to wait for some time (tSUS). Figure 16. Resume (RESM) Self-timed Write Cycle tCHE/ tSE/ tSSE/ tPP/ tPPL CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI 30h MSB SO High Impedance www.onsemi.com 29 LE25S161 10-13. Read ID Read ID is an operation that reads the manufacturer code (RJID) and device ID informat ion (RID). These Read ID commands are not accepted during writing. There are t wo methods of reading the silicon ID, each of wh ich is assigned a device ID. 10-13-1. Read JEDEC ID (RJID) This command (RJID) is compatible with the JEDEC standard for SPI compatible serial memories. "Table 6. JEDEC ID codes" lists the silicon ID codes. "Figure 17. Read JEDEC ID (RJID)" shows the timing waveforms. The sequence of RJID operation : CS goes to low input RJID command (9Fh) Manufacture code (62h) out on SO Memory type code (16h) out on SO Memory capacity code out on SO (15h) Reserve code (00h) completed by CS =high * The 4-byte code is output repeatedly as long as clock inputs are present * The data output starts from the falling edge of SCK(7th clock) By setting CS to high, the device is deselected, and Read JEDEC ID cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state. Table 6. JEDEC ID codes Output code 62h Manuf acturer code Memory ty pe 16h Memory capacity code 15h (16M Bit) 2 by te dev ice ID 00h Reserv e code Figure 17. Read JEDEC ID (RJID) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 Mode0 8CLK SI SO 9Fh High Impedance 62h MSB 16h MSB 15h MSB www.onsemi.com 30 00h MSB 62h MSB LE25S161 10-13-2. Read Device ID (RID) This command (RID) is an operation that reads the Device ID. "Table 7. Device ID code" lists the device ID codes. "Figure 18. Read Device ID (RID)" shows the timing waveforms. The sequence of RID operation : CS goes to low input RID command (ABh) 3 byte dummy cycle Device ID (88h) out on SO completed by CS =high * The Device ID (88h) is output repeatedly as long as clock inputs are present * The data output starts from the falling edge of SCK(31th) By setting CS to h igh, the device is deselected, and Read ID cycle is comp leted. While the device is deselected, the output pin SO is in a high-impedance state. Table 7. Device ID code Output Code 1 by te dev ice ID 88h (LE25S161) Figure 18. Read Device ID (RID) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 Mode0 8CLK SI SO ABh X X X High Impedance 88h MSB www.onsemi.com 31 88h MSB LE25S161 10-14. Deep Power-down (DP) The standby current can be further reduced with this command (DP). "Figure 19. Deep Power-down (DP)" shows the timing waveforms. The sequence of DP operation : CS goes to low input DP command (B9h) CS goes to high (be executed by the rising CS edge) The deep power-down command issued during an internal write operation will be ignored. The deep power-down state is exited using the deep power-down exit (EDP). All other commands are ignored. Figure 19. Deep Power-down (DP) Standby current (Isb) CS tDP Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI B9h MSB SO High Impedance www.onsemi.com 32 Deep Pow er-down Standby Current (Idsb) LE25S161 10-15. Exit Deep Power-down (EDP) / Read Device ID (RDDI) The Exit Deep Power-down (EDP) / Read Device ID (RID) co mmand is a multi-purpose command. It can be used to exit the device from the deep power-down state, or read the device ID information. Exit Deep Power-down (EDP) The exit deep power-down command consists only of the first byte cycle, and it is initiated by inputting (ABh). "Figure 20. Exiting from Deep Power-down" shows the timing waveforms. The sequence of EDP operation : CS goes to low input EDP command (ABh) CS goes to high (be executed by the rising CS edge) Figure 20. Exiting from Deep Power-down (EDP) Deep Pow er-down Standby current (Idsb) Standby current (Isb) CS tRDP Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI ABh MSB SO High Impedance www.onsemi.com 33 LE25S161 Read Device ID (RDDI) Also the exit from deep power-down is completed by one byte cycle or more of the Read Device ID (RID: ABh). "Table 7. Device ID code" lists the device ID codes. "Figure 21. Read Device ID " shows the timing waveforms. The sequence of EDP & RID operation : CS goes to low input RID command (ABh) 3 byte dummy cycle Device ID out on SO completed by CS =high * The Device ID is output repeatedly as long as clock inputs are present * The data output starts from the falling edge of SCK(31th clock) By setting CS to h igh, the device is deselected, and Read ID cycle is comp leted. While the device is deselected, the output pin SO is in a high-impedance state. Figure 21. Read Device ID Standby current (Isb) Deep Pow er-down Standbycurrent (Idsb) CS tRDP Mode3 SCK 0 1 2 3 4 5 6 7 8 SO 39 Mode0 8CL SI 31 32 ABh 24 Dummy Bits X X High Impedance Dev ID MSB www.onsemi.com 34 Dev ID Dev ID LE25S161 10-16. Software Reset The Software Reset reset the device to the state just after power-on. This operation consists of two commands: the Reset Enable (RSTEN) and the Reset command (RST). "Figure 22. Software Reset" shows the timing waveforms. The sequence of Software Reset operation : CS goes to low input RSTEN command (66h) CS goes to high CS goes to low input RST command (99h) CS goes to high (be executed by the rising CS edge) When the Software Reset is executed, an internal write (erase/program) operation is cancel, a suspended status is reset, and all volatility status register bits (WEN/ RDY/SUS) are reset. After the internal reset time (t RST), the device will become stand-by state. If the Software Reset is executed during a write (erase/program) operation, any dates on the write operation will be broken. The Reset command must input just after input the Reset Enable co mmand. If another command input after the Reset Enable command, the Reset-Enable state will be invalid. Figure 22. Software Reset Internal reset time (tRST) CS Mode3 SCK 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8CLK 8CLK 66h 99h Mode0 SI MSB SO MSB High Impedance www.onsemi.com 35 LE25S161 10-17. Read SFDP (RSFDP) The Read SFDP (Serial Flash Discoverable Parameter) is an operation that reads the parameter about device configurations, available co mmands and other features. The SFDP parameters are stored in internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. SFDP is a standard of JEDEC. JESD216. Rev 1.0. "Table 8. SFDP Header" shows SFDP Header. "Table 9. SFDP Parameter Table" shows SFDP Parameter Table. "Figure 23. Read SFDP (RSFDP)" shows the timing waveforms. The sequence of RSFDP operation : CS goes to low input RSFDP command (5Ah) 3 Byte address (A23-A0) input on SI 1 byte dummy cycle the corresponding parameter out on SO continuous parameter out (n-byte) completed by CS =high * A10 to A0 are valid address * The parameter output starts from the falling edge of SCK(39th clock) The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the corresponding parameter is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte parameter is shifted out. By setting CS to high, the device is deselected, and Read SFDP cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state. Figure 23. Read SFDP (RSFDP) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 Mode0 8CLK SI 5Ah Add Add Add (A23-A16) (A15-A8) (A7-A0) X MSB Byte 1 SO High Impedance Param1 Param2 Param3 MSB www.onsemi.com 36 Byte 2 Byte 3 MSB MSB LE25S161 Table 8. SFDP Header SFDP Header 1st and 2nd DWORD Description SFDP Signature Comment 50444653h (SFDP) By te Address (Hex) Bits Data (Hex) 00h 7:0 53h 01h 15:8 46h 02h 23:16 44h 03h 31:24 50h 7:0 05h 01h SFDP Minor Rev ision Number Start f rom 00h 04h SFDP Major Rev ision Number Start f rom 01h 05h 15:8 Number of Parameter Headers 02h indicates 3 parameters 06h 23:16 02h 07h 31:24 FFh By te Address (Hex) Bits Data (Hex) Unused 1st Parameter Header (JDEC Basic Flash parameters) Description ID number (JEDEC ID) Parameter Table Minor Rev ision Number Parameter Table Major Rev ision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) Comment 00h(JEDEC specif ied header) 08h 7:0 00h Start f rom 00h 09h 15:8 00h Start f rom 01h 0Ah 23:16 01h How many DWORDs in the Parameter table 10h indicates 16 DWORDs 0Bh 31:24 10h 0Ch 7:0 40h 0Dh 15:8 00h 0Eh 23:16 00h 0Fh 31:24 FFh By te Address (Hex) Bits Data (Hex) 62h(ON Semiconductor manuf acturer ID) 10h 7:0 62h Start f rom 00h 11h 15:8 00h Start f rom 01h 12h 23:16 01h How many DWORDs in the Parameter table 04h indicates 4 DWORDs 13h 31:24 04h 14h 7:0 C0h 15h 15:8 00h 16h 23:16 00h 17h 31:24 FFh First address of JEDEC Flash Parameter table Unused 2nd Parameter Header (Vender parameters 1) Description ID number (ON Semiconductor manuf acturer ID) Parameter Table Minor Rev ision Number Parameter Table Major Rev ision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) Comment First address of On Semiconductor Parameter table Unused www.onsemi.com 37 LE25S161 Table 9. SFDP Parameter Tables Parameter Table : JDEC Basic Flash Parameter Tables (f rom 1th DWORD to 4th DWORD) Description Block/Sector Erase Sizes Write Granularity Comment By te Address (Hex) 00b: Reserv ed 01b: support 4 KB Erase 10b: Reserv ed 11b: not support 4KB Erase 0: 1By te, 1:64 By te or larger 40h Unused 0: Non-v olatile 1: Volatile 0: use 50h opcode, 1: use 06h opcode Note: If target f lash status register is nonv olatile, then bits 3 and 4 must be set to 00b. Contains 111b and can nev er be changed 4KB Erase Instruction 20h 41h (1-1-2) Fast Read 0=not support 1=support 00: 3By te only , 01: 3 or 4By te, 10: 4By te only , 11: Reserv ed Volatile Status Register Block Protect bits Write Enable Instruction Select f or Writing to Volatile Status Register Address By tes Bits Data (Binary ) 1:0 01b 2 1b 3 0b 4 0b 7:5 111b 15:8 0010_0000b 16 1b 18:17 00b 19 0b 20 1b Double Transf er Rate (DTR) Clocking 0=not support 1=support (1-2-2) Fast Read 0=not support 1=support (1-4-4) Fast Read 0=not support 1=support 21 0b (1-1-4) Fast Read 0=not support 1=support 22 0b 42h Unused 23 1b Data (Hex) E5h 20h 91h Unused 43h 31:24 1111_1111b FFh Flash Memory Density 44h 45h 46h 47h 31:0 - 00FFFFFFh 4:0 0_0000b 7:5 000b 15:8 1111_1111b 20:16 0_0000b 23:21 000b 31:24 1111_1111b 4:0 0_1000b 7:5 000b (1-4-4) Fast Read Number of Wait states (dummy clocks) (1-4-4) Fast Read Number of Mode Clocks (1-4-4) Fast Read Instruction (1-1-4) Fast Read Number of Wait states (dummy clocks) (1-1-4) Fast Read Number of Mode Clocks (1-1-4) Fast Read Instruction (1-1-2) Fast Read Number of Wait states (dummy clocks) (1-1-2) Fast Read Number of Mode Clocks 16 M bits 0 0000b: Wait states (dummy Clocks) not support 48h 000b: Mode Bits not support 49h 0 0000b: Wait states (dummy Clocks) not support 4Ah 000b: Mode Bits not support 4Bh 0 0000b: Wait states (dummy Clocks) not support 000b: Mode Bits not support 4Dh 0 0000b: Wait states (dummy Clocks) not support (1-2-2) Fast Read Instruction 4Fh www.onsemi.com 38 FFh 08h 15:8 0011_1011b 20:16 0_0100b 23:21 000b 31:24 1011_1011b 4Eh 000b: Mode Bits not support FFh 00h 4Ch (1-1-2) Fast Read Instruction (1-2-2) Fast Read Number of Wait states (dummy clocks) (1-2-2) Fast Read Number of Mode Clocks 00h 3Bh 04h BBh LE25S161 Parameter Table : JDEC Basic Flash Parameter Tables (f rom 5th DWORD to 8th DWORD) Description Comment (2-2-2) Fast Read 0=not support 1=support Reserv ed Def ault all 1’s (4-4-4) Fast Read 0=not support 1=support Reserv ed Def ault all 1’s Reserv ed Def ault all 1’s Reserv ed Def ault all 1’s (2-2-2) Fast Read Number of Wait states (dummy clocks) (2-2-2) Fast Read Number of Mode Clocks (4-4-4) Fast Read Number of Wait states (dummy clocks) (4-4-4) Fast Read Number of Mode Clocks 0b 4 0b 7:5 111b 31:8 - 15:0 - 20:16 0_0000b 23:21 000b 57h 31:24 1111_1111b FFh 58h 59h 15:0 - FFh FFh 20:16 0_0000b 23:21 000b 31:24 1111_1111b FFh 5Ch 7:0 0000_1100b 0Ch 5Dh 15:8 0010_0000b 20h 5Eh 23:16 0001_0000b 10h 5Fh 31:24 1101_1000b D8h 50h 000b: Mode Bits not support Def ault all 1’s 0 0000b: Wait states (dummy Clocks) not support 000b: Mode Bits not support 5Bh Sector/block size = 2^N by tes 10h indicates 64Kby tes Sector Ty pe 2 erase Instruction www.onsemi.com 39 EEh FFh FFh FFh FFh FFh 00h 5Ah Sector/block size = 2^N by tes 0Ch indicates 4Kby tes Data (Hex) 111b 56h Sector Ty pe 1 erase Instruction Sector Ty pe 2 Size Data (Binary ) 0 0 0000b: Wait states (dummy Clocks) not support (4-4-4) Fast Read Instruction Sector Ty pe 1 Size Bits 3:1 51h 52h 53h 54h 55h (2-2-2) Fast Read Instruction Reserv ed By te Address (Hex) 00h LE25S161 Parameter Table : JDEC Basic Flash Parameter Tables (f rom 9th DWORD to 12th DWORD) By te Address (Hex) Bits Data (Binary ) Data (Hex) Sector/block size = 2^N by tes 00h indicates not exist 60h 7:0 0000_0000b 00h 61h 15:8 1111_1111b FFh Sector/block size = 2^N by tes 00h indicates not exist 62h 23:16 0000_0000b 00h 63h 31:24 1111_1111b FFh 3:0 0100b 10:4 00_01001b 17:11 00_01110b 24:18 00_00000b 31:25 00_00000b 3:0 0010b 7:4 1000b 13:8 1_00110b Description Sector Ty pe 3 Size Comment Sector Ty pe 3 erase Instruction Sector Ty pe 4 Size Sector Ty pe 4 erase Instruction Multiplier f rom ty pical erase time to maximum erase time Sector Ty pe 1 Erase, Ty pical time Sector Ty pe 2 Erase, Ty pical time SE (64K-By te erase): 150ms=2*(n+1)*15ms n=4 SSE (4K-By te erase) 10ms: ((n+1)*1ms=10ms) n=9 SE (64K-By te erase) 15ms: ((n+1)*1ms=15ms) n=14 Sector Ty pe 3 Erase, Ty pical time - Sector Ty pe 4 Erase, Ty pical time - Multiplier f rom ty pical time to max time f or Page or by te program (n+1)*0.3ms =0.9ms: n=2, 256By tes=2^8 Page Size 0.9ms > 0.7ms(spec) (n+1)*64µs =448us: n=6, By te Program Ty pical time, f irst by te (n+1)*8us =128us: n=15, By te Program Ty pical time, additional by te (count+1)*1µs/by te =1us/by te: Count=0 (n+1)*16ms =208ms: n=12 208ms = 210ms(spec) Reserv ed Prohibited Operations During Program Suspend Prohibited Operations During Erase Suspend 448µs > 400µs(spec) 00h 82h E6h 1_1111b 6Ah 6Bh xxx0b: May not initiate a new erase anywhere xxx1b: May not initiate a new eras e in the program suspended page size xx0xb: May not initiate a new page program anywhere xx1xb: May not initi ate a new page program i n the program suspended page size x0xxb: Refer to vendor datasheet for read restrictions x1xxb: May not initi ate a read i n the program s uspended page size 0xxxb: Additional erase or program restrictions apply 1xxxb: The erase and program restrictions in bits 1:0 are sufficient xxx0b: May not initiate a new erase anywhere xxx1b: M ay not initi ate a new erase i n the erase suspended sector size xx0xb: May not initiate a page program anywhere xx1xb: May not initiate a page program i n the erase suspended sector size x0xxb: Refer to vendor datasheet for read restrictions x1xxb: May not i nitiate a read in the erase s uspended sector size 0xxxb: Additional erase or program restrictions apply 1xxxb: The erase and program restrictions in bits 5:4 are sufficient <64µs: (count+1)*64µs, count=0 Suspend /resume supported 69h 00h 18:16 Program Resume to Suspend Interv al Erase Resume to Suspend Interv al Suspend in-progress erase max latency 66h 68h 94h 70h 15:14 Reserv ed Suspend in-progress Program max latency 65h 67h Page Program Ty pical time Chip Erase, Ty pical time 64h 23:19 0_0000b 30:24 00_01100b 31 0b 3:0 1101b 6Ch 6Dh 7:4 1111b 8 0b 12:9 0000b 19:16 6Eh <64µs: (count+1)*64µs, count=0 40µs: ((4+1)*8µs=40us) 0=support 1=not support www.onsemi.com 40 6Fh 0Ch FDh 15:13 40µs: ((4+1)*8us=40µs) 07h 80h 10_00100b 23:20 0000b 30:24 10_00100b 31 0b 08h 44h LE25S161 Parameter Table : JDEC Basic Flash Parameter Tables (f rom 13th DWORD to 16th DWORD) By te Address (Hex) Bits Data (Binary ) Data (Hex) 30h (as same as erase resume) 70h 7:0 0011_0000b 30h B0h (as same as erase suspend) 71h 15:8 1011_0000b B0h 30h (as same as program resume) 72h 23:16 0011_0000b 30h B0h (as same as program suspend) 73h 31:24 1011_0000b B0h 1:0 00b 7:2 0000_01b 14:8 10_00100b Description Program Resume Instruction (program operation) Program Suspend Instruction (program operation) Resume Instruction (write or erase ty pe operation) Suspend Instruction (write or erase ty pe operation) Comment Reserv ed Status Register Polling Dev ice Busy Use legacy polling by reading the Status Register with 05h instruction Exit Deep Power down to next operation delay 40µs: ((4+1)*8µs=40µs) Exit Deep Power down Instruction 74h 75h 15 ABh 76h B9h Deep Power down Supported 0=support 1=not support (4-4-4) Mode Disable Sequences - 77h 78h (4-4-4) Mode Enable Sequences - (0-4-4) Mode supported 0=not support 1=support (0-4-4) Mode Exit Method - (0-4-4) Mode Entry Method - Quad Enable requirements (QER) 00b:not hav e a QE bit Hold and WP Disable 0: not supported Reserv ed - Volatile or Non-Vol atile Register and Write Enable Instruction f or Status Register 1 xxx_xxx1b: Non-Volatile Status Register 1, powers-up to last written value, use instruction 06h to enable write xx1_xxxxb: Status Register 1 contai ns a mix of volatile and non- vol atile bits . The 06h instruc tion is used to enable writing of the register. 79h Issue reset enable instruction 66h, and then issue reset instruction 99h. Exit 4-By te Addressing Enter 4-By te Addressing www.onsemi.com 41 D5h 1011_1001b 30:24 31 0b 3:0 0000b 7:4 0000b 8 0b 5Ch 00h 0b 15:10 00_0000b 19:16 0000b 22:20 000b 23 0b 31:24 0000_0000b 6:0 001_1001b 7 0b 13:8 01_0000b 15:14 00b 7Eh 23:16 0000_0000b 00h 7Fh 31:24 0000_0000b 00h 7Bh Sof t Reset and Rescue Sequence Support 1010_1011b 9 7Ah Reserv ed C4h 22:16 23 Enter Deep Power down Instruction 04h 7Ch 7Dh 00h 00h 00h 19h 10h LE25S161 Parameter Table : Vender(ON Semiconductor) Parameter 1 Tables (f rom 1th DWORD to 4th DWORD) By te Data Address Bits Description Comment (Binary ) (Hex) 1900h=1.900V 2400h=2.400V 1950h=1.950V 2700h=2.700V C0h 15:0 Supply Maximum Voltage 3000h=3.000V C1h 2000h=2.000V 3600h=3.600V 2200h=2.200V 1600h=1.600V 20000h=2.000V 1650h=1.650V 22000h=2.200V C2h 31:16 Supply Minimum Voltage 1700h=1.700V 23000h=2.300V C3h 1800h=1.800V 27000h=2.700V 0=not support RESET Pin 0 0b 1= support 0=activ e logic is 0 1 0b RESET Activ e Logic Lev el 1=activ e logic is 1 0=not support HOLD Pin 2 1b 1= support 0=activ e logic is 0 C4h 3 0b HOLD Activ e Logic Lev el 1=activ e logic is 1 0=not support 4 1b WP Pin 1= support 0=activ e logic is 0 5 0b WP Activ e Logic Lev el 1=activ e logic is 1 Reserv ed 00b Reserv ed All FFh C5h C6h C7h JDEC ID Operation code 9Fh C8h JDEC ID Read Data (Manuf acture code) JDEC ID Read Data (Memory ty pe) JDEC ID Read Data (Memory capacity code) Data (Hex) LE25S161 50h 19h 50h 16h 14h 7:6 00b 31:8 1111_1111b 1111_1111b 1111_1111b 7:0 1001_1111b 9Fh FFh FFh FFh 62h (ON Semiconductor) C9h 15:8 0110_0010b 62h 16h CAh 23:16 0001_0110b 16h 15h (16M bits) CBh 31:24 0001_0101b 15h Dev ice ID Operation code ABh CCh 7:0 1010_1011b ABh Dev ice ID Read Data 88h(LE25S161) CDh 15:8 1000_1000b 88h Reserv ed All FFh CEh CFh 31:16 1111_1111b 1111_1111b FFh FFh www.onsemi.com 42 LE25S161 11. Hold Function Using the HOLD pin, the hold function suspends serial commun ication (it p laces it in the hold status). "Figure 24. HOLD Function" shows the timing wavefo rms. The device is placed in the hold status at the falling HOLD edge while the logic level of SCK is lo w, and it exits fro m the hold status at the rising HOLD edge. When the logic level of SCK is high, HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited and serial co mmun ication is reset at the rising CS edge. In the hold status, the SO output is in the h igh-impedance state, and SI and SCK are "don't care". Figure 24. HOLD Function CS Active Active HOLD tHS tHS SCK tHH tHH HOLD tHHZ SO tHLZ High Impedance www.onsemi.com 43 LE25S161 12. Power-on In order to protect against unintentional writing, CS must be within at VDD-0.3 to VDD+0.3 on power-on. After power-on, the supply voltage has stabilized at VDD (min) or higher, and waits for tVSL before CS is driven to "Low". The device is in the standby state after power is turned on. Figure 25. Power-on Timing V DD V DD(Max) Program, Erase and Write Commands are Ignored Chip Select ( CS="L") is Not Allow ed V DD(Min) tVSL Reset State Full Access Allowed Read Command is allow ed V WI tPUW 0V time Power-up timing Parameter Sy mbol spec min max unit µs t VSL 300 Time to Write Operation t PUW 100 500 µs Operation Inhibit Voltage VWI 1.0 1.5 V VDD (Min) to CS Low www.onsemi.com 44 LE25S161 13. Hardware Data Protection LE25S161 incorporates a power-on reset function. The following conditions must be met in order to ensure that the power reset circuit will operate stably. No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period. Figure 26. Power-down Timing V DD V DD(Max) V DD(Min) tPD 0V vBOT Power-down timing Parameter Sy mbol power-down time t PD power-down v oltage VBOT spec min max 10 unit ms 0.2 V 14. Software Data Protection The LE25S161 eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. • When a write command is input and the rising CS edge timing is not in a byte cycle (8 CLK units of SCK) • When the Page Program data is not in 1-byte increments • When the Write Status Register command is input for 2 bytes cycles or more 15. Decoupling Capacitor 0.1µF ceramic capacitor must be provided to each device and connected between VDD and VSS in o rder to ensure that the device will operate stably. www.onsemi.com 45 LE25S161 16. Specifications 16-1. Absolute Maximum Ratings Parameter Sy mbol Conditions Ratings unit Maximum supply v oltage With respect to VSS −0.5 to +2.6 V DC v oltage (all pins) With respect to VSS −0.5 to VDD +0.5 V −55 to +150 °C Storage temperature Tstg Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 16-2. Operating Conditions Parameter Sy mbol Conditions Operating supply v oltage Ratings unit 1.65 to 1.95 V −40 to +90 °C Operating ambient temperature Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 16-3. Data retention, Rewriting cycles Parameter Sy mbol condition Status resister write Rewrite Cy cles min max 1,000 cy cles/ cy cRW Program/Erase Data retention Sector 100,000 tDRET unit 20 y ear 16-4. Pin Capacitance at Ta=25°C, f=1MHz Ratings Parameter Sy mbol Conditions unit max Output pin capacitance C SO VSO=0V 12 pF Input pin Capacitance C IN VIN =0V 6 pF Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices. 16-5. AC Test Conditions Input pulse level············· 0.2VDD to 0.8VDD Input rising/falling time ··· 5ns Input timing level··········· 0.3VDD, 0.7VDD Output timing level········· 1/2×VDD Output load ··················· 15pF Note: As the test conditions for "typ", the measurements are conducted using 1.8V for VDD at room temperature. 0.8VDD Input level Input / Output timing level 0.7VDD 1/2VDD 0.3VDD 0.2VDD www.onsemi.com 46 LE25S161 16-6. DC Characteristics VDD =1.65 to 1.95V Parameter Sy mbol Conditions Ratings min Low-Power Read (RDLP: 03h) SCK= 0.1VDD/0.9VDD, Read mode operating current unit ty p max 33.33MHz 3.5 4.5 mA 33.33MHz 4.0 5.5 mA 70MHz 6.0 7.0 mA 33.33MHz 5.0 7.0 mA 50MHz 6.0 8.0 mA High-Speed Read (RDHS: 0Bh) I CCR HOLD= WP = 0.9VDD, SO=open Dual Output Read (RDDO: 3Bh) or Dual I/O Read (RDIO: BBh) Small Sector Erase operating current Sector Erase operating current Chip Erase operating current I CCSSE t SSE=max, Av erage current 3.5 4.5 mA I CCSE t SE=max Av erage current 3.5 4.5 mA I CCCHE t CHE=max Av erage current 4.0 5.0 mA 6.5 7.5 mA 5.0 6.5 mA Normal Program mode I CCPP operating current Low-Power Program mode I CCPPL operating current CMOS standby current Deep Power-down standby current t PP=max Av erage current t PPL=max Av erage current I SB CS=VDD , HOLD =WP=VDD , SI=VSS/VDD, SO=open, 9 50 µA I DSB CS=VDD , HOLD =WP=VDD , SI=VSS/VDD, SO=open, 3.0 12 µA Input leakage current I LI 2.0 µA Output leakage current I LO 2.0 µA Input low v oltage VIL −0.3 0.3VDD V Input high v oltage VIH 0.7VDD VDD +0.3 V Output low v oltage VOL Output high v oltage VOH I OL=100µA, VDD =VDD min 0.2 I OL=1.6mA, VDD =VDD min 0.4 V I OH =−100µA, VDD =VDD min VDD -0.2 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 47 LE25S161 16-7. AC Characteristics Ratings Parameter Clock f requency Sy mbol Low-Power Read (RDLP: 03h) Dual Output Read (RDDO: 3Bh) Dual I/O Read (RDIO: BBh) min ty p 33.33 50 f CLK Other instructions t RF 33.33MHz width SCK logic low lev el pulse width MHz 70 Input signal rising/f alling time SCK logic high lev el pulse unit max 50MHz 0.1 11 t CLHI 8 70MHz 6 33.33MHz 11 50MHz V/ns t CLLO 70MHz ns 8 ns 6 CS activ e setup time t SLCH 6 ns CS not activ e hold time t CHSL 6 ns Data setup time t DS 3 ns Data hold time t DH 3 ns CS wait pulse width t CPH 20 ns CS activ e hold time t CHSH 6 ns CS not activ e setup time t SHCH 6 Output high impedance time f rom CS ns t CHZ 8 10 33.33MHz Output data time f rom SCK 50MHz ns 8 tV ns 8 70MHz Output data hold time t HO 1 ns Output low impedance time f rom SCK t CLZ 0 ns t HS 6 ns HOLD hold time t HH 6 Output low impedance time f rom HOLD t HLZ 8 ns Output high impedance time f rom HOLD t HHZ 8 ns HOLD setup time WP setup time t WPS 20 WP hold time t WPH 20 Write status register time Normal Page Programming cy cle time Low-Power Page Programming cy cle time Small Sector Erase cy cle time Sector Erase cy cle time Chip Erase cy cle time Recov ery time f rom suspend Deep Power-down time t WRSR 256By te nBy te t PP ns ns 5 8 0.40 0.70 0.14 + n * 0.26/256 256By te nBy te ns 0.60 t PPL 0.14 + n * 0.46/256 ms ms 0.35 + n * 0.35/256 1.20 ms 0.50 + n * 0.70/256 t SSE 10 120 ms t SE 15 150 ms t CHE 210 2400 ms t RSUS 40 µs t DP 5 µs Deep Power-down recov ery time t RDP 40 µs Internal reset time tRST 40 µs Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 48 LE25S161 17. Timing waveforms Figure 27. Serial Input Timing tCPH CS tCHSL tSLCH tCLHI tCLLO tCHSH tSHCH SCK tDS SI tDH DATA VALID High Impedance SO High Impedance Figure 28. Serial Output Timing CS SCK tCLZ SO tHO tCHZ DATA VALID tV SI Figure 29. Hold Timing CS tHH tHH tHS tHS SCK HOLD tHLZ tHHZ High Impedance SI Figure 30. Status Resister Write Timing CS tWPS tWPH WP www.onsemi.com 49 LE25S161 Figure 31. Write Status Register Flowcharts Write Status Register Start 06h 01h Data Write enable (WREN) Set Write Status Register command (WRSR) Program start on rising edge of CS 05h Set Read Status Register command (RDSR) NO Bit 0= "0" ? YES End of Write Status Register * Automatically placed in w rite disabled state at the end of the Write Status Register www.onsemi.com 50 LE25S161 Figure 32. Small Sector Erase Flowcharts Small Sector Erase Sector Erase Start Start 06h 20h / D7h Write enable (WREN) 06h Set Small Sector Erase command (SSE) D8h Address 1 Address 1 Address 2 Address 2 Address 3 Address 3 Start erase on rising edge of CS Start erase on rising edge of CS Set Read Status Register command (RDSR) 05h NO Figure 33. Sector Erase Flowcharts 05h NO Write enable (WREN) Set Sector Erase command (SE) Set Read Status Register command (RDSR) Bit 0 = "0" ? Bit 0 = "0" ? YES YES End of erase End of erase * Automatically placed in write dis abled state at the end of the erase * Automatically placed in w rite disabled state at the end of the erase www.onsemi.com 51 LE25S161 Figure 34. Chip Erase Flowcharts Chip Erase Start 06h 60h / C7h Write enable (WREN) Set Chip Erase command (CHE) Start erase on rising edge of CS 05h Set Read Status Register command (RDSR) Bit 0 = "0" ? YES NO End of erase * Automatically placed in w rite disabled state at the end of the erase www.onsemi.com 52 LE25S161 Figure 35. Page Program Flowcharts Page Program Start 06h Write enable (WREN) 02h or 0Ah Address 1 Address 2 Set Page Program command (PP/PPL) *02h: Normal Program Mode (PP) *0Ah: Low -Power Program Mode (PPL) Address 3 Data 0 Data n Start program on rising edge of CS Set Read Status Register command (RDSR) 05h NO Bit 0= "0" ? YES End of programming * Automatically placed in w rite disabled state at the end of the programming operation. www.onsemi.com 53 LE25S161 ORDERING INFORMATION Package Shipping (Qty / Packing) LE25S161MDTWG Device SOIC 8, 150 mils (Pb-Free / Halogen Free) 2000 / Tape & Reel LE25S161FDTWG VSOIC8 NB (Pb-Free / Halogen Free) 3000 / Tape & Reel LE25S161XATAG WLCSP8, 2.92x1.53 (Pb-Free / Halogen Free) 4000 / Tape & Reel LE25S161PCTXG UDFN8 4x3, 0.8P (Pb-Free / Halogen Free) 2000 / Tape & Reel † For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. www.onsemi.com 54