CD74HC125-Q1
HIGH-SPEED CMOS LOGIC
QUAD BUFFER WITH 3-STATE OUTPUTS
SCLS579A − APRIL 2004 − REVISED SEPTEMBER 2008
D
D
D
D
D
D
D
D
D
Qualified for Automotive Applications
3-State Outputs
Separate Output Enable Inputs
Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus Driver Outputs . . . 15 LSTTL Loads
Extended Temperature Performance of
−40°C to 125°C
Balanced Propagation Delay and Transition
Times
Significant Power Reduction, Compared to
LSTTL Logic ICs
2-V to 6-V VCC Operation
High Noise Immunity NIL or NIH = 30% of
VCC at VCC = 5 V
M OR PW PACKAGE
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4Y
3OE
3A
3Y
description/ordering information
The CD74HC125 contains four independent 3-state buffers, each having its own output enable input which,
when HIGH, puts the output in the high-impedance state.
ORDERING INFORMATION{
−40°C
40°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE‡
TA
TOP-SIDE
MARKING
SOIC − M
Reel of 2500
CD74HC125QM96Q1
HC125Q
TSSOP − PW
Reel of 2000
CD74HC125QPWRQ1
HC125Q
†
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
(each gate)
INPUTS
A
OE
OUTPUT
Y
H
L
H
L
L
L
X
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CD74HC125-Q1
HIGH-SPEED CMOS LOGIC
QUAD BUFFER WITH 3-STATE OUTPUTS
SCLS579A − APRIL 2004 − REVISED SEPTEMBER 2008
logic diagram (positive logic)
1OE
1A
2OE
2A
1
2
3OE
3
1Y
3A
4
5
4OE
6
2Y
4A
10
9
8
3Y
13
12
11
4Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < −0.5 V or VI > VCC + 0.5 V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < −0.5 V or VO > VCC + 0.5 V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO > −0.5 or VO < VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Output source or sink current per output pin, IO (VO > −0.5 or VO < VCC + 0.5 V) . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
High-level
High
level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
MIN
NOM
MAX
2
5
6
V
4.2
0.5
VCC = 4.5 V
Low-level
Low
level input voltage
V
1.5
3.15
VCC = 2 V
VIL
UNIT
1.35
VCC = 6 V
V
1.8
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
tt
Input transition rise/fall time
VCC = 2 V
TA
1000
VCC = 4.5 V
500
VCC = 6 V
400
Operating free-air temperature
−40
125
ns
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CD74HC125-Q1
HIGH-SPEED CMOS LOGIC
QUAD BUFFER WITH 3-STATE OUTPUTS
SCLS579A − APRIL 2004 − REVISED SEPTEMBER 2008
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IO
(mA)
TEST CONDITIONS
CMOS loads
VOH
VI = VIH or VIL
TTL loads
CMOS loads
VOL
VI = VIH or VIL
TTL loads
II
VI = VCC or GND
ICC
VI = VCC or GND
IOZ
VI = VIL or VIH
VCC
TA = 25°C
MIN
TYP
MIN
−0.02
2V
1.9
1.9
−0.02
4.5 V
4.4
4.4
−0.02
6V
5.9
5.9
3.7
MAX
UNIT
V
−6
4.5 V
3.98
−7.8
6V
5.48
0.02
2V
0.1
0.1
0.02
4.5 V
0.1
0.1
0.02
6V
0.1
0.1
6
4.5 V
0.26
0.4
7.8
6V
0.26
0.4
6V
±0.1
±1
µA
6V
8
160
µA
6V
±0.5
±10
µA
10
10
pF
20
20
pF
0
5.2
CI
CO
MAX
3−state
V
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
A
TO
(OUTPUT)
Y
CONDITIONS
OE
Y
TA = 25°C
MIN
TYP
tt
OE
Y
Y
MIN
MAX
5V
2V
100
150
CL = 50 pF
4.5 V
20
30
6V
17
26
2V
125
190
4.5 V
25
38
21
32
CL = 50 pF
5V
5V
2V
125
190
CL = 50 pF
4.5 V
25
38
6V
21
32
POST OFFICE BOX 655303
ns
10
2V
60
90
4.5 V
12
18
6V
10
15
• DALLAS, TEXAS 75265
ns
10
CL = 15 pF
CL = 50 pF
p
UNIT
8
6V
tdis
MAX
CL = 15 pF
CL = 15 pF
ten
VCC
ns
ns
3
CD74HC125-Q1
HIGH-SPEED CMOS LOGIC
QUAD BUFFER WITH 3-STATE OUTPUTS
SCLS579A − APRIL 2004 − REVISED SEPTEMBER 2008
operating characteristics, TA = 25°C, VCC = 5V
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate (see Note 4)
No load
NOTE 4: Cpd is used to determine the dynamic power consumption, per channel.
PD = VCC2 fI (Cpd + CL)
fI = input frequency
CL = output load capacitance
VCC = supply voltage
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
29
UNIT
pF
CD74HC125-Q1
HIGH-SPEED CMOS LOGIC
QUAD BUFFER WITH 3-STATE OUTPUTS
SCLS579A − APRIL 2004 − REVISED SEPTEMBER 2008
PARAMETER MEASUREMENT INFORMATION
VCC
PARAMETER
Test
Point
From Output
Under Test
S1
ten
RL
CL
(see Note A)
tdis
S2
tPZH
RL
1 kΩ
CL
1 kΩ
50 pF
tPLZ
tpd or tt
−−
Output
Control
(Low-Level
Enabling)
50%
S2
Open
Closed
Closed
Open
Open
Closed
Closed
Open
Open
Open
50 pF
tPZL
tPHZ
S1
50 pF
LOAD CIRCUIT
VCC
Input
50%
50%
0V
tPLH
In-Phase
Output
50%
10%
tPHL
90%
VOH
50%
10% V
OL
tf
90%
tr
tPHL
Out-of-Phase
Output
90%
tPLH
50%
10%
50%
10%
90%
VOH
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
0V
tPZL
VOL
tf
VCC
50%
Output
Waveform 1
(See Note B)
tPLZ
10%
tPZH
Input
50%
10%
90%
VCC
90%
50%
10% 0 V
tr
Output
Waveform 2
(See Note B)
≈VCC
≈VCC
50%
VOL
tPHZ
50%
90%
VOH
≈0 V
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
CD74HC125QM96G4Q1
ACTIVE
Package Type Package
Drawing
SOIC
Pins
Package Qty
D
14
2500
Green (RoHS
& no Sb/Br)
Eco Plan
(2)
TBD
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CU NIPDAU Level-1-260C-UNLIM
CD74HC125QM96Q1
OBSOLETE
SOIC
D
14
CD74HC125QPWRG4Q1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Call TI
Call TI
CD74HC125QPWRQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD74HC125-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
• Catalog: CD74HC125
• Military: CD54HC125
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
CD74HC125QPWRG4Q1 TSSOP
PW
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HC125QPWRG4Q1
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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