TI1 DLP7000BFLP Lvds type a dmd Datasheet

Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
DLP7000 DLP® 0.7 XGA 2x LVDS Type A DMD
1 Features
3 Description
•
The DLP7000 XGA Chipset is part of the DLP®
Discovery™ 4100 platform, which enables high
resolution and high performance spatial light
modulation. The DLP7000 is the digital micromirror
device (DMD) fundamental to the 0.7 XGA chipset,
and currently supports the fastest pattern rates in the
DLP catalog portfolio. The DLP Discovery 4100
platform also provides the highest level of individual
micromirror control with the option for random row
addressing. Combined with a hermetic package, the
unique capability and value offered by DLP7000
makes it well suited to support a wide variety of
industrial,
medical,
and
advanced
display
applications.
1
•
•
•
•
•
0.7-Inch Diagonal Micromirror Array
– 1024 x 768 Array of Aluminum, MicrometerSized Mirrors
– 13.68 µm Micromirror Pitch
– ±12° Micromirror Tilt Angle (Relative to Flat
State)
– Designed for Corner Illumination
Designed for Use With Broadband Visible Light
(400 to 700 nm):
– Window Transmission 97% (Single Pass,
Through Two Window Surfaces)
– Micromirror Reflectivity 88%
– Array Diffraction Efficiency 86%
– Array Fill Factor 92%
Two 16-Bit, Low Voltage Differential Signaling
(LVDS) Double Data Rate (DDR) Input Data
Buses
Up to 400 MHz Input Data Clock Rate
40.64-mm by 31.75-mm by 6.0-mm Package
Footprint
Hermetic Package
2 Applications
•
•
•
Industrial
– Digital Imaging Lithography
– Laser Marking
– LCD and OLED Repair
– Computer-to-Plate Printers
– SLA 3D Printers
– 3D Scanners for Machine Vision and Factory
Automation
– Flat Panel Lithography
Medical
– Phototherapy Devices
– Ophthalmology
– Direct Manufacturing
– Hyperspectral Imaging
– 3D Biometrics
– Confocal Microscopes
Display
– 3D Imaging Microscopes
– Adaptive Illumination
– Augmented Reality and Information Overlay
In addition to the DLP7000 DMD, the 0.7 XGA
Chipset includes these components:
• Dedicated DLPC410 controller for high speed
pattern rates of >32000 Hz (1-bit binary) and
>1900 Hz (8-bit gray)
• One unit DLPR410 (DLP Discovery 4100
Configuration PROM)
• One unit DLPA200 (DMD Micromirror Driver)
Device Information(1)
PART NUMBER
DLP7000
PACKAGE
LCCC (203)
BODY SIZE (NOM)
40.64 mm x 31.75 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Description (continued)......................................... 4
Pin Configuration and Functions ......................... 4
Specifications....................................................... 11
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
8
Absolute Maximum Ratings .................................... 11
Storage Conditions.................................................. 11
ESD Ratings............................................................ 11
Recommended Operating Conditions..................... 12
Thermal Information ................................................ 13
Electrical Characteristics......................................... 14
LVDS Timing Requirements ................................... 15
LVDS Waveform Requirements.............................. 15
Serial Control Bus Timing Requirements................ 15
Systems Mounting Interface Loads....................... 18
Micromirror Array Physical Characteristics ........... 19
Micromirror Array Optical Characteristics ............. 20
Window Characteristics......................................... 21
Chipset Component Usage Specification ............. 21
Detailed Description ............................................ 22
8.1 Overview ................................................................. 22
8.2
8.3
8.4
8.5
8.6
8.7
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Window Characteristics and Optics .......................
Micromirror Array Temperature Calculation............
Micromirror Landed-On/Landed-Off Duty Cycle .....
22
24
31
33
34
35
Application and Implementation ........................ 38
9.1 Application Information............................................ 38
9.2 Typical Application .................................................. 39
10 Power Supply Recommendations ..................... 41
10.1 DMD Power-Up and Power-Down Procedures..... 41
11 Layout................................................................... 41
11.1 Layout Guidelines ................................................. 41
11.2 Layout Example .................................................... 43
12 Device and Documentation Support ................. 44
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
44
45
45
45
45
45
13 Mechanical, Packaging, and Orderable
Information ........................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2014) to Revision D
Page
•
Updated Figure 21 ............................................................................................................................................................... 44
•
Updated Figure 22................................................................................................................................................................ 44
Changes from Revision B (June 2013) to Revision C
Page
•
Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Deleted / DLPR4101 Enhanced PROM from Chipset List ..................................................................................................... 1
•
Corrected VCC2 max to 8 V ................................................................................................................................................ 11
•
Added array temperature vs duty cycle graph...................................................................................................................... 13
•
Replaced serial communications bus timing parameters ..................................................................................................... 17
•
Converted interface loads to Newtons.................................................................................................................................. 18
•
Grayed out LVDS buses that are unused on DLP7000 ....................................................................................................... 26
•
Added micromirror landed duty cycle section....................................................................................................................... 35
•
Changed to DLP7000 ........................................................................................................................................................... 38
•
Deleted / DLPR4101 Enhanced PROM from Related Documentation................................................................................. 45
2
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
Changes from Revision A (September 2012) to Revision B
Page
•
Added / DLPR4101 Enhanced PROM to DLPR410 in Chipset List ....................................................................................... 1
•
Changed pin number of DCLK_AN From: D19 To: B22 ....................................................................................................... 8
•
Changed pin number of DCLK_AP From: E19 To: B24 ........................................................................................................ 8
•
Changed pin number of DCLK_BN From: M19 To: AB22 ..................................................................................................... 8
•
Changed pin number of DCLK_BP From: N19 To: AB24 ..................................................................................................... 8
•
Added / DLPR4101 Enhanced PROM to DLPR410 in Related Documentation .................................................................. 45
Changes from Original (August 2012) to Revision A
•
Page
Changed the device From: Product Preview To: Production ................................................................................................. 1
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
3
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
5 Description (continued)
Reliable function and operation of the DLP7000 requires that it be used in conjunction with the other components
of the chipset. A dedicated chipset provides developers easier access to the DMD as well as high speed,
independent micromirror control.
DLP7000 is a digitally controlled micro-electromechanical system (MEMS) spatial light modulator (SLM). When
coupled to an appropriate optical system, the DLP7000 can be used to modulate the amplitude, direction, and/or
phase of incoming light.
Electrically, the DLP7000 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of
1024 memory cell columns by 768 memory cell rows. The CMOS memory array is addressed on a row-by-row
basis, over two 16-bit Low Voltage Differential Signaling (LVDS) double data rate (DDR) buses. Addressing is
handled via a serial control bus. The specific CMOS memory access protocol is handled by the DLPC410 digital
controller.
6 Pin Configuration and Functions
FLP Package
203-Pin LCCC
Bottom View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
30
28
29
4
26
27
24
25
22
23
20
21
18
19
16
17
14
15
12
13
Submit Documentation Feedback
10
11
8
9
6
7
4
5
2
3
1
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
Pin Functions
PIN (1)
NO.
TYPE
(I/O/P)
INTERNAL
TERM (3)
CLOCK
D_AN(0)
B10
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
368.72
D_AN(1)
A13
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
424.61
D_AN(2)
D16
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
433.87
D_AN(3)
C17
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
391.39
D_AN(4)
B18
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
438.57
D_AN(5)
A17
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
391.13
D_AN(6)
A25
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
563.26
D_AN(7)
D22
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
411.62
D_AN(8)
C29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
D_AN(9)
D28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
543.07
D_AN(10)
E27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
455.98
D_AN(11)
F26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
359.5
D_AN(12)
G29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
542.67
D_AN(13)
H28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
551.51
D_AN(14)
J27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
528.04
D_AN(15)
K26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
484.38
D_AP(0)
B12
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
366.99
D_AP(1)
A11
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
417.47
NAME
SIGNAL
DATA
RATE (2)
DESCRIPTION
TRACE
DATA INPUT
(1)
(2)
(3)
Input data bus A
(2x LVDS)
595.11
The following power supplies are required to operate the DMD: VCC, VCC1, VCC2. VSS must also be connected.
DDR = Double Data Rate. SDR = Single Data Rate. Refer to the LVDS Timing Requirements for specifications and relationships.
Refer to Electrical Characteristics for differential termination specification.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
5
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
Pin Functions (continued)
PIN
(1)
NO.
TYPE
(I/O/P)
INTERNAL
TERM (3)
CLOCK
D_AP(2)
D14
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
434.89
D_AP(3)
C15
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
394.67
D_AP(4)
B16
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
437.3
D_AP(5)
A19
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
389.01
D_AP(6)
A23
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
562.92
D_AP(7)
D20
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
410.34
D_AP(8)
A29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
594.61
D_AP(9)
B28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
539.88
D_AP(10)
C27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
456.78
D_AP(11)
D26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
360.68
D_AP(12)
F30
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
D_AP(13)
H30
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
570.85
D_AP(14)
J29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
527.18
D_AP(15)
K28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
481.02
D_BN(0)
AB10
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
368.72
D_BN(1)
AC13
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
424.61
D_BN(2)
Y16
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
433.87
D_BN(3)
AA17
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
391.39
D_BN(4)
AB18
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
438.57
NAME
6
SIGNAL
DATA
RATE (2)
Submit Documentation Feedback
DESCRIPTION
Input data bus A
(2x LVDS)
TRACE
543.97
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
Pin Functions (continued)
PIN
(1)
NO.
TYPE
(I/O/P)
INTERNAL
TERM (3)
CLOCK
D_BN(5)
AC17
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
391.13
D_BN(6)
AC25
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
563.26
D_BN(7)
Y22
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
411.62
D_BN(8)
AA29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
595.11
D_BN(9)
Y28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
543.07
D_BN(10)
W27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
455.98
D_BN(11)
V26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
360.94
D_BN(12)
T30
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
575.85
D_BN(13)
R29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
519.37
D_BN(14)
R27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
D_BN(15)
N27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
441.14
D_BP(0)
AB12
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
366.99
D_BP(1)
AC11
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
417.47
D_BP(2)
Y14
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
434.89
D_BP(3)
AA15
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
394.67
D_BP(4)
AB16
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
437.3
D_BP(5)
AC19
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
389.01
DCLK_B
DCLK_B
NAME
SIGNAL
DATA
RATE (2)
D_BP(6)
AC23
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
D_BP(7)
Y20
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DESCRIPTION
Input data bus A continued (2x
LVDS)
Input data bus B
(2x LVDS)Input
data bus B (2x
LVDS)
TRACE
532.59
562.92
410.34
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
7
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
Pin Functions (continued)
PIN
(1)
NO.
TYPE
(I/O/P)
INTERNAL
TERM (3)
CLOCK
D_BP(8)
AC29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
594.61
D_BP(9)
AB28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
539.88
D_BP(10)
AA27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
456.78
D_BP(11)
Y26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
360.68
D_BP(12)
U29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
578.46
D_BP(13)
T28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
509.74
D_BP(14)
P28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
D_BP(15)
P26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
DCLK_AN
B22
Input
LVCMOS
–
Differential
Terminated 100 Ω
–
DCLK_AP
B24
Input
LVCMOS
–
Differential
Terminated 100 Ω
–
DCLK_BN
AB22
Input
LVCMOS
–
Differential
Terminated 100 Ω
–
DCLK_BP
AB24
Input
LVCMOS
–
Differential
Terminated 100 Ω
–
NAME
SIGNAL
DATA
RATE (2)
DESCRIPTION
Input data bus B
(2x LVDS)
TRACE
534.59
440
DATA CLOCK
DATA CONTROL INPUTS
SCTRL_AN
C21
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
Serial control for
data bus A (2x
LVDS)
SCTRL_AP
C23
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
477.14
SCTRL_BN
AA21
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
Serial control for
data bus B (2x
LVDS)
SCTRL_BP
AA23
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
477.14
477.07
477.07
SERIAL COMMUNICATION AND CONFIGURATION
SCPCLK
E3
Input
LVCMOS
–
Pull-down
SCPDO
B2
Output
LVCMOS
–
SCPDI
F4
Input
LVCMOS
–
SCPENZ
D4
Input
LVCMOS
PWRDNZ
C3
Input
LVCMOS
8
–
Serial port clock
379.29
–
SCPCLK
Serial port output
480.91
Pull-down
SCPCLK
Serial port input
323.56
–
Pull-down
SCPCLK
Serial port enable
326.99
–
Pull-down
–
Device Reset
406.28
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
Pin Functions (continued)
PIN
(1)
NAME
NO.
TYPE
(I/O/P)
MODE_A
D8
Input
LVCMOS
–
Pull-down
–
MODE_B
C11
Input
LVCMOS
–
Pull-down
–
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
CLOCK
DESCRIPTION
Data bandwidth
mode select
TRACE
396.05
208.86
MICROMIRROR BIAS CLOCKING PULSE
MBRST(0)
P2
Input
Analog
–
–
–
MBRST(1)
AB4
Input
Analog
–
–
–
MBRST(2)
AA7
Input
Analog
–
–
–
MBRST(3)
N3
Input
Analog
–
–
–
MBRST(4)
M4
Input
Analog
–
–
–
MBRST(5)
AB6
Input
Analog
–
–
–
MBRST(6)
AA5
Input
Analog
–
–
–
Micromirror Bias
Clocking Pulse
"MBRST" signals
"clock"
micromirrors into
state of LVCMOS
memory cell
associated with
each mirror.
MBRST(7)
L3
Input
Analog
–
–
–
MBRST(8)
Y6
Input
Analog
–
–
–
MBRST(9)
K4
Input
Analog
–
–
–
MBRST(10)
L5
Input
Analog
–
–
–
MBRST(11)
AC5
Input
Analog
–
–
–
MBRST(12)
Y8
Input
Analog
–
–
–
MBRST(13)
J5
Input
Analog
–
–
–
MBRST(14)
K6
Input
Analog
–
–
–
MBRST(15)
AC7
Input
Analog
–
–
–
VCC
A7, A15,
C1, E1, U1,
W1, AB2,
AC9, AC15
Power
Analog
–
–
–
Power for
LVCMOS Logic
–
VCC1
A21, A27,
D30, M30,
Y30, AC21,
AC27
Power
Analog
–
–
–
Power supply for
LVDS Interface
–
VCC2
G1, J1, L1,
N1, R1
Power
Analog
–
–
–
Power for High
Voltage CMOS
Logic
–
POWER
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
9
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
Pin Functions (continued)
PIN
NAME
(1)
NO.
A1, A3, A5,
A9, B4, B8,
B14, B20,
B26, B30,
C7, C13,
C19, C25,
D6, D12,
D18, D24,
E29, F2,
F28, G3,
G27, H2,
H4, H26, J3,
J25, K2,
K30, L25,
L27, L29,
M2, M6,
M26, M28,
N5, N25,
N29, P4,
P30, R3,
R5, R25,
T2, T26,
U27, V28,
V30, W5,
W29, Y4,
Y12, Y18,
Y24, AA3,
AA9, AA13,
AA19,
AA25, AB8,
AB14,
AB20,
AB26, AB30
VSS
TYPE
(I/O/P)
Power
SIGNAL
Analog
DATA
RATE (2)
INTERNAL
TERM (3)
CLOCK
DESCRIPTION
TRACE
–
–
–
Common return
for all power
inputs
–
RESERVED SIGNALS (NOT FOR USE IN SYSTEM)
RESERVED
_AA1
AA1
Input
LVCMOS
–
Pull-down
–
Pins should be
connected to VSS
–
RESERVED
_B6
B6
Input
LVCMOS
–
Pull-down
–
–
–
RESERVED
_T4
T4
Input
LVCMOS
–
Pull-down
–
–
–
RESERVED
_U5
U5
Input
LVCMOS
–
Pull-down
–
–
–
NO_CONN
ECT
AA11, AC3,
C5, C9,
D10, D2,
E5, G5, H6,
P6, T6, U3,
V2, V4, W3,
Y10, Y2
–
–
–
–
–
Do not connect
–
10
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
ELECTRICAL
VCC
Voltage applied to VCC
(2) (3)
–0.5
4
V
VCCI
Voltage applied to VCCI
(2) (3)
–0.5
4
V
VCC2
Voltage applied to VVCC2
–0.5
8
V
VMBRST
Micromirror Clocking Pulse Waveform Voltage applied to MBRST[15:0]
Input Pins (supplied by DLPA200)
–28
28
V
0.3
V
|VCC – VCCI|
(2) (3) (4)
Supply voltage delta (absolute value)
Voltage applied to all other input pins
(4)
(2)
VCC + 0.3
V
|VID|
Maximum differential voltage, Damage can occur to internal termination
resistor if exceeded, See Figure 3
–0.5
700
mV
IOH
Current required from a high-level
output
VOH = 2.4 V
–20
mA
IOL
Current required from a low-level
output
VOL = 0.4 V
15
mA
ENVIRONMENTAL
TC
Case temperature: operational (5)
10
65
°C
Case temperature: non-operational (5)
–40
80
°C
10
°C
95
%RH
Device temperature gradient - operational (6)
TGRADIENT
Operating relative humidity (non-condensing)
(1)
(2)
(3)
(4)
(5)
(6)
0
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS (ground).
VOFFSET supply transients must fall within specified max voltages.
To prevent excess current, the supply voltage delta |VCC – VCCI| must be less than specified limit.
DMD Temperature is the worst-case of any test point shown in Figure 18, or the active array as calculated by the Micromirror Array
Temperature Calculation.
As measured between any two points on the exterior of the package, or as predicted between any two points inside the micromirror
array cavity. Refer to Thermal Information and Micromirror Array Temperature Calculation.
7.2 Storage Conditions
applicable before the DMD is installed in the final product
Storage temperature
Tstg
Storage humidity, non-condensing
MIN
MAX
–40
80
UNIT
°C
0
95
%RH
7.3 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
All pins except MBRST[15:0]
±2000
Pins MBRST[15:0]
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
11
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
SUPPLY VOLTAGES
MIN
NOM
MAX
UNIT
(1) (2)
VCC
Supply voltage for LVCMOS core logic
3
3.3
3.6
V
VCCI
Supply voltage for LVDS receivers
3
3.3
3.6
V
VCC2
Mirror electrode and HVCMOS supply voltage
7.25
7.5
7.75
V
VMBRST
Clocking Pulse Waveform Voltage applied to MBRST[29:0] Input Pins
(supplied by DLPA200s)
26.5
V
|VCC – VCCI|
Supply voltage delta (absolute value)
0.3
V
ENVIRONMENTAL
(5)
(3)
(4)
For Illumination Source between 420 and 700 nm
Operating Case Temperature (6): Thermal Test Points 1 and 2 (7)
TC
(6)
Operating Case Temperature : Thermal Test Point 3 and Array
TGRADIENT
Device temperature gradient – operational
(7)
Illumination
ENVIRONMENTAL (5)
For Illumination Source between 400 and 420 nm
(6)
Operating Case Temperature : Thermal Test Point 3 and Array
Device temperature gradient – operational
(7)
°C
10
25-45
65 (7)
°C
10
°C
95
%RH
ILLVIS
Illumination
ENVIRONMENTAL (5)
For Illumination Source <400 and >700 nm
(6)
Operating Case Temperature : Thermal Test Point 3 and Array
Device temperature gradient – operational
25-45
65 (7)
°C
10
25-45
65 (7)
°C
0
Operating Case Temperature (6): Thermal Test Points 1 and 2 (7)
(7)
10
°C
95
%RH
2.5
W/cm2
10
25-45
65 (7)
°C
10
25-45
65 (7)
°C
10
°C
(8)
Operating relative humidity (non-condensing)
W/cm2
10
(8)
Operating relative humidity (non-condensing)
TGRADIENT
65 (7)
0
Operating Case Temperature (6): Thermal Test Points 1 and 2 (7)
TC
25-45
Thermally
Limited (9)
ILLVIS
TGRADIENT
10
(8)
Operating relative humidity (non-condensing)
TC
–27
0
95
%RH
ILLUV
Illumination, wavelength <400 nm
0.68
mW/cm2
ILLIR
Illumination, wavelength >700 nm
10
mW/cm2
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
12
Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
All voltages are referenced to common ground VSS.
Voltages VCC, VCCI, and VCC2, are required for proper DMD operation.
To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
Optimal, long-term performance and optical efficiency of the digital micromirror device (DMD) can be affected by various application
parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle (Refer to Figure 1), ambient
temperature (storage and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI
recommends that application-specific effects be considered as early as possible in the design cycle.
In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See the Thermal
Information for further details.
See theThermal Information and the Micromirror Array Temperature Calculation for Thermal Test Point Locations, Package Thermal
Resistance, and Device Temperature Calculation.
As measured between any two points on the exterior of the package, or as predicted between any two points inside the micromirror
array cavity. Refer to Thermal Information and Micromirror Array Temperature Calculation.
Refer to Thermal Information and Micromirror Array Temperature Calculation.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
Figure 1. Max Recommended DMD Temperature – Derating Curve
7.5 Thermal Information
DLP7000
THERMAL METRIC
(1)
FLP (LCCC)
UNIT
203 PINS
Active micromirror array resistance to TC2
(1)
0.90
°C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate
heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the
Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area;
although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical
systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in
this area can significantly degrade the reliability of the device.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
13
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
7.6 Electrical Characteristics
over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted).
PARAMETERS
TEST CONDITIONS
High-level output voltage
See Figure 11
VOH
(1)
,
NOM
MAX
UNIT
2.4
V
(1)
VOL
Low-level output voltage
See Figure 11
VMBRST
Clocking Pulse Waveform applied to
MBRST[29:0] Input Pins (supplied
by DLPA200)
IOZ
High impedance output current (1)
IOH
High-level output current (1)
IOL
VCC = 3.0 V, IOH = –20 mA
MIN
,
Low-level output current (1)
VCC = 3.6 V, IOH = 15 mA
–27
VCC = 3.6 V
0.4
V
26.5
V
10
µA
VOH = 2.4 V, VCC ≥3 V
–20
VOH = 1.7 V, VCC ≥2.25 V
–15
VOL = 0.4 V, VCC ≥3 V
15
VOL = 0.4 V, VCC ≥2.25 V
14
mA
mA
VIH
High-level input voltage (1)
1.7
VCC + .3
V
VIL
Low-level input voltage (1)
–0.3
0.7
V
µA
(1)
IIL
Low-level input current
VCC = 3.6 V, VI = 0 V
–60
IIH
High-level input current (1)
VCC = 3.6 V, VI = VCC
200
µA
ICC
Current into VCC pin
VCC = 3.6 V,
1475
mA
ICCI
Current into VCCI pin (2)
VCCI = 3.6 V
450
mA
ICC2
Current into VCC2 pin
VCC2 = 8.75 V
ZIN
Internal Differential Impedance
95
ZLINE
Line Differential Impedance (PWB,
Trace)
90
CI
Input capacitance (1)
CO
Output capacitance (1)
CIM
Input capacitance for MBRST[29:0]
pins
f = 1 MHz
(1)
(2)
14
25
mA
105
Ω
110
Ω
f = 1 MHz
10
pF
f = 1 MHz
10
pF
270
pF
220
100
Applies to LVCMOS pins only.
Exceeding the maximum allowable absolute voltage difference between VCC and VCCI may result in excess current draw. See the
Absolute Maximum Ratings for details.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
7.7 LVDS Timing Requirements
over operating free-air temperature range (unless otherwise noted). See Figure 2
MIN
fDCLK_*
DCLK_* clock frequency {where * = [A, or B]}
200
tc
Clock Cycle - DLCK_*
2.5
tw
Pulse Width - DLCK_*
ts
Setup Time - D_*[15:0] and SCTRL_* before DCLK_*
th
Hold Time, D_*[15:0] and SCTRL_* after DCLK_*
tskew
Skew between bus A and B
NOM
MAX
UNIT
400
MHz
ns
1.25
ns
.35
ns
.35
ns
–1.25
1.25
ns
7.8 LVDS Waveform Requirements
over operating free-air temperature range (unless otherwise noted). See Figure 3
|VID|
Input Differential Voltage (absolute difference)
VCM
Common Mode Voltage
VLVDS
LVDS Voltage
tr
tr
MIN
NOM
MAX
UNIT
100
400
600
mV
1200
mV
0
2000
mV
Rise Time (20% to 80%)
100
400
ps
Fall Time (80% to 20%)
100
400
ps
7.9 Serial Control Bus Timing Requirements
over operating free-air temperature range (unless otherwise noted). See Figure 4 and Figure 5
MIN
MAX
UNIT
50
NOM
500
kHz
–300
300
ns
960
ns
fSCP_CLK
SCP Clock Frequency
tSCP_SKEW
Time between valid SCP_DI and rising edge of SCP_CLK
tSCP_DELAY
Time between valid SCP_DO and rising edge of SCP_CLK
tSCP_EN
Time between falling edge of SCP_EN and the first rising edge of
SCP_CLK
t_SCP
Rise time for SCP signals
200
ns
tf_SCP
Fall time for SCP signals
200
ns
30
ns
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
15
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
tw
DCLK_AN
DCLK_AP
th
tw
tc
ts
ts
th
SCTRL_AN
SCTRL_AP
tskew
D_AN(15:0)
D_AP(15:0)
DCLK_BN
DCLK_BP
th
tw
tw
tc
ts
ts
th
SCTRL_BN
SCTRL_BP
D_BN(15:0)
D_BP(15:0)
Figure 2. LVDS Timing Waveforms
VLVDS
(v)
VLVDSmax = VCM + |½VID|
VLVDSmax
Tf (20% - 80%)
VLVDS = V CM +/- | 1/2 V ID |
VID
VCM
T r (20% - 80%)
VLVDS min
VLVDS min = 0
Time
Figure 3. LVDS Waveform Requirements
16
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
tc
SCPCLK
fclock = 1 / tc
50%
50%
tSCP_SKEW
SCPDI
50%
tSCP_DELAY
SCPD0
50%
Figure 4. Serial Communications Bus Timing Parameters
tr_SCP
tf_SCP
Input Controller VCC
SCP_CLK,
SCP_DI,
SCP_EN
VCC/2
0v
Figure 5. Serial Communications Bus Waveform Requirements
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
17
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
7.10 Systems Mounting Interface Loads
MIN
Maximum system mounting interface
load to be applied to the:
Thermal Interface area
Electrical Interface area
Datum “A” Interface area
(1)
(See Figure 6)
(1)
NOM
MAX
UNIT
111
N
423
N
400
N
Combined loads of the thermal and electrical interface areas in excess of Datum “A” load shall be evenly distributed outside the Datum
“A” area (425 + 111 – Datum “A").
Figure 6. System Interface Loads
18
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
7.11 Micromirror Array Physical Characteristics
PARAMETER
M
Number of active columns
N
Number of active rows
P
Micromirror (pixel) pitch
UNIT
1024
micromirrors
768
micromirrors
13.68
µm
Micromirror active array width
M×P
14.008
mm
Micromirror active array height
N×P
10.506
Micromirror active border
Pond of micromirror (POM) (1)
10
mm
micromirrors/side
M±4
M±3
M±2
M±1
The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
0
1
2
3
(1)
VALUE
See Figure 7
0
1
2
3
DMD Active Array
NxP
M x N Micromirrors
N±4
N±3
N±2
N±1
MxP
P
Border micromirrors omitted for clarity.
Details omitted for clarity.
P
Not to scale.
P
P
Refer to Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 7. Micromirror Array Physical Characteristics
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
19
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
7.12 Micromirror Array Optical Characteristics
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
PARAMETER
a
Micromirror tilt angle
β
Micromirror tilt angle tolerance(1) (4) (6) (7)
CONDITIONS
MIN
DMD “parked” state(1) (2) (3), See
Figure 13
DMD “landed” state(1) (4)
See Figure 13
(8)
Non operating micromirrors(11)
–1
16
1
degrees
22
µs
43
µs
Non-adjacent micromirrors
10
adjacent micromirrors
Orientation of the micromirror axis-ofrotation(12)
See Figure 12
Micromirror array optical efficiency(13) (14)
400 nm to 700 nm, with all
micromirrors in the ON state
UNIT
degrees
12
Micromirror crossover time(9)
Micromirror switching time at 400 MHz with
global reset(10)
MAX
0
(5)
See Figure 13
NOM
0
44
45
46
micromirrors
degrees
68%
(1) Measured relative to the plane formed by the overall micromirror array.
(2) “Parking” the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed
by the overall micromirror array).
(3) When the micromirror array is “parked”, the tilt angle of each individual micromirror is uncontrolled.
(4) Additional variation exists between the micromirror array and the package datums, as shown in the Mechanical, Packaging, and
Orderable Information.
(5) When the micromirror array is “landed”, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS
memory cell associated with each individual micromirror. A binary value of “1” will result in a micromirror “landing” in an nominal angular
position of “+12°”. A binary value of 0 results in a micromirror “landing” in an nominal angular position of “-12°”.
(6) Represents the “landed” tilt angle variation relative to the Nominal “landed” tilt angle.
(7) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(8) For some applications, it is critical to account for the micromirror tilt angle variation in the overall System Optical Design. With some
System Optical Designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some System Optical Designs, the micromirror tilt angle variation between devices may result
in colorimetry variations and/or system contrast variations.
(9) Micromirror Cross Over time is primarily a function of the natural response time of the micromirrors.
(10) Micromirror switching is controlled and coordinated by the DLPC410 (DLPS024) and DLPA200 (DLPS015). Nominal Switching time
depends on the system implementation and represents the time for the entire micromirror array to be refreshed.
(11) Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the -12° position to +12° or vice versa.
(12) Measured relative to the package datums “B” and “C”, shown in Mechanical, Packaging, and Orderable Information.
(13) The minimum or maximum DMD optical efficiency observed depends on numerous application-specific design variables, such as:
– Illumination wavelength, bandwidth/line-width, degree of coherence
– Illumination angle, plus angle tolerance
– Illumination and projection aperture size, and location in the system optical path
– IIlumination overfill of the DMD micromirror array
– Aberrations present in the illumination source and/or path
– Aberrations present in the projection path
The specified nominal DMD optical efficiency is based on the following use conditions:
– Visible illumination (400 nm – 700 nm)
– Input illumination optical axis oriented at 24° relative to the window normal
– Projection optical axis oriented at 0° relative to the window normal
– f/3.0 illumination aperture
– f/2.4 projection aperture
Based on these use conditions, the nominal DMD optical efficiency results from the following four components:
– Micromirror array fill factor: nominally 92%
– Micromirror array diffraction efficiency: nominally 86%
– Micromirror surface reflectivity: nominally 88%
20
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
– Window transmission: nominally 97% (single pass, through two surface transitions)
(14) Does not account for the effect of micromirror switching duty cycle, which is application dependent. Micromirror switching duty cycle
represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection
path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate.
7.13 Window Characteristics
PARAMETER (1)
CONDITIONS
Window material designation
Corning 7056
Window refractive index
at wavelength 589 nm
Window flatness (2)
Per 25 mm
Within the Window Aperture
Window aperture
See
Illumination overfill
Refer to Illumination Overfill
(1)
(2)
(3)
(4)
(5)
TYP
MAX
UNIT
1.487
4
Window artifact size
Window transmittance, single–pass
through both surfaces and glass (5)
MIN
(3)
400
fringes
µm
(4)
At wavelength 405 nm. Applies to 0° and 24° AOI only.
95%
Minimum within the wavelength range 420 nm to 680 nm.
Applies to all angles 0° to 30° AOI.
97%
Average over the wavelength range 420 nm to 680 nm.
Applies to all angles 30° to 45° AOI.
97%
See Window Characteristics and Optics for more information.
At a wavelength of 632.8 nm.
See the Mechanical, Packaging, and Orderable Information section at the end of this document for details regarding the size and
location of the window aperture.
For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical
ICD in the Mechanical, Packaging, and Orderable Information.
See the TI application report DLPA031, Wavelength Transmittance Considerations for DLP DMD Window.
7.14 Chipset Component Usage Specification
The DLP7000 is a component of one or more DLP chipsets. Reliable function and operation of the DLP7000
requires that it be used in conjunction with the other components of the applicable DLP chipset, including those
components that contain or implement TI DMD control technology. TI DMD control technology is the TI
technology and devices for operating or controlling a DLP DMD.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
21
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
8 Detailed Description
8.1 Overview
Optically, the DLP7000 consists of 786,432 highly reflective, digitally switchable, micrometer-sized mirrors
(“micromirrors”), organized in a two-dimensional array of 1024 micromirror columns by 768 micromirror rows
(Figure 12). Each aluminum micromirror is approximately 13.68 microns in size (see the “Micromirror Pitch” in
Figure 12), and is switchable between two discrete angular positions: –12° and +12°. The angular positions are
measured relative to a 0° “flat state”, which is parallel to the array plane (see Figure 13). The tilt direction is
perpendicular to the hinge-axis which is positioned diagonally relative to the overall array. The “On State” landed
position is directed towards “Row 0, Column 0” (upper left) corner of the device package (see the “Micromirror
Hinge-Axis Orientation” in Figure 12). In the field of visual displays, the 1024 by 768 “pixel” resolution is referred
to as "XGA".
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a
specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell
contents, after the micromirror "clocking pulse" is applied. The angular position (–12° or +12°) of the individual
micromirrors changes synchronously with a micromirror “clocking pulse”, rather than being synchronous with the
CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a micromirror
"clocking pulse" will result in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a
memory cell followed by a micromirror "clocking pulse" will result in the corresponding micromirror switching to a
–12° position.
Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the
CMOS memory. Second, application of a Micromirror Clocking Pulse to all or a portion of the micromirror array
(depending upon the configuration of the system). Micromirror Clocking Pulses are generated externally by a
DLPA200, with application of the pulses being coordinated by the DLPC410 controller.
Around the perimeter of the 1024 by 768 array of micromirrors is a uniform band of “border” micromirrors. The
border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has
been applied to the device. There are 10 border micromirrors on each side of the 1024 by 768 active array.
Figure 8 shows a DLPC410 and DLP7000 Chipset Block Diagram. The DLPC410 and DLPA200 control and
coordinate the data loading and micromirror switching for reliable DLP7000 operation. The DLPR410 is the
programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset
components, see Application and Implementation. For a typical system application using the DLP Discovery 4100
chipset including the DLP7000, see Figure 19.
8.2 Functional Block Diagram
Figure 8 is a simplified system block diagram showing the use of the following components:
22
● DLPC410
– Xilinx [XC5VLX30] FPGA configured to provide high-speed DMD data and
control, and DLPA200 timing and control
● DLPR410
– [XCF16PFSG48C] serial flash PROM contains startup configuration information
(EEPROM)
● DLPA200
– DMD micromirror driver for the DLP7000 DMD
● DLP7000
– Spatial Light Modulator (DMD)
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
Figure 8. DLPC410 and DLP7000 Chipset Block Diagram
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
23
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
8.3 Feature Description
8.3.1 Discovery 4100 Chipset DMD FeaturesWa
Table 1. DLP7000 Overview
DMD
ARRAY
PATTERNS/s
DATA RATE (Gbps)
MIRROR PITCH
DLP7000 - 0.7”XGA
1024 x 768
32552
25.6
13.6 μm
8.3.1.1 DLPC410 Controller
The DLP7000 chipset includes the DLPC410 controller which provides a high-speed LVDS data and control
interface for DMD control. This interface is also connected to a second FPGA used to drive applications (not
included in the chipset). The DLPC410 generates DMD and DLPA200 initialization and control signals in
response to the inputs on the control interface.
For more information, see the DLPC410 data sheet DLPS024.
8.3.1.2 DLPA200 DMD Micromirror Driver
DLPA200 micromirror driver provides the micromirror clocking pulse driver functions for the DMD. One DLPA200
is required for DLP7000.
For more information on the DLPA200, see the DLPA200 data sheet DLPS015.
8.3.1.3 Flash Configuration PROM
The DLPC410 is configured at startup from the serial flash PROM. The contents of this PROM can not be
altered. For more information, see the DLPC410 data sheet DLPS024 and DLPR410 data sheet DLPS027.
8.3.1.4 DMD
8.3.1.4.1 DLP7000 XGA Chip Set Interfaces
This section will describe the interface between the different components included in the chipset. For more
information on component interfacing, see Application and Implementation.
8.3.1.4.1.1 DLPC410 Interface Description
8.3.1.4.1.1.1 DLPC410 IO
Table 2 describes the inputs and outputs of the DLPC410 to the user. For more details on these signals, see the
DLPC410 data sheet (DLPS024).
Table 2. Input/Output Description
PIN NAME
DESCRIPTION
I/O
ARST
Asynchronous active low reset
I
CLKIN_R
Reference clock, 50 MHz
I
DIN_[A,B,C,D](15:0)
LVDS DDR input for data bus A,B,C,D (15:0)
I
DCLKIN[A,B,C,D]
LVDS inputs for data clock (200 - 400 MHz) on bus A, B, C, and D
I
DVALID[A,B,C,D]
LVDS input used to start write sequence for bus A, B, C, and D
I
ROWMD(1:0)
DMD row address and row counter control
I
ROWAD(10:0)
DMD row address pointer
I
BLK_AD(3:0)
DMD mirror block address pointer
I
BLK_MD(1:0)
DMD mirror block reset and clear command modes
I
PWR_FLOAT
Used to float DMD mirrors before complete loss of power
I
DMD_TYPE(3:0)
DMD type in use
O
RST_ACTIVE
Indicates DMD mirror reset in progress
O
INIT_ACTIVE
Initialization in progress.
O
VLED0
System “heartbeat” signal
O
24
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
Table 2. Input/Output Description (continued)
PIN NAME
VLED1
DESCRIPTION
I/O
Denotes initialization complete
O
8.3.1.4.1.1.2 Initialization
The INIT_ACTIVE (Table 2) signal indicates that the DLP7000, DLPA200, and DLPC410 are in an initialization
state after power is applied. During this initialization period, the DLPC410 is initializing the DLP7000 and
DLPA200 by setting all internal registers to their correct states. When this signal goes low, the system has
completed initialization. System initialization takes approximately 220 ms to complete. Data and command write
cycles should not be asserted during the initialization.
During initialization the user must send a training pattern to the DLPC410 on all data and DVALID lines to
correctly align the data inputs to the data clock. For more information about the interface training pattern, see the
DLPC410 data sheet (DLPS024).
8.3.1.4.1.1.3 DMD Device Detection
The DLPC410 automatically detects the DMD type and device ID. DMD_TYPE (Table 2) is an output from the
DLPC410 that contains the DMD information. Only DMDs sold with the chipset or kit are recognized by the
automatic detection function. All other DMDs do not operate with the DLPC410.
8.3.1.4.1.1.4 Power Down
To ensure long term reliability of the DLP7000, a shutdown procedure must be executed. Prior to power removal,
assert the PWR_FLOAT (Table 2) signal and allow approximately 300 µs for the procedure to complete. This
procedure assures the mirrors are in a flat state.
8.3.1.4.2 DLPC410 to DMD Interface
8.3.1.4.2.1 DLPC410 to DMD IO Description
Table 3 lists the available controls and status pin names and their corresponding signal type, along with a brief
functional description.
Table 3. DLPC410 to DMD I/O Pin Descriptions
PIN NAME
DESCRIPTION
I/O
DDC_DOUT_[A,B,C,D](15:0)
LVDS DDR output to DMD data bus A,B,C,D (15:0)
O
DDC_DCLKOUT_[A,B,C,D]
LVDS output to DMD data clock A,B,C,D
O
DDC_SCTRL_[A,B,C,D]
LVDS DDR output to DMD data control A,B,C,D
O
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
25
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
8.3.1.4.2.2 Data Flow
Figure 9 shows the data traffic through the DLPC410. Special considerations are necessary when laying out the
DLPC410 to allow best signal flow.
LVDS BUS A
sDIN_A(15:0)
sDCLK_A
sDVALID_A
LVDS BUS B
sDIN_B(15:0)
sDCLK_B
sDVALID_B
LVDS BUS D
LVDS BUS C
sDIN_D(15:0)
sDCLK_D
sDVALID_D
sDIN_C(15:0)
sDCLK_C
sDVALID_C
DLPC410
LVDS BUS A
LVDS BUS D
sDOUT_A(15:0)
sDCLKOUT_A
sSCTRL_A
sDOUT_D(15:0)
sDCLKOUT_D
sSCTRL_D
LVDS BUS C
sDOUT_C(15:0)
sDCLKOUT_C
sSCTRL_C
LVDS BUS B
sDIN_B(15:0)
sDCLK_B
sDVALID_B
Figure 9. DLPC410 Data Flow
Two LVDS buses transfer the data from the user to the DLPC410. Each bus has its data clock that is input edge
aligned with the data (DCLK). Each bus also has its own validation signal that qualifies the data input to the
DLPC410 (DVALID).
Output LVDS buses transfer data from the DLPC410 to the DLP7000. Output buses LVDS A and LVDS B are
used as highlighted in Figure 9.
8.3.1.4.3 DLPC410 to DLPA200 Interface
8.3.1.4.3.1 DLPA200 Operation
The DLPA200 DMD Micromirror Driver is a mixed-signal Application Specific Integrated Circuit (ASIC) that
combines the necessary high-voltage power supply generation and Micromirror Clocking Pulse functions for a
family of DMDs. The DLPA200 is programmable and controllable to meet all current and anticipated DMD
requirements.
The DLPA200 operates from a 12-V power supply input. For more detailed information on the DLPA200, see the
DLPA200 data sheet.
8.3.1.4.3.2 DLPC410 to DLPA200 IO Description
The Serial Communications Port (SCP) is a full duplex, synchronous, character-oriented (byte) port that allows
exchange of commands from the DLPC410 to the DLPA200. One SCP bus is used for the DLP7000.
26
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
DLPA200
SCP bus
DLPC410
SCP bus
DLPA200
(Only with 1080p DMD)
Figure 10. Serial Port System Configuration
There are five signal lines associated with the SCP bus: SCPEN, SCPCK, SCPDI, SCPDO, and IRQ .
Table 4 lists the available controls and status pin names and their corresponding signal type, along with a brief
functional description.
Table 4. DLPC410 to DLPA200 I/O Pin Descriptions
PIN NAME
DESCRIPTION
I/O
A_SCPEN
Active low chip select for DLPA200 serial bus
O
A_STROBE
DLPA200 control signal strobe
O
A_MODE(1:0)
DLPA200 mode control
O
A_SEL(1:0)
DLPA200 select control
O
A_ADDR(3:0)
DLPA200 address control
O
B_SCPEN
Active low chip select for DLPA200 serial bus (2)
O
B_STROBE
DLPA200 control signal strobe (2)
O
B_MODE(1:0)
DLPA200 mode control
O
B_SEL(1:0)
DLPA200 select control
O
B_ADDR(3:0)
DLPA200 address control
O
The DLPA200 provides a variety of output options to the DMD by selecting logic control inputs: MODE[1:0],
SEL[1:0] and reset group address A[3:0] (Table 4). The MODE[1:0] input determines whether a single output, two
outputs, four outputs, or all outputs, will be selected. Output levels (VBIAS, VOFFSET, or VRESET) are selected
by SEL[1:0] pins. Selected outputs are tri-stated on the rising edge of the STROBE signal and latched to the
selected voltage level after a break-before-make delay. Outputs will remain latched at the last Micromirror
Clocking Pulse waveform level until the next Micromirror Clocking Pulse waveform cycle.
8.3.1.4.4 DLPA200 to DLP7000 Interface
8.3.1.4.4.1 DLPA200 to DLP7000 Interface Overview
The DLPA200 generates three voltages: VBIAS, VRESET, and VOFFSET that are supplied to the DMD MBRST
lines in various sequences through the Micromirror Clocking Pulse driver function. VOFFSET is also supplied
directly to the DMD as DMDVCC2. A fourth DMD power supply, DMDVCC, is supplied directly to the DMD by
regulators.
The function of the Micromirror Clocking Pulse driver is to switch selected outputs in patterns between the three
voltage levels (VBIAS, VRESET and VOFFSET) to generate one of several Micromirror Clocking Pulse
waveforms. The order of these Micromirror Clocking Pulse waveform events is controlled externally by the logic
control inputs and timed by the STROBE signal. DLPC410 automatically detects the DMD type and then uses the
DMD type to determine the appropriate Micromirror Clocking Pulse waveform.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
27
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
A direct Micromirror Clocking Pulse operation causes a mirror to transition directly from one latched state to the
next. The address must already be set up on the mirror electrodes when the Micromirror Clocking Pulse is
initiated. Where the desired mirror display period does not allow for time to set up the address, a Micromirror
Clocking Pulse with release can be performed. This operation allows the mirror to go to a relaxed state
regardless of the address while a new address is set up, after which the mirror can be driven to a new latched
state.
A mirror in the relaxed state typically reflects light into a system collection aperture and can be thought of as “off”
although the light is likely to be more than a mirror latched in the “off” state. System designers should carefully
evaluate the impact of relaxed mirror conditions on optical performance.
8.3.1.5 Measurement Conditions
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 11 shows an equivalent test load circuit for the
output under test. The load capacitance value stated is only for characterization and measurement of AC timing
signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All rise
and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH
MIN for output clocks.
LOAD CIRCUIT
RL
From Output
Under Test
Tester
Channel
CL = 50 pF
CL = 5 pF for Disable Time
Figure 11. Test Load Circuit for AC Timing Measurements
28
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
Incident
Illumination
Package Pin
A1 Corner
Details Omitted For Clarity.
Not To Scale.
DMD
Micromirror
Array
0
(Border micromirrors eliminated for clarity)
M±1
Active Micromirror Array
0
N±1
Micromirror Hinge-Axis Orientation
Micromirror Pitch
³2Q-6WDWH´
Tilt Direction
45°
P (um)
P (um)
P (um)
³2II-6WDWH´
Tilt Direction
P (um)
Figure 12. DMD Micromirror Array, Pitch, and Hinge-Axis Orientation
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
29
DLP7000
www.ti.com
Ill Inc
um id
in en
at t
io
n
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
Package Pin
A1 Corner
Ill Inc
um id
in en
at t
io
n
DLP7000
Two
“On-State”
Micromirrors
Two
“Off-State”
Micromirrors
h
Pat
nt
ide ht
Inc n-Lig
tio
ina
Projected-Light
Path
m
Illu
th
nt t Pa
ide gh
Inc on-Li
ati
m in
Illu
For Reference
t
gh
Li
et
a h
St at
ff- P
Flat-State
( “parked” )
Micromirror Position
O
a±b
-a ± b
Silicon Substrate
“On-State”
Micromirror
Silicon Substrate
“Off-State”
Micromirror
Figure 13. Micromirror Landed Positions and Light Paths
30
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
8.4 Device Functional Modes
8.4.1 DMD Operation
The DLP7000 has only one functional mode, it is set to be highly optimized for low latency and high speed in
generating mirror clocking pulses and timings.
When operated with the DLPC410 controller in conjunction with the DLPA200 driver, the DLP7000 can be
operated in several display modes. The DLP7000 is loaded as 16 blocks of 48 rows each. Figure 14, Figure 15,
Figure 16, and Figure 17 show how the image is loaded by the different Micromirror Clocking Pulse modes.
There are four Micromirror Clocking Pulse modes that determine which blocks are "reset" when a Micromirror
Clocking Pulse command is issued:
• Single block mode
• Dual block mode
• Quad block mode
• Global mode
8.4.1.1 Single Block Mode
In single block mode, a single block can be loaded and reset in any order. After a block is loaded, it can be reset
to transfer the information to the mechanical state of the mirrors.
Reset
Data Loaded
1 6 Re se t Line s
(0 – 15 )
Figure 14. Single Block Mode Diagram
8.4.1.2 Dual Block Mode
In dual block mode, reset blocks are paired together as follows (0-1), (2-3), (4-5) . . . (14-15). These pairs can be
reset in any order. After data is loaded a pair can be reset to transfer the information to the mechanical state of
the mirrors.
Reset
Data Loaded
1 6 Re se t Line s
(0 – 15 )
Figure 15. Dual Block Mode Diagram
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
31
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
Device Functional Modes (continued)
8.4.1.3 Quad Block Mode
In quad block mode, reset blocks are grouped together in fours as follows (0-3), (4-7), (8-11) and (12-15). Each
quad group can be randomly addressed and reset. After a quad group is loaded, it can be reset to transfer the
information to the mechanical state of the mirrors.
1 6 Re se t Line s
(0 – 15 )
Data Loaded
Reset
Figure 16. Quad Block Mode Diagram
8.4.1.4 Global Mode
In global mode, all reset blocks are grouped into a single group and reset together. The entire DMD must be
loaded with the desired data before issuing a Global Reset to transfer the information to the mechanical state of
the mirrors.
1 6 Re se t Line s
(0 – 15 )
Data Loaded
Reset
Figure 17. Global Mode Diagram
32
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
8.5 Window Characteristics and Optics
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously.
8.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
8.5.2 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light
path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other
system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt
angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination
numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
8.5.3 Pupil Match
TI recommends the exit pupil of the illumination is nominally centered within 2° of the entrance pupil of the
projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border and/or active
area, which may require additional system apertures to control, especially if the numerical aperture of the system
exceeds the pixel tilt angle.
8.5.4 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical
operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the
window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical
system should be designed to limit light flux incident anywhere on the window aperture from exceeding
approximately 10% of the average flux level in the active area. Depending on the particular system’s optical
architecture, overfill light may have to be further reduced below the suggested 10% level in order to be
acceptable.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
33
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
8.6 Micromirror Array Temperature Calculation
Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the
maximum temperature of any individual micromirror in the active array, the maximum temperature of the window
aperture, and the temperature gradient between case temperature and the predicted micromirror array
temperature. (see Figure 18).
See the Recommended Operating Conditions for applicable temperature limits.
8.6.1 Package Thermal Resistance
The DMD is designed to conduct absorbed and dissipated heat to the back of the Type A package where it can
be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the
package within the specified operational temperatures, refer to Figure 18. The total heat load on the DMD is
typically driven by the incident light absorbed by the active area; although other contributions include light energy
absorbed by the window aperture and electrical power dissipation of the array.
8.6.2 Case Temperature
The temperature of the DMD case can be measured directly. For consistency, a Thermal Test Point locations 1
and 2 are defined, as shown in Figure 18.
INCIDENT
LIGHT
A
A
1
2
1
ARRAY
2
1
3X (15.88 [.625])
3
2
3
(10.16 [.400])
Figure 18. Thermal Test Point Location
34
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
Micromirror Array Temperature Calculation (continued)
8.6.3 Micromirror Array Temperature Calculation
Micromirror array temperature cannot be measured directly; therefore, it must be computed analytically from
measurement points (Figure 18), the package thermal resistance, the electrical power, and the illumination heat
load. The relationship between micromirror array temperature and the case temperature are provided by
Equation 1 and Equation 2:
TArray = T Ceramic + (QArray x RArray-To-Ceramic)
(1)
QArray = QELE + QILL
Where the following elements are defined as:
•
•
•
•
•
•
TArray = computed micromirror array temperature (°C)
TCeramic = Ceramic temperature (°C) (TC2 Location Figure 18)
QArray = Total DMD array power (electrical + absorbed) (measured in Watts)
RArray-To-Ceramic = thermal resistance of DMD package from array to TC2 (°C/W) (see Package Thermal
Resistance)
QELE = Nominal electrical power (W)
QILL = Absorbed illumination energy (W)
(2)
An example calculation is provided below based on a traditional DLP Video projection system. The electrical
power dissipation of the DMD is variable and depends on the voltages, data rates, and operating frequencies.
The nominal electrical power dissipation to be used in the calculation is 2 Watts. Thus, QELE = 2 Watts. The
absorbed power from the illumination source is variable and depends on the operating state of the mirrors and
the intensity of the light source. Based on modeling and measured data from DLP projection system
QILL = CL2W x SL.
where
•
•
•
•
•
•
CL2W is a Lumens to Watts constant, and can be estimated at 0.00274 W/lm
SL = Screen Lumens nominally measured to be 2000 lm
Qarray = 2.0 + (0.00274 x 2000) = 7.48 W, Estimated total power on micromirror Array
TCeramic = 55°C, assumed system measurement
Finally, TArray (micromirror active array temperature) is
TArray = 55°C + (7.48 W x 0.9°C/W) = 61.7°C
(3)
8.7 Micromirror Landed-On/Landed-Off Duty Cycle
8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the On–state versus the amount of time the same
micromirror is landed in the Off–state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the
time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of
the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)
always add to 100.
8.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
35
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
Micromirror Landed-On/Landed-Off Duty Cycle (continued)
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
8.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this
interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s
usable life. This is quantified in the de-rating curve shown in Figure 1. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
• All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at
for a give long-term average Landed Duty Cycle.
8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the
pixel will experience a 0/100 Landed Duty Cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 5.
Table 5. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
0/100
10%
10/90
20%
20/80
30%
30/70
40%
40/60
50%
50/50
60%
60/40
70%
70/30
80%
80/20
90%
90/10
100%
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given
primary must be displayed in order to achieve the desired white point.
During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_%
× Blue_Scale_Value)
where
•
36
Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red,
Green, and Blue are displayed (respectively) to achieve the desired white point.
(4)
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,
blue color intensities would be as shown in Table 6.
Table 6. Example Landed Duty Cycle for Full-Color
RED CYCLE PERCENTAGE
50%
GREEN CYCLE PERCENTAGE
20%
BLUE CYCLE PERCENTAGE
30%
RED SCALE VALUE
GREEN SCALE VALUE
BLUE SCALE VALUE
0%
0%
0%
0/100
100%
0%
0%
50/50
0%
100%
0%
20/80
0%
0%
100%
30/70
12%
0%
0%
6/94
0%
35%
0%
7/93
0%
0%
60%
18/82
100%
100%
0%
70/30
LANDED DUTY CYCLE
0%
100%
100%
50/50
100%
0%
100%
80/20
12%
35%
0%
13/87
0%
35%
60%
25/75
12%
0%
60%
24/76
100%
100%
100%
100/0
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
37
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DLP7000 devices require they be coupled with the DLPC410 controller to provide a reliable solution for
many different applications. The DMDs are spatial light modulators which reflect incoming light from an
illumination source to one of two directions, with the primary direction being into a projection collection optic.
Each application is derived primarily from the optical architecture of the system and the format of the data
coming into the DLPC410. Applications of interest include 3D measurement systems, lithography, medical
systems, and compressive sensing.
9.1.1 Device Description
The DLP7000 XGA chipset offers developers a convenient way to design a wide variety of industrial, medical,
telecom and advanced display applications by delivering maximum flexibility in formatting data, sequencing data,
and light patterns.
The DLP7000 XGA chipset includes the following four components: DMD Digital Controller (DLPC410),
EEPROM (DLPR410), DMD Micromirror Driver (DLPA200), and a DMD (DLP7000).
DLPC410 DMD Digital Controller
• Provides high speed LVDS data and control interface to the DLP7000.
• Drives mirror clocking pulse and timing information to the DLPA200.
• Supports random row addressing.
DLPR410 EEPROM
• Contains startup configuration information for the DLPC410.
DLPA200 DMD Micromirror Driver
• Generates Micromirror Clocking Pulse control (sometimes referred to as a "Reset") of DMD mirrors.
DLP7000: Digital Micromirror Device
• Steers light in two digital positions (+12º and -12º) using 1024 x 768 micromirror array of aluminum
mirrors.
Table 7. DLP Discovery 4100 Chipset Configuration for 0.7 XGA Chipset
QUANTITY
TI PART
DESCRIPTION
1
DLP7000
0.7 XGA Type A DMD (digital micromirror device)
1
DLPC410
DLP Discovery 4100 DMD controller
1
DLPR410
DLP Discovery 4100 configuration PROM
1
DLPA200
DMD micromirror driver
Reliable function and operation of DLP7000 XGA chipsets require the components be used in conjunction with
each other. This document describes the proper integration and use of the DLP7000 XGA chipset components.
The DLP7000 XGA chipset can be combined with a user programmable Application FPGA (not included) to
create high performance systems.
38
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
9.2 Typical Application
A typical embedded system application using the DLPC410 controller and DLP7000 is shown in Figure 19. In this configuration, the DLPC410 controller
supports input from an FPGA. The FPGA sends low-level data to the controller, enabling the system to be highly optimized for low latency and high
speed.
Figure 19. DLPC410 and DLP7000 Embedded Example Block Diagram
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
39
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
9.2.1 Design Requirements
All applications using the DLP7000 XGA chipset require both the controller and the DMD components for
operation. The system also requires an external parallel flash memory device loaded with the DLPC410
Configuration and Support Firmware. The chipset has several system interfaces and requires some support
circuitry. The following interfaces and support circuitry are required:
• DLPC410 System Interfaces:
– Control Interface
– Trigger Interface
– Input Data Interface
– Illumination Interface
– Reference Clock
• DLP7000 Interfaces:
– DLPC410 to DLP7000 Digital Data
– DLPC410 to DLP7000 Control Interface
– DLPC410 to DLP7000 Micromirror Reset Control Interface
– DLPC410 to DLPA200 Micromirror Driver
– DLPA200 to DLP7000 Micromirror Reset
9.2.2 Detailed Design Procedure
The DLP7000 DMD is well suited for visible light applications requiring fast, spatially programmable light patterns
using the micromirror array. See the Functional Block Diagram to see the connections between the DLP7000
DMD, the DLPC410 digital controller, the DLPR410 EEPROM, and the DLPA200 DMD micromirror drivers. See
the Figure 19 for an application example. Follow the Layout Guidelines for reliability.
40
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
10 Power Supply Recommendations
10.1 DMD Power-Up and Power-Down Procedures
Repeated failure to adhere to the prescribed power-up and power-down procedures may affect device reliability.
The DLP7000 power-up and power-down procedures are defined by the DLPC410 data sheet (DLPS024) and
the DLP Discovery Chipset data sheet (DLPU008). These procedures must be followed to ensure reliable
operation of the device.
11 Layout
11.1 Layout Guidelines
The DLP7000 is part of a chipset that is controlled by the DLPC410 in conjunction with the DLPA200. These
guidelines are targeted at designing a PCB board with these components.
A target impedance of 50 Ω for single ended signals and 100 Ω between LVDS signals is specified for all signal
layers.
11.1.1 Impedance Requirements
Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs
(DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn), which should be matched to 100 Ω ±10% across
each pair.
11.1.2 PCB Signal Routing
When designing a PCB for the DLP7000 controlled by the DLPC410 in conjunction with the DLPA200, the
following are recommended:
Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces
routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2
Memory, DMD (LVDS signals), then DLPA200 signals.
TI does not recommend signal routing on power or ground planes.
TI does not recommend ground plane slots.
High speed signal traces should not cross over slots in adjacent power and/or ground planes.
Table 8. Important Signal Trace Constraints
SIGNAL
CONSTRAINTS
LVDS (DMD_DAT_xnn,
DMD_DCKL_xn, and
DMD_SCTRL_xn)
P-to-N data, clock, and SCTRL: <10 mils (0.25 mm); Pair-to-pair <10 mils (0.25 mm); Bundle-to-bundle
<2000 mils (50 mm, for example DMD_DAT_Ann to DMD_DAT_Bnn)
Trace width: 4 mil (0.1 mm)
Trace spacing: In ball field – 4 mil (0.11 mm); PCB etch – 14 mil (0.36 mm)
Maximum recommended trace length <6 inches (150 mm)
Table 9. Power Trace Widths and Spacing
SIGNAL NAME
MINIMUM TRACE
WIDTH
MINIMUM TRACE
SPACING
GND
Maximize
5 mil (0.13 mm)
VCC, VCC2
20 mil (0.51 mm)
10 mil (0.25 mm)
MBRST[15:0]
11 mil (0.23 mm)
15 mil (0.38 mm)
LAYOUT REQUIREMENTS
Maximize trace width to connecting pin as a minimum
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
41
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
11.1.3 Fiducials
Fiducials for automatic component insertion should be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials
for optical auto insertion are placed on three corners of both sides of the PCB.
11.1.4 DMD Interface
The digital interface from the DLPC410 to the DMD are LVDS signals that run at clock rates up to 400 MHz. Data
is clocked into the DMD on both the rising and falling edge of the clock, so the data rate is 800 MHz. The LVDS
signals should have 100 Ω differential impedance. The differential signals should be matched but kept as short
as possible. Parallel termination at the LVDS receiver is in the DMD; therefore, on board termination is not
necessary.
11.1.4.1 Trace Length Matching
The DLPC410 DMD data signals require precise length matching. Differential signals should have impedance of
100Ω (with 5% tolerance). It is important that the propagation delays are matched. The maximum differential pair
uncoupled length is 100 mils with a relative propagation delay of ±25 mil between the p and n. Matching all
signals exactly will maximize the channel margin. The signal path through all boards, flex cables and internal
DMD routing must be considered in this calculation.
11.1.5 DLP7000 Decoupling
General decoupling capacitors for the DLP7000 should be distributed around the PCB and placed to minimize
the distance from IC voltage and ground pads. Each decoupling capacitor (0.1 µF recommended) should have
vias directly to the ground and power planes. Via sharing between components (discreet or integrated) is
discouraged. The power and ground pads of the DLP7000 should be tied to the voltage and ground planes with
their own vias.
11.1.5.1 Decoupling Capacitors
Decoupling capacitors should be placed to minimize the distance from the decoupling capacitor to the supply and
ground pin of the component. It is recommended that the placement of and routing for the decoupling capacitors
meet the following guidelines:
• The supply voltage pin of the capacitor should be located close to the device supply voltage pin(s). The
decoupling capacitor should have vias to ground and voltage planes. The device can be connected directly to
the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component should be
tied to the voltage or ground plane through separate vias.
• The trace lengths of the voltage and ground connections for decoupling capacitors and components should
be less than 0.1 inch to minimize inductance.
• The trace width of the power and ground connection to decoupling capacitors and components should be as
wide as possible to minimize inductance.
• Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance
and improve noise performance.
• Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.
11.1.6 VCC and VCC2
The VCC pins of the DMD should be connected directly to the DMD VCC plane. Decoupling for the VCC should
be distributed around the DMD and placed to minimize the distance from the voltage and ground pads. Each
decoupling capacitor should have vias directly connected to the ground and power planes. The VCC and GND
pads of the DMD should be tied to the VCC and ground planes with their own vias.
The VCC2 voltage can be routed to the DMD as a trace. Decoupling capacitors should be placed to minimize the
distance from the DMD’s VCC2 and ground pads. Using wide etch from the decoupling capacitors to the DMD
connection will reduce inductance and improve decoupling performance.
11.1.7 DMD Layout
See the respective sections in this data sheet for package dimensions, timing and pin out information.
42
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
11.1.8 DLPA200
The DLPA200 generates the micromirror clocking pulses for the DMD. The DMD-drive outputs from the
DLPA200 (MBRST[15:0] should be routed with minimum trace width of 11 mil and a minimum spacing of 15 mil.
The VCC and VCC2 traces from the output capacitors to the DLPA200 should also be routed with a minimum
trace width and spacing of 11 mil and 15 mil, respectively. See the DLPA200 customer data sheet for mechanical
package and layout information.
11.2 Layout Example
For LVDS (and other differential signal) pairs and groups, it is important to match trace lengths. In the area of the
dashed lines, Figure 20 shows correct matching of signal pair lengths with serpentine sections to maintain the
correct impedance.
Figure 20. Mitering LVDS Traces to Match Lengths
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
43
DLP7000
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
Figure 21 provides a legend of reading the complete device name for any DLP device.
Figure 21. Device Nomenclature
12.1.1.1 Device Marking
The device marking consists of the fields shown in Figure 22.
Figure 22. Device Marking
44
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
DLP7000
www.ti.com
DLPS026D – AUGUST 2012 – REVISED NOVEMBER 2015
12.2 Documentation Support
12.2.1 Related Documents
The following documents contain additional information related to the use of the DLP7000 device:
• DLP Discovery 4100 Chipset data sheet, DLPU008
• DLPC410 Digital Controller data sheet, DLPS024
• DLPA200 DMD Micromirror Driver data sheet, DLPS015
• DLPR410 EEPROM data sheet, DLPS027
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 10. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DLP7000
Click here
Click here
Click here
Click here
Click here
DLPA200
Click here
Click here
Click here
Click here
Click here
DLPC410
Click here
Click here
Click here
Click here
Click here
12.4 Trademarks
Discovery is a trademark of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DLP7000
45
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
DLP7000BFLP
ACTIVE
LCCC
FLP
203
3
Green (RoHS
& no Sb/Br)
W NIPDAU
N / A for Pkg Type
DLP7000FLP
LIFEBUY
LCCC
FLP
203
3
Green (RoHS
& no Sb/Br)
W NIAU
N / A for Pkg Type
Op Temp (°C)
Device Marking
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jan-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated