NB3W800L 3.3 V 100/133 MHz Differential 1:8 HCSLCompatible Push-Pull Clock ZDB/Fanout Buffer for PCIe) www.onsemi.com Description The NB3W800L is a low−power 8−output differential buffer that meets all the performance requirements of the DB800ZL specification. The NB3W800L is capable of distributing the reference clocks for Intel ® QuickPath Interconnect (Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. A fixed, internal feedback path maintains low drift for critical QPI applications. MARKING DIAGRAM 1 NB3W800L AWLYYWWG 1 48 CASE 485DP Features • • • • • • • • • • • • • • • 8 Differential Clock Output Pairs @ 0.7 V Low−power NMOS Push−pull HCSL Compatible Outputs Cycle−to−cycle Jitter <50 ps Output−to−output Skew <50 ps Input−to−output Delay Variation <100 ps PCIe Gen3 Phase Jitter <1.0 ps RMS QPI 9.6GT/s 12UI Phase Jitter <0.2 ps RMS Pseudo−External Fixed Feedback for Lowest Input−to−output Delay Individual OE Control; Hardware Control of Each Output PLL Configurable for PLL Mode or Bypass Mode (Fanout Operation) 100 MHz or 133 MHz PLL Mode Operation; Supports PCIe and QPI Applications Selectable PLL Bandwidth; Minimizes Jitter Peaking in Downstream PLL’s SMBus Programmable Configurations Spread Spectrum Compatible; Tracks Input Clock Spreading for Low EMI These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2015 August, 2015 − Rev. 1 1 NB3W800L A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Package Shipping† NB3W800LMNG QFN48 (Pb−Free) 490 / Tray NB3W800LMNTXG QFN48 (Pb−Free) 2500 / Tape & Reel NB3W800LMNTWG QFN48 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NB3W800L/D NB3W800L 8 OE[7:0]# FB_OUT FB_OUT# SSC Compatible PLL CLK_IN DIF[7:0] MUX DIF[7:0]# CLK_IN# 100M_133M# HBW_BYP_LBW# Control Logic PWRGD/PWRDN# SDA SCL Figure 1. Simplified Block Diagram Table 1. OE AND POWER PIN TABLE Inputs PWRGD/ PWRDN# OE# Hardware Pins & Control Register Bits CLK_IN/ CLK_IN# SMBUS Enable Bit OE# Pin DIF/DIF# [7:0] 0 X X X 1 Running 0 X 1 1 Outputs FB_OUT/ FB_OUT# PLL State Hi−Z Hi−Z OFF Hi−Z Running ON 0 Running Running ON 1 Hi−Z Running ON Table 2. FUNCTIONALITY AT POWER−UP (PLL MODE) Table 5. PLL OPERATING MODE READBACK TABLE 100M_133M# CLK_IN MHz DIF(7:0) HBW_BYP_LBW# Byte0, bit 7 Byte 0, bit 6 1 100.00 CLK_IN Low (Low BW) 0 0 0 133.33 CLK_IN Mid (Bypass) 0 1 High (High BW) 1 1 Table 3. POWER CONNECTIONS Table 6. TRI−LEVEL INPUT THRESHOLDS Pin Number VDD GND Description 44 49 Analog PLL 3 2 Analog Input 10, 15, 19, 27, 34, 38, 42 49 DIF clocks Level Voltage Low <0.8 V Mid 1.2<Vin<1.8 V High Vin > 2.2 V Table 7. PLL OPERATING MODE Table 4. SMBus ADDRESS HBW_BYP_LBW# Mode Address + Read/Write bit Low PLL Lo BW D8 R Mid Bypass High PLL Hi BW NOTE: www.onsemi.com 2 PLL is OFF in Bypass Mode OE6# VDD DIF7 DIF7# OE7# VDD NC VDDA NC NC 100M_133M# HBW_BYP_LBW# NB3W800L 48 37 36 1 DIF6# PWRGD/PWRDN# GNDA DIF6 VDDR VDD DIF5# CLK_IN CLK_IN# DIF5 Bottom EPAD must be connected to Ground SDA SCL OE5# OE4# FB_OUT_NC# DIF4# FB_OUT_NC DIF4 VDD VDD DIF3# OE0# DIF3 NC 12 25 24 OE3# OE2# DIF2# DIF2 NC VDD OE1# DIF1 DIF1# VDD DIF0 DIF0# 13 Figure 2. Pin Configuration Table 8. PIN DESCRIPTIONS Pin # Pin Name Type Description 1 PWRGD/PWRDN# IN 3.3 V Input notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on subsequent assertions. Low enters Power Down Mode. 2 GNDA GND Ground for Input Receiver and PLL Core 3 VDDR PWR 3.3 V power for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered appropriately. 4 CLK_IN IN 0.7 V Differential true input 5 CLK_IN# IN 0.7 V Differential complementary Input 6 SDA I/O Data pin of SMBus circuitry 7 SCL IN Clock pin of SMBus circuitry 8 FB_OUT_NC# OUT Complementary half of differential feedback output provides feedback signal to the PLL for synchronization with input clock to eliminate phase error. This pin should NOT be connected on the circuit board; the feedback is internal to the package. 9 FB_OUT_NC OUT True half of differential feedback output provides feedback signal to the PLL for synchronization with the input clock to eliminate phase error. This pin should NOT be connected on the circuit board; the feedback is internal to the package. 10 VDD PWR Power supply, nominal 3.3 V 11 OE0# IN Active low input for enabling DIF pair 0. This pin has an internal pull−down. 1 = disable outputs, 0 = enable outputs 12 NC N/A No Connection. 13 DIF0 OUT 0.7 V differential true clock output 14 DIF0# OUT 0.7 V differential complementary clock output 15 VDD PWR Power supply, nominal 3.3 V 16 DIF1 OUT 0.7 V differential true clock output www.onsemi.com 3 NB3W800L Table 8. PIN DESCRIPTIONS Pin # Pin Name Type Description 17 DIF1# OUT 0.7 V differential complementary clock output 18 OE1# IN Active low input for enabling DIF pair 1. This pin has an internal pull−down. 1 =disable outputs, 0 = enable outputs 19 VDD PWR Power supply, nominal 3.3 V 20 NC N/A No Connection. 21 DIF2 OUT 0.7 V differential true clock output 22 DIF2# OUT 0.7 V differential complementary clock output 23 OE2# IN Active low input for enabling DIF pair 2. This pin has an internal pull−down. 1 = disable outputs, 0 = enable outputs 24 OE3# IN Active low input for enabling DIF pair 3. This pin has an internal pull−down. 1 = disable outputs, 0 = enable outputs 25 DIF3 OUT 0.7 V differential true clock output 26 DIF3# OUT 0.7 V differential complementary clock output 27 VDD PWR Power supply, nominal 3.3 V 28 DIF4 OUT 0.7 V differential true clock output 29 DIF4# OUT 0.7 V differential complementary clock output 30 OE4# IN Active low input for enabling DIF pair 4. This pin has an internal pull−down. 1 = disable outputs, 0 = enable outputs 31 OE5# IN Active low input for enabling DIF pair 5. This pin has an internal pull−down. 1 =disable outputs, 0 = enable outputs 32 DIF5 OUT 0.7 V differential true clock output 33 DIF5# OUT 0.7 V differential complementary clock output 34 VDD PWR Power supply, nominal 3.3 V 35 DIF6 OUT 0.7 V differential true clock output 36 DIF6# OUT 0.7 V differential complementary clock output 37 OE6# IN Active low input for enabling DIF pair 6. This pin has an internal pull−down. 1 = disable outputs, 0 = enable outputs 38 VDD PWR Power supply, nominal 3.3 V 39 DIF7 OUT 0.7 V differential true clock output 40 DIF7# OUT 0.7 V differential complementary clock output 41 OE7# IN Active low input for enabling DIF pair 7. This pin has an internal pull−down. 1 = disable outputs, 0 = enable outputs 42 VDD PWR Power supply, nominal 3.3 V 43 NC N/A No Connection. 44 VDDA PWR 3.3 V power for the PLL core. 45 NC N/A No Connection. 46 NC N/A No Connection. 47 100M_133M# IN 3.3 V Input to select operating frequency. See Functionality Table for Definition 48 HBW_BYP_LBW# IN Trilevel input to select High BW, Bypass or Low BW mode. See PLL Operating Mode Table for Details. 49 GND PWR EPAD, must be connected to Ground www.onsemi.com 4 NB3W800L Table 9. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Min Typ Max Units VDD, VDDA 3.3 V Supply Voltage (Notes 1, 2) VDD for core logic and PLL 4.6 V VIL Input Low Voltage (Note 1) VIH Input High Voltage (Note 1) Except for SMBus interface VDD + 0.5 V VIHSMB Input High Voltage (Note 1) SMBus clock and data pins 5.5 V 150 °C 125 °C GND−0.5 Ts Storage Temperature (Note 1) Tj Junction Temperature (Note 1) ESD prot Input ESD protection (Note 1) Human Body Model qJA Thermal Resistance, Junction−to−Ambient Still air qJC Thermal Resistance, Junction−to−Case V −65 2000 V 17 °C/W 7 °C/W Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Guaranteed by design and characterization, not tested in production. 2. Operation under these conditions is neither implied nor guaranteed. Table 10. ELECTRICAL CHARACTERISTICS–CLOCK INPUT PARAMETERS (HCSL−COMPATIBLE) (VDD = VDDA = 3.3 V ±5%, TA = 0°C * 70°C), See Test Loads for Loading Conditions. (Note 5) Symbol Parameter Conditions Min Typ Max Units VIHCLK_IN Input High Voltage - CLK_IN (Note 3) Differential inputs (single−ended measurement) 600 800 1150 mV VILCLK_IN Input Low Voltage - CLK_IN (Note 3) Differential inputs (single−ended measurement) VSS - 300 0 300 mV VCOM Input Common Mode Voltage - CLK_IN (Note 3) Common Mode Input Voltage (Single−ended measurement) 300 1000 mV VSWING Input Amplitude - CLK_IN (Note 3) Peak to Peak (differential) 300 1450 mV dv/dt Input Slew Rate - CLK_IN (Notes 3, 4) Measured differentially 0.35 8 V/ns IIN Input Leakage Current (Note 3) VIN = VDD , VIN = GND −5 5 mA dtin Input Duty Cycle (Note 3) Measurement from differential waveform 45 55 % JDIFIn Input Jitter - Cycle to Cycle (Note 3) Differential Measurement 125 ps Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Guaranteed by design and characterization, not tested in production. 4. Slew rate measured through ±75 mV window centered around differential zero. 5. Test configuration is; Rs = 27 W, 2 pF for 85 W transmission line. www.onsemi.com 5 NB3W800L Table 11. ELECTRICAL CHARACTERISTICS – Input/Supply/Common Parameters (VDD = VDDA = 3.3 V ±5%, TA = 0°C * 70°C), See Test Loads for Loading Conditions. (Note 11) Symbol Parameter Conditions Min Max Units VIH Input High Voltage (Note 6) Single−ended inputs, except SMBus, low threshold and tri−level inputs 2 VDD + 0.3 V VIL Input Low Voltage (Note 6) Single−ended inputs, except SMBus, low threshold and tri−level inputs GND − 0.3 0.8 V IIN Input Current (Note 6) Single−ended inputs, VIN = GND, VIN = VDD −5 5 mA Single−ended inputs VIN = 0 V; Inputs with internal pull−up resistors VIN = VDD; Inputs with internal pull−down resistors −200 200 mA VDD = 3.3 V, Bypass mode 33 150 MHz IINP Fibyp Input Frequency (Note 7) Typ Fipll VDD = 3.3 V, 100 MHz PLL mode 99 100.00 101 MHz Fipll VDD = 3.3 V, 133.33 MHz PLL mode 132.33 133.33 134.33 MHz 7 nH Lpin Pin Inductance (Note 6) CIN Capacitance (Note 6) Logic Inputs, except CLK_IN 1.5 4.5 pF CINCLK_IN CLK_INdifferential clock inputs (Note 9) 1.5 2.7 pF COUT Output pin capacitance 4.5 pF fMODIN Input SS Modulation Frequency (Note 6) Allowable Frequency (Triangular Modulation) 30 33 kHz tLATOE# OE# Latency (Notes 6. 8) DIF start after OE# assertion DIF stop after OE# deassertion 4 8 cycles tDRVPD Tdrive_PD# (Notes 6, 8) DIF output enable after PD# de−assertion 300 ms tF Tfall (Notes 6, 7) Fall time of control inputs 10 ns tR Trise (Notes 6, 7) Rise time of control inputs 10 ns VILSMB SMBus Input Low Voltage (Note 6) 0.8 V VIHSMB SMBus Input High Voltage (Note 6) VDDSMB V VOLSMB SMBus Output Low Voltage (Note 6) @ IPULLUP IPULLUP SMBus Sink Current (Note 6) @ VOL 4 VDDSMB Nominal Bus Voltage (Note 6) 3 V to 5 V ±10% 2.7 tRSMB SCL/SDA Rise Time (Note 6) tFSMB fMAXSMB 2.1 0.4 V mA 5.0 V (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns SCL/SDA Fall Time (Note 6) (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns SMBus Operating Frequency (Notes 6, 10) Maximum SMBus operating frequency 100 kHz 6. Guaranteed by design and characterization, not tested in production. 7. Control input must be monotonic from 20% to 80% of input swing. 8. Time from deassertion until outputs are >200 mV 9. CLK_IN input 10. The differential input clock must be running for the SMBus to be active 11. Test configuration is; Rs = 27 W, 2 pF for 85 W transmission line. www.onsemi.com 6 NB3W800L Table 12. DIF 0.7 V AC TIMING CHARACTERISTICS (Non−Spread or −0.5% Spread Spectrum Mode) (VDD = VDDA = 3.3 V ±5%, TA = 0°C * 70°C), See Test Loads for Loading Conditions. CLK = 100 MHz, 133.33 MHz Min Symbol Parameter Tstab (Note 32) Clock Stabilization Time Laccuracy (Notes 15, 19, 27, 33) Tabs (Notes 15, 16, 19) Long Accuracy Absolute Min/Max Host CLK Period No Spread −0.5% Spread Slew_rate (Notes 13, 15, 19) DIFF OUT Slew_rate DTrise / DTfall (Notes 15, 19, 29) Rise and Fall Time Variation 9.94900 for 100 MHz Max Unit 1.8 ms 100 ppm 10.05100 for 100 MHz ns 7.44925 for 133 MHz 7.55075 for 133 MHz 9.49900 for 100 MHz 10.10126 for 100 MHz 7.44925 for 133 MHz 7.58845 for 133 MHz 1.0 Rise/Fall Matching (Notes 15, 19, 30, 31) 4.0 V/ns 125 ps 20 % VHigh (Notes 15, 18, 21) Voltage High (typ 0.70 Volts) 660 850 mV VLow (Notes 15, 18, 22) Voltage Low (typ 0.0 Volts) −150 150 mV Vmax (Note 18) Maximum Voltage 1150 mV Vcross absolute (Notes 12, 14, 15, 18, 25) Absolute Crossing Point Voltages 250 550 mV Vcross relative (Notes 15, 17, 18, 25) Relative Crossing Point Voltages Calc Calc Total D Vcross (Notes 15, 18, 26) Total Variation of Vcross Over All Edges 140 mV Vovs (Notes 15, 18, 23) Maximum Voltage (Overshoot) Vhigh + 0.3 V Vuds (Notes 15, 18, 24) Maximum Voltage (Undershoot) Vlow − 0.3 V 12. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#. 13. Measurment taken from differential waveform on a component test board. The slew rate is measured from −150 mV to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge Only valid for Rising CLK_IN and Falling CLK_IN#. Signal must be monotonic through the Vol to Voh region for Trise and Tfall. 14. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. 15. Test configuration is; Rs = 27 W, 2 pF for 85 W transmission line. 16. The average period over any 1 ms period of time must be greater than the minimum and less than the maximum specified period. 17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg − 0.700), Vcross(rel) Max = 0.550 − 0.5 (0.700 – Vhavg) 18. Measurement taken from Single Ended waveform. 19. Measurement taken from differential waveform. Bypass mode, input duty cycle = 50%. 20. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 21. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function. 22. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function. 23. Overshoot is defined as the absolute value of the maximum voltage. 24. Undershoot is defined as the absolute value of the minimum voltage. 25. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 26. DVcross is defined as the total variation of all crossing voltages of Rising DIF and Falling DIF#. This is the maximum allowed variance in Vcross for any particular system. 27. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 100,000,000 Hz, 133,333,333 Hz. 28. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 Hz, 133,000,000 Hz. 29. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max. 30. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of DIF versus the falling edge rate (average) of DIF#. Measured in a ±75 mV window around the crosspoint of DIF and DIF#. 31. Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall). 32. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8 V – 2.0 V to the time that stable clocks are output from the buffer chip (PLL locked). 33. All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK420BQ accuracy requirements. The NB3W800L itself does not contribute to ppm error. www.onsemi.com 7 NB3W800L Table 13. ELECTRICAL CHARACTERISTICS – Current Consumption (VDD = VDDA = 3.3 V ±5%, TA = 0°C − 70°C), See Test Loads for Loading Conditions. (Note 35) Symbol Parameter Conditions Typ Max Units IDDVDD Operating Current (Note 34) 133 MHz, VDD rail 94 105 mA 133 MHz, VDDA + VDDR rail, PLL Mode 38 50 mA Power Down, VDD Rail 2.0 3.5 mA Power Down, VDDA Rail 0.5 1.0 mA Typ Max Units IDDVDDA IDDVDDPD Powerdown Current (Note 34) IDDVDDAPD Min 34. Guaranteed by design and characterization, not tested in production. 35. CL = 2 pF with RS = 27 W for Zo = 85 W differential trace impedance. Table 14. ELECTRICAL CHARACTERISTICS – Skew and Differential Jitter Parameters (VDD = VDDA = 3.3 V ±5%, TA = 0°C − 70°C), See Test Loads for Loading Conditions. Symbol Parameter Conditions Min tSPO_PLL CLK_IN, DIF[x:0] (Notes 36, 37, 39, 40, 43) Input−to−Output Skew in PLL mode nominal value @ 25°C, 3.3 V −100 100 ps tPD_BYP CLK_IN, DIF[x:0] (Notes 36, 37, 39, 40, 43) Input−to−Output Skew in Bypass mode nominal value @ 25°C, 3.3 V 2.5 4.5 ns tDSPO_PLL CLK_IN, DIF[x:0] (Notes 36, 37, 39, 40, 43) Input−to−Output Skew Varation in PLL mode across voltage and temperature −100 100 ps tDSPO_BYP CLK_IN, DIF[x:0] (Notes 36, 37, 39, 40, 43) Input−to−Output Skew Varation in Bypass mode across voltage and temperature −250 250 ps tSKEW_ALL DIF{x:0] (Notes 36, 37, 39, 43) Output−to−Output Skew across all outputs (Common to Bypass and PLL mode) 50 ps jpeak−hbw PLL Jitter Peaking (Notes 36, 42, 43) HBW_BYP_LBW# = 1 2.5 dB jpeak−lbw PLL Jitter Peaking (Notes 36, 42, 43) HBW_BYP_LBW# = 0 2 dB pllHBW PLL Bandwidth (Notes 36, 43, 44) HBW_BYP_LBW# = 1 2 3 4 MHz pllLBW PLL Bandwidth (Notes 36, 43, 44) HBW_BYP_LBW# = 0 0.7 1 1.4 MHz tDC Duty Cycle (Note 36, 46) Measured differentially, PLL and Bypass Mode 45 50 55 % tDCD Duty Cycle Distortion (Notes 36, 45) Measured differentially, Bypass Mode @ 100 MHz −2 0 2 % tjcyc−cyc Jitter, Cycle to cycle (Notes 36, 46) PLL mode 50 ps Additive Jitter in Bypass Mode 50 ps 36. CL = 2 pF with RS = 27 W for Zo = 85 W differential trace impedance. Input to output skew is measured at the first output edge following the corresponding input. 37. Measured from differential cross−point to differential cross−point. This parameter can be tuned with external feedback path, if present. 38. All Bypass Mode Input−to−Output specs refer to the timing between an input edge and the specific output edge created by it. 39. This parameter is deterministic for a given device 40. Measured with scope averaging on to find mean value. 41. t is the period of the input clock 42. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 43. Guaranteed by design and characterization, not tested in production. 44. Measured at 3 db down or half power point. 45. Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 46. Measured from differential waveform. Bypass mode, input duty cycle = 50%. www.onsemi.com 8 NB3W800L Table 15. ELECTRICAL CHARACTERISTICS – PHASE JITTER PARAMETERS (VDD = VDDA = 3.3 V ±5%, TA = 0°C − 70°C), See Test Loads for Loading Conditions. (Note 35) Symbol Max Units tjphPCIeG1 Parameter PCIe Gen 1 (Notes 48, 49) 86 ps (p−p) tjphPCIeG2 PCIe Gen 2 Lo Band 10 kHz < f < 1.5 MHz (Note 48) 3 ps (rms) PCIe Gen 2 High Band 1.5 MHz < f < Nyquist (50 MHz) (Note 48) 3.1 ps (rms) PCIe Gen 3 (PLL BW of 2−4 MHz, CDR = 10 MHz) (Notes 48, 50) 1 ps (rms) QPI & SMI (100 MHz or 133 MHz, 4.8 Gb/s, 6.4 Gb/s 12 UI) (Note 51) 0.5 ps (rms) QPI & SMI (100 MHz, 8.0 Gb/s, 12 UI) (Note 51) 0.3 ps (rms) QPI & SMI (100 MHz, 9.6 Gb/s, 12 UI) (Note 51) 0.2 ps (rms) tjphPCIeG1 PCIe Gen 1 (Notes 48, 49) 10 ps (p−p) tjphPCIeG2 PCIe Gen 2 Lo Band 10 kHz < f < 1.5 MHz (Notes 48, 52) 0.3 ps (rms) PCIe Gen 2 High Band 1.5 MHz < f < Nyquist (50 MHz) (Notes 48, 52) 0.6 ps (rms) PCIe Gen 3 (PLL BW of 2−4 MHz, 2−5 MHz, CDR = 10 MHz) (Notes 48, 50, 52) 0.2 ps (rms) QPI & SMI (100 MHz or 133 MHz, 4.8 Gb/s, 6.4 Gb/s 12 UI) (Notes 51, 52) 0.2 ps (rms) QPI & SMI (100 MHz, 8.0 Gb/s, 12 UI) (Notes 51, 52) 0.1 ps (rms) QPI & SMI (100 MHz, 9.6 Gb/s, 12 UI) (Notes 51, 52) 0.1 ps (rms) tjphPCIeG3 Phase Jitter, PLL Mode (Note 47) tjphQPI_SMI tjphPCIeG3 tjphQPI_SMI Additive Phase Jitter, Bypass mode (Note 47) Conditions Min Typ 47. Applies to all outputs. 48. See http://www.pcisig.com for complete specs 49. Sample size of at least 100K cycles. This figures extrapolates to 108ps pk−pk @ 1M cycles for a BER of 1−12. 50. Subject to final ratification by PCI SIG. 51. Calculated from Intel−supplied Clock Jitter Tool v 1.6.3 52. For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)2 = (total jittter)2 - (input jitter)2 www.onsemi.com 9 NB3W800L Table 16. CLOCK PERIODS – Differential Outputs with Spread Spectrum Disabled Measurement Window 1 Clock 1 ms 0.1 s 0.1 s 0.1 s 1 ms 1 Clock Center Freq. MHz −c2c Jitter Abs Per Min −SSC Short−Term Average Min − ppm Long−Term Average Min 0 ppm Period Nominal + ppm Long−Term Average Max +SSC Short−Term Average Max +c2c Jitter Abs Per Max Units DIF (Notes 53, 54, 55) 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns DIF (Notes 53, 54, 56) 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns SSC OFF Table 17. CLOCK PERIODS – Differential Outputs with Spread Spectrum Enabled Measurement Window 1 Clock 1 ms 0.1 s 0.1 s 0.1 s 1 ms 1 Clock Center Freq. MHz −c2c Jitter Abs Per Min −SSC Short−Term Average Min − ppm Long−Term Average Min 0 ppm Period Nominal + ppm Long−Term Average Max +SSC Short−Term Average Max +c2c Jitter Abs Per Max Units DIF (Notes 53, 54, 55) 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns DIF (Notes 53, 54, 56) 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns SSC ON 53. Guaranteed by design and characterization, not tested in production. 54. All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+ accuracy requirements (±100 ppm). The device itself does not contribute to ppm error. 55. Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode 56. Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode Measurement Points for Differential DIFFX# Trise (DIFFX) VOH = 0.525 V VCross VOL = 0.175 V DIFFX Tfall (DIFFX#) Figure 3. Single−Ended Measurement Points for Trise, Tfall www.onsemi.com 10 NB3W800L Measurement Points for Differential Vovs VHigh Vrb Vrb VLow Vuds Figure 4. Single−Ended Measurement Points for Vovs, Vuds, Vrb TPeriod High Duty Cycle% Low Duty Cycle% Skew measurement point 0.0 V Figure 5. Differential (DIFFX – DIFFX#) Measurement Points (Tperiod, Duty Cycle, Jitter) Test Loads Differential Output Terminations DIF Zo (W) Rs (W) 100 33 85 27 Rs 10 inches 85 W Differential Zo 2 pF Rs Low−Power HCSL− Compatible Output Buffer Figure 6. Differential Test Loads www.onsemi.com 11 2 pF NB3W800L SIGNAL AND FEATURE OPERATION CLK_IN, CLK_IN# PWRGD / PWRDN# The differential input clock is expected to be sourced from a clock synthesizer with an HCSL−compatible output, e.g. CK420BQ, CK−NET, CK−uS, or CK509B or another driver. PWRGD is asserted high and de−asserted low. De−assertion of PWRGD (pulling the signal low) is equivalent to indicating a powerdown condition. PWRGD (assertion) is used by the NB3W800L to sample initial configurations such as frequency select condition. After PWRGD has been asserted high for the first time, the pin becomes a PWRDN# (Power Down) pin that can be used to shut off all clocks cleanly and instruct the device to invoke power savings mode. PWRDN# is a completely asynchronous active low input. When entering power savings mode, PWRDN# should be asserted low prior to shutting off the input clock or power to ensure all clocks shut down in a glitch free manner. The assertion and de−assertion of PWRDN# is absolutely asynchronous. When PWRDN# is sampled low by two consecutive rising edges of DIF#, all differential outputs are held tri−stated on the next DIF# high to low transition. OE# and Output Enables (Control Registers) Each output can be individually enabled or disabled by SMBus control register bits. Additionally, each output of the DIF[7:0] has a dedicated OE# pin. The OE# pins are asynchronous asserted−low signals. The Output Enable bits in the SMBus registers are active high and are set to enable by default. The disabled state for the NB3W800L low power NMOS Push−Pull outputs is Low/Low. Please note that the logic level for assertion or deassertion is different in software than it is on hardware. Output is enabled if OE# pin is pulled low and still maintains software programming logic with output enabled if OE register is true. The assertion and de−assertion of this signal is absolutely asynchronous. HBW_BYPASS_LBW# The HBW_BYPASS_LBW# is a tri level function input pin. It is used to select between PLL high bandwidth, bypass mode and PLL low bandwidth mode. OE# Assertion (Transition from ‘1’ to ‘0’) All differential outputs that were tristated will resume normal operation in a glitch free manner. Device Power Up Sequence OE# De−Assertion (Transition from ‘0’ to ‘1’) The device power up should follow the sequence mentioned below for proper functioning of the device: PWRGD/PWRDN# should be asserted Low. All other Control pins should be defined to the required state. Power should be given to the device. PWRGD/PWRDN# should be asserted High. Note: if no clock is present on the CLK_IN/CLK_IN# pins, whenever device is Powered Up,there will be no clock on DIF/DIF# outputs Corresponding output will transition from normal operation to tri−state in a glitch free manner. 100M_133M# − Frequency Selection The 100M_133M# is a hardware pin, which programs the appropriate output frequency of the DIF pairs. Note that the CLK_IN frequency is equal to CLK_OUT frequency. An external pull−up or pull−down resistor is attached to this pin to select the input/output frequency. POWER FILTERING EXAMPLE V3P3 Place at pin FB1 R1 FERRITE 2.2 VDDA C9 1 mF R2 2.2 VDD for PLL C7 0.1 mF VDDR C10 1 mF VDD for Input Receiver VDD_DIF C8 0.1 mF C5 0.1 mF C6 0.1 mF C5 0.1 mF C6 0.1 mF VDD_DIF C1 10 mF C4 0.1 mF C2 0.1 mF C3 0.1 mF Figure 7. Schematic Example of the NB3W800L Power Filtering www.onsemi.com 12 NB3W800L General SMBus Serial Interface Information for NB3W800L How to Write • • • • • • • • • • How to Read • • • • • • • • • • • Controller (host) sends a start bit Controller (host) sends the write address Clock(device) will acknowledge Controller (host) sends the beginning byte location = N Clock(device) will acknowledge Controller (host) sends the byte count = X Clock(device) will acknowledge Controller (host) starts sending Byte N through Byte N+X−1 Clock(device) will acknowledge each byte one at a time Controller (host) sends a Stop bit • • • Index Block Write Operation Controller (Host) T Clock (Device) Controller (host) will send a start bit Controller (host) sends the write address Clock(device) will acknowledge Controller (host) sends the beginning byte location = N Clock(device) will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address Clock(device) will acknowledge Clock(device) will send the data byte count = X Clock(device) sends Byte N+X−1 Clock(device) sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit starT bit Index Block Read Operation Slave Address WR Controller (Host) WRite T ACK Clock (Device) starT bit Slave Address Beginning Byte = N WR ACK WRite ACK Data Byte Count = X Beginning Byte = N ACK ACK Beginning Byte N RT ACK Repeat starT Slave Address O O X Byte O RD O ReaD ACK O O Data Byte Count = X Byte N + X − 1 ACK ACK P Beginning Byte N stoP bit ACK O O O X Byte O O O Byte N + X - 1 N Not acknowledge P stoP bit www.onsemi.com 13 NB3W800L Table 18. SMBus TABLE: PLL MODE, AND FREQUENCY SELECT REGISTER Byte 0 Pin # Name Control Function Type Bit 7 48 PLL Mode 1 PLL Operating Mode Rd back 1 R Bit 6 48 PLL Mode 0 PLL Operating Mode Rd back 0 R Bit 5 See PLL Operating Mode Readback Table Default Latched at power up Latched at power up 0 Reserved 0 Bit 3 PLL_SW_EN Enable S/W control of PLL BW RW Bit 2 PLL Mode 1 PLL Operating Mode 1 RW Bit 1 PLL Mode 0 PLL Operating Mode 0 RW 100M_133M# Frequency Select Readback R NOTE: 1 Reserved Bit 4 Bit 0 0 47 HW Latch SMBus Control 0 See PLL Operating Mode Readback Table 133 MHz 100 MHz 1 1 Latched at power up Setting bit 3 to ‘1’ allows the user to overide the Latch value from pin 48 via use of bits 2 and 1. Use the values from the PLL Operating Mode Readback Table. Note that Bits 7 and 6 will keep the value originally latched on pin 48. A warm reset of the system will have to accomplished if the user changes these bits. Table 19. SMBus TABLE: OUTPUT CONTROL REGISTER Byte 1 Pin # Name Control Function Type 0 1 Default Bit 7 32/33 DIF_5_En Output Control - ‘0’ overrides OE# pin RW Low/Low Enable 1 Bit 6 28/29 DIF_4_En Output Control - ‘0’ overrides OE# pin RW 1 Bit 5 25/26 DIF_3_En Output Control - ‘0’ overrides OE# pin RW 1 Bit 4 21/22 DIF_2_En Output Control - ‘0’ overrides OE# pin RW 1 Bit 3 Reserved 1 Bit 2 16/17 DIF_1_En Output Control - ‘0’ overrides OE# pin RW Bit 1 13/14 DIF_0_En Output Control - ‘0’ overrides OE# pin RW Bit 0 Low/Low Enable 1 1 Reserved 1 Table 20. SMBus TABLE: OUTPUT CONTROL REGISTER Byte 2 Pin # Name Control Function Type 0 1 Default Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 0 Bit 3 Reserved 1 Bit 2 39/40 DIF_7_En 35/36 DIF_6_En Output Control - ‘0’ overrides OE# pin Bit 1 Bit 0 RW Low/Low Enable RW Low/Low Enable 1 Type 0 1 Default Reserved Output Control - ‘0’ overrides OE# pin 1 1 Table 21. SMBus TABLE: RESERVED REGISTER Byte 3 Pin # Name Control Function Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 0 Bit 3 Reserved 0 Bit 2 Reserved 0 Bit 1 Reserved 0 Bit 0 Reserved 0 www.onsemi.com 14 NB3W800L Table 22. SMBus TABLE: RESERVED REGISTER Byte 4 Pin # Name Control Function Type 0 1 Default Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 0 Bit 3 Reserved 0 Bit 2 Reserved 0 Bit 1 Reserved 0 Bit 0 Reserved 0 Table 23. SMBus TABLE: VENDOR & REVISION ID REGISTER Byte 5 Pin # Name Control Function Bit 7 − RID3 R Bit 6 − RID2 R REVISION ID Type 1 Default 0 0 A rev = 0000 Bit 5 − RID1 Bit 4 − RID0 R Bit 3 − VID3 R − − 1 Bit 2 − VID2 R − − 1 R − − 1 R − − 1 Type 0 1 Default Bit 1 − VID1 Bit 0 − VID0 VENDOR ID R 0 0 0 Table 24. SMBus TABLE: DEVICE ID Byte 6 Pin # Name Control Function Bit 7 − Device ID 7 (MSB) R 1 Bit 6 − Device ID 6 R 1 Bit 5 − Device ID 5 R 1 Bit 4 − Device ID 4 R 0 Bit 3 − Device ID 3 R 0 Bit 2 − Device ID 2 R 1 Bit 1 − Device ID 1 R 1 Bit 0 − Device ID 0 R 1 Table 25. SMBus TABLE: BYTE COUNT REGISTER Byte 7 Pin # Name Control Function Type 0 1 Default Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 − BC4 Bit 3 − BC3 RW RW Writing to this register configures how many bytes will be read back. Bit 2 − BC2 Bit 1 − BC1 RW Bit 0 − BC0 RW www.onsemi.com 15 RW 0 Default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. 1 0 0 0 NB3W800L PACKAGE DIMENSIONS QFN48 6x6, 0.4P CASE 485DP ISSUE O L2 A B D ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ L1 PIN ONE REFERENCE E L DETAIL A 2X DIM A A1 A3 b D D2 E E2 e L L1 L2 ALTERNATE TERMINAL CONSTRUCTIONS 0.10 C 2X L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. EXPOSED Cu A (A3) 0.10 C ÉÉÉ ÉÉÉ TOP VIEW 0.10 C DETAIL B 0.08 C DETAIL B A1 NOTE 4 SIDE VIEW C SEATING PLANE ALTERNATE CONSTRUCTION SOLDERING FOOTPRINT* D2 DETAIL A MOLD CMPD MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.15 0.25 6.00 BSC 3.90 4.10 6.00 BSC 3.90 4.10 0.40 BSC 0.30 0.50 0.00 0.15 0.08 REF 48X L 6.30 4.16 13 25 48X 0.63 E2 4.16 1 48 6.30 37 e 48X e/2 BOTTOM VIEW b 0.07 C A B 0.05 C NOTE 3 PKG OUTLINE 0.40 PITCH 48X 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PCIe is a registered trademark of PCI−Special Interest Group (PCI−SIG) Corporation. Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 16 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB3W800L/D