Intersil HS1-82C55ARH Radiation hardened cmos programmable peripheral interface Datasheet

HS-82C55ARH
Radiation Hardened
CMOS Programmable Peripheral Interface
September 1995
Features
Pinout
• Radiation Hardened
- Total Dose >105 RAD (Si)
- Transient Upset <108 RAD (Si)/s
- Latch Up Free EPI-CMOS
40 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T40
TOP VIEW
• Low Power Consumption
- IDDSB = 20µA
• Pin Compatible with NMOS 8255A and the Intersil 82C55A
PA3
1
40 PA4
PA2
2
39 PA5
PA1
3
38 PA6
PA0
4
37 PA7
RD
5
36 WR
• High Speed, No “Wait State” Operation with 5MHz HS-80C86RH
CS
6
35 RESET
GND
7
34 D0
• Bus-Hold Circuitry on All I/O Ports Eliminates Pull-Up Resistors
A1
8
33 D1
• Direct Bit Set/Reset Capability
A0
9
32 D2
PC7
10
31 D3
PC6
11
30 D4
PC5
12
29 D5
• Single 5V Supply
PC4
13
28 D6
• 2.0mA Drive Capability on All I/O Port Outputs
PC0
14
27 D7
PC1
15
26 VDD
PC2
16
25 PB7
PC3
17
24 PB6
PB0
18
23 PB5
PB1
19
22 PB4
PB2
20
21 PB3
• 24 Programmable I/O Pins
• Hardened Field, Self-Aligned, Junction Isolated CMOS Process
• Military Temperature Range: -55oC to +125oC
Description
The Intersil HS-82C55ARH is a high performance, radiation hardened
CMOS version of the industry standard 8255A and is manufactured using a
hardened field, self-aligned silicongate CMOS process. It is a general
purpose programmable I/O device which may be used with many different
microprocessors. There are 24 I/O pins which are organized into two 8-bit
and two 4-bit ports. Each port may be programmed to function as either an
input or an output. Additionally, one of the 8-bit ports may be programmed
for bi-directional operation,and the two 4-bit ports can be programmed to
provide handshaking capabilities. The high performance, radiation
hardness, and industry standard configuration of the HS-82C55ARH make
it compatible with the HS-80C86RH radiation hardened microprocessor.
Static CMOS circuit design insures low operating power. Bus hold circuitry
eliminates the need for pull-up resistors. The Intersil hardened field CMOS
process results in performance equal to or greater than existing radiation
resistant products at a fraction of the power.
Ordering Information
PART NUMBER
TEMPERATURE
PACKAGE
HS1-82C55ARH-Q
-55oC to +125oC
40 Lead SBDIP
HS1-82C55ARH-8
-55oC to +125oC
40 Lead SBDIP
+25oC
40 Lead SBDIP
HS1-82C55ARH/Sample
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
970
Pin Description
PIN
DESCRIPTION
D7 - D0
Data Bus (Bi-Directional
RESET
Reset Input
CS
Chip Select
RD
Read Input
WR
Write Input
A0 - A1
Port Address
PA7 - PA0
Port A (Bit)
PB& - PB0
Port B (Bit)
PC7 - PC0
Port C (Bit)
VDD
+5 volts
GND
0 volts
Spec Number
File Number
DB NA
• Enhanced Control Word Read Capability
518060
3191.1
HS-82C55ARH
Pin Description
SYMBOL
PIN
NUMBERS
TYPE
DESCRIPTION
PA0-7
1-4, 37-40
I/O
Port A: General purpose I/O Port. Data direction and mode is determined by the contents
of the Control Word.
PB0-7
18-25
I/O
Port B: General purpose I/O port. See Port A.
PC0-3
14-17
I/O
Port C (Lower): Combination I/O port and control port associated with Port B. See Port A.
PC4-7
10-13
I/O
Port C (Upper): Combination I/O Port and control port associated with Port A. See Port A.
D0-7
27-34
I/O
Bidirectional Data Bus: Three-State data bus enabled as an input when CS and WR are
low and as an output when CS and RD are low.
VDD
26
I
VDD: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is recommended for decoupling.
GND
7
I
Ground.
CS
6
I
Chip Select: A “low” on this input pin enables the communication between the
HS-82C55ARH and the CPU.
RD
5
I
Read: A “low” on this input pin enables the HS-82C55ARH to send the data or status
information to the CPU on the data bus. In essence, it allows the CPU to “read from” the
HS-82C55ARH.
WR
36
I
Write: A “low” on this input pin enables the CPU to write data or control words into the
HS-82C55ARH.
A0 and A1
8, 9
I
Port Select 0 and Port Select 1: These input signals, in conjunction with the RD and WR
inputs, control the selection of one of the three ports or the control word registers. They are
normally connected to the Least Significant Bits of the address bus (A0 and A1).
Reset
35
I
Reset: A “high” on this input clears the control register and all ports (A, B, C) are set to the
input mode. “Bus hold” devices internal to the HS-82C55ARH will hold the I/O port inputs
to a logic “1” state with a maximum hold current of 400µA.
Functional Diagram
POWER
SUPPLIES
+5V
GND
GROUP A
CONTROL
BIDIRECTIONAL
DATA BUS
D7 - D0
I/O
PA7 - PA0
GROUP A
PORT C
UPPER (4)
I/O
PC7 - PC4
GROUP B
PORT C
LOWER (4)
I/O
PC3 - PC0
GROUP B
PORT B
(8)
I/O
PB7 - PB0
DATA
BUS
BUFFER
8-BIT INTERNAL
DATA BUS
RD
WR
A1
A0
RESET
GROUP A
PORT A
(8)
READ/WRITE
CONTROL
LOGIC
GROUP B
CONTROL
CS
Spec Number
971
518060
Specifications HS-82C55ARH
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . .VSS-0.3V to VDD+0.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . .
40oC/W
6oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25.0mW/C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -1.5V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
GROUP A
SUBGROUP
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
TTL Output High Voltage
VOH1
VDD = 4.5V, IO = -2.5mA,
VIN = 0V, 4.5V
1, 2, 3
-55oC, +25oC,
+125oC
3.0
-
V
CMOS Output High Voltage
VOH2
VDD = 4.5V, IO = -100µA,
VIN = 0V, 4.5V
1, 2, 3
-55oC, +25oC,
+125oC
VDD0.4
-
V
VOL
VDD = 4.5V, IO = 2.5mA,
VIN = 0V, 4.5V
1, 2, 3
-55oC, +25oC,
+125oC
-
0.4
V
Output Low Voltage
Input Leakage Current
IIL or IIH
VDD = 5.5V, VIN = 0V, 5.5V
1, 2, 3
-55oC, +25oC,
+125oC
-1.0
1.0
µA
Output Leakage Current
IOZL or
IOZH
VDD = 5.5V, VIN = 0V, 5.5V
1, 2, 3
-55oC, +25oC,
+125oC
-10
10
µA
Input Current Bus Hold
High
IBHH
VDD = 4.5V or 5.5V,
VIN = 3.0V (See Note 1)
Ports A, B, C
1, 2, 3
-55oC, +25oC,
+125oC
-800
-60
µA
Input Current Bus Hold
Low
IBHL
VDD = 4.5V or 5.5V,
VIN = 1.0V (See Note 2)
Port A
1, 2, 3
-55oC, +25oC,
+125oC
60
800
µA
Standby Power Supply
Current
IDDSB
VDD = 5.5V, IO = 0mA,
VIN =GND or VDD
1, 2, 3
-55oC, +25oC,
+125oC
-
20
µA
Darlington Drive Voltage
VDAR
VDD = 4.5V, IO = -2.0mA,
VIN = GND or VDD
1, 2, 3
-55oC, +25oC,
+125oC
3.9
-
V
Functional Tests
FT
VDD = 4.5V and 5.5V,
VIN = GND or VDD,
f = 1MHz
7, 8A, 8B
-55oC, +25oC,
+125oC
-
-
-
Noise Immunity Functional
Test (Note 4)
FN
VDD = 5.5V, VIN = GND or
VDD - 1.5V and
VDD = 4.5V, VIN = 0.8V or
VDD
7, 8A, 8B
-55oC, +25oC,
+125oC
-
-
-
NOTES:
1. IBHH should be measured after raising VIN and then lowering to 3.0V.
2. IBHL should be measured after lowering VIN to VSS and then raising to 0.8V.
3. No internal current limiting exists on the Port Outputs. A resistor must be added externally to limit the current.
4. For VIH (VDD = 5.5V) and VIL (VDD = 4.5V) each of the following groups is tested separately with all other inputs using VIH = 2.6V,
VIL = 0.4V: PA, PB, PC, Control Pins (Pins 5, 6, 8, 9, 35, 36).
Spec Number
972
518060
Specifications HS-82C55ARH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS TA = -55oC to +125oC
LIMITS
SYMBOL
CONDITIONS
SUBGROUPS
Address Stable Before
RD
TAVRL
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
0
-
ns
Address Stable After RD
TRHAX
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
0
-
ns
RD Pulse Width
TRLRH
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
250
-
ns
Data Valid From RD
TRLDV
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
-
200
ns
Data Float After RD
TRHDX
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
10
-
ns
TRWHRWL
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
300
-
ns
Address Stable Before
WR
TAVWL
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
0
-
ns
Address Stable After WR
TWHAX
VDD = 4.5, 5.5V,
Ports A and B
9, 10, 11
-55oC, +25oC, +125oC
20
-
ns
VDD = 4.5, 5.5V,
Port C
9, 10, 11
-55oC, +25oC, +125oC
100
-
ns
PARAMETER
TEMPERATURE
MIN
MAX
UNITS
READ
Time Between RDs and/
or WRs
WRITE
WR Pulse Width
TWLWH
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
100
-
ns
Data Valid to WR High
TDVWH
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
100
-
ns
Data Valid After WR High
TWHDX
VDD = 4.5, 5.5V,
Ports A and B
9, 10, 11
-55oC, +25oC, +125oC
30
-
ns
VDD = 4.5, 5.5V,
Port C
9, 10, 11
-55oC, +25oC, +125oC
100
-
OTHER TIMINGS
WR = 1 to Output
TWHPV
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
-
350
ns
Peripheral Data Before
RD
TPVRL
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
0
-
ns
Peripheral Data After RD
TRHPX
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
0
-
ns
ACK Pulse Width
TKLKH
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
200
-
ns
STB Pulse Width
TSLSH
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
100
-
ns
Peripheral Data Before
STB High
TPVSH
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
20
-
ns
Peripheral Data After
STB High
TSHPX
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
50
-
ns
ACK = 0 to Output
TKLPV
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
-
175
ns
ACK = 1 to output Float
TKHPZ
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
10
-
ns
Spec Number
973
518060
Specifications HS-82C55ARH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS TA = -55oC to +125oC (Continued)
LIMITS
SYMBOL
CONDITIONS
SUBGROUPS
WR = 1 to OBF = 0
TWHOL
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
-
150
ns
ACK = 0 to OBF = 1
TKLOH
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
-
150
ns
STB = 0 to IBF = 1
TSLIH
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
-
150
ns
RD = 1 to IBF = 0
TRHIL
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
-
150
ns
RD = 0 to INTR = 1
TRLNL
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
-
200
ns
STB = 1 t INTR = 1
TSHNH
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
-
150
ns
ACK = 1 to INTR = 1
TKHNH
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
-
150
ns
WR = 0 to INTR = 0
TWLNL
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
-
200
ns
RESET Pulse Width
TRSHRSL
VDD = 4.5, 5.5V
(Note 2)
9, 10, 11
-55oC, +25oC, +125oC
500
-
ns
PARAMETER
TEMPERATURE
MIN
MAX
UNITS
NOTES:
1. AC’s tested at worst case VDD, guaranteed over full operating range.
2. Period of initial RESET pulse after power-on must be at least 50µs. Subsequenct RESET pulses may be 500ns minimum.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
Input Capacitance
CIN
VDD = Open, f = 1MHz, All
measurements referenced to
device ground
TA = +25oC
-
10
pF
I/O Capacitance
CI/O
VDD = Open, f = 1MHz, All
measurements referenced to
device ground
TA = +25oC
-
20
pF
Data Float After RD
TRHDX
VDD = 4.5V and 5.5V
-55oC < TA < +125oC
-
75
ns
ACK = 1 to Output Float
TKHPZ
VDD = 4.5V and 5.5V
-55oC < TA < +125oC
-
250
ns
NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics
TALBE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS
See
+25oC
limits in Table 1 and Table 2 for Post RAD limits (Subgroups 1, 7, 9)
Spec Number
974
518060
Specifications HS-82C55ARH
TABLE 5. BURN-IN DELTA PARAMETERS (+25oC)
PARAMETER
SYMBOL
DELTA LIMITS
Static Current
IDDSB
±10µA
Input Leakage Current
IIL, IIH
±200nA
IOZL, IOZH
±2µA
Low Level Output Voltage
VOL
±80mV
TTL Output High Voltage
VOH1
±600mV
CMOS Output High Voltage
VOH2
±150mV
Output Leakage Current
TABLE 6. APPLICABLE SUBGROUPS
GROUP A SUBGROUPS
CONFORMANCE
GROUP
MIL-STD-883
METHOD
TESTED FOR -Q
RECORDED
FOR -Q
TESTED FOR -8
Initial Test
100% 5004
1, 7, 9
1 (Note 2)
1, 7, 9
Interim Test
100% 5004
1, 7, 9, ∆
1, ∆ (Note 2)
1, 7, 9
PDA
100% 5004
1, 7, ∆
-
1, 7
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
-
2, 3, 8A, 8B, 10, 11
Group A (Note 1)
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
-
1, 2, 3, 7, 8A, 8B, 9,
10, 11
Subgroup B5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, ∆
1, 2, 3, ∆ (Note 2)
N/A
Subgroup B6
Sample 5005
1, 7, 9
-
N/A
Group C
Sample 5005
N/A
N/A
1, 2, 3, 7, 8A, 8B, 9,
10, 11
Group D
Sample 5005
1, 7, 9
-
1, 7, 9
Group E, Subgroup 2
Sample 5005
1, 7, 9
-
1, 7, 9
RECORDED
FOR -8
NOTES:
1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised.
2. Table 5 parameters only
Spec Number
975
518060
HS-82C55ARH
Intersil Space Level Product Flow -Q
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
2 Samples/Wafer, 0 Rejects
100% PDA 1, Method 5004 (Note 1)
100% Delta Calculation (T0-T1)
100% Die Attach
100% Dynamic Burn-In, Condition D, 240 Hours, +125oC or
Equivalent, Method 1015
100% Nondestructive Bond Pull, Method 2023
100% Interim Electrical Test 2(T2)
Sample - Wire Bond Pull Monitor, Method 2011
100% Delta Calculation (T0-T2)
Sample - Die Shear Monitor, Method 2019 or 2027
100% PDA 2, Method 5004 (Note 1)
100% Internal Visual Inspection, Method 2010, Condition A
100% Final Electrical Test
CSI and/or GSI PreCap (Note 6)
100% Fine/Gross Leak, Method 1014
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Radiographic (X-Ray), Method 2012 (Note 2)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
Sample - Group A, Method 5005 (Note 3)
100% External Visual, Method 2009
Sample - Group B, Method 5005 (Note 4)
100% PIND, Method 2020, Condition A
Sample - Group D, Method 5005 (Notes 4 and 5)
100% External Visual
100% Data Package Generation (Note 7)
100% Serialization
CSI and/or GSI Final (Note 6)
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 72 Hours Min,
+125oC Min, Method 1015
NOTES:
1. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
2. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
3. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
4. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include
separate line items for Group B Test, Group B Samples, Group D Test and Group D Samples.
5. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the
P.O. should include a separate line item for Group D Generic Data. Generic data is not guaranteed to be available and is therefore not
available in all cases.
6. CSI and/or GSI inspections are optional and will not be performed unless required by theP.O. When required, the P.O. should include
separate line items for CSI PreCap inspection, CSI final inspection, GSI PreCap inspection, and/or GSI final inspection.
7. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• Group B and D attributes and/or Generic data is included when required by the P.O.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number
976
518060
HS-82C55ARH
Intersil Space Level Product Flow -8
GAMMA Radiation Verification (Each Wafer) Method 1019,
2 Samples/Wafer, 0 Rejects
100% Dynamic Burn-In, Condition D, 160 Hours, +125oC or
Equivalent, Method 1015
100% Die Attach
100% Interim Electrical Test
Periodic- Wire Bond Pull Monitor, Method 2011
100% PDA, Method 5004 (Note 1)
Periodic- Die Shear Monitor, Method 2019 or 2027
100% Final Electrical Test
100% Internal Visual Inspection, Method 2010, Condition B
100% Fine/Gross Leak, Method 1014
CSI an/or GSI PreCap (Note 5)
100% External Visual, Method 2009
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
Sample - Group A, Method 5005 (Note 2)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
Sample - Group C, Method 5005 (Notes 3 and 4)
100% External Visual
Sample - Group B, Method 5005 (Note 3)
Sample - Group D, Method 5005 (Notes 3 and 4)
100% Data Package Generation (Note 6)
100% Initial Electrical Test
CSI and/or GSI Final (Note 5)
NOTES:
1. Failures from subgroup 1, 7 are used for calculating PDA. The maximum allowable PDA = 5%.
2. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
3. Group B, C and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include
separate line items for Group B Test, Group C Test, Group C Samples, Group D Test and Group D Samples.
4. Group C and/or Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When
required, the P.O. should include a separate line item for Group C Generic Data and/or Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases.
5. CSI and/or GSI inspections are optional and will not be performed unless required by theP.O. When required, the P.O. should include
separate line items for CSI PreCap inspection, CSI final inspection, GSI PreCap inspection, and/or GSI final inspection.
6. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Group B, C and D attributes and/or Generic data is included when required by the P.O.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
AC Test Circuit
AC Testing Input, Output Waveforms
V1
INPUT
R1
2.8V
TEST
POINT
FROM OUTPUT
UNDER TEST
1.5V
1.5V
0.4V
C1*
R2
NOTE: AC Testing: All parameters tested as per test circuits. Input
rise and fall times are driven at 1V/ns.
* Includes stray and jig capacitance
TEST CONDITIONS DEFINITION TABLE
V1
R1
R2
C1
1.7V
523Ω
Open
150pF
Spec Number
977
518060
HS-82C55ARH
Waveforms
TWLWH
TRLRH
RD
WR
TDVWH
TPVRL
TRHPX
TWHDX
INPUT
D7 - D0
TAVRL
TAVWL
TRHAX
CS, A1, A0
TWHAX
CS, A1, A0
OUTPUT
D7 - D0
TRLDV
TRHDZ
TWHPV
FIGURE 1. MODE 0 (BASIC INPUT)
FIGURE 2. MODE 0 (BASIC OUTPUT)
TWHOL
TSLSH
WR
STB
TKLOH
IBF
OBF
TRLNL
TSLIH
TRHIL
INTR
INTR
TWLNL
TSHNH
ACK
RD
TKLKH
TSHPX
TKHNH
INPUT FROM
PERIPHERAL
OUTPUT
TPVSH
TWHPV
FIGURE 3. MODE 1 (STROBED INPUT)
FIGURE 4. MODE 1 (STROBED OUTPUT)
DATA FROM CPU
TO HS-82C55ARH
A0 - A1, CS
WR
TKLOH
TAVWL
TWHAX
OBF
TWHOL
DATA BUS
INTR
TKLKH
TDVWH
TWHDX
ACK
WR
TSLSH
TWLWH
STB
FIGURE 6. WRITE TIMING
IBF
TSLIH
TKHPX
TKLPV
A0 - A1, CS
TPVSH
TAVRL
PERIPHERAL
BUS
TSHPX
RD
DATA FROM PERIPHERAL TO
HS-82C55ARH
TRHAX
TRLRH
TRHIL
RD
DATA FROM
HS-82C55ARH
TO PERIPHERAL
TRHDX
DATA FROM
HS-82C55ARH
TO CPU
TAVRL
DATA BUS
HIGH IMPEDANCE
VALID
HIGH IMPEDANCE
FIGURE 7. READ TIMING
FIGURE 5. MODE 2 (BIDIRECTIONAL)
NOTE: Any sequence where WR occurs before ACK and STB occurs
before RD is permissible.
Spec Number
978
518060
HS-82C55ARH
Burn-In Circuits
PROGRAMMABLE PERIPHERAL INTERFACE
PROGRAMMABLE PERIPHERAL INTERFACE
VDD
1
40
1
40
2
39
2
39
3
38
3
38
4
37
4
37
5
36
5
36
6
35
6
35
7
34
7
34
8
33
F4
8
33
F0
F2
F0
9
32
9
32
F6
10
31
F5
10
31
F5
11
30
F0
11
30
12
29
12
29
13
28
13
28
14
27
14
27
15
26
15
26
16
25
16
25
17
24
17
24
18
23
18
23
19
22
19
22
20
21
20
21
F1
F0
F4
STATIC CONFIGURATION
NOTES:
F7
F3
VDD
DYNAMIC CONFIGURATION
NOTES:
1. VDD = 6.0V ± 0. 5%
1. VDD = 6.0V ± 5% for Burn-In
2. IDD <500µA
2. VDD = 5.0V ± 5% for Life Test
3. TA Min = +125oC
3. All resistors are 10KΩ ± 5%
4. -0.3V ≤ VIL ≤ 0.8V
5. VDD - 1.0V ≤ VIH ≤ VDD
6. IDD < 5mA
7. F0 = 10KHz, 50% Duty cycle
8. F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2 . . . F7 = F6/2
9. TA Min = +125oC
Spec Number
979
518060
HS-82C55ARH
Irradiation Circuit
CMOS PROGRAMMABLE PERIPHERAL INTERFACE
+5.5V
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
+5.5V
NOTE:
1. VDD = 5.5V
Spec Number
980
518060
HS-82C55ARH
Functional Description
Ports A, B, C
The HS-82C55ARH is a programmable peripheral interface
designed to allow microcomputer systems to control and
interface with all types of peripheral devices.It has the
ability to generate and respond to all asynchronous handshaking signals necessary to transfer data to and from
peripheral devices, and it can also interrupt the processor
when a peripheral needs servicing. These capabilities allow
the HS-82C55ARH to be used in an unlimited number of
applications including EXTERNAL SYSTEM CONTROL,
ASYNCHRONOUS DATA TRANSFER, and SYSTEMS
MONITORING.
The HS-82C55ARH contains three 8-bit ports (A, B and C).
All can be configured to a wide variety of functional
characteristics by the system software but each has its own
special features or “personality” to further enhance the
power and flexibility of the HS-82C55ARH.
Port A
One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus hold
devices are present on Port A. See Figure 9A.
Port B
One 8-bit data input/output latch/buffer and one 8bit data input buffer. See Figure 9B.
Port C
One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be
divided into two 4-bit ports under the mode control.
Each 4-bit port contains a 4-bit latch and can be used
for the control signal outputs and status signal inputs
in conjunction with Ports A and B. See Figure 9B.
Data Bus Buffer
This tri-state bidirectional 8-bit buffer is used to interface the
HS-82C55ARH to the system data bus (see Figure 8). Data
is transmitted or received by the buffer upon execution of
input or output instructions by the CPU. Control words and
status information are also transferred through the data bus
buffer.
RD
CONTROL
MASTER
RESET
+5V
GND
POWER
SUPPLIES
GROUP
A
CONTROL
BIDIRECTIONAL
DATA BUS
D7D0
DATA
BUS
BUFFER
8-BIT INTERNAL
DATA BUS
RD
WR
A1
A0
RESET
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
GROUP
A PORT
A (8)
I/O
PA 7PA0
GROUP
A PORT
C UPPER
(4)
I/O
PC 7PC4
GROUP
B PORT
C LOWER
(4)
I/O
PC3PC0
GROUP
B PORT
B (8)
I/O
PB 7PB0
EXTERNAL
PORT A PIN
INTERNAL
DATA IN
INTERNAL
DATA OUT
WR
SIGNAL
(A)
VDD
MASTER
RESET
P
CS
FIGURE 8. BLOCK DIAGRAM DATA BUS BUFFER, READ/WRITE,
GROUP A AND B CONTROL LOGIC FUNCTIONS
Read/Write and Control Logic
EXTERNAL
PORT B, C
PIN
INTERNAL
DATA IN
The function of this block is to manage all of the internal and
external transfer of both Data and Control or Status words. It
accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
INTERNAL
DATA OUT
WR
SIGNAL
(B)
Group A and Group B Controls
The functional configuration of each port is programmed by
the systems software. In essence, the CPU writes a control
word to the HS-82C55ARH. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the HS-82C55ARH.
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control Logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
Control Group - Port A and Port C upper (C7 - C4)
Control Group - Port B and Port C lower (C3 - C0).
FIGURE 9. I/O PORT CONFIGURATION
Operational Description
Control Word
The data direction and mode of Ports A, B and C are
determined by the contents of the Control Word. See Figure
11. The Control Word can be both written and read as shown
in Table 1 and 2. During write operations, the function of the
Control Word being written is determined by data bit D7. If
D7 is low, the data on D0 - D3 will set or reset one of the bits
of Port C. See Figure 12. During read Operations, the
Spec Number
981
518060
HS-82C55ARH
Control Word will always be in the format illustrated in Figure
11 with Bit D7 high to indicate Control Word Mode Information.
TABLE 3.
ADDRESS BUS
A1
A0
RD
WR
CS
DISABLE FUNCTION
X
X
X
X
1
Data Bus - 3-State
X
X
1
1
0
Data Bus - 3-State
CONTROL BUS
DATA BUS
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
RD, WR
D7 - D0
A0 - A1
CS
B
C
A
MODE 0
8 I/O
4 I/O
4 I/O
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
8 I/O
GROUP A
PB7 - PB0 PC3 - PC0 PC7 - PC4 PA7 - PA0
B
MODE 1
C
8 I/O
PORT C (UPPER)
1 = INPUT
0 = OUTPUT
A
PORT A
1 = INPUT
0 = OUTPUT
8 I/O
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
PB7 - PB0 CONTROL CONTROL PA7 - PA0
OR I/O
OR I/O
B
MODE 2
C
MODE SET FLAG
1 = ACTIVE
A
FIGURE 11. MODE SET CONTROL WORD FORMAT
8 I/O
8
I/O
PB7 - PB0
CONTROL
BIDIRECTIONAL
PA7 - PA0
Mode Selection
There are three basic modes of operation that can be
selected by the system software:
FIGURE 10. BASIC MODE DEFINITIONS & BUS INTERFACE
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bidirectional Bus
TABLE 1.
INPUT OPERATION
(READ)
A1
A0
RD
WR
CS
0
0
0
1
0
Port A - Data Bus
0
1
0
1
0
Port B - Data Bus
1
0
0
1
0
Port C - Data Bus
1
1
0
1
0
Control Word - Data Bus
TABLE 2.
OUTPUT OPERATION
(WRITE)
A1
A0
RD
WR
CS
0
0
1
0
0
Data Bus - Port A
0
1
1
0
0
Data Bus - Port B
1
0
1
0
0
Data Bus - Port C
1
1
1
0
0
Data Bus - Control Word
When the RESET input goes “high”, all ports will be set to
the input mode with all 24 port lines held at the logic “one”
level by internal bus hold devices. After reset, the HS82C55ARH can remain in the input mode with no additional
initialization required. This eliminates the need for pullup or
pulldown resistors in all CMOS designs. During the
execution of the system program, any of the other modes
may be selected using a single output instruction. This
allows a single HS-82C55ARH to service a variety of
peripheral devices with a simple software maintenance
routine.
The modes for Port A and Port B can be separately defined
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status register, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O structure. For instance: Group B can be programmed in Mode 0
to monitor simple switch closings or display computational
results, Group A could be programmed in Mode 1 to monitor
a keyboard or tape recorder on an interrupt-driven basis.
Spec Number
982
518060
HS-82C55ARH
The mode definitions and possible mode combinations may
seem confusing at first but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the HS-82C55ARH has taken into
account things such as efficient PC board layout, control
signal definition vs PC layout and complete functional
flexibility to support almost any peripheral device with no
external logic. Such design represents the maximum use of
the available pins.
CONTROL WORD
X
BIT SET/RESET
1 = SET
0 = RESET
X
DON’T
CARE
When the HS-82C55ARH is programmed to operate in
Mode 1 or Mode 2, control signals are provided that can be
used as interrupt request inputs to the CPU. The interrupt
request signals, generated from Port C, can be inhibited or
enable by setting or resetting the associated INTE flip-flop,
using the Bit Set/Reset function of Port C.
This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.
INTE Flip-Flop Definition:
D7 D6 D5 D4 D3 D2 D1 D0
X
Interrupt Control Functions
(BIT-SET) - INTE is SET - Interrupt enable.
(BIT-RESET) - INTE is RESET - Interrupt disable.
NOTE: All mask flip-flops are automatically reset during
mode selection and device Reset.
BIT SELECT
0
0
0
0
1
1
0
0
2
0
1
0
3
1
1
0
4
0
0
1
5
1
0
1
6
0
1
1
7
1 B0
1 B1
1 B2
Operating Modes
Mode 0 (Basic Input/Output)
BIT SET/RESET FLAG
0 = ACTIVE
This functional configuration provides simple input and output operations for each of the three ports. No handshaking it
required, data is simply written to or read from a specific
port.
FIGURE 12. BIT SET/RESET CONTROL WORD FORMAT
Single Bit/Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset using a
single OUTput instruction. See Figure 12. This feature
reduces
software
requirements
in
control-based
applications.
Mode 0 Basic Functional Definitions:
• Two 8-bit ports and two 4-bit ports
• Any port can be input or output
• Outputs are latched
• Inputs are not latched
• 16 different Input/Output configurations possible
TRLRH
RD
TPVRL
TRHPX
INPUT
TAVRL
TRHAX
CS, A1, A0
D7 - D0
TRLDV
TRHDX
FIGURE 13. MODE 0 (BASIC INPUT)
TWLWH
WR
TWHDX
TDVWH
D7 - D0
TWHAX
TAVWL
CS, A1, A0
OUTPUT
TWHPV
FIGURE 14. MODE 0 (BASIC OUTPUT)
Spec Number
983
518060
HS-82C55ARH
Mode 0 Port Definition
A
B
GROUP A
GROUP B
D4
D3
D1
D0
PORT A
PORT C (UPPER)
NO.
PORT B
PORT C (LOWER)
0
0
0
0
Output
Output
0
Output
Output
0
0
0
1
Output
Output
1
Output
Input
0
0
1
0
Output
Output
2
Input
Output
0
0
1
1
Output
Output
3
Input
Input
0
1
0
0
Output
Input
4
Output
Output
0
1
0
1
Output
Input
5
Output
Input
0
1
1
0
Output
Input
6
Input
Output
0
1
1
1
Output
Input
7
Input
Input
1
0
0
0
Input
Output
8
Output
Output
1
0
0
1
Input
Output
9
Output
Input
1
0
1
0
Input
Output
10
Input
Output
1
0
1
1
Input
Output
11
Input
Input
1
1
0
0
Input
Input
12
Output
Output
1
1
0
1
Input
Input
13
Output
Input
1
1
1
0
Input
Input
14
Input
Output
1
1
1
1
Input
Input
15
Input
Input
Mode 0 Configurations
CONTROL WORD #0
CONTROL WORD #1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
8
A
4
C
D7 - D0
B
8
PA7 - PA0
4
8
A
4
PC7 - PC4
C
D7 - D0
PB7 - PB0
0
0
0
0
1
PC7 - PC4
PC3 - PC0
PB7 - PB0
CONTROL WORD #3
D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
0
0
1
1
8
A
C
B
8
PA7 - PA0
4
D7 - D0
8
B
D7 D6 D5 D4 D3 D2 D1 D0
0
4
PC3 - PC0
CONTROL WORD #2
1
PA7 - PA0
4
8
A
PA7 - PA0
4
PC7 - PC4
D7 - D0
C
PC3 - PC0
PB7 - PB0
B
4
8
PC7 - PC4
PC3 - PC0
PB7 - PB0
Spec Number
984
518060
HS-82C55ARH
Mode 0 Configurations
(Continued)
CONTROL WORD #4
CONTROL WORD #5
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
8
A
4
C
D7 - D0
B
8
PA7 - PA0
4
8
A
PC7 - PC4
C
D7 - D0
PB7 - PB0
0
0
1
0
1
8
B
1
0
0
0
1
0
1
C
B
8
PA7 - PA0
4
4
8
A
PC7 - PC4
C
D7 - D0
1
0
0
0
4
PC3 - PC0
PB7 - PB0
8
B
1
0
0
1
0
0
0
C
B
8
PA7 - PA0
4
4
8
A
4
C
D7 - D0
1
0
0
1
PB7 - PB0
8
B
PC7 - PC4
PC3 - PC0
PB7 - PB0
CONTROL WORD #11
D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
1
0
0
1
1
8
A
C
B
8
PA7 - PA0
4
D7 - D0
4
PC3 - PC0
D7 D6 D5 D4 D3 D2 D1 D0
0
PA7 - PA0
PC7 - PC4
CONTROL WORD #10
0
PB7 - PB0
1
8
A
1
PC3 - PC0
D7 D6 D5 D4 D3 D2 D1 D0
0
D7 - D0
PC7 - PC4
CONTROL WORD #9
D7 D6 D5 D4 D3 D2 D1 D0
0
PA7 - PA0
4
CONTROL WORD #8
0
PB7 - PB0
1
8
A
1
PC3 - PC0
D7 D6 D5 D4 D3 D2 D1 D0
0
D7 - D0
PC7 - PC4
CONTROL WORD #7
D7 D6 D5 D4 D3 D2 D1 D0
0
4
PC3 - PC0
CONTROL WORD #6
1
PA7 - PA0
4
4
8
A
PA7 - PA0
4
PC7 - PC4
D7 - D0
C
PC3 - PC0
PB7 - PB0
B
4
8
PC7 - PC4
PC3 - PC0
PB7 - PB0
Spec Number
985
518060
HS-82C55ARH
Mode 0 Configurations
(Continued)
CONTROL WORD #12
CONTROL WORD #13
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
8
A
4
C
D7 - D0
B
8
PA7 - PA0
4
8
A
PC7 - PC4
C
D7 - D0
PB7 - PB0
0
1
1
0
1
8
B
PC3 - PC0
PB7 - PB0
D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
1
1
0
1
1
8
A
C
B
8
PA7 - PA0
4
D7 - D0
PC7 - PC4
CONTROL WORD #15
D7 D6 D5 D4 D3 D2 D1 D0
0
4
PC3 - PC0
CONTROL WORD #14
1
PA7 - PA0
4
4
8
A
PA7 - PA0
4
PC7 - PC4
C
D7 - D0
4
PC3 - PC0
PB7 - PB0
8
B
PC7 - PC4
PC3 - PC0
PB7 - PB0
INTR (Interrupt Request)
Operating Modes
Mode 1 (Strobed Input/Output)
This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with
strobes or “handshaking” signals. In Mode 1, Port A and Port
B use the lines on Port C to generate or accept these “handshaking” signals.
A “high” on this output can be used to interrupt the CPU
when an input device is requesting service. INTR is set by
the rising edge of STB and reset by the falling edge of RD.
This procedure allows an input device to request service
from the CPU by simply strobing its data into the port.
INTE A
Controlled by Bit Set/Reset of PC4.
Mode 1 Basic Functional Definitions:
• Two Groups (Group A and Group B)
INTE B
• Each group contains one 8-bit port and one 4-bit control/
data port.
Controlled by Bit Set/Reset of PC2.
MODE 1 (PORT A)
• The 8-bit data port can be either input or output. Both
inputs and outputs are latched.
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
• The 4-bit port is used for control and status of the 8-bit
port.
MODE 1 (PORT B)
CONTROL WORD
0
1
1 1/0
1
1
1
PC6, 7
1 = INPUT
0 = OUTPUT
Input Control Signal Definition
PA7 - PA0
STB (Strobe Input)
INTE
A
A “low” on this input loads data into the input latch.
INTE
B
STB
A
IBF
A
PC4
PC5
IBF (Input Buffer Full F/F)
A “high” on this output indicates that the data has been
loaded into the input latch; in essence, an acknowledgment.
IBF is set by STB input being low and is reset by the rising
edge of the RD input.
PB7 - PB0
8
RD
PC2
PC1
8
STB
B
IBF
B
RD
INTR
A
PC3
PC0
INTR
B
2
PC6, 7
I/O
FIGURE 15. MODE 1 INPUT
Spec Number
986
518060
HS-82C55ARH
INTE A
TSLSH
Controlled by Bit Set/Reset of PC6.
STB
INTE B
IBF
TRLNL
Controlled by Bit Set/Reset of PC2.
TSLIH
TRHIL
INTR
TWHOL
TSHNH
WR
RD
TKHOL
OBF
TSHPX
INPUT FROM
PERIPHERAL
TPVSH
INTR
TWLNL
FIGURE 16. MODE 1 (STROBED INPUT)
ACK
Output Control Signal Definition
TKLKH
TKHNH
OBF (Output Buffer Full F/F)
OUTPUT
The OBF output will go “low” to indicate that the CPU has
written data out to the specified port. This does not mean
valid data is sent out of the port at this time since OBF can
go true before data is available. Data is guaranteed valid at
the rising edge of OBF. See Note 1. The OBF F/F will be set
by the rising edge of the WR input and reset by ACK input
being low.
TWHPV
FIGURE 18. MODE 1 (STROBED OUTPUT)
NOTE:
1. To strobe data into the peripheral device, the user must operate
the strobe line in a hand shaking mode. The user needs to send
OBF to the peripheral device, generate an ACK from the peripheral device and then latch data into the peripheral device on the
rising edge of OBF.
ACK (Acknowledge Input)
A “low” on this input informs the HS-82C55ARH that the data
from Port A or Port B is ready to be accepted. In essence, a
response from the peripheral device indicating that it is
ready to accept data. See Note 1.
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide
variety of strobed I/O applications.
INTR (Interrupt Request)
A “high” on this output can be used to interrupt the CPU
when an output device has accepted data transmitted by the
CPU. INTR is set by the rising edge of ACK and reset by the
falling edge of WR.
MODE 1 (PORT A)
MODE 1 (PORT B)
CONTROL WORD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0 1/0
1
1
PORT A (STROBED INPUT)
PORT B (STROBED OUTPUT)
CONTROL WORD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
PC4, 5
1 = INPUT
0 = OUTPUT
PA7 - PA0
PB7 - PB0
8
0
1
1 1/0 1
0
PC6, 7
1 = INPUT
0 = OUTPUT
RD
0
PORT A (STROBED OUTPUT)
PORT B (STROBED INPUT)
0
1
0 1/0 1
PA7 - PA0
8
WR
PA7 - PA0
STB A
PC7
OBF A
PC5
IBF A
PC6
ACK A
INTR A
PC3
INTE
A
PC6
WR
PC1
INTE
B
PC2
OBF
B
ACK
B
WR
WR
INTR
A
PC3
PC0
INTR
B
2
PC4, 5
I/O
PB7 - PB0
INTR A
2
I/O
PC6, 7
OBF
A
ACK
A
8
PC4
2
PC7
1
PC4, 5
1 = INPUT
0 = OUTPUT
PC3
8
1
8
I/O
PC4, 5
RD
PB7 - PB0
8
PC1
OBF B
PC2
STB B
PC2
ACK B
PC1
IBF B
PC0
INTR B
PC0
INTR B
FIGURE 19. COMBINATIONS OF MODE 1
FIGURE 17. MODE 1 OUTPUT
Spec Number
987
518060
HS-82C55ARH
Operating Modes
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
MODE 2 (Strobed Bidirectional Bus I/O)
1
0
1/0 1/0 1/0
The functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit
bus for both transmitting and receiving data (bidirectional
bus I/O). “Handshaking” signals are provided to maintain
proper bus flow discipline similar to MODE 1. Interrupt generation and enable/disable functions are also available.
PC2 - PC0
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
GROUP B MODE
0 = MODE 0
1 = MODE 1
Mode 2 Basic Functional Definitions:
• Used in Group A only.
FIGURE 20. MODE CONTROL WORD
• One 8-bit, bidirectional bus port (Port A) and a 5-bit control
port (Port C).
• Both inputs and outputs are latched.
PC3
• The 5-bit control port (Port C) is used for control and
status for the 8-bit, bidirectional bus port (Port A).
INTR A
8
PA7- PA0
Bidirectional Bus I/O Control Signal Definition
INTR (Interrupt Request)
A high on this output can be used to interrupt the CPU for
both input or output operations. INTR will be set either by the
rising edge of ACK (INTE1 = 1) or the rising edge of STB
(INTE2 = 1). INTR will be reset by the falling edge of WR (if
previously set by the rising edge or ACK), the falling edge of
RD (if previously set by the rising edge of STB), or the falling
edge of WR when immediately following a low RD pulse or
the falling edge of RD when immediately following a low WR
pulse (if previously set by the rising edges of both ACK and
STB).
PC7
OBF A
INTE
1
PC6
ACK A
INTE
2
PC7
STB A
PC6
IBF A
WR
RD
3
PC2- PC0
I/O
FIGURE 21. MODE 2 (BIDIRECTIONAL)
Output Operations
DATA FROM CPU
TO HS-82C55ARH
OBF (Output Buffer Full)
WR
The OBF output will go “low” to indicate that the CPU has
written data out to Port A.
TKHOL
OBF
TWHOL
ACK (Acknowledge)
INTR
A “low” on this input enables the tri-state output buffer of Port
A to send out the data. Otherwise, the output buffer will be in
the high impedance state.
TKLKH
ACK
TSLSH
STB
INTE 1 (The INTE Flip-Flop Associated with OBF)
Controlled by Bit Set/Reset of PC6.
IBF
TSLIH
Input Operations
TKHPX
TKLPV
TPVSH
PERIPHERAL
BUS
STB (Strobe Input)
A “low” on this input loads data into the input latch.
RD
DATA FROM PERIPHERAL TO
HS-82C55ARH
IBF (Input Buffer Full F/F)
A “high” on this output indicates that data has been loaded
into the input latch.
INTE 2 (The INTE Flip-Flop Associated with IBF)
TSHPX
TRHIL
DATA FROM
HS-82C55ARH
TO PERIPHERAL
DATA FROM
HS-82C55ARH
TO CPU
NOTE: Any sequence where WR occurs before ACK and STB occurs
before RD is permissible.
FIGURE 22. MODE 2 (BIDIRECTIONAL)
Controlled by Bit Set/Reset of PC4.
Spec Number
988
518060
HS-82C55ARH
MODE DEFINITION SUMMARY
MODE 0
MODE 1
MODE 2
IN
OUT
IN
OUT
PA0
AP1
PA2
PA3
PA4
PA5
PA6
PA7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
-
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
INTR B
IBF B
STB B
INTR A
STB A
IBF A
I/O
I/O
INTR B
OBF B
ACK B
INTR A
I/O
I/O
ACK A
OBF A
I/O
I/O
I/O
INTR A
STB A
IBF A
ACK A
OBF A
Special Mode Combination Considerations
GROUP A ONLY
Mode 0 or
Mode 1 Only
INPUT CONFIGURATION
There are several combinations of modes possible. For any
combination, some or all of Port C lines are used for control
or status. The remaining bits are either inputs or outputs as
defined by a “Set Mode” command.
D6
D5
D4
D3
D2
D1
D0
I/O
I/O
IBFA
INTEA
INTRA
INTEB
IBFB
INTRB
GROUP A
During a read of Port C, the state of all the Port C lines,
except the ACK and STB lines, will be placed on the data
bus. In place of the ACK and STB line states, flag status will
appear on the data bus in the PC2, PC4, and PC6 bit
positions as illustrated by Figure 25.
GROUP B
OUTPUT CONFIGURATION
Through a “Write Port C” command, only the Port C pins programmed as outputs in a Mode 0 group can be written. No
other pins can be affected by a “Write Port C” command, nor
can the interrupt enable flags be accessed. To write to any
Port C output programmed as an output in a Mode 1 group
or to change an interrupt enable flag, the “Set/Reset Port C
Bit” command must be used.
With a “Set/Reset Port C Bit” command, any Port C line
programmed as an output (including IBF and OBF) can be
written, or an interrupt enable flag can be either set or reset.
Port C lines programmed as inputs, including ACK and STB
lines, associated with Port C fare not affected by a “Set/
Reset Port C Bit” command. Writing to the corresponding
Port C bit positions of the ACK and STB lines with the “Set/
Reset Port C Bit” command will affect the Group A and
Group B interrupt enable flags, as illustrated in Figure 25.
D7
D7
D6
D5
D4
D3
D2
D1
D0
OBFA
INTEA
I/O
I/O
INTRA
INTEB
OBFB
INTRB
GROUP A
GROUP B
FIGURE 23. MODE 1 STATUS WORD FORMAT
D7
D6
D5
D4
D3
D2
D1
D0
OBFA
INTE1
IBFA
INTE2
INTRA
X
X
X
GROUP A
GROUP B
NOTE: (Defined by Mode 0 or Mode 1 Selection)
FIGURE 24. MODE 2 STATUS WORD FORMAT
Spec Number
989
518060
HS-82C55ARH
Current Drive Capability
Any output on Port A, B or C can sink or source 2.5mA. This
feature allows the 82C55A to directly drive Darlington type
drivers and high-voltage displays that require such sink or
source current.
There is no special instruction to read the status information
from Port C. A normal read operation of Port C is executed
to perform this function.
Reading Port C Status (Figures 23 and 24)
In Mode 0, Port C transfers data to or from the peripheral
device. When the 82C55A is programmed to function in
Modes 1 or 2, Port C generates or accepts “hand shaking”
signals with the peripheral device. Reading the contents of
Port C allows the programmer to test or verify the “status” of
each peripheral device and change the program flow
accordingly.
INTERRUPT
ENABLE FLAG*
POSITION
ALTERNATE PORT C
PIN SIGNAL (MODE)
INTE B
PC2
ACKB (Output Mode 1) or
STBB (Input Mode 1)
INTE A2
PC4
STBA (Input Mode 1 or
Mode 2)
INTE A1
PC6
ACKA (Output Mode 1 or
Mode 2)
FIGURE 25. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2
Spec Number
990
518060
HS-82C55ARH
Metallization Topology
DIE DIMENSIONS:
3420µm x 4350µm x 485µm ± 25µm
METALLIZATION:
Type: Al/Si
Thickness: 11kÅ ± 2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ± 1kÅ
WORST CASE CURRENT DENSITY:
7.7 x 104 A/cm2
Metallization Mask Layout
(6) CS
(7) VSS
(8) A1
(9) A0
(10) PC7
(11) PC6
(12) PC5
(13) PC4
(14) PC0
(15) PC1
HS-82C55ARH
PB3 (21)
(40) PA4
PB4 (22)
(39) PA5
PB5 (23)
(38) PA6
PB6 (24)
(37) PA7
PB7 (25)
(36) WR
RESET (35)
(1) PA3
D0 (34)
PB2 (20)
D1 (33)
(2) PA2
D2 (32)
PB1 (19)
D3 (31)
(3) PA1
D4 (30)
PB0 (18)
D5 (29)
(4) PA0
D6 (28)
PC3 (17)
D7 (27)
(5) RD
VDD (26)
PC2 (16)
Spec Number
991
518060
HS-82C55ARH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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Spec Number
992