TI1 ADS1252U2K5 24-bit, 40khz analog-to-digital converter Datasheet

ADS1252
ADS
125
2
SBAS127D – SEPTEMBER 2000 – REVISED JUNE 2006
24-Bit, 40kHz
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 24 BITS—NO MISSING CODES
● 19 BITS EFFECTIVE RESOLUTION UP TO
40kHz DATA RATE
● LOW NOISE: 2.5ppm
● DIFFERENTIAL INPUTS
● INL: 0.0015% (max)
● EXTERNAL REFERENCE (0.5V to 5V)
● POWER-DOWN MODE
● SYNC MODE
The ADS1252 is a precision, wide dynamic range, deltasigma, Analog-to-Digital (A/D) converter with 24-bit resolution operating from a single +5V supply. The delta-sigma
architecture is used for wide dynamic range and to ensure 24
bits of no missing code performance. An effective resolution
of 19 bits (2.5ppm of rms noise) is achieved for conversion
rates up to 40kHz.
The ADS1252 is designed for high-resolution measurement
applications in cardiac diagnostics, smart transmitters, industrial process control, weight scales, chromatography, and
portable instrumentation. The converter includes a flexible,
2-wire synchronous serial interface for low-cost isolation.
The ADS1252 is a single-channel converter and is offered in
an SO-8 package.
APPLICATIONS
●
●
●
●
●
●
CARDIAC DIAGNOSTICS
DIRECT THERMOCOUPLE INTERFACES
BLOOD ANALYSIS
INFRARED PYROMETERS
LIQUID/GAS CHROMATOGRAPHY
PRECISION PROCESS CONTROL
ADS1252
VREF
CLK
+VIN
–VIN
4th-Order
∆Σ
Modulator
Digital
Filter
Serial
Interface
SCLK
DOUT/DRDY
+VDD
GND
Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2000-2006, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
Analog Input: Current ............................................... ±100mA, Momentary
±10mA, Continuous
Voltage .................................... GND – 0.3V to VDD + 0.3V
VDD to GND ............................................................................ –0.3V to 6V
VREF Voltage to GND ............................................... –0.3V to VDD + 0.3V
Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V
Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V
Lead Temperature (soldering, 10s) .............................................. +300°C
Power Dissipation (any package) ................................................. 500mW
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
ADS1252
"
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
SO-8
D
–40°C to +85°C
ADS1252U
"
"
"
"
ADS1252U
ADS1252U/2K5
Rails, 100
Tape and Reel, 2500
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
PIN CONFIGURATION
PIN DESCRIPTIONS
Top View
+VIN
–VIN
SO
8
1
2
PIN
NAME
1
+VIN
Analog Input: Positive Input of the Differential Analog Input
2
–VIN
Analog Input: Negative Input of the Differential Analog Input
3
+VDD
Input: Power-Supply Voltage, +5V
4
CLK
Digital Input: Device System Clock. The
system clock is in the form of a CMOScompatible clock. This is a Schmitt-Trigger
input.
5
DOUT/DRDY
Digital Output: Serial Data Output/Data
Ready. A logic LOW on this output indicates that a new output word is available
from the ADS1252 data output register.
The serial data is clocked out of the serial
data output shift register using SCLK.
6
SCLK
Digital Input: Serial Clock. The serial clock
is in the form of a CMOS-compatible clock.
The serial clock operates independently
from the system clock, therefore, it is possible to run SCLK at a higher frequency
than CLK. The normal state of SCLK is
LOW. Holding SCLK HIGH will either initiate a modulator reset for synchronizing
multiple converters or enter power-down
mode. This is a Schmitt-Trigger input.
7
GND
Input: Ground
8
VREF
Analog Input: Reference Voltage Input
VREF
7
GND
ADS1252U
2
+VDD
3
6
SCLK
CLK
4
5
DOUT/DRDY
PIN DESCRIPTION
ADS1252
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SBAS127D
ELECTRICAL CHARACTERISTICS
All specifications at TMIN to TMAX, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified.
ADS1252U
PARAMETER
ANALOG INPUT
Full-Scale Input Voltage
Absolute Input Voltage
Differential Input Impedance
Input Capacitance
Input Leakage
CONDITIONS
+VIN or –VIN to GND
CLK = 3.84kHz
CLK = 1MHz
CLK = 16MHz
PERFORMANCE OVER TEMPERATURE
Offset Drift
Gain Drift
POWER-SUPPLY REQUIREMENTS
Operation
Quiescent Current
Operating Power
Power-Down Current
0
–0.3
±VREF
MAX
VDD
125
480
30
20
5
50
1
41.7
–3dB
9
16
16
±0.0003
97
2.5
1kHz Input; 0.1dB below FS
24
24
90
at DC
60
CLK
CLK
CLK
CLK
=
=
=
<
±0.0015
3.8
100
0.4
±100
1:1
80
VREF = 4.096V ±0.1V
1
±200
0.5
UNITS
V
V
MΩ
kΩ
kΩ
pF
pA
nA
kHz
kHz
MHz
MHz
% of FSR
dB
ppm of FSR, rms
Bits
Bits
dB
% of FSR
ppm of FSR
dB
0.07
7.5
5.2
3.9
3.4
16MHz
14MHz
12MHz
10MHz
VOLTAGE REFERENCE
VREF
Load Current
DIGITAL INPUT/OUTPUT
Logic Family
Logic Level: VIH
VIL
VOH
VOL
Input (SCLK, CLK) Hysteresis
Data Format
TYP
At +25°C
At TMIN to TMAX
DYNAMIC CHARACTERISTICS
Data Rate
Bandwidth
Serial Clock (SCLK)
System Clock Input (CLK)
ACCURACY
Integral Nonlinearity(1)
THD
Noise
Resolution
No Missing Codes
Common-Mode Rejection(2)
Gain Error
Offset Error
Gain Sensitivity to VREF
Power-Supply Rejection Ratio
MIN
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
4.096
220
VDD
V
µA
+VDD + 0.3
+0.8
V
V
V
V
V
CMOS
+4.0
–0.3
+4.5
IOH = –500µA
IOL = 500µA
0.4
0.6
Offset Binary Two’s Complement
+4.75
VDD = +5VDC
TEMPERATURE RANGE
Operating
Storage
–40
–60
+5
8
40
1
+5.25
10
50
10
V
mA
mW
µA
+85
+100
°C
°C
NOTES: (1) Applies to full-differential signals.
(2) The common-mode rejection test is performed with a 100mV differential input.
ADS1252
SBAS127D
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3
TYPICAL CHARACTERISTICS
At TA = +25°C, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified.
EFFECTIVE RESOLUTION vs DATA OUTPUT RATE
RMS NOISE vs DATA OUTPUT RATE
19.50
3.0
Effective Resolution (bits)
RMS Noise (ppm of FS)
2.5
2.0
1.5
1.0
19.25
19.00
18.75
0.5
18.5
0
100
1k
10k
100
100k
1k
10k
100k
Data Output Rate (Hz)
Data Output Rate (Hz)
RMS NOISE vs TEMPERATURE
EFFECTIVE RESOLUTION vs TEMPERATURE
3.0
19.0
18.9
Effective Resolution (bits)
RMS Noise (ppm of FS)
2.5
2.0
1.5
1.0
0.5
18.8
18.7
18.6
18.5
18.4
18.3
18.2
18.1
0
18.0
–40
–20
0
20
40
60
80
100
–40
–20
0
20
Temperature (°C)
40
60
80
100
Temperature (°C)
RMS NOISE vs VREF VOLTAGE
RMS NOISE vs VREF VOLTAGE
25
10
9
RMS Noise (ppm of FS)
RMS Noise (µV)
20
15
10
5
8
7
6
5
4
3
2
1
0
0
0
1
2
3
4
5
6
0
VREF (V)
4
1
2
3
4
5
6
VREF (V)
ADS1252
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SBAS127D
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified.
RMS NOISE vs INPUT VOLTAGE
EFFECTIVE RESOLUTION vs VREF
3.0
19.00
Effective Resolution (Bits)
RMS Noise (ppm of FS)
2.5
2.0
1.5
1.0
0.5
0
18.50
18.00
17.50
17.00
16.50
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
1
2
3
Differential Input Voltage (V)
4
5
6
VREF (V)
INTEGRAL NON-LINEARITY vs DATA OUTPUT RATE
INTEGRAL NON-LINEARITY vs TEMPERATURE
4
4.0
3.5
3
INL (ppm of FS)
INL (ppm of FS)
3.0
2.5
2.0
1.5
2
1
1.0
0.5
0
–40
0
–20
0
20
40
60
80
100
100
1k
10k
OFFSET DRIFT vs TEMPERATURE
GAIN DRIFT vs TEMPERATURE
800
10
8
CLK = 16MHz
600
6
4
400
Drift (ppm)
Offset Drift (ppm of FS)
100k
Data Output Rate (Hz)
Temperature (°C)
2
0
–2
CLK = 14.3MHz
200
CLK < 10MHz
0
–4
CLK < 10MHz
–6
–200
–8
CLK = 16MHz
–400
–40
–10
–40
–20
0
20
40
60
80
100
Temperature (°C)
0
20
40
60
80
100
Temperature (°C)
ADS1252
SBAS127D
–20
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5
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified.
POWER-SUPPLY REJECTION RATIO
vs CLK FREQUENCY
COMMON-MODE REJECTION RATIO
vs CLK FREQUENCY
100
110
95
105
85
CMRR (dB)
PSRR (dB)
90
80
75
100
95
90
70
85
65
60
80
0
5
10
15
0
20
5
CURRENT vs TEMPERATURE
15
20
POWER DISSIPATION vs CLOCK FREQUENCY
9.5
45
9.0
40
8.5
35
Power Dissipation (mW)
Supply Current (mA)
10
CLK Frequency (MHz)
CLK Frequency (MHz)
8.0
7.5
7.0
6.5
6.0
30
25
20
15
10
5
5.5
0
5.0
–40
–20
0
20
40
60
80
100
0
Temperature (°C)
5
10
15
20
CLK Frequency (MHz)
TYPICAL FFT ANALYSIS
OF THE 1kHz fS INPUT SIGNAL
0
Dynamic Range (dB)
–20
–40
–60
–80
–100
–120
–140
–160
–180
0
2000
4000
6000
8000
10000 12000
14000
Imput Signal Frequency (Hz)
6
ADS1252
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SBAS127D
THEORY OF OPERATION
The ADS1252 is a precision, high-dynamic range, 24-bit, deltasigma, A/D converter capable of achieving very high-resolution
digital results at high data rates. The analog-input signal
is sampled at a rate determined by the frequency of the system
clock (CLK). The sampled analog input is modulated by
the delta-sigma A/D modulator, which is followed by a digital
filter. A Sinc5 digital low-pass filter processes the output of
the delta-sigma modulator and writes the result into the dataoutput register. The DOUT/DRDY pin is pulled LOW, indicating
that new data is available to be read by the external
microcontroller/microprocessor. As shown in the block diagram, the main functional blocks of the ADS1252 are the
4th-order delta-sigma modulator, a digital filter, control logic,
and a serial interface. Each of these functional blocks is
described below.
ANALOG INPUT
The ADS1252 contains a fully differential analog input. In
order to provide low system noise, common-mode rejection
of 100dB, and excellent power-supply rejection, the design
topology is based on a fully differential switched-capacitor
architecture. The bipolar input voltage range is from –4.096
to +4.096V, when the reference input voltage equals +4.096V;
the bipolar range is with respect to –VIN, and not with respect
to GND.
With regard to the analog input signal, the overall analog
performance of the device is affected by three items. First,
the input impedance can affect accuracy; therefore, if the
source impedance of the input signal is significant, or if there
is passive filtering prior to the ADS1252, a significant portion
of the signal can be lost across this external impedance. The
magnitude of the effect is dependent on the desired system
performance. See application note Understanding the
ADS1251, ADS1253, and ADS1254 Input Circuitry
(SBAA086), available for download from TI’s web site,
www.ti.com.
Second, the current into or out of the analog inputs must be
limited. Under no conditions should the current into or out of
the analog inputs exceed 10mA.
Third, to prevent aliasing of the input signal, the bandwidth of
the analog input signal must be band limited; the bandwidth
is a function of the system clock frequency. With a system
clock frequency of 16MHz, the data-output rate is 41.667kHz
with a –3dB frequency of 9kHz, where the –3dB frequency
scales with the system clock frequency.
To ensure the best linearity of the ADS1252, a fully differential signal is recommended.
BIPOLAR INPUT
The differential inputs of the ADS1252 are designed to
accept differential signals; however, each analog input voltage must stay between –0.3V and VDD. With a reference
voltage at less than half of VDD, one input can be tied to the
reference voltage, and the other input can range from 0V to
2 • VREF. By using a single op amp circuit featuring a single
amplifier and four external resistors, the ADS1252 can be
configured to accept bipolar inputs referenced to ground. The
conventional ±2.5V, ±5V, and ±10V input ranges can be
interfaced to the ADS1252 using the resistor values shown in
Figure 1.
R1
10kΩ
ADS1252
–IN
VREF
R2
OPA2350
BIPOLAR INPUT
±10V
±5V
±2.5V
R1
R2
2.5kΩ
5kΩ
10kΩ
5kΩ
10kΩ
20kΩ
REF
2.5V
FIGURE 1. Level Shift Circuit for Bipolar Input Ranges.
ADS1252
SBAS127D
+IN
OPA2350
20kΩ
Bipolar Input
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7
DELTA-SIGMA MODULATOR
REFERENCE INPUT
The ADS1252 operates from a nominal system clock frequency of 16MHz which is fixed in relation to the system
clock frequency that is divided by 6 to derive the modulator
frequency; therefore, with a system clock frequency of 16MHz,
the modulator frequency is 2.667MHz. Furthermore, the
oversampling ratio of the modulator is fixed in relation to the
modulator frequency. The oversampling ratio of the modulator is 64, and with the modulator frequency running at
2.667MHz, the data rate is 41.667kHz; thus, using a slower
system clock frequency will result in a lower data output rate,
as shown in Table I.
Reference input takes an average current of 220µA with a
16MHz system clock; this current will be proportional to the
system clock. A buffered reference is recommended for
ADS1252. The recommended reference circuit is shown in
Figure 2.
CLK (MHz)
DATA OUTPUT RATE (Hz)
16.000(1)
41 667
40 000
30 063
38 400
37 287
32 000
31 250
28 800
26 042
25 000
19 200
16 000
15 625
12 800
9 600
8 000
6 400
4 800
2 400
1 200
1 000
500
100
60
50
30
25
20
16.67
15
12.50
10
15.360(1)
15.000(1)
14.745600(1)
14.318180(1)
12.288000(1)
12.000000(1)
11.059220(1)
10.000000(1)
9.600000
7.372800(1)
6.144000(1)
6.000000(1)
4.915200(1)
3.686400(1)
3.072000(1)
2.457600(1)
1.843200(1)
0.921600
0.460800
0.384000
0.192000
0.038400
0.023040
0.019200
0.011520
0.009600
0.007680
0.006400
0.005760
0.004800
0.003840
Reference voltages higher than 4.096V will increase the fullscale range, whereas the absolute internal circuit noise of the
converter remains the same. This will decrease the noise in
terms of ppm of full scale, which increases the effective
resolution (see the typical characteristic curve, RMS Noise vs
VREF).
DIGITAL FILTER
The digital filter of the ADS1252, referred to as a sinc5 filter,
computes the digital result based on the most recent outputs
from the delta-sigma modulator. At the most basic level, the
digital filter can be thought of as simply averaging the
modulator results in a weighted form and presenting this
average as the digital output. The digital output rate, or data
rate, scales directly with the system CLK frequency, this
allows the data output rate to be changed over a very wide
range (five orders of magnitude) by changing the system
CLK frequency. However, it is important to note that the
–3dB point of the filter is 0.216 times the data output rate, so
the data output rate must allow for sufficient margin to
prevent attenuation of the signal of interest.
As the conversion result is essentially an average, the
data-output rate determines the location of the resulting
notches in the digital filter (see Figure 3). Note that the first
notch is located at the data-output rate frequency, and
subsequent notches are located at integer multiples of the
data-output rate to allow for rejection of not only the fundamental frequency, but also harmonic frequencies. In this
manner, the data-output rate can be used to set specific
notch frequencies in the digital filter response.
NOTE: (1) Standard Clock Oscillator.
TABLE I. CLK Rate versus Data Output Rate.
+5V
+5V
0.10µF
7
0.1µF
2
1
REF3140
3
OPA350
+
+
3
To VREF
Pin 8 of
the ADS1252
6
10kΩ
2
0.1µF
10µF
0.10µF
4
10µF
0.1µF
FIGURE 2. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the ADS1252.
8
ADS1252
www.ti.com
SBAS127D
For example, if the rejection of power-line frequencies is
desired, then the data-output rate can simply be set to the
power-line frequency. For 50Hz rejection, the system CLK
frequency must be 19.200kHz, and this will set the dataoutput rate to 50Hz (see Table I and Figure 4). For 60Hz
rejection, the system CLK frequency must be 20.040kHz,
and this will set the data-output rate to 60Hz (see Table I and
Figure 5). If both 50Hz and 60Hz rejection is required, then
the system CLK must be 3.840kHz; this will set the dataoutput rate to 10Hz and reject both 50Hz and 60Hz (see Table
I and Figure 6).
The digital filter requires five conversions to fully settle. The
modulator has an oversampling ratio of 64; therefore, it
requires 5 • 64, or 320 modulator results, or clocks, to fully
settle. As the modulator clock is derived from the system
clock (CLK) (modulator clock = CLK ÷ 6), the number of
system clocks required for the digital filter to fully settle is
5 • 64 • 6, or 1920 CLKs. This means that any significant step
change at the analog input requires five full conversions to
settle. However, if the analog input change occurs asynchronously to the DOUT/DRDY pulse, then six conversions are
required to ensure full settling.
There is an additional benefit in using a lower data-output
rate: it provides better rejection of signals in the frequency
band of interest. For example, with a 50Hz data-output rate,
a significant signal at 75Hz can alias back into the passband
at 25Hz; this is due to the fact that rejection at 75Hz must
only be 66dB in the stopband—frequencies higher than the
first-notch frequency (see Figure 4). However, setting the
data-output rate to 10Hz will provide 135dB rejection at 75Hz
(see Figure 6). A similar benefit is gained at frequencies near
the data-output rate (see Figures 7, 8, 9, and 10). For
example, with a 50Hz data-output rate, rejection at 55Hz may
only be 105dB (see Figure 7); however, with a 10Hz dataoutput rate, rejection at 55Hz will be 122dB (see Figure 8).
If a slower data-output rate does not meet the system
requirements, then the analog front end can be designed to
provide the needed attenuation to prevent aliasing. Additionally, the data-output rate can be increased and additional
digital filtering can be done in the processor or controller.
CONTROL LOGIC
Application note SBAA103, A Spreadsheet to Calculate the
Frequency Response of the ADS1250-54 (available for download at www.ti.com) provides a simple tool for calculating the
ADS1250 frequency response for any CLK frequency.
The digital filter is described by the following transfer function:
 π • f • 64 
sin 

 fMOD 
H(f) =
 π•f 
64 • sin 

 fMOD 
5
The control logic is used for communications and control of
the ADS1252.
Power-Up Sequence
Prior to power-up, all digital and analog-input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they must never
exceed +VDD.
Once the ADS1252 powers up, the DOUT/DRDY line pulses
LOW on the first conversion; this data is not valid. The sixth
pulse of DOUT/DRDY is valid data from the analog input
signal.
DOUT/ DRDY
The DOUT/DRDY output signal alternates between two
modes of operation. The first mode of operation is the Data
Ready (DRDY) mode to indicate that new data has been
loaded into the data-output register and is ready to be read.
The second mode of operation is the Data Output (DOUT)
mode and is used to serially shift data out of the Data Output
Register (DOR). See Figure 11 for the time domain partitioning of the DRDY and DOUT function.
See Figure 12 for the basic timing of DOUT/DRDY. During
the time defined by t2, t 3, and t 4, the DOUT/DRDY
pin functions in DRDY mode. The state of the
DOUT/DRDY pin is HIGH prior to the internal transfer of new
data to the DOR. The result of the A/D conversion is written
or

1 – z –64
H(z) = 
 64 • 1 – z –1

(
)




5
ADS1252
SBAS127D
www.ti.com
9
DIGITAL FILTER RESPONSE
0
–20
–20
–40
–40
–60
–60
–80
Gain (dB)
Gain (dB)
NORMALIZED DIGITAL FILTER RESPONSE
0
–100
–120
–80
–100
–120
–140
–140
–160
–160
–180
–180
–200
–200
0
1
2
3
4
5
6
7
8
9
10
0
50
100
Frequency (Hz)
FIGURE 3. Normalized Digital Filter Response.
–20
–20
–40
–40
–60
–60
–80
–100
–120
–80
–120
–140
–160
–160
–180
–180
–200
150
200
250
–200
300
0
10
20
30
Frequency (Hz)
50
60
70
80
90
100
FIGURE 6. Digital Filter Response (10Hz Multiples).
DIGITAL FILTER RESPONSE
DIGITAL FILTER RESPONSE
0
0
–20
–20
–40
–40
–60
–60
–80
Gain (dB)
Gain (dB)
40
Frequency (Hz)
FIGURE 5. Digital Filter Response (60Hz).
–100
–120
–80
–100
–120
–140
–140
–160
–160
–180
–180
–200
–200
45
46
47
48
49
50
51
52
53
54
45
55
46
47
48
49
50
51
52
53
54
55
Frequency (Hz)
Frequency (Hz)
FIGURE 7. Expanded Digital Filter Response (50Hz with a
50Hz Notch).
10
300
–100
–140
100
250
DIGITAL FILTER RESPONSE
0
Gain (dB)
Gain (dB)
DIGITAL FILTER RESPONSE
50
200
FIGURE 4. Digital Filter Response (50Hz).
0
0
150
Frequency (Hz)
FIGURE 8. Expanded Digital Filter Response (50Hz with a
10Hz Notch).
ADS1252
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SBAS127D
DIGITAL FILTER RESPONSE
0
–20
–40
Gain (dB)
–60
–80
–100
–120
–140
–160
–180
–200
55
56
57
58
59
60
61
62
63
64
65
Frequency (Hz)
FIGURE 9. Expanded Digital Filter Response (60Hz with a
60Hz Notch).
DIGITAL FILTER RESPONSE
0
–20
–40
If SCLKs are not provided to the ADS1252 during the DOUT
mode, the MSB of the DOR is present on the DOUT/DRDY
line until the beginning of the time defined by t4. If an
incomplete read of the ADS1252 takes place in DOUT mode
(that is, fewer than 24 SCLKs are provided), the state of the
last bit read is present on the DOUT/DRDY line until the
beginning of the time defined by t4. If more than 24 SCLKs
are provided during DOUT mode, the DOUT/DRDY line
stays LOW until the beginning of the time defined by t4.
The internal data pointer for shifting data out on
DOUT/DRDY is reset on the falling edge of the time defined
by t1 and t4. This ensures that the first bit of data shifted out
of the ADS1252 after DRDY mode is always the MSB of new
data.
–60
Gain (dB)
to the DOR from MSB to LSB in the time defined by t1 (see
Figures 11 and 12). The DOUT/DRDY line then drives the
line LOW for the time defined by t2, and then drives the line
HIGH for the time defined by t3 to indicate that new data is
available to be read. At this point, the function of the DOUT/
DRDY pin changes to DOUT mode, and data is shifted out
on the pin after t7. If the MSB is high (because of a negative
result) the DOUT/DRDY signal will stay HIGH after the end
of time t3. The device communicating with the ADS1252 can
provide SCLKs to the ADS1252 after the time defined by t6.
The normal mode of reading data from the ADS1252 is for
the device reading the ADS1252 to latch the data on the
rising edge of SCLK (since data is shifted out of the ADS1252
on the falling edge of SCLK). In order to retrieve valid data,
the entire DOR must be read before the DOUT/DRDY pin
reverts back to DRDY mode.
–80
–100
–120
–140
–160
SYNCHRONIZING MULTIPLE CONVERTERS
–180
–200
55
56
57
58
59
60
61
62
63
64
65
Frequency (Hz)
FIGURE 10. Expanded Digital Filter Response (60Hz with a
10Hz Notch).
The normal state of SCLK is LOW; however, by holding SCLK
HIGH, multiple ADS1252s can be synchronized. This is accomplished by holding SCLK HIGH for at least four, but less
than 20, consecutive DOUT/DRDY cycles (see Figure 13).
After the ADS1252 circuitry detects that SCLK has been held
HIGH for four consecutive DOUT/DRDY cycles, the DOUT/
DRDY pin pulses LOW for 3 CLK cycles and then held HIGH,
and the modulator is held in a reset state. The modulator
is released from reset and synchronization occurs on the
falling edge of SCLK. It is important to note that prior
to synchronization, the DOUT/DRDY pulse of multiple
ADS1252s in the system can have a difference in timing up
to one DRDY period. Therefore, to ensure synchronization,
the SCLK must be held HIGH for at least five DRDY cycles.
The first DOUT/DRDY pulse after the falling edge of
SCLK occurs at t14. Valid data is not present until the sixth
DOUT/DRDY pulse.
ADS1252
SBAS127D
www.ti.com
11
POWER-DOWN MODE
SERIAL INTERFACE
The normal state of SCLK is LOW; however, by holding
SCLK HIGH, the ADS1252 enters power-down mode. This is
accomplished by holding SCLK HIGH for at least 20 consecutive DOUT/DRDY periods (see Figure 14). After the
ADS1252 circuitry detects that SCLK is held HIGH for four
consecutive DOUT/DRDY cycles, the DOUT/DRDY pin pulses
LOW for three CLK cycles, then held HIGH, and the modulator will be held in a reset state. If SCLK is held HIGH for an
additional 16 DOUT/DRDY periods, the ADS1252 enters
power-down mode and the part is released from power-down
mode on the falling edge of SCLK. It is important to note that
the DOUT/DRDY pin is held HIGH after four DOUT/DRDY
cycles, but power-down mode is not entered for an additional
16 DOUT/DRDY periods. The first DOUT/DRDY pulse after
the falling edge of SCLK occurs at t16; however, subsequent
DOUT/DRDY pulses occur normally. Valid data is not present
until the sixth DOUT/DRDY pulse.
The ADS1252 includes a simple serial interface which can be
connected to microcontrollers and digital signal processors in
a variety of ways. Communications with the ADS1252 can
commence on the first detection of the DOUT/DRDY pulse
after power up, although data is valid until the sixth conversion.
It is important to note that the data from the ADS1252 is a
24-bit result transmitted MSB-first in Offset Binary Two’s
Complement format, as shown in Table III.
The data must be clocked out before the ADS1252 enters
DRDY mode to ensure reception of valid data, as described
in the DOUT/DRDY section of this data sheet.
DIFFERENTIAL VOLTAGE INPUT
DIGITAL OUTPUT (HEX)
+Full-Scale
Zero
–Full-Scale
7FFFFFH
000000H
800000H
TABLE III. ADS1252 Data Format (Offset Binary Two's
Complement).
SYMBOL
tDRDY
DRDY Mode
DOUT Mode
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
DESCRIPTION
MIN
Conversion Cycle
DRDY Mode
DOUT Mode
DOR Write Time
DOUT/DRDY LOW Time
DOUT/DRDY HIGH Time (Prior to Data Out)
DOUT/DRDY HIGH Time (Prior to Data Ready)
Rising Edge of CLK to Falling Edge of DOUT/DRDY
End of DRDY Mode to Rising Edge of First SCLK
End of DRDY Mode to Data Valid (Propagation Delay)
Falling Edge of SCLK to Data Valid (Hold Time)
Falling Edge of SCLK to Next Data Out Valid (Propagation Delay)
SCLK Setup Time for Synchronization or Power Down
DOUT/DRDY Pulse for Synchronization or Power Down
Rising Edge of SCLK Until Start of Synchronization
Synchronization Time
Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode
Rising Edge of SCLK Until Start of Power Down
Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode
Falling Edge of Last DOUT/DRDY to Start of Power Down
TYP
MAX
UNITS
384 • CLK
36 • CLK
348 • CLK
6 • CLK
6 • CLK
6 • CLK
24 • CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
30
5
30
30
3 • CLK
1537 • CLK
0.5 • CLK
7679 • CLK
6143.5 • CLK
2042.5 • CLK
7681 • CLK
591.5 • CLK
592.5 • CLK
6143.5 • CLK
TABLE II. Digital Timing.
DOUT Mode
DRDY Mode
t2
t4
DOUT/DRDY
DOUT Mode
DATA
DRDY Mode
t3
DATA
DATA
t1
FIGURE 11. DOUT/DRDY Partitioning.
12
ADS1252
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SBAS127D
ADS1252
SBAS127D
www.ti.com
13
t4
t1
t10
t2
t3
tDRDY
t10
t2
t3
FIGURE 14. Power-Down Mode.
DOUT/DRDY
SCLK
CLK
tDRDY
FIGURE 13. Synchronization Mode.
DOUT/DRDY
SCLK
CLK
FIGURE 12. DOUT/DRDY Timing.
DOUT/DRDY
SCLK
CLK
t2
DOUT
Mode
DATA
DOUT
Mode
DATA
t4
t4
DRDY Mode
t5
4 tDRDY
4 tDRDY
t12
t3
t15
t11
MSB
t7
t6
DATA
DATA
t8
t9
tDRDY
t11
t17
t13
t11
t16
Power Down Occurs Here
t14
Synchronization Begins Here
Synchronization Mode Starts Here
DOUT Mode
LSB
t2
t2
t3
t3
DATA
DATA
tDRDY
DOUT
Mode
tDRDY
DOUT
Mode
t4
t4
ISOLATION
The serial interface of the ADS1252 provides for simple
isolation methods. The CLK signal can be local to the
ADS1252, which then only requires two signals (SCLK and
DOUT/DRDY) to be used for isolated data acquisition.
LAYOUT
POWER SUPPLY
The power supply should be well regulated and low noise.
For designs requiring very high resolution from the ADS1252,
power-supply rejection will be a concern. Avoid running
digital lines under the device because they can couple noise
onto the die. High-frequency noise can capacitively couple
into the analog portion of the device and will alias back into
the passband of the digital filter, affecting the conversion
result.
GROUNDING
The analog and digital sections of the system design must be
carefully and cleanly partitionedl; each section must have its
own ground plane with no overlap between them. GND must
be connected to the analog ground plane, as well as all other
analog grounds. Do not join the analog and digital ground
planes on the board, but instead connect the two with a
moderate signal trace. For multiple converters, connect the
two ground planes at one location as central to all of the
converters as possible. In some cases, experimentation is
required to find the best point to connect the two planes
together. The printed circuit board can be designed to provide different analog/digital ground connections via short
jumpers; the initial prototype can be used to establish which
connection works best.
SYSTEM CONSIDERATIONS
The recommendations for power supplies and grounding
change depending on the requirements and specific design
of the overall system. Achieving 24 bits of noise performance
is a great deal more difficult than achieving 12 bits of noise
performance. In general, a system can be broken up into four
different stages:
•
•
•
•
Analog Processing
Analog Portion of the ADS1252
Digital Portion of the ADS1252
Digital Processing
For the simplest system consisting of minimal analog signal
processing (basic filtering and gain), a microcontroller, and
one clock source, one can achieve high resolution by powering all components by a common power supply. In addition,
all components can share a common ground plane; thus,
there would be no distinctions between analog power and
ground, and digital power and ground. The layout must still
include a power plane, a ground plane, and careful decoupling.
In a more extreme case, the design can include:
• Multiple ADS1252s
• Extensive Analog Signal Processing
• One or More Microcontrollers, Digital Signal Processors, or
Microprocessors
• Many Different Clock Sources
• Interconnections to Various Other Systems
High resolution will be very difficult to achieve for this design.
The approach would be to break the system into as many
different parts as possible. For example, each ADS1252 may
have its own analog processing front end.
DEFINITION OF TERMS
DECOUPLING
Good decoupling practices must be used for the ADS1252
and for all components in the design. All decoupling capacitors, and specifically the 0.1µF ceramic capacitors, must be
placed as close as possible to the pin being decoupled. A
1µF to 10µF capacitor, in parallel with a 0.1µF ceramic
capacitor, must be used to decouple VDD to GND.
14
An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the definition
of each term is given as follows:
Analog-Input Differential Voltage—for an analog signal
that is fully differential, the voltage range can be compared to
that of an instrumentation amplifier. For example, if both
analog inputs of the ADS1252 are at 2.048V, the differential
voltage is 0V; however, if one analog input is at 0V and the
other analog input is at 4.096V, then the differential voltage
magnitude is 4.096V. This is the case regardless of which
input is at 0V and which is at 4.096V. The digital-output
ADS1252
www.ti.com
SBAS127D
result, however, is quite different. The analog-input differential voltage is given by the following equation:
+VIN – (–VIN)
A positive digital output is produced whenever the
analog-input differential voltage is positive, whereas negative
digital output is produced whenever the differential is negative. For example, a positive full-scale output is produced
when the converter is configured with a 4.096V reference,
and the analog-input differential is 4.096V, the negative fullscale output is produced when the differential voltage is
–4.096V. In each case, the actual input voltages must remain
within the –0.3V to +VDD range.
Actual Analog-Input Voltage—the voltage at any one analog input relative to GND.
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1252 is defined as the input which
produces the positive full-scale digital output minus the input
which produces the negative full-scale digital output. For
example, when the converter is configured with a 4.096V
reference, the differential full-scale range is:
[4.096V (positive full-scale) – (–4.096V) (negative full-scale)] = 8.192V
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input has to change in order to observe a change in the
output data of one least significant bit. It is computed as
follows:
LSB Weight =
each is a statistical calculation based on a given number of
results. Noise occurs randomly; the rms value represents a
statistical measure which is one standard deviation. The ER
in bits can be computed as follows:
 2 • VREF 
20 • log 

 Vrms noise 
ER in bits rms =
6.02
The 2 • VREF figure in each calculation represents the
full-scale range of the ADS1252, this means that both units
are absolute expressions of resolution—the performance in
different configurations can be directly compared, regardless
of the units.
Noise Reduction—for random noise, the ER can be improved with averaging. The result is the reduction in noise by
the factor √N, where N is the number of averages, as shown
in Table IV; this can be used to achieve true 24-bit performance at a lower data rate. To achieve 24 bits of resolution,
more than 24 bits must be accumulated. A 36-bit accumulator is required to achieve an ER of 24 bits. The following uses
VREF = 4.096V, with the ADS1252 outputting data at 40kHz,
a 4096 point average takes 102.4ms. The benefits of averaging is degraded if the input signal drifts during that 100ms.
N
(NUMBER
OF AVERAGES)
NOISE
REDUCTION
FACTOR
ER
IN
µVrms
ER
IN
BITS rms
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
1
1.414
2
2.82
4
5.66
8
11.3
16
22.6
32
45.25
64
31.3µV
22.1µV
15.6µV
11.1µV
7.82µV
5.53µV
3.91µV
2.77µV
1.96µV
1.38µV
978nV
692nV
489nV
18
18.5
19
19.5
20
20.5
21
21.5
22
22.5
23
23.5
24
Full−ScaleRange
2N
where N is the number of bits in the digital output.
Conversion Cycle—as used here, a conversion cycle refers
to the time period between DOUT/DRDY pulses.
Effective Resolution (ER)—of the ADS1252 in a particular
configuration can be expressed in two different units:
bits rms (referenced to output) and µVrms (referenced to
input). Computed directly from the converter output data,
TABLE IV. Averaging.
ADS1252
SBAS127D
www.ti.com
15
Revision History
DATE
REVISION
PAGE
SECTION
6/06
D
11
DOUT/DRDY
DESCRIPTION
Text changes to DOUT/DRDY section.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
16
ADS1252
www.ti.com
SBAS127D
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ADS1252U
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS
1252U
ADS1252U/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS
1252U
ADS1252U/2K5G4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS
1252U
ADS1252UG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS
1252U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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24-Jan-2013
Addendum-Page 2
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