TI1 CY74FCT16841ATPVC 20-bit latch Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16841T
CY74FCT162841T
20-Bit Latches
SCCS067A - July 1994 - Revised October 2001
Features
•
•
•
•
•
•
•
•
Functional Description
FCT-C speed at 5.5 ns (FCT16841T Com’l)
Ioff supports partial-power-down mode operation
Edge-rate control circuitry for significantly improved
noise characteristics
Typical output skew < 250 ps
ESD > 2000V
TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
Industrial temperature range of −40˚C to +85˚C
VCC = 5V ± 10%
The CY74FCT16841T and CY74FCT162841T are 20-bit
D-type latches designed for use in bus applications requiring
high speed and low power. These devices can be used as two
independent 10-bit latches, or as a single 10-bit latch, or as a
single 20-bit latch by connecting the Output Enable (OE) and
Latch (LE) inputs. Flow-through pinout and small shrink
packaging aid in simplifying board layout.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device
when it is powered down.
The CY74FCT16841T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
CY74FCT16841T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
The CY74FCT162841T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162841T is ideal for driving transmission lines.
CY74FCT162841T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
Pin Configuration
Logic Block Diagrams
SSOP/TSSOP
Top View
1OE
1LE
1D1
D
1Q1
C
TO 9 OTHER CHANNELS
FCT16841-1
2OE
2LE
2D1
D
2Q1
C
TO 9 OTHER CHANNELS
FCT16841-2
1OE
1
56
1LE
1Q1
2
55
1 D1
1Q2
GND
3
4
54
53
1Q3
5
52
1Q4
6
51
1 D4
VCC
7
50
VCC
1 D5
1 D2
GND
1 D3
1Q5
8
49
1Q6
9
48
1 D6
1Q7
10
47
1 D7
GND
11
46
GND
1Q8
12
45
1 D8
1Q9
13
44
1 D9
1Q10
14
43
1D10
2Q1
15
42
2 D1
2Q2
16
41
2 D2
2Q3
17
40
2 D3
GND
18
39
GND
2Q4
19
38
2 D4
2Q5
20
37
2 D5
2Q6
21
36
2 D6
VCC
2Q7
22
35
VCC
23
34
2 D7
2Q8
24
33
2 D8
GND
2Q9
25
32
GND
26
31
2 D9
2Q10
27
30
2D10
2OE
28
29
2LE
FCT16841-3
Copyright
© 2001, Texas Instruments Incorporated
CY74FCT16841T
CY74FCT162841T
Function Table[1]
Pin Description
Name
Description
Inputs
Outputs
D
Data Inputs
D
LE
OE
Q
LE
Latch Enable Input (Active HIGH)
H
H
L
H
OE
Output Enable Input (Active LOW)
L
H
L
L
O
Three-State Outputs
X
L
L
Q[2]
X
X
H
Z
Maximum Ratings[3, 4]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Power Dissipation .......................................................... 1.0W
Storage Temperature ...................................... −55°C to +125°C
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied .................................................. −55°C to +125°C
Operating Range
DC Input Voltage .................................................−0.5V to +7.0V
Range
DC Output Voltage ..............................................−0.5V to +7.0V
Industrial
DC Output Current
(Maximum Sink Current/Pin) ...........................−60 to +120 mA
Ambient
Temperature
VCC
−40°C to +85°C
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VIH
Input HIGH Voltage
Logic HIGH Level
VIL
Input LOW Voltage
Logic LOW Level
VH
Input
Hysteresis[6]
VIK
Input Clamp Diode Voltage
VCC=Min., IIN=−18 mA
IIH
Input HIGH Current
IIL
Input LOW Current
IOZH
Min.
Typ.[5]
Max.
2.0
Unit
V
0.8
100
mV
−1.2
V
VCC=Max., VI=VCC
±1
µA
VCC=Max., VI=GND
±1
µA
High Impedance Output
Current (Three-State Output pins)
VCC=Max., VOUT=2.7V
±1
µA
IOZL
High Impedance Output
Current (Three-State Output pins)
VCC=Max., VOUT=0.5V
±1
µA
IOS
Short Circuit Current[7]
VCC=Max., VOUT=GND
−80
−200
mA
IO
Output Drive Current[7]
VCC=Max., VOUT=2.5V
−50
−180
mA
±1
µA
IOFF
Power-Off Disable
VCC=0V, VOUT
≤4.5V[8]
−0.7
V
−140
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance.
2. Output level before LE HIGH-to-LOW Transition.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
5. Typical values are at VCC= 5.0V, TA= +25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
8. Tested at +25˚C.
2
CY74FCT16841T
CY74FCT162841T
Output Drive Characteristics for CY74FCT16841T
Parameter
VOH
VOL
Min.
Typ.[5]
VCC=Min., IOH=−3 mA
2.5
3.5
VCC=Min., IOH=−15 mA
2.4
3.5
VCC=Min., IOH=−32 mA
2.0
3.0
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
VCC=Min., IOL=64 mA
Max.
Unit
V
0.2
0.55
V
Min.
Typ.[5]
Max.
Unit
Output Drive Characteristics for CY74FCT162841T
Parameter
Description
Test Conditions
Output LOW
Current[7]
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
60
115
150
mA
IODH
Output HIGH
Current[7]
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
−60
−115
−150
mA
VOH
Output HIGH Voltage
VCC=Min., IOH=−24 mA
2.4
3.3
VOL
Output LOW Voltage
VCC=Min., IOL=24 mA
IODL
V
0.3
0.55
V
Typ.[5]
Max.
Unit
Capacitance[6] (TA =+25˚C, f = 1.0 MHz)
Symbol
Description
Conditions
CIN
Input Capacitance
VIN = 0V
4.5
6.0
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8.0
pF
Min.
Typ.[5]
Power Supply Characteristics
Parameter
Description
Test Conditions
Max.
Unit
ICC
Quiescent Power Supply
Current
VCC=Max.
VIN<0.2V
VIN>VCC-0.2V
—
5
500
µA
∆ICC
Quiescent Power Supply
Current (TTL inputs HIGH)
VCC=Max.,
VIN=3.4V[9]
—
0.5
1.5
mA
ICCD
Dynamic Power Supply
Current[10]
VCC=Max., One Input
Toggling, 50% Duty
Cycle, Outputs Open,
OE=GND
VIN=VCC or
VIN=GND
—
60
100
µA/MHz
IC
Total Power Supply Current[11] VCC=Max., f1=10 MHz,
50% Duty Cycle,
Outputs Open, One Bit
Toggling, OE=GND
LE = VCC
VIN=VCC or
VIN=GND
—
0.6
1.5
mA
VIN=3.4V or
VIN=GND
—
0.9
2.3
VIN=VCC or
VIN=GND
—
3.0
5.5[12]
VIN=3.4V or
VIN=GND
—
8.0
20.5[12]
VCC=Max., f1=2.5 MHz,
50% Duty Cycle, Outputs
Open, Twenty Bits
Toggling, OE=GND
LE = VCC
Notes:
9. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
10. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
= IQUIESCENT + IINPUTS + IDYNAMIC
11. IC
IC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
= Duty Cycle for TTL inputs HIGH
DH
= Number of TTL inputs at DH
NT
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f0
= Input signal frequency
f1
= Number of inputs changing at f1
N1
All currents are in milliamps and all frequencies are in megahertz.
12. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
3
CY74FCT16841T
CY74FCT162841T
Switching Characteristics Over the Operating Range[13]
74FCT16841AT
Parameter
tPLH
tPHL
tPLH
tPHL
tPHZ
tPZL
tPHZ
tPLZ
Description
Propagation Delay
D to Q
(LE=HIGH)
Propagation Delay
LE to Q
Output Enable Time
OE to Q
Output Disable Time
OE to Q
74FCT16841CT
74FCT162841CT
Condition[14]
Min.
Max.
Min.
Max.
Unit
Fig.
No.[15]
CL=50 pF
RL=500Ω
1.5
9.0
1.5
5.5
ns
1, 5
CL=300 pF[16]
RL=500Ω
1.5
13.0
1.5
13.0
CL=50 pF
RL=500Ω
1.5
12.0
1.5
6.4
ns
1, 5
CL=300 pF[16]
RL=500Ω
1.5
16.0
1.5
15.0
CL=50 pF
RL=500Ω
1.5
11.5
1.5
6.5
ns
1, 7, 8
CL=300 pF[16]
RL=500Ω
1.5
23.0
1.5
12.0
CL=5 pF[16]
RL=500Ω
1.5
7.0
1.5
5.7
ns
1, 7, 8
CL=50 pF
RL=500Ω
1.5
8.0
1.5
6.0
CL=50 pF
RL=500Ω
2.5
—
2.0
—
ns
9
tSU
Set-Up Time
HIGH or LOW, D to LE
tH
Hold Time
HIGH or LOW, D to LE
2.5
—
1.5
—
ns
9
tW
LE Pulse Width HIGH
4.0[17]
—
4.0[17]
—
ns
5
—
0.5
—
0.5
ns
—
tSK(O)
Output
Skew[18]
Notes:
13. Minimum limits are specified but not tested on Propagation Delays.
14. See test circuit and waveform.
15. See “Parameter Measurement Information” in the General Information section.
16. These conditions are specified but not tested.
17. These limits are specified but not tested.
18. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
Ordering Information for CY74FCT16841T
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
5.5
CY74FCT16841CTPVC/PVCT
O56
56-Lead (300-Mil) SSOP
Industrial
6.5
CY74FCT16841ATPVC/PVCT
O56
56-Lead (300-Mil) SSOP
Industrial
Ordering Information CY74FCT162841T
Speed
(ns)
5.5
Ordering Code
Package
Name
Package Type
74FCT162841CTPACT
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162841CTPVC
O56
56-Lead (300-Mil) SSOP
74FCT162841CTPVCT
O56
56-Lead (300-Mil) SSOP
4
Operating
Range
Industrial
CY74FCT16841T
CY74FCT162841T
Package Diagrams
56-Lead Shrunk Small Outline PackageO56
56-Lead Thin Shrunk Small Outline Package Z56
5
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74FCT162841CTPACT
ACTIVE
TSSOP
DGG
56
74FCT162841CTPVCG4
ACTIVE
SSOP
DL
56
74FCT162841CTPVCT
ACTIVE
SSOP
DL
56
2000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
20
74FCT162841ETPVCT
OBSOLETE
SSOP
DL
56
TBD
Call TI
74FCT16841ATPVCG4
ACTIVE
SSOP
DL
56
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74FCT16841CTPVCG4
ACTIVE
SSOP
DL
56
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74FCT16841CTPVCTG4
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT162841CTPVC
ACTIVE
SSOP
DL
56
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT162841ETPVC
OBSOLETE
SSOP
DL
56
TBD
Call TI
CY74FCT16841ATPVC
ACTIVE
SSOP
DL
56
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT16841CTPVC
ACTIVE
SSOP
DL
56
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT16841CTPVCT
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
FCT162841CTPACTE4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
FCT162841CTPACTG4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
FCT162841CTPVCTG4
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
20
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
74FCT162841CTPACT
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
74FCT162841CTPVCT
SSOP
DL
56
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
CY74FCT16841CTPVCT
SSOP
DL
56
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74FCT162841CTPACT
TSSOP
DGG
56
2000
346.0
346.0
41.0
74FCT162841CTPVCT
SSOP
DL
56
1000
346.0
346.0
49.0
CY74FCT16841CTPVCT
SSOP
DL
56
1000
346.0
346.0
49.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74FCT162841CTPACT
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT162841C
74FCT162841CTPVCG4
ACTIVE
SSOP
DL
56
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT162841C
74FCT162841ETPVCT
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
74FCT16841ATPVCG4
ACTIVE
SSOP
DL
56
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT16841A
CY74FCT162841CTPVC
ACTIVE
SSOP
DL
56
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT162841C
CY74FCT162841ETPVC
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
CY74FCT16841ATPVC
ACTIVE
SSOP
DL
56
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT16841A
CY74FCT16841CTPVC
ACTIVE
SSOP
DL
56
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT16841C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74FCT162841CTPACT
Package Package Pins
Type Drawing
TSSOP
DGG
56
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
8.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.6
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74FCT162841CTPACT
TSSOP
DGG
56
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
SCALE 1.200
SMALL OUTLINE PACKAGE
C
8.3
TYP
7.9
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
6.2
6.0
29
56X
0.27
0.17
0.08
1.2 MAX
C A
B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
29
28
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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