ON NCP1219BD100R2G Pwm controller with adjustable skip level and external latch input Datasheet

NCP1219
PWM Controller with
Adjustable Skip Level and
External Latch Input
The NCP1219 represents a new, pin to pin compatible, generation
of the successful 7−pin current mode NCP12XX product series. The
controller allows for excellent standby power consumption by use of
its adjustable skip mode and integrated high voltage startup FET.
Internal frequency jittering, ramp compensation, timer−based fault
detection and a latch input make this controller an excellent
candidate for converters where ruggedness and component cost are
the key constraints.
The Dynamic Self Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1219. This feature is particularly useful in
applications where the output voltage varies during operation (e.g.
battery chargers). Due to its high voltage technology, the IC can be
directly connected to the high voltage dc rail.
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SOIC−7
D SUFFIX
CASE 751U
MARKING DIAGRAM
8
1
Features
• Fixed−Frequency Current−Mode Operation with Ramp
•
•
•
•
•
•
•
•
•
•
•
•
Compensation (65 kHz and 100 kHz Options)
Dynamic Self Supply Eliminates the Need for an Auxiliary Winding
Timer−Based Fault Protection for Improved Overload Detection
Cycle Skip Reduces Input Power in Standby Mode
Latch and Auto−Recovery Overload Protection Options
Internal High Voltage Startup Circuit
Accurate Current Limit Detector (±5%)
Adjustable Skip Level
Latch Input for Easy Implementation of Overvoltage and
Overtemperature Protection
Frequency Modulation for Softened EMI Signature
500 mA/800 mA Peak Source/Sink Current Drive Capability
Pin to Pin Compatible with the Existing NCP12XX Series
These Devices are Pb−Free and Halogen Free/BFR Free*
• AC−DC Adapters for Notebooks, LCD Monitors
• Offline Battery Chargers
• Consumer Electronic Appliances STB, DVD, DVDR
PIN CONNECTIONS
Skip/latch
1
HV
FB
VCC
CS
Drv
GND
ORDERING INFORMATION
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
October, 2009 − Rev. 3
1219 = Specific Device Code
X
= Overcurrent
= (A = latch, B = auto−retry)
Z
= Frequency
= (6 = 65 kHz, 1 = 100 kHz)
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Top View)
Typical Applications
© Semiconductor Components Industries, LLC, 2009
1219XZ
ALYW
G
1
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
Publication Order Number:
NCP1219/D
NCP1219
+
AC
Input
EMI
Filter
Output
Voltage
−
latch input*
* Optional
Skip/latch HV
FB
VCC
CS
GND
DRV
NCP1219
Rramp*
Figure 1. Typical Application Circuit
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2
NCP1219
2V
Skip/latch
Rupper
42.0k*
Vlatch
50 ms*
filter
+
Latched overload
(Option A)
latch−off, reset when
VCC < VCC(reset) R
S
Rlower
51.3k*
Rskip
Istart when VCC > Vinhibit
Iinhibit when VCC < Vinhibit
Q
S
(Option A)
VFB(open)
FB
VFB
Skip
Comparator
VSkip/latch
Soft−Start/PWM Clamp
VFB / 3
VILIM
tSSTART
clamp
detect
Iramp(peak)
Iramp
CS
Rramp
VCC(on)
VDD
+
TSD
+
-
16.7k*
75 ms*
filter
soft−
start
set
Normal = VCC(min)
Fault = VCC(hiccup)
−
+
time
VCC(reset)
tOVLD
UVLO
timer
reset
+
VCS
VCC
+
-
PWM
0
Q
+
-
VSkip
VSkip(max)
HV
R
Fault
Management
Double Hiccup
Counter
LEB
CS
RCS
disable
internal
bias
Maximum
Duty Ratio
detect
Oscillator
GND
7.5%* Jittering
R
S
* Typical values are shown
Figure 2. Functional Block Diagram
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3
Q
VCC
DRV
NCP1219
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Description
1
Skip/latch
This pin provides a latch input to permanently disable the device under a fault condition. It also allows the user to
adjust the skip threshold. A resistor between this pin and GND provides noise immunity to the latch input and sets
the skip threshold. The voltage on this pin is determined by the combination of the internal voltage divider and the
external resistor to ground. The default skip threshold is 1.1 V (typical) if no external resistor is used. An internal
clamp prevents the skip level from increasing above 1.3 V if the Skip/latch pin is pulled high to latch the controller.
2
FB
The voltage on this pin is proportional to the output load on the converter. An internal resistor divider sets the
voltage on this pin above the regulation threshold (3 V) and an external optocoupler pulls the pin low to achieve
regulation. While the FB voltage is above its regulation threshold, the overload timer is enabled. If the overload
timer expires, the controller enters a double hiccup mode (option B) or is latched (option A) depending on the version of the device. The converter enters skip mode if the FB voltage is below the skip threshold.
3
CS
A voltage ramp proportional to the primary current is applied to this pin. The maximum current is reached once the
ramp voltage reaches 1 V (typical). A 100 mA (typical) current source provides ramp compensation. The amount of
ramp compensation is adjusted with a series resistor between the CS pin and the current sense resistor.
4
GND
Analog ground.
5
DRV
Main output of the PWM Controller. DRV has a source resistance of 12.6 W (typical) and a sink resistance of 6.7 W
(typical).
6
VCC
Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source
supplies current from the HV pin to this pin. Once the VCC voltage reaches VCC(on) (12.7 V typical), the current
source turns off and the DRV is enabled. The current source turns on once VCC falls to VCC(min) (9.9 V typical).
This mode of operation is known as dynamic self supply (DSS).
If the bias current consumption exceeds the startup current, and VCC drops 0.5 V (typical) below VCC(min) the converter turns off and enters a double hiccup mode. If the VCC voltage is below 0.67 V (typical) the startup current is
reduced to 200 mA (typical), reducing power dissipation.
8
HV
This is the input of the high voltage startup regulator and connects directly to the bulk voltage. A controlled current
source supplies current from this pin to the VCC capacitor, eliminating the need for an external startup resistor. The
charge current is 12.8 mA (typical).
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4
NCP1219
Table 2. MAXIMUM RATINGS (Notes 1 − 4)
Symbol
Value
Unit
HV Voltage
VHV
−0.3 to 500
V
HV Current
IHV
100
mA
Supply Voltage
VCC
−0.3 to 20
V
Rating
Supply Current
ICC
100
mA
Skip/latch Voltage
VSkip/latch
−0.3 to 9.5
V
Skip/latch Current
ISkip/latch
100
mA
FB Voltage
VFB
−0.3 to 5.0
V
FB Current
IFB
100
mA
CS Voltage
VCS
−0.3 to 5.0
V
CS Current
ICS
100
mA
DRV Voltage
VDRV
−0.3 to 20
V
DRV Current
IDRV
−500 to 800
mA
Operating Junction Temperature
TJ
–40 to 150
°C
Storage Temperature Range
Tstg
–60 to 150
°C
Power Dissipation (TA = 25°C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad)
D Suffix, Plastic Package Case 751U (SOIC−7) (Note 4)
PD
Thermal Resistance, Junction to Ambient (2.0 Oz Cu Printed Circuit Copper Clad)
D Suffix, Plastic Package Case 751U (SOIC−7)
Junction to Air, Low conductivity PCB (Note 3)
Junction to Lead, Low conductivity PCB (Note 3)
Junction to Air, High conductivity PCB (Note 4)
Junction to Lead, High conductivity PCB (Note 4)
0.92
W
°C/W
RθJA
RθJL
RθJA
RθJL
177
75
136
69
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1– 6: Human Body Model 3000 V per JEDEC JESD22−A114−F.
Pins 1– 6: Machine Model Method 300 V per JEDEC JESD22−A115−A.
Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V.
2. This device contains Latch−Up protection and exceeds ±100 mA per JEDEC Standard JESD78.
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm2 of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
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NCP1219
Table 3. ELECTRICAL CHARACTERISTICS (VHV = 60 V, VCC = 11.3 V, VFB = 2 V, VSkip/latch = 0 V, VCS = 0 V, VDRV = open, CCC =
0.1 mF, for typical values TJ = 25°C, for min/max values, TJ is –40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
VCC Increasing
VCC Decreasing
VCC Decreasing
VCC Decreasing
VCC Decreasing
VCC(on)
VCC(MIN)
UVLO
VCC(hiccup)
VCC(reset)
11.2
9.0
8.4
4.9
–
12.7
9.9
9.4
5.7
4.0
13.8
10.8
10.6
6.3
–
tUVLO(delay)
–
50
–
Iinhibit = 500 mA
Vinhibit
0.35
0.67
0.90
V
VCC = 0 V
Iinhibit
100
200
350
mA
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Undervoltage Lockout
Double Hiccup Threshold
Logic Reset Voltage
V
UVLO Filter Delay
Inhibit Threshold Voltage
Inhibit Bias Current
Minimum Startup Voltage
ms
Istart = 0.5 mA, VCC = VCC(on) – 0.5 V
Vstart(min)
–
20
28
V
Startup Current
VCC = VCC (on) – 0.5 V
Istart
5.5
12.8
18.5
mA
Startup Circuit Reverse Current
VHV = 0 V, VCC = 14 V
IHV(reverse)
–
–
100
mA
Off−State Leakage Current
VHV = 500 V, VCC = 14 V
IHV(off)
–
12
50
mA
Breakdown Voltage (Note 5)
IHV = 50 mA
VBR(DS)
500
–
–
V
VSkip/latch = 5.2 V, VFB = open
VSkip/latch = open, VFB = 0 V
VSkip/latch = open, CDRV = 1000 pF
VSkip/latch = open, CDRV = 1000 pF
ICC1
ICC2
ICC3A
ICC3B
–
–
–
–
0.6
1.4
2.2
2.4
0.8
2.1
2.7
3.2
Apply voltage step on CS pin
VILIM
0.95
1.0
1.05
V
tLEB
100
184
330
ns
VCS > VILIM to 50% DRV turns off,
CDRV = 1000 pF
tdelay
–
59
150
ns
Ramp Compensation Peak Current
Iramp(peak)
–
100
–
mA
Ramp Compensation Valley Current
Iramp(valley)
–
0
–
mA
VFB(open)
3.2
3.6
3.9
V
RFB
–
16.7
–
kW
IFB
141
280
392
mA
Iratio
–
3.0
–
tSSTART
–
4.8
–
61.75
58
55
95
89
85
65
–
–
100
–
–
68.25
71
71
105
107
107
Frequency Modulation in
Percentage of fOSC
–
±7.5
–
%
Frequency Modulation Period
–
6.0
–
ms
75
80
85
%
Supply Current
Device Disabled/Fault
Device Enabled/No Switching
Device Switching (65 kHz)
Device Switching (100 kHz)
mA
CURRENT SENSE
Current Sense Voltage Threshold
Leading Edge Blanking Duration
Propagation Delay
FEEDBACK INPUT
Open Feedback Voltage
Internal Pull−up Resistance
Feedback Pull−up Current
VFB = 0 V
Feedback to Current Set Point Ratio
SOFT−START
Soft−Start Period
Measured at 0.9 VILIM
ms
OSCILLATOR
Oscillator Frequency
65 kHz Option
100 kHz Option
fOSC
TJ = 25_C
TJ = −40_C to 85_C
TJ = −40_C to 125_C
TJ = 25_C
TJ = −40_C to 85_C
TJ = −40_C to 125_C
Maximum Duty Ratio
D
5. Guaranteed by the IHV(off) test.
6. Guaranteed by design only.
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6
kHz
NCP1219
Table 3. ELECTRICAL CHARACTERISTICS (VHV = 60 V, VCC = 11.3 V, VFB = 2 V, VSkip/latch = 0 V, VCS = 0 V, VDRV = open, CCC =
0.1 mF, for typical values TJ = 25°C, for min/max values, TJ is –40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
VFB = 0 V, VDRV = 1 V
VDRV = VCC – 1 V
RSNK
RSRC
2.0
6.0
6.7
12.6
13
25
Rise Time (10% to 90%)
CDRV = 1000 pF (10% to 90%)
tr
–
30
–
ns
Fall Time (90% to 10%)
CDRV = 1000 pF (90% to 10%)
tf
–
20
–
ns
Vlatch
3.4
3.9
4.6
V
VSkip/latch = 5.2 V, apply voltage step
on Skip/latch pin
tlatch(delay)
–
50
–
ms
VFB increasing, VSkip/latch = Open
Vskip
0.9
1.1
1.3
V
GATE DRIVE
Drive Resistance
DRV Sink
DRV Source
W
LATCH INPUT
Latch Voltage Threshold
Latch Filter Delay
CYCLE SKIP
Default Skip Threshold
Skip Clamp Voltage
VFB increasing, VSkip/latch = 2.0 V
Vskip(MAX)
1.1
1.3
1.5
V
Skip Comparator Hysteresis
VFB decreasing, VSkip/latch = 0.5 V
Vskip(HYS1)
–
75
–
mV
Skip Clamp Comparator
Hysteresis
VFB decreasing, VSkip/latch = 2.0 V
Vskip(HYS2)
–
75
–
mV
VSkip/latch = 0 V
Iskip
30
47
56
mA
Thermal Shutdown (Note 6)
Temperature Increasing
TSHDN
–
155
–
°C
Thermal Shutdown Hysteresis
Temperature Decreasing
Skip Current
FAULTS PROTECTION
Thermal Shutdown Delay
Overload Timer
Apply voltage step on FB pin
5. Guaranteed by the IHV(off) test.
6. Guaranteed by design only.
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TSHDN(HYS)
–
40
–
°C
TSHDN(delay)
–
75
–
ms
tOVLD
–
118
–
ms
NCP1219
TYPICAL CHARACTERISTICS
1.40
14
1.26
Vinhibit, INHIBIT THRESHOLD
VOLTAGE (V)
15
VCC, SUPPLY VOLTAGE
THRESHOLDS (V)
13
VCC(on)
12
11
VCC(MIN)
10
9
UVLO
8
7
VCC(reset)
−25
0
25
50
75
100
150
1.12
0.98
0.84
0.70
0.56
0.42
0.28
0.14
0
−50
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Supply Voltage Thresholds vs.
Junction Temperature
Figure 4. Inhibit Threshold Voltage vs.
Junction Temperature
15.0
280
14.5
VCC = 0 V
260
240
220
200
180
160
140
120
−25
0
25
50
75
100
125
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
−50
150
150
VHV = 60 V
VCC = VCC(on) − 0.5 V
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Inhibit Current vs. Junction
Temperature
Figure 6. Startup Current vs. Junction
Temperature
150
30
16
VHV = 60 V
VHV = 60 V
VCC = 14 V
27
Istart(off), STARTUP CIRCUIT
LEAKAGE CURRENT (mA)
14
12
10
8
6
4
2
0
−25
TJ, JUNCTION TEMPERATURE (°C)
300
100
−50
Istart, STARTUP CURRENT (mA)
125
Istart, STARTUP CURRENT (mA)
Iinhibit, INHIBIT CURRENT (mA)
6
5
−50
Iinhibit = 500 mA
24
21
18
15
12
9
6
3
0
2
4
6
8
10
12
14
16
18
0
−50
20
−25
0
25
50
75
100
125
150
VCC, SUPPLY VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Startup Current vs. Supply Voltage
Figure 8. Startup Circuit Leakage Current vs.
Junction Temperature
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NCP1219
TYPICAL CHARACTERISTICS
3.0
50
45
2.7
ICC, SUPPLY CURRENT (mA)
Istart(off), STARTUP CIRCUIT
LEAKAGE CURRENT (mA)
VCC = 14 V
40
35
30
25
20
TJ = −40°C
15
10
0
75
150
225
300
375
450
2.1
1.8
ICC3 (fOSC ~ 65 kHz)
1.5
1.2
ICC2
0.9
0.6
0.3
ICC1
−25
0
25
50
75
100
125
VHV, HV VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Startup Circuit Leakage Current vs.
HV Voltage
Figure 10. Supply Current vs. Junction
Temperature
150
1.05
4.0
3.0
VILIM, CURRENT SENSE VOLTAGE
THRESHOLD (V)
TJ = 25°C
3.5
fOSC = 100 kHz
2.5
fOSC = 65 kHz
2.0
1.5
1.0
0.5
0
2.4
0.0
−50
525
9
10
11
12
13 14
15 16
17 18
19 20
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
−50
21
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Operating Supply Current vs.
Supply Voltage
Figure 12. Current Sense Voltage Threshold
vs. Junction Temperature
300
125
280
115
260
240
220
200
180
160
140
120
100
−50
−25
VCC, SUPPLY VOLTAGE (V)
tdelay, CURRENT SENSE
PROPAGATION DELAY (ns)
tLEB, LEADING EDGE BLANKING TIME (ns)
ICC3, OPERATING SUPPLY CURRENT (mA)
5
0
TJ = 125°C
ICC3 (fOSC ~ 100 kHz)
105
95
85
75
65
55
45
35
−25
0
25
50
75
100
125
25
−50
150
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Leading Edge Blanking Time vs.
Junction Temperature
Figure 14. Current Sense Propagation Delay
vs. Junction Temperature
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NCP1219
120
85
D, MAXIMUM DUTY RATIO (%)
110
100 kHz Option
100
90
80
65 kHz Option
70
60
50
40
−50
−25
0
25
50
75
125
83
82
81
80
79
78
77
76
75
−50
150
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Oscillator Frequency vs. Junction
Temperature
Figure 16. Maximum Duty Ratio vs. Junction
Temperature
VCC = 11.3 V
18
16
14
12
10
Source, VDRV = VCC − 1 V
8
6
Sink, VDRV = 1 V
4
2
0
−50
−25
0
25
50
75
100
125
150
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. Drive Sink and Source Resistances
vs. Junction Temperature
Figure 18. Latch Voltage Threshold vs.
Junction Temperature
1.30
Vskip(MAX), SKIP CLAMP VOLTAGE (V)
Vskip, DEFAULT SKIP THRESHOLD (V)
84
TJ, JUNCTION TEMPERATURE (°C)
20
RSNK/RSRC, DRIVE SINK/SOURCE
RESISTANCE (W)
100
Vlatch, LATCH VOLTAGE THRESHOLD (V)
fOSC, OSCILLATOR FREQUENCY (kHz)
TYPICAL CHARACTERISTICS
VSkip/latch = open
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
−50
−25
0
25
50
75
100
125
150
1.55
1.50
VSkip/latch = 2 V
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Default Skip Threshold vs. Junction
Temperature
Figure 20. Skip Clamp Voltage vs. Junction
Temperature
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10
150
150
NCP1219
1.2
1.2
Rskip = 48.7 kW
1.1
Vskip, SKIP THRESHOLD (V)
Vskip2, ADJUSTABLE SKIP THRESHOLD (V)
TYPICAL CHARACTERISTICS
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
−50
−25
0
25
50
75
100
125
0.6
0.4
0.2
1
10
100
1000
10000
TJ, JUNCTION TEMPERATURE (°C)
RSkip, EXTERNAL SKIP RESISTOR (kW)
Figure 21. Adjustable Skip Threshold vs.
Junction Temperature
Figure 22. Skip Threshold vs. Skip Resistor
tOVLD, OVERLOAD TIMER PERIOD (ms)
tSSTART, SOFT−START PERIOD (ms)
0.8
0
150
10
9
8
7
6
5
4
3
2
1
0
−50
1.0
−25
0
25
50
75
100
125
150
140
135
130
125
120
115
110
105
100
95
90
−50
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. Soft−Start Period vs. Junction
Temperature
Figure 24. Overload Timer Period vs. Junction
Temperature
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NCP1219
DETAILED OPERATING DESCRIPTION
supply current consumption exceeds the startup current,
VCC will decay below VCC(MIN). The NCP1219 has an
undervoltage lockout (UVLO) to prevent operation at low
VCC levels. The UVLO threshold is typically 9.4 V. The
DRV signal is immediately disabled upon reaching UVLO.
It is re−enabled if VCC increases above UVLO before the
50 ms (typical) timer expires. Otherwise, the controller
enters double hiccup mode.
The controller enters a double hiccup mode if an
overload (option B), thermal shutdown, UVLO or latch
fault is detected. A double hiccup fault disables the DRV
signal, sets the controller in a low current mode and allows
VCC to discharge to VCC(hiccup), typically 5.7 V. This cycle
is repeated twice to minimize power dissipation in external
components during a fault event. Figures 25 and 26 show
double hiccup mode operation with a fault occurring while
the startup circuit is disabled and enabled, respectively. A
soft−start sequence is initiated the second time VCC reaches
VCC(on). If the fault is present or the controller is latched
upon reaching VCC(on), the controller stays in hiccup mode.
During this mode, VCC never drops below 4 V, the
controller logic reset level. This prevents latched faults
from being cleared unless power to the controller is
completely removed (i.e. unplugging the supply from the
AC line). There are two options available in the NCP1219,
options A and B. Option A latches off after the overload
timer expires if an overload fault is detected. In this case,
VCC cycles between VCC(on) and VCC(hiccup) without
enabling the DRV signal until the power to the controller
is reset. On the other hand, option B has auto−retry circuitry
allowing the DRV signal to restart after a double hiccup
sequence triggered by an overload condition.
The NCP1219 is part of a product family of current mode
controllers designed for ac−dc applications requiring low
standby power. The controller operates in skip or burst
mode at light load. Its high integration reduces component
count resulting in a more compact and lower cost power
supply. This device family has 2 options, A and B. Option
A latches where as option B auto restarts after an overload
fault.
The internal high voltage startup circuit with dynamic
self supply (DSS) allows the controller to operate without
an auxiliary supply, simplifying the transformer design.
This feature is particularly useful in applications where the
output voltage varies during operation (e.g. printer
adapters).
Other features found in the NCP1219 are frequency
jittering, adjustable ramp compensation, timer based fault
detection and a dedicated latch input.
High Voltage Startup Circuit
The NCP1219 internal high voltage startup circuit
eliminates the need for external startup components and
provides a faster startup time compared to an external
startup resistor. The startup circuit consists of a constant
current source that supplies current from the HV pin to the
supply capacitor on the VCC pin (CCC). The HV pin is rated
at 500 V allowing direct connection to the bulk capacitor.
The start−up current (Istart) is typically 12.8 mA.
The startup current source is disabled once the VCC
voltage reaches VCC(on), typically 12.7 V. The controller is
then biased by the VCC capacitor. The current source is
enabled once the VCC voltage decays to its minimum
operating threshold (VCC(MIN)) typically 9.9 V. If the
VCC(on)
VCC(MIN)
UVLO
VCC(hiccup)
VCC(reset)
Fault1
DRV
Fault
ON
OFF
ON
Figure 25. VCC Double Hiccup Operation with a Fault Occurring While the Startup Circuit is Disabled.
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NCP1219
VCC(on)
VCC(MIN)
UVLO
VCC(hiccup)
VCC(reset)
Fault2
DRV
Fault
ON
OFF
ON
Figure 26. VCC Double Hiccup Operation with a Fault Occurring While the Startup Circuit is Enabled
An internal supervisory circuit monitors the VCC voltage
to prevent the controller from dissipating excessive power
if the VCC pin is accidentally grounded. A lower level
current source (Iinhibit) charges CCC from 0 V to Vinhibit,
typically 0.67 V. Once VCC exceeds Vinhibit, the startup
current source is enabled. This behavior is illustrated in
Figure 27. This slightly increases the total time to charge
VCC, but it is generally not noticeable.
In comparison, the power dissipation when the startup
circuit is disabled and VCC is being supplied by the
auxiliary winding is a function of the VCC voltage. This is
shown in Equation 2.
PAUX + I CC3 @ V CC
Startup Current
Soft−Start Operation
Figures 28 and 29 show how the soft−start feature is
included in the pulse−width modulation (PWM)
comparator. When the NCP1219 starts up, a soft−start
voltage VSSTART begins at 0 V. VSSTART increases
gradually from 0 V to 1.0 V in 4.8 ms and stays at 1.0 V
afterward. VSSTART is compared with the divided by 3
feedback pin voltage (VFB/3). The lesser of VSSTART and
(VFB/3) becomes the modulation voltage, VPWM, in the
PWM duty ratio generation. Initially, (VFB/3) is above
1.0 V because the FB pin is brought to VFB(open), typically
3.6 V, by the internal pullup resistor. As a result, VPWM is
limited by the soft−start function and slowly ramps up the
duty ratio (and therefore the primary current) for the initial
4.8 ms. This provides a greatly reduced stress on the power
devices during startup.
Istart
VCC
Iinhibit
Vinhibit
(eq. 2)
It is recommended that an external filter capacitor be
placed as close as possible to the VCC pin to improve the
noise immunity.
VCC(MIN)
VCC(on)
Figure 27. Startup Current at Various VCC Levels
The start−up circuit is rated at a maximum voltage of
500 V. If the device operates in the DSS mode, power
dissipation should be controlled to avoid exceeding the
maximum power dissipation of the controller. If dissipation
on the controller is excessive, a resistor can be placed in
series with the HV pin. This will reduce power dissipation
on the controller and transfer it to the series resistor.
Standby mode losses and normal mode power dissipation
can be reduced by biasing the controller with an auxiliary
winding. The auxiliary winding needs to maintain VCC
above VCC(MIN) once the startup circuit is disabled.
The power dissipation of the controller when operated in
DSS mode, PDSS, can be calculated using equation 1, where
ICC3 is the operating current of the NCP1219 during
switching and VHV is the voltage at the HV pin. The HV pin
is most often connected to the bulk capacitor.
PDSS + I CC3 @ (V HV * V CC)
VSSTART
VFB/3
−
)
0
1
VPWM
Figure 28. VPWM is the lesser of VSSTART and (VFB/3)
(eq. 1)
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NCP1219
Vbulk
Soft−start voltage, VSSTART
Iramp(peak)
1V
PWM
Output
tSSTART
Feedback pin voltage divided by 3, VFB/3
R
S
80%
max duty
Q
−
+
time
180 ns VCS
LEB
VPWM
(1 V max. signal)
Iramp
CS
Clock
ID
RCS
1V
Figure 30. Current−Mode Implementation
Figure 31 shows the timing diagram for the
current−mode pulse width modulation operation. An
internal clock sets the output RS latch, pulling the DRV pin
high. The latch is then reset when the voltage on the CS pin
intersects the modulation voltage, VPWM. This generates
the duty ratio of the DRV pulse. The maximum duty ratio
is internally limited to 80% (typical) by the output RS latch.
time
time must be less than tOVLD
to prevent fault condition
Pulse Width Modulation voltage, VPWM
1V
PWM
Output
time
tSSTART
Drain Current, ID
VPWM
time
VCS
tSSTART
Figure 29. Soft−Start (Time = 0 at VCC = VCC(on))
clock
Current−Mode Pulse Width Modulation
The NCP1219 is a current−mode, fixed frequency pulse
width modulation controller with ramp compensation. The
PWM block of the NCP1219 is shown in Figure 30. The
DRV signal is enabled by a clock pulse. At this time,
current begins to flow in the power MOSFET and the sense
resistor. A corresponding voltage is generated on the CS
pin of the device, ranging from very low to as high as the
maximum modulation voltage, VPWM (maximum of 1 V).
This sets the primary current on a cycle−by−cycle basis.
Equation 3 gives the maximum drain current, ID(MAX),
where RCS is the current sense resistor value and VILIM is
the current sense voltage threshold.
ID(MAX) +
V ILIM
R CS
Figure 31. Current−Mode Timing Diagram
The VPWM voltage is the scaled representation of the FB
pin voltage. The scale factor, Iratio, is 3. The FB pin voltage
is provided by an external error amplifier, whose output is
a function of the power supply output. An FB signal
between Vskip and 3 V determines the duty ratio of the
controller output. The FB voltage operates in a closed loop
with the output voltage to regulate the power supply.
It is recommended that an external filter capacitor be
placed as close to the FB pin as possible to improve the
noise immunity.
(eq. 3)
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NCP1219
Ramp Compensation
Ramp compensation is a known mean to cure
subharmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
continuous conduction mode (CCM) with a duty ratio
greater than 50%. To lower the current loop gain, one
usually injects 50 to 75% of the inductor current down
slope. The NCP1219 generates an internal current ramp
that is synchronized with the clock. This current ramp is
then routed to the CS pin. Figures 32 and 33 depict how the
ramp is generated and utilized. Ramp compensation is
simply formed by placing a resistor, Rramp, between the CS
pin and the sense resistor.
Rramp +
ǒS off,primary
ǒ
I
ramp(peak)
D
ǒ Ǔ
(Vout ) V f)
Iramp(peak)
NS
100% of period
Figure 32. Internal Ramp Compensation Current
Source
Rramp +
Iramp(peak)
mA
8.1 ms
+ 3.5 kW
(eq. 7)
The internal oscillator of the NCP1219 provides the
clock signal that sets the DRV signal high and limits the
duty ratio to 80% (typical). The oscillator has a fixed
frequency of 65 kHz or 100 kHz. The NCP1219 employs
frequency jittering to smooth the EMI signature of the
system by spreading the energy of the main switching
component across a range of frequencies. An internal low
frequency oscillator continuously varies the switching
frequency of the controller by ±7.5%. The period of
modulation is 6 ms, typical. Figure 34 illustrates the
oscillator frequency modulation.
Oscillator
RCS
Figure 33. Inserting a Resistor in Series with the
Current Sense Information Provides Ramp
Compensation
In order to calculate the value of the ramp compensation
resistor, Rramp, the off time primary current slope,
Soff,primary must be calculated using Equation 4,
LP
28.5 mV
ms
Internal Oscillator
Rramp
CS
Soff,primary +
(eq. 6)
Ramp compensation greater than 50% of the inductor
down slope can be used if necessary; however,
overcompensating will degrade the transient response of
the system. The addition of ramp compensation also
reduces the total available output power of the system.
DRV
(V out ) V f) @
+ 571 mA
ms
When projected over an RCS of 0.1 W (for example), this
becomes 57 mV/ms. If we select 50% of the downslope as
the required amount of ramp compensation, then we shall
inject 28.5 mV/ms. Therefore, Rramp is simply equal to
Equation 7.
time
80% of period
Current
Ramp
Ǔ
(eq. 5)
OSC
NP
LP
Clock
f
where RCS is the current sense resistor and %slope is the
percentage of the current downslope to be used for ramp
compensation.
The NCP1219 has a peak ramp compensation current of
100 mA. A frequency of 65 kHz with an 80% maximum
duty ratio corresponds to an 8.1 mA/ms ramp. For a typical
flyback design, let’s assume that the primary inductance is
350 mH, the converter output is 19 V, the Vf of the output
diode is 1 V and the NP:NS ratio is 10:1. The off time
primary current slope is given by Equation 6.
Ramp current, Iramp
0
R CSǓ @ %slope
ǒ Ǔ
NP
NS
(eq. 4)
where Vout is the converter output voltage, Vf is the forward
diode drop of the secondary diode, NP/NS is the primary to
secondary turns ratio, and LP is the primary inductance of
the transformer. The value of Rramp can be calculated using
Equation 5,
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NCP1219
Oscillator Frequency
Startup current source is
charging the VCC capacitor
Startup current source is
off when V CC is VCC(on)
VCC(on)
FOSC + 7.5%
FOSC
FOSC − 7.5%
VCC(hiccup)
6 ms
time
Figure 35. Latch−off VCC Timing Diagram
The external latch feature allows the circuit designers to
implement different kinds of latching protection. Figure 36
shows an example circuit in which a bipolar transistor is
used to pull the Skip/latch pin above the latch threshold.
The RLIM value is chosen to prevent the Skip/latch pin from
exceeding the maximum rated voltage. The NCP1219
applications note (AND8393/D) details several simple
circuits to implement overtemperature protection (OTP)
and overvoltage protection (OVP).
Figure 34. Oscillator Frequency Modulation
Gate Drive
The output drive of the NCP1219 is designed to directly
drive the gate of an n−channel power MOSFET. The DRV
pin is capable of sourcing 500 mA and sinking 800 mA of
drive current. It has typical rise and fall times of 30 ns and
20 ns, respectively, driving a 1 nF capacitive load.
The power dissipation of the output stage while driving
the capacitance of the power MOSFET must be considered
when calculating the NCP1219 power dissipation. The
driver power dissipation can be calculated using
Equation 8,
PDRV + f OSC @ Q G @ V CC
time
Startup current source turns
on when VCC reaches VCC(hiccup)
VCC
RLIM
(eq. 8)
Fault
output
where QG is the gate charge of the power MOSFET.
Skip/latch HV
External Latch Input
Board level protection functionality is often
incorporated using external circuits to suit a specific
application. An external fault condition can be used to
disable the controller by bringing the voltage on the
Skip/latch pin above the latch threshold, Vlatch (3.9 V
typical). When an external fault condition is detected, the
DRV signal is stopped, and the controller enters low current
operation mode. The external capacitor CCC discharges
and VCC drops until VCC(hiccup) is reached. The high
voltage startup circuit turns on and Istart charges CCC until
VCC(on) is reached. VCC cycles between VCC(on) and
VCC(hiccup) until VCC reaches VCC(reset). Voltage must be
removed from the HV pin, disabling the startup current and
allowing CCC to discharge to VCC(reset). Therefore, the
controller is reset by unplugging the power supply from the
wall to allow Vbulk to discharge. Figure 35 illustrates the
timing diagram of VCC in the latch−off condition.
Cskip
Rskip
FB
CS
VCC
GND
DRV
NCP1219
Figure 36. Circuit Example of an External
Latch−off Circuit
An internal blanking filter prevents fast voltage spikes
caused by noise from latching the part. However, it is
recommended that an external filter capacitor be placed as
close as possible to the Skip/latch pin to further improve the
noise immunity.
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NCP1219
Skip Cycle Operation
Skip peak current, %ICSSKIP, is the percentage of the
maximum peak current at which the controller enters skip
mode. %ICSSKIP can be any value from 0 to 43% as defined
by Equation 9. However, the higher %ICSSKIP is, the greater
the drain current when skip is entered. This increases
acoustic noise. Conversely, the lower %ICSSKIP is, the
larger the percentage of energy is expended turning the
switch on and off. Therefore, it is important to adjust
%ICSSKIP to the optimal level for a given application.
During standby or light load operation the duty ratio on
the controller becomes very small. At this point, a
significant portion of the power dissipation is related to the
power MOSFET switching on and off. To reduce this power
dissipation, the NCP1219 “skips” pulses when the FB level
drops below the skip threshold. The level at which this
occurs is completely adjustable by setting a resistor on the
Skip/latch pin.
By discontinuing pulses, the output voltage slowly drops
and the FB voltage rises. When the FB voltage rises above
the Vskip level, DRV is turned back on. This feature
produces the timing diagram shown in Figure 37.
%ICSSKIP +
3V
@ 100
Skip
ID
Figure 37. Skip Operation
latch-off, reset
when V CC < VCC(reset)
2V
Skip/latch
+
VSkip/latch Rskip
Cskip
(eq. 9)
Figure 38 shows the details of the Skip/latch pin
circuitry. The voltage on the Skip/latch pin determines the
voltage required on the FB pin to place the controller into
skip mode. If the pin is left open, the default skip threshold
is 1.1 V. This corresponds to a 37% %ICSSKIP (%ICSSKIP =
1.1 V / 3.0 V * 100% = 37%). Therefore, the controller will
enter skip mode when the peak current is less than 37% of
the maximum peak current.
Vskip
VFB
V skip
Rupper
42.0 k
Vlatch
+
R lower
51.3 k
50 us
filter
S
R Q
VSkip
-
Vskip(MAX)
Vskip/Latch
+
-
VFB
Skip
Comparator
Figure 38. Skip Adjust Circuit
The skip level is reduced by placing an external resistor,
Rskip, between the Skip/latch and GND pins. Figure 39
summarizes the operating voltage regions of the Skip/latch
pin.
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To DRV
latch
reset
NCP1219
Vskip/latch
Within the adjustable Vskip range, the skip level changes
according to Equation 10.
9.5 V (maximum pin voltage)
Vskip +
Controller is latched
2 V @ (R lower ø R skip)
(R lower ø R skip) ) R upper
(eq. 10)
An internal clamp limits the skip threshold (Vskip(MAX))
to 1.3 V. Increasing the voltage on the Skip/latch pin
beyond the value of the internal clamp will induce no
further change in the skip level. This prevents the act of
disabling the controller in the presence of an external latch
event from causing it to enter skip mode. The relationship
between %ICSSKIP, VSkip/latch, Vskip, and Rskip is
summarized in Table 4.
Vlatch
Skip threshold clamped to Vskip(MAX)
Vskip(MAX)(maximum skip threshold)
Adjustable Vskip range.
0 V (no skip)
Figure 39. NCP1219 VSkip/latch Pin Operating
Regions
Table 4. %ICSskip and Skip Threshold Relationship with Rskip
%ICSskip
VSkip/latch
Vskip
Rskip
Comment
0%
0V
0V
0W
12%
0.36 V
0.36 V
11.8 kW
–
25%
0.75 V
0.75 V
52.3 kW
–
37%
1.10 V
1.10 V
Open
43%
2.00 V
1.30 V
–
No further increase in Skip threshold
43 %
3.00 V
1.30 V
–
No further increase in Skip threshold
Never skips
Default Skip Threshold
External Non−Latched Shutdown
Figure 40 summarizes the operating regions of the FB
pin. An external non−latched shutdown can be easily
implemented by simply pulling FB below the skip level.
This is an inherent feature of the standby skip operation,
allowing additional flexibility in the SMPS design.
Skip/latch HV
FB
OFF
VCC
GND
DRV
NCP1219
opto
coupler
V FB
Fault operation when staying
in this region longer than 118 ms
Figure 41. Example Circuit for Non−Latched
Shutdown
3V
PWM operation
V skip
CS
Overload Protection
Figure 42 details the timer based fault detection circuitry.
When an overload (or short circuit) event occurs, the output
voltage collapses and the optocoupler does not conduct
current. This opens the FB pin and VFB is internally pulled
higher than 3.0 V. Since VFB/3 is greater than 1 V, the
controller activates an error flag and starts a timer, tOVLD
(118 ms typical). If the output recovers during this time, the
timer is reset and the device continues to operate normally.
No DRV pulses
0V
Figure 40. NCP1219 Operation Threshold
Figure 41 shows an example implementation of a
non−latched shutdown circuit using a bipolar transistor to
pull the FB pin low.
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NCP1219
However, if the fault lasts for more than 118 ms, then the
driver turns off and the device enters the VCC double hiccup
mode described earlier.
The NCP1219 also has an internal temperature shutdown
circuit. If the junction temperature of the controller reaches
155°C (typical), the driver turns off and the controller
enters double hiccup mode.
4.8 V
FB
Latched and Auto−Retry Options
The NCP1219A offers a latched fault circuitry. An
overload fault condition detected by the controller results
in a latch−off shutdown, requiring the controller to be reset
by cycling VCC (removing the ac line input). NCP1219B
provides an auto−retry circuit. All fault conditions except
the external latch fault result in the controller entering
double hiccup mode, attempting to restart the controller
every other VCC cycle, as mentioned earlier.
V FB
V FB
3
V SS
+
−
118 ms
delay
Fault
disable Drv
Soft−start
1 V max
Figure 42. Block Diagram of Timer−Based Fault
Detection
Table 5. ORDERING INFORMATION
Device
Overcurrent
Frequency
NCP1219AD65R2G
Latch
65 kHz
NCP1219BD65R2G
Auto−Recovery
65 kHz
NCP1219AD100R2G
Latch
100 kHz
NCP1219BD100R2G
Auto−Recovery
100 kHz
Package
Shipping†
SOIC−7 (Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCP1219
PACKAGE DIMENSIONS
SOIC−7
CASE 751U−01
ISSUE D
−A−
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5
−B− S
1
0.25 (0.010)
B
M
M
4
G
C
R
X 45 _
J
−T−
SEATING
PLANE
H
0.25 (0.010)
K
M
D 7 PL
M
T B
S
A
S
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0 _
8_
0.25
0.50
5.80
6.20
INCHES
MIN MAX
0.189 0.197
0.150 0.157
0.053 0.069
0.013 0.020
0.050 BSC
0.004 0.010
0.007 0.010
0.016 0.050
0_
8_
0.010 0.020
0.228 0.244
The products described herein (NCP1219) may be covered by one or more of the following U.S. patents: 6,271,735, 6,362,067, 6,385,060,
6,597,221, 6,633,193, 6,587,351, 6,940,320. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
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NCP1219/D