128Mx64 bits DDR2 SDRAM SO-DIMM HYMP112S64(L)MP8 Revision History No. 0.1 History 1) Defined target spec. 2) Corrected Pin assignment table Date Remark July 2004 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ July 2004 1 128Mx64 bits DDR2 SDRAM SO-DIMM HYMP112S64(L)MP8 DESCRIPTION Hynix HYMP112S64MP8 series is unbuffered 200-pin double data rate 2 Synchronous DRAM Small Outline Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMP112S64MP8 series consists of eight 128Mx8 DDR2 SDRAMs in 63 ball FBGA Dual Die Pacakge(DDP)s. Hynix HYMP112S64MP8 series provide a high performance 8-byte interface in 67.60mm X 30.00mm form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMP512S64MP8 series is designed for high speed and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_1.8. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMP512S64MP8 series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES • 1GB (128M x 64) Unbuffered DDR2 SO - DIMM based on 128Mx8 DDR2 DDP SDRAMs • Programmable Burst Length 4 / 8 with both sequential and interleave mode • JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply • Auto refresh and self refresh supported • All inputs and outputs are compatible with SSTL_1.8 interface • 7.8us refresh period at Lower than TCASE 85℃, 3.9us( 85 • OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) • Fully differential clock operations (CK & /CK) • Programmable CAS Latency 3 / 4 /5 supported ℃ ＜ TCASE ≤ 95℃) • Serial Presence Detect(SPD) with EEPROM • Lead free product ORDERING INFORMATION Type Part No. Description CL-tRCD-tRP 4-4-4 HYMP112S64(L)MP8-E4 PC2-3200 (DDR2-400) HYMP112S64(L)MP8-E3 HYMP112S64(L)MP8-C5 2 rank 1GB Lead-free SO-DIMM 3-3-3 5-5-5 PC2-4300 (DDR2-533) HYMP112S64(L)MP8-C4 Form Factor 200pin Unbuffered SODIMM 67.60 mm x 30,00 mm (MO-224) 4-4-4 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ July 2004 2 HYMP112S64(L)MP8 PIN Functional Description Symbol Type Polarity Pin Description CK[1:0], CK[1:0] Input Cross Point The system clock inputs. All adress an commands lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. CKE[1:0] Input Active High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. /S[1:0] Input Active Low Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 /RAS, /CAS, /WE Input Active Low When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS and WE define the operation to be excecuted by the SDRAM. BA[1:0] Input ODT[1:0] Input Selects which DDR2 SDRAM internal bank of four or eight is activated. Active High Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 SDRAM mode register. During a Bank Activate command cycle, difines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. A[9:0], A10/ AP, A[15:11] Input DQ[63:0] In/Out Data Input/Output pins. Input Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. Cross point The data strobe, associated with one data byte, sourced whit data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed approriately. Active Low When hign, the PLL outputs are always driven when the PLL input clock is active. When low, the PLL remains locked on the input clock, if active, but output clocks are stopped. Pulled high via 10Kߟ resistor on the SO-DIMM . Only used on DDR2 SO-DIMMs with a PLL. DM[7:0] DQS[7:0], DQS[7:0] In/Out RESET Input VDD, VDDSPD,VSS Supply Power supplies for core, I/O, Serial Presense Detect, and ground for the module. SDA In/Out This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister must be connected to VDD to act as a pull up. SCL Input This signals is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as a pull up. SA[1:0] Input Address pins used to select the Serial Presence Detect base address. TEST In/Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SODIMMs). Rev. 0.1/ July 2004 3 HYMP112S64(L)MP8 PIN ASSIGNMENT Pin NO. Front Side Pin NO. Back Side Pin NO. Front Side Pin NO. Back Side Pin NO. Front Side Pin NO. Back Side Pin NO. Front Side Pin NO. Back Side 1 VREF 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47 5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS 7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 RAS 157 DQ48 158 DQ52 9 VSS 10 DM0 59 VSS 60 VSS 109 WE 110 S0 159 DQ49 160 DQ53 11 DQS0 12 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 161 VSS 162 VSS 13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODT0 163 NC,TEST 164 CK1 15 VSS 16 DQ7 65 VSS 66 VSS 115 NC/S1 116 A13 165 VSS 166 CK1 17 DQ2 18 VSS 67 DM3 68 DQS3 117 VDD 118 VDD 167 DQS6 168 VSS 19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 169 DQS6 170 DM6 21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS 23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS 29 DQS1 30 CK0 79 CKE0 80 NC/CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60 31 DQS1 32 CK0 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61 33 VSS 34 VSS 83 NC 84 NC/A15 133 VSS 134 DQ38 183 VSS 184 VSS 35 DQ10 36 DQ14 85 BA2 86 NC/A14 135 DQ34 136 DQ39 185 DM7 186 DQS7 37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7 39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS 41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63 45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS5 195 SDA 196 VSS 47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 49 DQS2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1 Pin Location 2 Back Front 1 39 41 Rev. 0.1/ July 2004 200 40 42 199 4 HYMP112S64(L)MP8 FUNCTIONAL BLOCK DIAGRAM 3Ω+/− 5% CKE1 ODT1 /S1 CKE0 ODT0 /S0 DQS0 DQS DQS4 DQS /DQS0 /DQS /DQS4 /DQS DM DM4 DM0 DQ0 I/O 0 DQ1 I/O 1 DQ2 I/O 2 DQ3 /CS0 ODT0 CKE0 /CS1 ODT1 CKE1 I/O 0 DQ33 I/O 1 DQ34 I/O 2 I/O 3 DQ35 I/O 3 DQ4 I/O 4 DQ36 I/O 4 DQ5 I/O 5 I/O 5 DQ6 DQ7 I/O 6 DQ37 DQ38 DQ39 I/O 7 I/O 6 DQS1 DQS DQS5 DQS /DQS /DQS5 /DQS DM DM5 DM1 DQ8 I/O 0 /CS1 ODT1 CKE1 I/O 0 DQ41 I/O 1 DQ42 I/O 2 DQ8 I/O 1 I/O 2 DQ11 I/O 3 DQ43 I/O 3 DQ12 I/O 4 DQ44 I/O 4 DQ13 I/O 5 DQ45 DQ14 I/O 6 DQ46 I/O 6 DQ15 I/O 7 DQ47 I/O 7 DQS2 DQS DQS6 DQS /DQS /DQS6 /DQS DM DM6 DM2 DQ16 I/O 0 DQ17 I/O 1 DQ18 I/O 2 DQ19 /CS1 ODT1 CKE1 I/O 0 DQ49 I/O 1 DQ50 I/O 2 I/O 3 DQ51 I/O 3 DQ20 I/O 4 DQ52 I/O 4 DQ21 I/O 5 DQ53 I/O 5 DQ22 I/O 6 DQ54 I/O 6 DQ23 I/O 7 DQ55 I/O 7 DQS3 DQS DQS7 DQS /DQS3 /DQS /DQS7 /DQS DM DM7 DM3 DQ24 I/O 0 DQ25 I/O 1 DQ26 I/O 2 DQ27 /CS0 ODT0 CKE0 /CS1 ODT1 CKE1 I/O 0 DQ57 I/O 1 DQ58 I/O 2 I/O 3 DQ59 I/O 3 DQ28 I/O 4 DQ60 I/O 4 DQ29 I/O 5 DQ61 I/O 5 DQ30 DQ31 I/O 6 DQ62 DQ63 I/O 7 I/O 7 SCL 3Ω +/- 5% BA0-BA2 A0-AN /RAS /CAS /W E SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS D0-15 D0-15 D0-15 D0-15 D0-15 SA0 SA1 /CS0 ODT0 CKE0 /CS1 ODT1 CKE1 D6,D14(DDP) /CS0 ODT0 CKE0 /CS1 ODT1 CKE1 DM DQ56 D3,D11(DDP) D5,D13(DDP) DM DQ48 D2,D10(DDP) /CS1 ODT1 CKE1 I/O 5 /DQS2 /CS0 ODT0 CKE0 /CS0 ODT0 CKE0 DM DQ40 DQ10 D1,D9(DDP) D4,D12(DDP) I/O 7 /DQS1 /CS0 ODT0 CKE0 /CS1 ODT1 CKE1 DM DQ32 D0,D8(DDP) /CS0 ODT0 CKE0 SCL A0 A1 A2 D7,D15(DDP) I/O 6 Serial PD SDA SDA WP Notes : 1. Unless otherwise noted, resistor values are 22 Ω ± 5% 2. DQ wring may differ form that described in this drawing; however , DQ,DM,DQS,/DQS relationships are maintained as shown. CK0 4 loads V DD SPD Serial PD /CK0 CK1 4 loads V REF SDRAMS DO-D15 V DD SDRAMS DO-D15, V DD and V DD Q V SS SDRAMS DO-D15, SPD /CK1 Rev. 0.1/ July 2004 5 HYMP112S64(L)MP8 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Note Unit Operating temperature(ambient) TOPR 0 ~ +55 o C 1 DRAM Component Case Temperature Range TCASE 0 ~+95 o C 2 Operating Humidity(relative) HOPR 10 to 90 % 1 Storage Temperature TSTG -50 ~ +100 o C 1 Storage Humidity(without condensation) HSTG 5 to 95 o C 1 Barometric Pressure(operating & storage) PBAR 105 to 69 K Pascal 1,3 Note : 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9㎲. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. 3. Up to 9850 ft. Operating Condtions(AC&DC) DC OPERATING CONDITIONS (SSTL_1.8) Parameter Min Max Unit VDD 1.7 1.9 V VDDQ 1.7 1.9 V 1 Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 2 EEPROM Supply Voltage VDDSPD 1.7 3.6 V Termination Voltage VTT VREF-0.04 VREF+0.04 V 3 Min Max Unit Note Power Supply Voltage Symbol Note Note : 1. VDDQ must be less than or equal to VDD. 2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc) 3. VTT of transmitting device must track VREF of receiving device. Input DC Logic Level Parameter Symbol Input High Voltage VIH(DC) VREF + 0.125 VDDQ + 0.3 V Input Low Voltage VIL(DC) -0.30 VREF - 0.125 V Rev. 0.1/ July 2004 6 HYMP112S64(L)MP8 Input AC Logic Level Parameter Symbol Min Max Unit AC Input logic High VIH(AC) VREF + 0.250 - V AC Input logic Low VIL(AC) - VREF - 0.250 V Note AC Input Test Conditions Symbol Condition Value Units Notes VREF Input reference voltage 0.5 * VDDQ V 1 VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1 SLEW Input signal minimum slew rate 1.0 V/ns 2, 3 Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VIL(dc) max to VIH(ac) min for rising edges and the range from VIH(dc) min to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Start of Falling Edge Input Timing Start of Rising Edge Input Timing VSWING(MAX) delta TF Falling Slew = delta TR VIH(dc) min - VIL(ac) max delta TF Rising Slew = VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS VIH(ac) min - VIL(dc) max delta TR < Figure : AC Input Test Signal Waveform > Rev. 0.1/ July 2004 7 HYMP112S64(L)MP8 Differential Input AC logic Level Symbol Parameter VID (ac) ac differential input voltage VIX (ac) ac differential cross point voltage Min. Max. Units Notes 0.5 VDDQ + 0.6 V 1 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2 Note: 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V IL(DC). VDDQ VTR Crossing point VID VIX or VOX VCP VSSQ < Differential signal levels > Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to VIH(AC) - V IL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross. Differential AC output parameters Symbol VOX (ac) Parameter ac differential cross point voltage Min. Max. Units Notes 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1 Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Rev. 0.1/ July 2004 8 HYMP112S64(L)MP8 Output Buffer Levels Output AC Test Conditions Symbol Parameter SSTL_18 Class II Units Notes VOH Minimum Required Output Pull-up under AC Test Load VTT + 0.603 V VOL Maximum Required Output Pull-down under AC Test Load VTT - 0.603 V VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V 1 SSTl_18 Class II Units Notes - 13.4 mA 1, 3, 4 13.4 mA 2, 3, 4 1. The VDDQ of the device under test is referenced. Output DC Current Drive Symbol Parameter IOH(dc) Output Minimum Source DC Current IOL(dc) Output Minimum Sink DC Current 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define a convenient driver current for measurement. OCD defalut characteristics Description Parameter Output impedance 12.6 Pull-up and pull-down mismatch Output slew rate Min Nom 18 0 Sout 1.5 - Max Unit Notes 23.4 ohms 1,2 4 ohms 1,2,3 5 V/ns 1,4,5,6 Note: 1. Absolute Specifications (0°C ≤ TCASE ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V) 2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4. Slew rate measured from vil(ac) to vih(ac). 5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. 6. DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins. Output slew rate at 667&800MT/s will be added with JEDEC process. Rev. 0.1/ July 2004 9 HYMP112S64(L)MP8 PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz ) Parameter Pin Symbol Min, Max, Unit Input Capacitance CK0, /CK0 CCK 15 33 pF Input Capacitance CKE0, /CS CI1 44 65 pF Input Capacitance Address, /RAS, /CAS, /WE CI2 27 65 pF Input Capacitance DQ,DM,DQS, /DQS CIO 8 12 pF Note : 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only. IDD Specifications HYMP112S64(L)MP8 PC2 3200 PC2 4300 Symbol max. max. Operating one bank active-precharge current IDD0 920 1040 mA Operating one bank active-read-precharge current IDD1 1000 1120 mA Precharge power-down current IDD2P 48 64 mA Precharge quiet standby current IDD2Q 520 600 mA Precharge standby current IDD2N 560 640 mA IDD3P(F) 240 320 mA IDD3P(S) 48 64 mA Active Standby Current IDD3N 720 840 mA Operating burst read current IDD4R 1320 1440 mA Operating Current IDD4W 1320 1440 mA Burst auto refresh current IDD5B 1560 1600 mA IDD6 80 80 mA IDD6(L) 48 48 mA IDD7 1960 2160 mA Unit Parameter Note Active power-down current Self Refresh Current Operating bank interleave read current Rev. 0.1/ July 2004 10 HYMP112S64(L)MP8 IDD Meauarement Conditions Symbol Conditions Units IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W mA IDD2P Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2Q Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 mA Slow PDN Exit MRS(12) = 1 mA IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W mA IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD6 Self refresh current; CK and CK at 0V; CKE £ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING mA IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions mA Note: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin ≤ VILAC(max) HIGH is defined as Vin ≥ VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 0.1/ July 2004 11 HYMP112S64(L)MP8 Electrical Characteristics & AC Timings Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin Speed DDR2-533(C4) DDR2-533(C5) DDR2-400(C3) DDR2-400(C4) Unit Bin(CL-tRCD-tRP) 4-4-4 5-5-5 3-3-3 4-4-4 Parameter min min min min CAS Latency 4 5 3 4 ns tRCD 15 18.75 15 20 ns tRP 15 18.75 15 20 ns tRC 60 63.75 55 65 ns tRAS 45 45 40 45 ns AC Timing Parameters by Speed Grade Parameter Symbol DDR2-400 DDR2-533 Min Max Min Max Unit Note Data-Out edge to Clock edge Skew tAC -600 600 -500 500 ps DQS-Out edge to Clock edge Skew tDQSCK -500 500 -500 450 ns Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK Clock Half Period tHP min (tCL,tCH) - min (tCL,tCH) - ns System Clock Cycle Time tCK 5000 8000 3750 8000 ps DQ and DM input hold time tDH 400 - 350 - ps 1 DQ and DM input setup time tDS 400 - 350 - ps 1 Control & Address input Pulse Width for each input tIPW 0.6 - 0.6 - tCK tDIPW 0.35 - 0.35 - tCK tHZ - tAC max - tAC max ps DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 - 300 ps DQ and DM input pulse witdth for each input pulse width for each input Data-out high-impedance window from CK, /CK DQ hold skew factor tQHS - 450 - 400 ps DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps Write command to first DQS latching transition tDQSS WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 tCK DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK Mode register set command cycle time tMRD 2 - 2 - tCK Rev. 0.1/ July 2004 12 HYMP112S64(L)MP8 - continued - Parameter Symbol DDR2 400 DDR2 533 Min Max Min Max 0.4 Unit Write postamble tWPST 0.4 0.6 0.6 tCK Write preamble tWPRE 0.25 - 0.25 - tCK Address and control input hold time tIH 600 - 500 - ps Address and control input setup time tIS 600 - 500 - ps Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Auto-Refresh to Active/Auto-Refresh command period tRFC 105 - 105 - ns Row Active to Row Active Delay tRRD 7.5 - 7.5 - ns CAS to CAS command delay tCCD 2 Write recovery time tWR 15 - 15 - ns Auto Precharge Write Recovery + Precharge Time tDAL (tWR/tCK) + (tRP/tCK) - (tWR/tCK) + (tRP/tCK) - tCK Write to Read Command Delay tWTR 10 - 7.5 - ns Internal read to precharge command delay 2 tCK tRTP 7.5 7.5 Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 Exit self refresh to a read command tXSRD 200 - 200 - tCK tXP 2 - 2 - tCK Exit active power down to read command tXARD 2 2 tCK Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) tXARDS 6 - AL 6 - AL tCK 3 3 tCK ODT turn-on delay t Exit precharge power down to any nonread command t CKE Note ns ns 2 2 2 2 tCK AON tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 ns AONPD tAC(min)+2 2tCK+ tAC(max)+1 tAC(min)+2 2tCK+ tAC(max)+1 ns 2.5 2.5 2.5 2.5 tCK AOF tAC(min) tAC(max)+ 0.6 tAC(min) tAC(max)+ 0.6 ns AOFPD tAC(min)+2 2.5tCK+ tAC(max)+1 tAC(min)+2 2.5tCK+ tAC(max)+1 ns ODT to power down entry latency tANPD 3 3 ODT power down exit latency tAXPD 8 8 OCD drive mode output delay tOIT 0 tDelay tIS+tCK+tIH tREFI - 7.8 - 7.8 us 2 tREFI - 3.9 - 3.9 us 3 AOND ODT turn-on ODT turn-on(Power-Down mode) t t t ODT turn-off delay t ODT turn-off ODT turn-off (Power-Down mode) Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval AOFD t 12 0 tCK tCK 12 tIS+tCK+tIH ns ns Note : 1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS1G821(L)M). 2. 0°C ≤ TCASE ≤ 85°C 3. 85°C ＜ TCASE ≤ 95°C Rev. 0.1/ July 2004 13 HYMP112S64(L)MP8 PACKAGE OUTLINE Front Side 67.60 3.8 max 20.00 Min 4.00 +/-0.10 30.00 20.00 PIN 1 PIN 39 PIN 41 PIN 199 1.00 +/- 0.10 2.45 11.40 2.40 PIN 2 6.00 11.40 2.70 4.20 Back 4.20 PIN 40 PIN 42 47.40 PIN 200 note: 1. all dimension Units are millimeters. 2. all outline dimensions and tolerances match up to the JEDEC standard. Rev. 0.1/ July 2004 14 SERIAL PRESENCE DETECT SPD SPECIFICATION (128Mx64 Unbuffered Lead-free DDR2 SO-DIMM) Rev. 0.1/ July 2004 15 HYMP112S64(L)MP8 SERIAL PRESENCE DETECT Byte# Function Description 0 1 2 3 4 5 6 7 8 Number of bytes utilized by module manufacturer Total number of Bytes in SPD device Fundamental memory type Number of row address on this assembly Number of column address on this assembly Number of DIMM ranks Module data width Module data width (continued) Voltage Interface level of this assembly 9 DDR SDRAM cycle time at CL=5 10 DDR SDRAM access time from clock (tAC) 11 12 13 14 15 16 17 18 19 20 21 22 DIMM Configuration type Refresh Rate and Type Primary DDR SDRAM width Error Checking DDR SDRAM data width Reserved Burst Lengths Supported Number of banks on each SDRAM Device CAS latency supported Reserved DIMM Type DDR SDRAM module attributes DDR SDRAM device attributes : General 23 DDR SDRAM cycle time at CL=4(tCK) 24 DDR SDRAM access time from clock at CL=4(tAC) 25 DDR SDRAM cycle time at CL=3(tCK) 26 DDR SDRAM access time from clock at CL=3(tAC) 27 Minimum Row Precharge Time(tRP) 28 Minimum Row Activate to Row Active delay(tRRD) 29 Minimum RAS to CAS delay(tRCD) 30 Minimum active to precharge time(tRAS) 31 Module rank density 32 Address and command input setup time before clock (tIS) 33 Address and command input hold time after clock (tIH) 34 Data input setup time before clock (tDS) 35 Data input hold time after clock (tDH) 36 Write recovery time(tWR) 37 Internal write to read command delay(tWTR) 38 39 Internal read to precharge command delay(tRTP) Memory analysis probe characteristics 40 Extension of byte 41 tRC and byte 42 tRFC 41 Minimum active / auto-refresh time ( tRC) Rev. 0.1/ July 2004 Bin Sort : E3(DDR2 400 3-3-3), E4(DDR2 400 4-4-4), C4(DDR2 533 4-4-4), C5(DDR2 533 5-5-5) Speed Grade all all all all all all all all all E3,E4 C4,C5 E3,E4 C4,C5 all all all all all all all all all all E3,E4,C5 C4 E3,E4,C5 C4 E3,C4 E4,C5 E3,C4 E4,C5 E3, C4 E4 C5 all E3, C4 E4 C5 E3 E4,C4,C5 all E3, E4 C4, C5 E3, E4 C4, C5 E3, E4 C4, C5 E3, E4 C4, C5 all E3, E4 C4, C5 all E3,E4,C4 C5 E3 C4 E4 C5 Function Supported 128 Bytes 256 Bytes DDR2 SDRAM 14 10 30.0mm/stack/2rank 64 Bits SSTL 1.8V 5.0 ns 3.75 ns +/-0.6ns +/-0.5ns non-ECC 7.8us & Self refresh x8 None 4,8 4 3, 4, 5 SO-DIMM Normal 5.0ns 3.75ns +/-0.6ns +/-0.5ns 5.0ns Undefined +/-0.6ns Undefined 15ns 20ns 18.75ns 7.5ns 15ns 20ns 18.75ns 40ns 45ns 512MB 0.6ns 0.5ns 0.6ns 0.5ns 0.40ns 0.35ns 0.40ns 0.35ns 15ns 10ns 7.5ns 7.5ns Undefined Undefined tRC extended 55ns 60ns 65ns 63.75ns Hexa Value 80 08 08 0E 0A 71 40 00 05 50 3D 60 50 00 82 08 00 00 0C 04 38 00 04 00 00 50 3D 60 50 50 00 60 00 3C 50 4B 1E 3C 50 4B 28 2D 80 60 50 60 50 40 35 40 35 3C 28 1E 1E 00 00 50 37 3C 41 3F Note 1 1 2 2 2 2 2 2 16 HYMP112S64(L)MP8 - continued Byte# Function Description 43 Minimum auto-refresh to active/auto-refresh command period(tRFC) Maximum cycle time (tCK max) 44 Maximim DQS-DQ skew time(tDQSQ) 45 Maximum read data hold skew factor(tQHS) 46 47~61 62 PLL Relock time Superset information(may be used in future) SPD Revision code 42 63 64 65~71 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) Manufacture part number (DDR2 SDRAM) ---------Manufacture part number(Memory density) Manufacture part number(Module Depth) ------- Manufacture part number(Module Depth) Manufacture part number(Module type) Manufacture part number(Data width) -------Manufacture part number(Data width) Manufacture part number(Package type) Manufacture part number(Package material) Manufacture part number(Component configuration) Manufacture part number(Hyphen) 87 Manufacture part number(Minimum cycle time) 88 -------Manufacture part number(Minimum cycle time) 89~90 91 92 93 94 95~98 99~127 128~255 all 105ns Hexa Note Value 69 8.0ns 0.35ns 0.30ns 0.45ns 0.40ns No PLL Undefined 1.0 E3 E4 C4 C5 Hynix JEDEC ID Hynix(Korea Area) HSA(United States Area) HSE(Europe Area) HSJ(Japan Area) Singapore Asia Area H Y M P 1 1 2 S 6 4 M P 8 ‘-’ E3, E4 E C4, C5 C E3 3 E4,C4 4 C5 5 Blank Manufacturer JEDEC ID Code --------- Manufacturer JEDEC ID Code Manufacturing location Function Supported all E3, E4 C4, C5 E3, E4 C4, C5 Checksum for Bytes 0~62 72 Speed Grade Manufacture part number(T.B.D) Manufacture revision code(for Component) Manufacture revision code (for PCB) Manufacturing date(Year) Manufacturing date(Week) Module serial number Manufacturer specific data (may be used in future) Open for customer use Undefined Undefined 80 23 1E 2D 28 00 00 10 C5 4C 3F 23 AD 00 0* 1* 2* 3* 4* 5* 48 59 4D 50 31 31 32 53 36 34 4D 50 38 2D 45 43 33 34 35 20 00 00 6 3 3 4 5 5 Note : 1. The bank address is excluded 2. This value is based on the component specification 3. These bytes are programmed by code of date week & date year 4. These bytes apply to Hynix’s own Module Serial Number System 5. These bytes undefined and coded as ‘00h’ 6. Refer to Hynix Web Site Byte 83~84, Low Power Part Byte # 83 84 Function Description Manufacture part number(Low power part) Manufacture part number(Package type) Rev. 0.1/ July 2004 Speed Grade Function Supported L M Hexa Value 4C 4D Note 17