Cypress CY7C64613 Ez-usb fx usb microcontroller Datasheet

CY7C64613
EZ-USB FX™ USB Microcontroller
Cypress Semiconductor Corporation
Document #: 38-08005 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 22, 2003
CY7C64613
TABLE OF CONTENTS
1.0 FEATURES ...................................................................................................................................... 4
1.1 EZ-USB FX Features .................................................................................................................. 4
1.2 Example Applications .................................................................................................................. 5
1.3 Other Resources ......................................................................................................................... 6
2.0 FUNCTIONAL OVERVIEW .............................................................................................................. 6
2.1 Microprocessor ........................................................................................................................... 6
2.2 USB SIE ...................................................................................................................................... 6
2.3 GPIF (General Programmable InterFace) ................................................................................... 6
2.4 Slave FIFOs ................................................................................................................................ 6
2.5 DMA ............................................................................................................................................ 7
2.6 Flexible Configuration ................................................................................................................. 7
2.7 Endpoints .................................................................................................................................... 9
2.8 Default USB Machine ................................................................................................................ 10
2.9 IBN (In-Bulk-NAK) Interrupts ..................................................................................................... 10
3.0 PINS ............................................................................................................................................... 11
3.1 Pin Diagrams ............................................................................................................................ 11
3.2 General Notes About the Pin Description Table ....................................................................... 14
3.3 CY7C64613 Pin Descriptions ................................................................................................... 14
4.0 REGISTER SUMMARY .................................................................................................................. 23
5.0 INPUT/OUTPUT PIN SPECIAL CONSIDERATION ...................................................................... 29
6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 29
7.0 OPERATING CONDITIONS ........................................................................................................... 29
8.0 DC CHARACTERISTICS ............................................................................................................... 29
9.0 AC ELECTRICAL CHARACTERISTICS ....................................................................................... 30
9.1 USB Transceiver ....................................................................................................................... 30
9.2 Program Memory Read ............................................................................................................. 30
9.3 Data Memory Read ................................................................................................................... 31
9.4 Data Memory Write ................................................................................................................... 32
9.5 DMA Read ................................................................................................................................ 33
9.6 DMA Write ................................................................................................................................. 34
9.7 Slave FIFOs—Output Enables .................................................................................................. 35
9.8 Slave FIFOs—Synchronous Read ............................................................................................ 35
9.9 Slave FIFOs—Synchronous Write ............................................................................................ 36
9.10 Slave FIFOs—Asynchronous Read ........................................................................................ 36
9.11 Slave FIFOs—Asynchronous Write ........................................................................................ 37
9.12 GPIF – Clocked with Fixed 48-MHz Internal Clock ................................................................. 37
9.13 GPIF Signals Externally Clocked – XCLK ............................................................................... 38
10.0 ORDERING INFORMATION ........................................................................................................ 38
11.0 PACKAGE DIAGRAMS ............................................................................................................... 38
11.1 52 PQFP ................................................................................................................................. 39
11.2 80 PQFP ................................................................................................................................. 40
11.3 128 PQFP ............................................................................................................................... 41
11.3 128-Lead Plastic Quad Flatpack ............................................................................................. 41
Document #: 38-08005 Rev. *B
Page 2 of 42
CY7C64613
LIST OF FIGURES
Figure 1-1. CY7C64613 Block Diagram .................................................................................................. 4
Figure 2-1. General Scheme of Multiplexed Pins for the 128-pin CY7C64613 ....................................... 8
Figure 3-1. CY7C64613 52-pin PQFP Assignment ............................................................................... 11
Figure 3-2. CY7C64613 80 Pin PQFP Assignment ............................................................................... 12
Figure 3-3. CY7C64613 128 Pin PQFP Assignment ............................................................................. 13
Document #: 38-08005 Rev. *B
Page 3 of 42
CY7C64613
1.0
Features
The CY7C64613 (EZ-USB FX) is Cypress Semiconductor’s second-generation full-speed USB family. FX products offer higher
performance and a higher level of integration than first-generation EZ-USB products. FX builds on the EZ-USB feature set,
including an intelligent USB core, enhanced 8051, 8-Kbyte RAM, and high-performance I/O while maintaining upward code
compatibility. The CY7C64613 enhances the EZ-USB family by providing faster operation and more ways to transfer data into
and out of the chip at very high speed.
8051 Core
48 / 24 MHz,
4-c lock ins truc . cy cle
Enhanc ed
USB Serial Interf ac e
Engine (SIE)
8 KB
RA M
G PIF
UA RT0
Data Bus (8)
USB Trans c eiv er
X4 PLL
USB
Data (8)
A DDR(16)
12 MHz
UA RT1
3
Timers
Up to 5 I/O Ports (Ports A -E)
4 FIFOs
Eac h 64 by tes
8/16
bits
2 KB
FIFO
(ISO)
DMA
Engine
I 2 C Compatible
Controller
C Y7C 64613
Figure 1-1. CY7C64613 Block Diagram
1.1
EZ-USB FX Features
• Single-chip integrated USB Transceiver, Serial Interface Engine (SIE), and enhanced 8051 microprocessor
• Certified compliant with USB Specifications 1.1 and 2.0 (full-speed device)
• Software operation: 8051 runs code from internal RAM or external RAM. Code can be:
— Downloaded via USB
— Loaded from EEPROM
— Executed in-place from external memory (e.g., Flash)
• Abundant endpoints and buffers
— 14 Bulk/Interrupt endpoints, each with a maximum packet size of 64 bytes (per USB specification)
— 16 Isochronous endpoints, with 2 KB of buffer space (1 KB, double buffered) which may be divided among the 16
isochronous endpoints
— One control endpoint (bidirectional)
• Integrated, industry standard 8051 with enhanced features:
— Four clocks per instruction cycle
— 48-MHz or 24-MHz 8051, selectable by EEPROM configuration bit
— Two UARTS (115 K baud)
— Three counter/timers
— Expanded interrupt system
— Two data pointers
• 3.3V operation
• Smart SIE
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CY7C64613
— Handles much of the low-level USB protocol in logic, simplifying 8051 code
• General Programmable InterFace (GPIF)
— Allows direct connection to most parallel interfaces: 8- and 16-bit wide
— Eliminates external glue logic in most applications
— Programmable Waveform Instructions and Configuration Registers to define waveforms
— Six Ready (RDY) inputs and six Control (CTL) outputs
• Vectored interrupt system expanded for USB, FIFO flags and DMA interrupts
• Separate buffers for SETUP and DATA portions of a CONTROL transfer
• Integrated I2C-compatible controller
— 400-KHz or 100-KHz operation
• Enhanced I/O
— I/O port registers mapped to 8051 SFRs (Special Function Registers) for high-speed bit operations
— Port bits can be controlled using 8051 bit addressing instructions
— Up to five 8-bit I/O ports
• Four integrated 8-bit-wide FIFOs
— Each 64 bytes deep
— Automatic conversion to and from 16-bit buses
— Easy, glueless interface to ASIC, DSP ICs and external logic
— Brings glue FIFOs inside for lower system cost
— Internal or external clock
— Synchronous (using strobes and a clock) or asynchronous (using strobes only)
• DMA controller
— Moves data between slave FIFOs, memory, and ports
— Very fast transfers—one clock (20.8 ns = 48 MHz) per byte for internal transfers
— Can use external RAM as additional FIFO (accessed via Address and Data buses)
• Special Autovectors for DMA and FIFO interrupts
• Glueless external memory expansion
— Up to 16-bit address bus and 8-bit data bus
— Strobes RD#, WR#, OE#, CS#, and PSEN#
— Buses not multiplexed (as in standard 8051), saving one clock per external memory cycle
• Three package options–128-pin PQFP, 80-pin PQFP, and 52-pin PQFP
1.2
Example Applications
• DSL modems
• ATAPI interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Home PNA
• Wireless LAN
• MP3 players
• Networking
Document #: 38-08005 Rev. *B
Page 5 of 42
CY7C64613
1.3
Other Resources
Other sources of EZ-USB FX information include:
• EZ-USB FX Technical Reference Manual (TRM), Version 1.2 or higher
• CY3671 EZ-USB FX Development Kit
• The web site www.cypress.com, which includes information about many Reference Designs, such as USB Mass Storage
Device, ADSL modem, MPEG.2 players, etc.
2.0
2.1
Functional Overview
Microprocessor
The CY7C64613 uses a 12-MHz crystal for low EMI. An internal oscillator and PLL develops an internal 48-MHz clock for use by
the USB Serial Interface Engine and the 8051 microprocessor. The 8051 can run at either 24 MHz or 48 MHz, controlled by a bit
in the EEPROM attached to the I2C-compatible bus. The default rate (with no EEPROM connected) is 24 MHz.
The internal microprocessor is an enhanced version of the industry-standard 8051. Enhancements include four clocks per
instruction cycle operation, a second data pointer, and an enhanced interrupt system. The 8051 includes two UARTS, three
counter-timers, and 256 bytes of register RAM.
The EZ-USB family implements I/O differently than the standard 8051 by having its I/O control registers in external memory space.
The CY7C64613 preserves this addressing for backward EZ-USB compatibility, and adds the ability to control I/O registers using
8051 Special Function Registers (SFRs). This improves I/O access time. For example, an I/O pin may be toggled using one 8051
instruction, e.g., CPL (bit).
The 8051 CODE and XDATA memory consists of an internal 8 KB RAM. This RAM is normally downloaded via the USB cable at
plug-in, followed by the 8051 starting up and executing the downloaded code. This gives the CY7C64613 family its “soft” operation
feature, whereby permanent memory such as ROM or Flash memory is not required. Program code updates can easily be done
in the field since the code is loaded from the PC, not by physically changing or reprogramming a memory device. The 8051
program memory can also be loaded from the EEPROM connected to the I2C compatible bus on reset for stand-alone use without
the USB connected.
The 128-pin version of the CY7C64613 brings out the full 8051 address and data buses, plus decoded control signals OE#, CS#,
RD#, PSEN#, and WR# to allow glueless connection to external memory devices. The 80- and 52-pin packages allow smaller
footprints and more cost effective solutions for certain designs, but do not have external access to the 8051 buses.
2.2
USB SIE
The CY7C64613 uses the EZ-USB family enhanced SIE (Serial Interface Engine). This SIE has the intelligence to perform full
USB enumeration, creating a default USB device with predefined endpoints and alternate settings. This enhanced SIE is essential
in achieving the family’s soft operation, since it provides the mechanism to download firmware prior to the 8051 running.
Once the 8051 is in control, it can use advanced features of the SIE to simplify its USB firmware. Endpoint zero SETUP data is
placed in a separate 8-byte RAM space for easy access. GET_DESCRIPTOR requests are simplified by using a special Setup
Data Pointer. The 8051 simply loads a descriptor address into this 16-bit register, and the SIE takes care of the remaining
overhead, i.e., dividing the descriptor into packets, sending them via endpoint 0 in response to IN tokens, and providing the
necessary handshakes. The 8051 can do other chores while the SIE completes this USB transfer.
2.3
GPIF (General Programmable InterFace)
The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable set of vectors that operate similarly to a finite
state machine. It allows the CY7C64613 to perform local bus mastering, and can implement a wide variety of protocols such as
ATAPI, printer parallel port, PCMCIA and Utopia.
The GPIF has six programmable Control Outputs (CTL), six Address Outputs (ADR), and six general purpose Ready Inputs
(RDY). The data bus width can be 8 or 16 bits. Each GPIF instruction defines the state of the control outputs, or determines what
state a ready input (or multiple inputs) must be before proceeding. A sequence of the GPIF instructions make up a single waveform
that will be executed to perform the desired data move between the CY7C64613 and the external circuit.
2.4
Slave FIFOs
Many high-bandwidth USB designs use a FIFO between the USB interface chip and external logic to match data rates, or to
smooth the USB data delivery (which, being packet oriented, occurs in bursts). The CY7C64613 moves this glue logic into the
part by providing four 64-byte internal slave FIFOs. The FIFOs also provide two important interface functions, external clocking
and bus width conversion.
Using external clocking, external logic (such as a DSP or ASIC) can clock data into or out of the slave FIFOs under control of its
own clock, rather than synchronizing with the clock supplied by the CY7C64613 (24 or 48 MHz). The externally supplied clock
Document #: 38-08005 Rev. *B
Page 6 of 42
CY7C64613
must be free running. The FIFOs can be controlled either synchronously (using strobe signals and a clock) or asynchronously
(using strobe signals only). The slave FIFO data is available as two 8-bit buses, which may be used simultaneously to operate
as a single 16-bit data bus. The 16-bit connection, along with fast double-byte mode, combine to give fast conversion between
8- and 16-bit buses. A flexible set of FIFO flags (full, empty, and programmable) provide FIFO flow control.
2.5
DMA
With many sources and destinations for USB data, such as endpoint buffers, slave FIFOs, and internal/external RAM buffers, it
is important to move blocks of data between them quickly. Using internal DMA, the 8051 sets up source, destination, and transfer
length registers, and then initiates a DMA transfer. The maximum DMA transfer rate occurs between internal resources, such as
endpoint buffers and slave FIFOs. This maximum rate is one byte per 48-MHz clock, or 48 Mbytes per second.
2.6
Flexible Configuration
The EZ-USB FX supports a highly configurable I/O structure. Figure 2-1 on page 8 shows the general scheme of the assignment
of pins to I/O ports. The 80- and 56-pin products are subsets of the 128-pin products, hence they follow a similar scheme. For
details of how to set the configuration registers to configure the I/O ports, consult “CY7C64613 Pin Descriptions” on page 14 of
this data sheet and the EZ-USB FX TRM.
Document #: 38-08005 Rev. *B
Page 7 of 42
D[7..0]
A[15..0]
PA3 / CS#
PA2 / OE#
PA4 / FWR# / RDY4 / SLWR
PA5 / FRD# / RDY5 / SLRD
PC6 / WR# / CTL4
PC7 / RD# / CTL5
PSEN#
BKPT
EA
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
X
X
ADR0
ADR1
ADR2
ADR3
ADR4
CTL3
CTL4
CTL5
RDY4
RDY5
ADR0
ADR1
ADR2
ADR3
ADR4
CTL3
CTL4
CTL5
RDY4
RDY5
BOUTFLAG
AINFULL
BINFULL
AOUTEMTY
BOUTEMTY
PE5
PE6
PE7
SLWR
SLRD
BOUTFLAG
AINFULL
BINFULL
AOUTEMTY
BOUTEMTY
PE5
PE6
PE7
SLWR
SLRD
SCL
X
X
ADR5
ADR5
X
X
SDA
X
X
X
X
PB[7..0]
X
X
X
X
D[7..0]
RDY0
RDY2
CTL0
CTL2
GDA[7..0]
RDY0
RDY2
CTL0
CTL2
GDA[7..0]
ASEL
AOE
AINFLAG
AOUTFLAG
AFI[7..0]
ASEL
AOE
AINFLAG
AOUTFLAG
AFI[7..0]
X
X
X
X
X
X
RDY1
RDY3
CTL1
RDY1
RDY3
CTL1
BSEL
BOE
BINFLAG
BSEL
BOE
BINFLAG
PD[7..0]
PD[7..0]
GDB[7..0]
PD[7..0]
BFI[7..0]
PD[7..0]
X
X
XCLK
XCLK
XCLK
XCLK
[111]
Slave FIFOs
16 bits
[011]
Slave FIFOs
8 bits
DISCON#
D+
D-
WAKEUP#
CLKOUT
XIN
XOUT
RESET#
PA0 / T0out
PA1 / T1out
PA6 / RxD0out
PA7 / RxD1out
PC0 / RxD0 / RDY0
PC1 / TxD0 / RDY1
PC2 / INT0
PC3 / INT1 / RDY3
PC4 / T0 / CTL1
PC5 / T1 / CTL3
Figure 2-1. General Scheme of Multiplexed Pins for the 128-pin CY7C64613
Document #: 38-08005 Rev. *B
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
X
X
[000]
PORTS
(Default)
[001]
MEMBUS
[110]
GPIF
16 bits
[010]
GPIF
8 bits
Page 8 of 42
CY7C64613
[nnn] = IFCONFIG[2..0]
CY7C64613
2.7
Endpoints
Endpoint
Type
Buffer Size
(Bytes)
EP0-IN
Control
64
EP0-OUT
Control
64
EP1-IN
Bulk/Interrupt
64
EP1-OUT
Bulk/Interrupt
64
EP2-IN
Bulk/Interrupt
64
EP2-OUT
Bulk/Interrupt
64
EP3-IN
Bulk/Interrupt
64
EP3-OUT
Bulk/Interrupt
64
EP4-IN
Bulk/Interrupt
64
EP4-OUT
Bulk/Interrupt
64
EP5-IN
Bulk/Interrupt
64
EP5-OUT
Bulk/Interrupt
64
EP6-IN
Bulk/Interrupt
64
EP6-OUT
Bulk/Interrupt
64
EP7-IN
Bulk/Interrupt
64
EP7-OUT
Bulk/Interrupt
64
EP8-IN
Isochronous
0–1023[1]
EP8-OUT
Isochronous
0–1023[1]
EP9-IN
Isochronous
0–1023[1]
EP9-OUT
Isochronous
0–1023[1]
EP10-IN
Isochronous
0–1023[1]
EP10-OUT
Isochronous
0–1023[1]
EP11-IN
Isochronous
0–1023[1]
EP11-OUT
Isochronous
0–1023[1]
EP12-IN
Isochronous
0–1023[1]
EP12-OUT
Isochronous
0–1023[1]
EP13-IN
Isochronous
0–1023[1]
EP13-OUT
Isochronous
0–1023[1]
EP14-IN
Isochronous
0–1023[1]
EP14-OUT
Isochronous
0–1023[1]
EP15-IN
Isochronous
0–1023[1]
EP15-OUT
Isochronous
0–1023[1]
The CY7C64613 has 16 Control, Bulk, and Interrupt endpoints. One endpoint pair is dedicated to endpoint zero, with separate
EP0-IN and EP0-OUT buffers. Fourteen additional 64-byte buffers may be used as Bulk or Interrupt endpoints. These endpoints
may be double-buffered by using an endpoint pairing mechanism. Double buffering allows the 8051 to access a packet as another
packet is being transmitted or received over USB. This technique is essential in high-bandwidth applications where NAKs by the
USB device would reduce performance.
The CY7C64613 also has sixteen Isochronous (ISO) endpoints which share 1024 bytes of double-buffered endpoint memory
(2 KB total). The ISO buffer sizes are programmable in 16-byte increments. The Isochronous endpoint buffers are accessed as
FIFOs.
Endpoint data is serviced either directly by the 8051, or moved on- or off-chip using the built in DMA controller. Bulk data is visible
either in 64-byte random access buffers, or as FIFOs (using the AutoPointer feature).
Each endpoint has its own interrupt vector, allowing ISRs (Interrupt Service Routines) to be called automatically, with minimum
overhead and latency.
Note:
1. A total of 1024 FIFO bytes can be divided among all Isochronous endpoints. (1023 is the maximum USB-specified Isochronous Full-speed packet size.)
Document #: 38-08005 Rev. *B
Page 9 of 42
CY7C64613
2.8
Default USB Machine
When the CY7C64613 is plugged into the USB with no EEPROM attached to its I2C compatible port (but with the SCL and SDA
pull-ups installed), the intelligent SIE enumerates as a generic USB device with the following characteristics.
ID Bytes
VID (Vendor ID)
0547h
PID (Product ID)
2235h
DID (Device ID)
0000h
Default Endpoints
Endpoint
Type
Alternate Setting
0
1
2
Max Packet Size (bytes)
0
CTL
64
64
64
1 IN
INT
0
16
64
2 IN
BULK
0
64
64
2 OUT
BULK
0
64
64
4 IN
BULK
0
64
64
4 OUT
BULK
0
64
64
6 IN
BULK
0
64
64
6 OUT
BULK
0
64
64
8 IN
ISO
0
16
256
8 OUT
ISO
0
16
256
9 IN
ISO
0
16
16
9 OUT
ISO
0
16
16
10 IN
ISO
0
16
16
10 OUT
ISO
0
16
16
2.9
IBN (In-Bulk-NAK) Interrupts
The CY7C64613 has a special interrupt called In-Bulk-NAK. IBN is triggered when an IN token has been received by an endpoint
(the host is attempting to read data), but the SIE has NAK’d the host (because there is no data in the endpoint). The 8051 program
can identify which endpoint triggered the interrupt by reading the IBNIRQ register, where a bit is set for the endpoint (EP1-IN to
EP7-IN) that caused the NAK.
Document #: 38-08005 Rev. *B
Page 10 of 42
CY7C64613
PC7 / RD# / CT L 5
PC6 / WR# / CT L 4
PC5 / T 1 / CT L 3
PC4 / T 0 / CT L 1
GND
PC3 / INT 1# / RDY3
PC2 / INT 0#
PC1 / T xD0 / RDY1
PC0 / RxD0 / RDY0
RDY2 / AOE
CT L 0 / AINFL AG
VCC
51
50
49
48
47
46
45
44
43
42
41
40
Pin Diagrams
GND
3.1
Pins
52
3.0
VCC
1
39
GND
SCL
2
38
XCLK
SDA
3
37
CTL2 / AOUTFLAG
WAKEUP#
4
36
PB7 / T2OUT / D[7] / GDA[7] / AFI[7]
AVCC
5
35
PB6 / INT6 / D[6] / GDA[6] / AFI[6]
XIN
6
34
PB5 / INT5# / D[5] / GDA[5] / AFI[5]
XOUT
7
33
PB4 / INT4 / D[4] / GDA[4] / AFI[4]
AGND
8
32
PB3 / TxD1 / D[3] / GDA[3] / AFI[3]
9
31
PB2 / RxD1 / D[2] / GDA[2] / AFI[2]
PA4 / FWR# / RDY4 / SLWR
10
30
PB1 / T2EX / D[1] / GDA[1] / AFI[1]
PA5 / FRD# / RDY5 / SLRD
11
29
PB0 / T2 / D[0] / GDA[0] / AFI[0]
CLKOUT
12
28
RESET#
GND
13
27
VCC
21
22
23
GND
RESERV ED
RESERV ED
26
20
RESERV ED
GND
19
RESERV ED
25
18
DISCON#
USBD+
17
RESERV ED
24
16
XCL KSEL
USBD-
15
RESERV ED
VCC
14
RESERV ED
52 PQFP
10 x 10 mm
Figure 3-1. CY7C64613 52-pin PQFP Assignment
Document #: 38-08005 Rev. *B
Page 11 of 42
CY7C64613
PC 0 / R xD 0 / R D Y0
NC
NC
R D Y2 / AOE
R D Y1 / B SEL
R D Y0 / ASEL
C TL0 / AIN FLAG
67
66
65
64
63
62
VC C
PC 1 / T xD 0 / R D Y1
68
61
PC 2 / IN T 0#
69
PC 4 / T 0 / C T L1
73
70
PC 5 / T 1 / C T L3
74
GN D
PC 6 / W R # / C TL4
75
PC 3 / IN T 1# / R D Y3
PC 7 / R D # / C TL 5
76
71
NC
77
72
NC
78
GN D
NC
80
VC C
79
Pin Diagrams (continued)
1
60
GN D
SC L
2
59
XC LK
SD A
3
58
C TL2 / AOU TF LAG
W AK EU P#
4
57
C TL1 / B IN FLAG
5
56
NC
XIN
6
55
PE0 / AD R 0 / B OU TF LAG
XOU T
7
54
PB 7 / T2OU T / D [7] / GD A[7] / AFI[7]
8
53
PB 6 / IN T6 / D [6] / GD A[6] / AFI[6]
9
52
PB 5 / IN T5# / D [5] / GD A[5] / AFI[5]
51
PB 4 / IN T4 / D [4] / GD A[4] / AFI[4]
50
PB 3 / TxD 1 / D [3] / GD A[3] / AFI[3]
49
PB 2 / R xD 1 / D [2] / GD A[2] / AFI[2]
AVC C
AGN D
R ESER VED
GN D
80 P QFP
14 x 14 mm
10
36
37
38
39
40
PD 7 / GD B [7] / B F I[7]
U SB D -
U SB D +
GN D
GN D
21
VC C
PD 6 / GD B [6] / B F I[6]
41
35
20
GN D
PD 5 / GD B [5] / B F I[5]
42
34
19
PD 4 / GD B [4] / B F I[4]
C LK OU T
33
43
PD 3 / GD B [3] / B F I[3]
18
32
NC
PA7 / R xD 1OU T
31
44
PD 2 / GD B [2] / B F I[2]
17
PD 1 / GD B [1] / B F I[1]
NC
PA6 / R xD 0OU T
30
45
PD 0 / GD B [0] / B F I[0]
16
29
NC
PA5 / F R D # / R D Y5
28
46
D ISC ON #
15
27
PB 0 / T2 / D [0] / GD A[0] / AFI[0]
PA4 / FW R # / R D Y4
R D Y5 / SLR D
47
26
14
R D Y4 / SLW R
PB 1 / T2EX / D [1] / GD A[1] / AFI[1]
PA3 / C S#
25
48
R D Y3 / B OE
13
24
PA2 / OE#
23
12
XC LK SEL
PA1 / T1OU T
R ESER VED
11
22
PA0 / T0OU T
R ESER VED
3.1
GN D
R ESET#
VC C
Figure 3-2. CY7C64613 80 Pin PQFP Assignment
Document #: 38-08005 Rev. *B
Page 12 of 42
CY7C64613
A2
A1
A0
R D Y2 / AOE
R D Y1 / B SEL
105
104
103
PC 0 / R xD 0 / R D Y0
106
PC 1 / TxD 0 / R D Y1
110
107
PC 2 / IN T 0#
111
VC C
PC 3 / IN T1# / R D Y3
112
A3
A4
113
108
A5
114
109
A6
A9
120
115
A10
121
A7
A11
122
116
PC 4 / T0 / C TL1
123
117
PC 5 / T1 / C TL3
124
GN D
PC 6 / W R # / C TL4
125
A8
PC 7 / R D # / C TL 5
126
118
A12
127
119
A13
128
Pin Diagrams (continued)
A 14
1
102
R D Y0 / A SEL
A 15
2
101
C T L0 / A IN FLA G
GN D
3
100
VC C
4
99
GN D
SC L
5
98
XC LK
VC C
SD A
6
97
C T L2 / A OU TFLA G
W A K EU P#
7
96
C T L1 / B IN FLA G
D0
8
95
PE7 / C TL5
D1
9
94
PE6 / C TL4
D2
10
93
PE5 / C TL3
D3
11
92
PE4 / A D R 4 / B OU TEM TY
12
91
PE3 / A D R 3 / A OU TEM TY
D4
13
90
PE2 / A D R 2 / B IN FU L L
D5
14
89
PE1 / A D R 1 / A IN FU LL
D6
15
88
PE0 / A D R 0 / B OU TFLA G
D7
16
87
VC C
17
86
PB 7 / T2OU T / D [7] / GD A [7] / A FI[7]
A VC C
18
85
PB 6 / IN T6 / D [6] / GD A [6] / A F I[6]
84
PB 5 / IN T5# / D [5] / GD A [5] / A FI[5]
83
PB 4 / IN T4 / D [4] / GD A [4] / A F I[4]
82
PB 3 / TxD 1 / D [3] / GD A [3] / A FI[3]
GN D
128 PQFP
14 x 20 mm
GN D
XIN
19
XOU T
A GN D
20
R ESER VED
22
81
PB 2 / R xD 1 / D [2] / GD A [2] / A FI[2]
GN D
23
80
PB 1 / T2EX / D [1] / GD A [1] / A FI[1]
ADR5
24
79
PB 0 / T2 / D [0] / GD A [0] / A FI[0]
PA 0 / T0OU T
25
78
PA 1 / T1OU T
26
77
R ESER VED
R ESER VED
21
GN D
PA 2 / 0E#
27
76
PA 3 / C S#
28
75
PA 4 / FW R # / R D Y4 / SLW R
29
74
R ESER VED
PA 5 / FR D # / R D Y5 / SLR D
30
73
R ESER VED
PA 6 / R xD 0OU T
31
72
PA 7 / R xD 1OU T
32
71
R ESER VED
VC C
GN D
64
61
PD 5 / GD B [5] / B F I[5]
PD 7 / GD B [7] / B FI[7]
60
PD 4 / GD B [4] / B F I[4]
63
59
PD 3 / GD B [3] / B F I[3]
PD 6 / GD B [6] / B FI[6]
58
PD 2 / GD B [2] / B F I[2]
62
57
PD 1 / GD B [1] / B F I[1]
GN D
56
PD 0 / GD B [0] / B F I[0]
55
54
R ESER VED
VC C
53
R ESER VED
51
EA
52
50
R ESER VED
GN D
49
R ESER VED
R ESER VED
48
U SB D -
D ISC ON #
65
47
38
GN D
XC LK SEL
46
U SB D +
R D Y5 / SL R D
66
45
37
R D Y4 / SLW R
GN D
R ESER VED
44
67
R D Y3 / B OE
36
43
VC C
VC C
N O C ON N EC T
68
42
35
N O C ON N EC T
R ESET#
GN D
41
R ESER VED
69
B K PT
70
34
40
33
39
PSEN #
C LK OU T
GN D
3.1
Figure 3-3. CY7C64613 128 Pin PQFP Assignment
Document #: 38-08005 Rev. *B
Page 13 of 42
CY7C64613
3.2
General Notes About the Pin Description Table
1. See the EZ-USB FX TRM: For multiplexed pins, consult the EZ-USB FX TRM (primarily Chapter 4) for details of setting the
configuration registers.
2. Multiple Routed Signals: In some cases, an internal signal can be routed to more than one pin. For example, in the 80 and
128-pin packages RDY4 can be routed to any combination of (neither, either or both) pins 15 and 26.
3. Tie Up Unused Inputs: It is important that the recommendations in the Pin Description Table be followed, especially for inputs.
Unused CMOS inputs can oscillate if they are left open (floating), which can cause higher power usage and decreased
reliability.
4. Tie Up Certain Outputs That Are Initially Inputs: Many alternate functions of the FX multiplexed pins are similar to the WR#
alternate functions (see the PC6 / WR# / CTL4 pin below) in the following respect:
If WR# is chosen as the function of PC6, it should be pulled up to VCC through a pull-up resistor. This is to ensure that
WR# is inactive (pulled HIGH) at power-up, since, before the 8051 can configure this pin to WR#, it defaults to ‘PC6 an input’
(not driven by the FX pin).
All multiplexed pins that you use should be carefully considered in your circuit design for the effects of the transition through
their default configuration at power-up. These are typically (though not always) active LOW signals such as WR#.
The critical time interval to be considered is between RESET# deasserted and the pin driven as an output (immediately after
the 8051 code has initialized the port to be an alternate function that it is an output).
3.3
CY7C64613 Pin Descriptions
128
80
52
Type
Default
Description
18
5
5
AVCC
Name
Power
N/A
Analog VCC. This signal provides power to the analog section of the
chip.
21
8
8
AGND
Power
N/A
Analog Ground. Connect to ground with as short a path as possible.
48
28
18
DISCON#
O/Z
H
Disconnect. This pin can drive HIGH, LOW, or float. DISCON# pin
floats when the register bit USBCS.2 is LOW, and drives when it is
HIGH. The drive level of the DISCON# pin is the invert of register bit
USBCS.3. The DISCON# pin is normally connected to the USB D+ line
through a 1500Ω resistor. The CY7C64613 signals a USB connection
by setting USBCS.3=0 (drive 3.3V) and USBCS.2=1 (output enable).
The CY7C64613 signals a USB disconnect by setting USBCS.2=0
which floats the pin and disconnects the 1500Ω resistor from D+.
65
38
24
USBD–
I/O/Z
Z
USB D– Connect to the USB D– signal through a 22 ±5% ohm resistor.
66
39
25
USBD+
I/O/Z
Z
USB D+ Connect to the USB D+ signal through a 22 ±5% ohm resistor.
8051 Address Bus. This bus is driven at all times. When the 8051 is
addressing internal RAM it reflects the internal address. During DMA
transfers that use the RD# and WR# strobes, the address bus contains
the incrementing DMA source or destination address for data transferred over D[7.0].
105
A0
Output
L
106
A1
Output
L
107
A2
Output
L
108
A3
Output
L
114
A4
Output
L
115
A5
Output
L
116
A6
Output
L
117
A7
Output
L
118
A8
Output
L
120
A9
Output
L
121
A10
Output
L
122
A11
Output
L
127
A12
Output
L
128
A13
Output
L
1
A14
Output
L
2
A15
Output
L
Document #: 38-08005 Rev. *B
Page 14 of 42
CY7C64613
3.3
128
CY7C64613 Pin Descriptions (continued)
80
52
Type
Default
Description
D0
I/O/Z
Z
9
D1
I/O/Z
Z
10
D2
I/O/Z
Z
8051 Data Bus. This bidirectional bus is:
– input for bus reads
– output for bus writes
– high-impedance when inactive.
The data bus is active only for external bus accesses, and is driven
LOW in suspend.
The data bus is used for:
– external 8051 program and data memory.
– DMA transfers that use the RD#, FRD#, WR#, FWR# pins as strobes.
8
Name
11
D3
I/O/Z
Z
13
D4
I/O/Z
Z
14
D5
I/O/Z
Z
15
D6
I/O/Z
Z
16
D7
I/O/Z
Z
33
PSEN#
Output
H
Program Store Enable PSEN# strobes LOW when the 8051 fetches
a CODE byte from external memory.
If EA = 0, the 8051 fetches CODE from external memory from
0x1B40 to 0xFFFF.
If EA = 1, the 8051 fetches CODE from external memory from
0x0000 to 0xFFFF.
See EA pin.
41
BKPT
Output
L
Breakpoint. This pin goes active (HIGH) when the 8051 address bus
matches the BPADDRH/L registers and breakpoints are enabled in the
USBBAV register (BPEN=1). If the BPPULSE bit in the USBBAV
register is HIGH, BKPT pulses HIGH for eight 24-/48-MHz clocks. If the
BPPULSE bit is LOW, BKPT stays HIGH until the 8051 clears the
BREAK bit (by writing a 1 to it) in the USBBAV register.
RESET#
Input
N/A
Active LOW Reset. This pin resets the entire chip. It is normally tied
to VCC through a 10K resistor and to GND through a 1-µF capacitor.
Hysteresis input.
EA
Input
N/A
External Access. This pin determines where the 8051 fetches code
between addresses 0x0000 and 0x1B3F.
If EA=0 the 8051 fetches this code from its internal RAM.
If EA=1 the 8051 fetches this code from external memory.
(normally used to boot from external memory, for example, boot from
Flash). This pin is “live”.
69
42
28
51
See PSEN# pin.
(EA is tied to GND internally in both the 80- and 52-pin packages.)
19
6
6
XIN
Input
N/A
Crystal Input. Connect this signal to a 12-MHz series-resonant, fundamental mode crystal and 22–33 pF capacitor to GND. Also connect a
1-MΩ resistor between XIN and XOUT.
It is also correct to drive XIN with an external 12-MHz square wave
derived from another clock source.
20
7
7
XOUT
Document #: 38-08005 Rev. *B
Output
N/A
Crystal Output. Connect this signal to a 12-MHz series-resonant,
fundamental mode crystal and 22–33 pF capacitor to GND. Also
connect a 1-MΩ resistor between XIN and XOUT.
If an external clock is used to drive XIN, leave this pin open.
Page 15 of 42
CY7C64613
3.3
CY7C64613 Pin Descriptions (continued)
128
80
52
34
19
12
Type
Default
CLKOUT
Name
O/Z
24 MHz Clock Output. This is the 24- or 48-MHz clock, the master clock for
the 8051, phase locked to the 12-MHz XIN/XOUT clock.
(Note: the GPIF always uses a 48-MHz clock or XCLK, regardless of
the 8051 clock. See XCLK and XCLKSEL.)
The frequency of the 8051 clock is set via a boot EEPROM bit:
If Config 0.2 = 0, CLKOUT is 24 MHz.
If Config 0.2 = 1, CLKOUT is 48 MHz.
CLKOUT may be inverted by setting a boot EEPROM bit CONFIG0.1
= 1.
If no EEPROM is connected to the I2C compatible port (the required
pull-up resistors must be present), the Config0 bits default to zero,
hence
– CLKOUT is 24 MHz
– CLKOUT is non-inverted.
The 8051 may three-state this output by setting CPUCS.1 = 1.
Description
Port A
25
11
PA0 or
T0OUT
I/O/Z
I
(PA0)
Multiplexed pin whose function is selected by two bits:
PORTACFG.0 and IFCONFIG.3.
PA0 is a bidirectional IO port pin.
T0OUT is an active-HIGH signal from 8051 Timer-counter0. T0OUT
outputs a high level for one CLKOUT clock cycle when Timer0
overflows. If Timer0 is operated in mode 3 (two separate
timer/counters), T0OUT is active when the low byte timer/counter
overflows.
26
12
PA1 or
T1OUT
I/O/Z
I
(PA1)
Multiplexed pin whose function is selected by two bits:
PORTACFG.1 and IFCONFIG.3.
PA1 is a bidirectional IO port pin.
T1OUT is an active-HIGH signal from 8051 Timer-counter1. T1OUT
outputs a high level for one CLKOUT clock cycle when Timer1
overflows. If Timer1 is operated in mode 3 (two separate
timer/counters), T1OUT is active when the low byte timer/counter
overflows.
27
13
PA2 or
OE# or
I/O/Z
I
(PA2)
Multiplexed pin whose function is selected by two bits:
PORTACFG.2 and IFCONFIG.3.
PA2 is a bidirectional IO port pin.
OE# is an active-LOW output enable for external memory.
If the OE# function is chosen for this pin, it should be externally pulled
up to VCC through a pull-up resistor. This is to ensure that OE# is
inactive (pulled HIGH) at power up, since, before the 8051 can
configure this pin to OE#, it defaults to ‘PA2 an input’
28
14
PA3 or
CS#
I/O/Z
I
(PA3)
Multiplexed pin whose function is selected by the PORTACFG.3 bit.
PA3 is a bidirectional I/O port pin.
CS# is an active-LOW chip select for external memory.
If the CS# function is chosen for this pin, it should be externally pulled
up to VCC. This is to ensure that CS# is inactive (pulled HIGH) at power
up, since, before the 8051 can configure this pin to CS#, it defaults to
‘PA3 an input’.
29
15
PA4 or
FWR# or
RDY4 or
SLWR
I/O/Z
I
(PA4)
Multiplexed pin whose function is selected by the following bits:
PORTACFG.4, PORTACF2.4, and IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FWR# is the write strobe output for an external FIFO connected to the
data bus D[7..0]. RDY4 is a GPIF input signal.
RDY4 is a GPIF input signal.
SLWR is the write strobe input for the slave FIFOs connected to
AFI[7..0] and/or BFI[7..0].
If the FWR# pin is used, it should be externally pulled up to VCC. This
is to ensure that FWR# is inactive (pulled HIGH) at power up, since,
before the 8051 can configure this pin to FWR#, it defaults to ‘PA4 an
input’.
10
Document #: 38-08005 Rev. *B
Page 16 of 42
CY7C64613
3.3
CY7C64613 Pin Descriptions (continued)
128
80
52
30
16
11
Type
Default
Description
PA5 or
FRD# or
RDY5 or
SLRD
31
32
Name
I/O/Z
I
(PA5)
Multiplexed pin whose function is selected by the following bits:
PORTACFG.5, PORTACF2.5, and IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FRD# is the write strobe output for an external FIFO connected to the
data bus D[7..0].
RDY5 is a GPIF input signal.
SLRD is the read strobe input for the slave FIFOs connected to
AFI[7..0] and/or BFI[7..0].
If the FRD# pin is used, it should be externally pulled up to VCC. This
is to ensure that FRD# is inactive (pulled HIGH) at power up, since,
before the 8051 can configure this pin to FRD#, it defaults to ‘PA5 an
input’.
17
PA6 or
RxD0OUT
I/O/Z
I
(PA6)
Multiplexed pin whose function is selected by the PORTACFG.6 bit.
PA6 is a bidirectional I/O port pin.
RxD0OUT is an active-HIGH signal from 8051 UART0.
If RxD0OUT is selected and UART0 is in mode 0, this pin provides the
output data for UART0 only when it is in sync mode. Otherwise it is a 1.
18
PA7 or
RxD1OUT
I/O/Z
I
(PA7)
Multiplexed pin whose function is selected by the PORTACFG.7 bit.
PA7 is a bidirectional I/O port pin.
RxD1OUT is an active-HIGH output from 8051 UART1.
When RxD1OUT is selected and UART1 is in mode 0, this pin provides
the output data for UART1 only when it is in sync mode. In modes 1,
2, and 3, this pin is HIGH.
Port B
The following descriptions apply to the PORT B pins:
D[7..0] is the bidirectional 8051 data bus.
GDA[7..0] is the bidirectional GPIF A data bus.
AFI[7..0] is the bidirectional A-FIFO data bus.
79
47
29
PB0 or
T2 or
D[0] or
GDA[0] or
AFI [0]
I/O/Z
I
(PB0)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.0 and IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides
the input to Timer2 when C/T2=1. When C/T2=0, Timer2 does not use
this pin.
D[0] is the bidirectional 8051 data bus, bit 0.
GDA[0] is the bidirectional GPIF A data bus, bit 0.
AFI [0] is the bidirectional A-FIFO data bus, bit 0.
80
48
30
PB1 or
T2EX or
D[1] or
GDA[1] or
AFI [1]
I/O/Z
I
(PB1)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.1 and IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
T2EX is an active-HIGH input signal to the 8051 Timer2. T2EX reloads
timer 2 on its falling edge. T2EX is active only if the EXEN2 bit is set
in T2CON.
D[1] is the bidirectional 8051 data bus, bit 1.
GDA[1] is the bidirectional GPIF A data bus, bit 1.
AFI [1] is the bidirectional A-FIFO data bus, bit 1.
81
49
31
PB2 or
RxD1 or
D[2] or
GDA[2] or
AFI [2]
I/O/Z
I
(PB2)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.2 and IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
RxD1 is an active-HIGH input signal for 8051 UART1, which provides
data to the UART in all modes.
D[2] is the bidirectional 8051 data bus, bit 2.
GDA[2] is the bidirectional GPIF A data bus, bit 2.
AFI [2] is the bidirectional A-FIFO data bus, bit 2.
Document #: 38-08005 Rev. *B
Page 17 of 42
CY7C64613
3.3
CY7C64613 Pin Descriptions (continued)
128
80
52
Name
Type
Default
Description
82
50
32
PB3 or
TxD1 or
D[3] or
GDA[3] or
AFI [3]
I/O/Z
I
(PB3)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.3 and IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
TxD1is an active-HIGH output pin from 8051 UART1, which provides
the output clock in sync mode, and the output data in async mode.
D[3] is the bidirectional 8051 data bus, bit 3.
GDA[3] is the bidirectional GPIF A data bus, bit 3.
AFI [3] is the bidirectional A-FIFO data bus, bit 3.
83
51
33
PB4 or
INT4 or
D[4] or
GDA[4] or
AFI [4]
I/O/Z
I
(PB4)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.4 and IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
INT4 is the 8051 INT4 interrupt request input signal. The INT4 interrupt
is triggered on the rising edge of this input signal.
D[4] is the bidirectional 8051 data bus, bit 4.
GDA[4] is the bidirectional GPIF A data bus, bit 4.
AFI [4] is the bidirectional A-FIFO data bus, bit 4.
84
52
34
PB5 or
INT5# or
D[5] or
GDA[5] or
AFI [5]
I/O/Z
I
(PB5)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.5 and IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
INT5# is the 8051 INT5 interrupt request input signal. The INT5
interrupt is triggered on the falling edge of this input signal.
D[5] is the bidirectional 8051 data bus, bit 5.
GDA[5] is the bidirectional GPIF A data bus, bit 5.
AFI [5] is the bidirectional A-FIFO data bus, bit 5.
85
53
35
PB6 or
INT6 or
D[6] or
GDA[6] or
AFI [6]
I/O/Z
I
(PB6)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.6 and IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
INT6 is the 8051 INT5 interrupt request input signal. The INT6 interrupt
is triggered on the rising edge of this input signal.
D[6] is the bidirectional 8051 data bus, bit 6.
GDA[6] is the bidirectional GPIF A data bus, bit 6.
AFI [6] is the bidirectional A-FIFO data bus, bit 6.
86
54
36
PB7 or
T2OUT or
D[7] or
GDA[7] or
AFI [7]
I/O/Z
I
(PB7)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.7 and IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signal from 8051 Timer2. T2OUT is
active (HIGH) for one clock cycle when Timer/Counter 2 overflows.
D[7] is the bidirectional 8051 data bus, bit 7.
GDA[7] is the bidirectional GPIF A data bus, bit 7.
AFI [7] is the bidirectional A-FIFO data bus, bit 7.
110
68
43
PC0 or
RxD0 or
RDY0
I/O/Z
I
(PC0)
Multiplexed pin whose function is selected by the PORTCCFG.0 and
PORTCGPIF.0 bits.
PC0 is a bidirectional I/O port pin.
RxD0 is the active-HIGH RxD0 input to 8051 UART0, which provides
data to the UART in all modes.
RDY0 is a GPIF input signal.
111
69
44
PC1 or
TxD0 or
RDY1
I/O/Z
I
(PC1)
Multiplexed pin whose function is selected by the PORTCCFG.1 and
PORTCGPIF.1 bits.
PC1 is a bidirectional I/O port pin.
TxD0 is the active-HIGH TxD0 output from 8051 UART0, which
provides the output clock in sync mode, and the output data in async
mode.
RDY1 is a GPIF input signal.
112
70
45
PC2 or
INT0#
I/O/Z
I
(PC2)
Multiplexed pin whose function is selected by the PORTCCFG.2 bit.
PC2 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is
either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
Port C
Document #: 38-08005 Rev. *B
Page 18 of 42
CY7C64613
3.3
CY7C64613 Pin Descriptions (continued)
128
80
52
Type
Default
Description
113
71
46
PC3 or
INT1# or
RDY3
Name
I/O/Z
I
(PC3)
Multiplexed pin whose function is selected by the: PORTCCFG.3 and
PORTCGPIF.3 bits.
PC3 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is
either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
RDY3 is a GPIF input signal.
123
73
48
PC4 or
T0 or
CTL1
I/O/Z
I
(PC4)
Multiplexed pin whose function is selected by the PORTCCFG.4 and
PORTCGPIF.4 bits.
PC4 is a bidirectional I/O port pin.
T0 is the active-HIGH T0 signal for 8051 Timer0, which provides the
input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use
this bit.
CTL1 is a GPIF output signal.
124
74
49
PC5 or
T1 or
CTL3
I/O/Z
I
(PC5)
Multiplexed pin whose function is selected by the PORTCCFG.5 and
PORTCGPIF.5 bits.
PC5 is a bidirectional I/O port pin.
T1 is the active-HIGH T1 signal for 8051 Timer1, which provides the
input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use
this bit.
CTL3 is a GPIF output signal.
125
75
50
PC6 or
WR# or
CTL4
I/O/Z
I
(PC6)
Multiplexed pin whose function is selected by the PORTCCFG.6 and
PORTCGPIF.6 bits.
PC6 is a bidirectional I/O port pin.
WR# is the active-LOW write strobe output for external memory.
CTL4 is a GPIF output signal.
This is to ensure that WR# is inactive (pulled high) at power up. Before
the 8051 can configure this pin to WR#, it defaults to ‘PC6 an input’
126
76
51
PC7 or
RD# or
CTL5
I/O/Z
I
(PC7)
Multiplexed pin whose function is selected by the PORTCCFG.7 and
PORTCGPIF.7 bits.
PC7 is a bidirectional I/O port pin.
RD# is the active-LOW read strobe output for external memory.
CTL5 is a GPIF output signal.
This is to ensure that RD# is inactive (pulled high) at power up. Before
the 8051 can configure this pin to RD#, it defaults to ‘PC6 an input’.
Port D
Port D is multiplexed between three sources:
PD0–PD7 are bidirectional I/O port pins.
GDB[7..0] is the GPIF B data bus.
BFI[7..0] is the bidirectional B-FIFO data bus.
56
30
PD0 or
GDB[0] or
BFI [0]
I/O/Z
I
(PD0)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
BFI [0] is the bidirectional B-FIFO data bus.
57
31
PD1 or
GDB[1] or
BFI [1]
I/O/Z
I
(PD1)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
BFI [1] is the bidirectional B-FIFO data bus.
58
32
PD2 or
GDB[2] or
BFI [2]
I/O/Z
I
(PD2)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
BFI [2] is the bidirectional B-FIFO data bus.
59
33
PD3 or
GDB[3] or
BFI [3]
I/O/Z
I
(PD3)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
BFI [3] is the bidirectional B-FIFO data bus.
60
34
PD4 or
GDB[4] or
BFI [4]
I/O/Z
I
(PD4)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
BFI [4] is the bidirectional B-FIFO data bus.
Document #: 38-08005 Rev. *B
Page 19 of 42
CY7C64613
3.3
CY7C64613 Pin Descriptions (continued)
128
80
Name
Type
Default
Description
61
35
52
PD5 or
GDB[5] or
BFI [5]
I/O/Z
I
(PD5)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
BFI [5] is the bidirectional B-FIFO data bus.
63
36
PD6 or
GDB[6] or
BFI [6]
I/O/Z
I
(PD6)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
BFI [6] is the bidirectional B-FIFO data bus.
64
37
PD7 or
GDB[7] or
BFI [7]
I/O/Z
I
(PD7)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
BFI [7] is the bidirectional B-FIFO data bus.
88
PE0 or
ADR0 or
BOUTFLAG
I/O/Z
I
(PE0)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
PE0 is a bidirectional I/O port pin.
ADR0 is a GPIF address output pin.
BOUTFLAG is the B-OUT FIFO flag output, which indicates a
programmable level of FIFO fullness.
89
PE1 or
ADR1 or
AINFULL
I/O/Z
I
(PE1)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
PE1 is a bidirectional I/O port pin.
ADR1 is a GPIF address output pin.
AINFULL is the A-IN FIFO flag output, which indicates FIFO full.
90
PE2 or
ADR2 or
BINFULL
I/O/Z
I
(PE2)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
PE2 is a bidirectional I/O port pin.
ADR2 is a GPIF address output pin.
BINFULL is the B-IN FIFO flag output, which indicates FIFO full.
91
PE3 or
ADR3 or
AOUTEMTY
I/O/Z
I
(PE3)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
PE3 is a bidirectional I/O port pin.
ADR3 is a GPIF address output pin.
AOUTEMTY is the A-OUT FIFO flag output, which indicates FIFO
empty.
92
PE4 or
ADR4 or
BOUTEMTY
I/O/Z
I
(PE4)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits.
PE4 is a bidirectional I/O port pin.
ADR4 is a GPIF address output pin.
BOUTEMTY is the B-OUT FIFO flag output, which indicates FIFO
empty.
93
PE5 or
CTL3
I/O/Z
I
(PE5)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PE5 is a bidirectional I/O port pin.
CTL3 is a GPIF output signal.
94
PE6 or
CTL4
I/O/Z
I
(PE6)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PE6 is a bidirectional I/O port pin.
CTL4 is a GPIF output signal.
95
PE7 or
CTL5
I/O/Z
I
(PE7)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PE7 is a bidirectional I/O port pin.
CTL5 is a GPIF output signal.
Port E
O
X
ADR5 is a GPIF address output pin.
102
24
63
ADR5
RDY0 or
ASEL
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
ASEL is the select input for the A-IN and A-OUT FIFOs.
103
64
RDY1 or
BSEL
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
BSEL is the select input for the B-IN and B-OUT FIFOs.
Document #: 38-08005 Rev. *B
Page 20 of 42
CY7C64613
3.3
CY7C64613 Pin Descriptions (continued)
128
80
52
104
65
42
Type
Default
RDY2 or
AOE
44
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY2 is a GPIF input signal.
AOE is the output enable input for the A-OUT FIFO.
25
RDY3 or
BOE
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY3 is a GPIF input signal.
BOE is the output enable input for the B-OUT FIFO.
45
26
RDY4 or
SLWR
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY4 is a GPIF input signal.
SLWR is the input-only write strobe for the slave FIFOs connected to
AFI[7..0] and/or BFI[7..0].
46
27
RDY5 or
SLRD
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY5 is a GPIF input signal.
SLRD is the input-only read strobe for the slave FIFOs connected to
AFI[7..0] and/or BFI[7..0].
101
62
CTL0 or
AINFLAG
Output
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
AINFLAG is the A-IN FIFO flag output which indicates a programmable
level of FIFO fullness.
96
57
CTL1 or
BINFLAG
Output
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
BINFLAG is the B-IN FIFO flag output which indicates a programmable
level of FIFO fullness.
97
58
37
CTL2 or
AOUTFLAG
Output
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
AOUTFLAG is the A-OUT FIFO flag output which indicates a programmable level of FIFO fullness.
98
59
38
XCLK
Input
N/A
External clock input, used for synchronously clocking data into the
slave FIFOs. XCLK also serves as a timing reference for all slave FIFO
control signals and GPIF. This clock must be free - running.
53
22
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
54
23
41
Name
Description
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
70
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
71
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
73
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
74
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
76
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
Reserved
Rsrvd
N/A
Reserved. Must be left open.
77
50
20
49
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
19
Reserved
Rsrvd
N/A
Reserved. Connect to 3.3V power source.
7
4
4
WAKEUP#
Input
N/A
USB Wakeup. If the 8051 is in suspend, a HIGH-to-LOW edge on this
pin starts up the oscillator and interrupts the 8051 to allow it to exit the
suspend mode. Holding WAKEUP# LOW inhibits the EZ-USB chip
from suspending.
5
2
2
SCL
Open
Drain
Z
I2C-compatible Clock. Connect to VCC with a 1K resistor, even if no
I2C-compatible peripheral is attached.
Document #: 38-08005 Rev. *B
Page 21 of 42
CY7C64613
3.3
CY7C64613 Pin Descriptions (continued)
128
80
52
Type
Default
Description
6
3
3
SDA
Open
Drain
Z
I2C-compatible Data. Connect to VCC with a 1K resistor, even if no
I2C-compatible peripheral is attached.
38
23
16
XCLKSEL
Input
N/A
HIGH: Use XCLK pin for GPIF and slave FIFOs.
LOW: Use internal 48-MHz clock for GPIF and slave FIFOs.
39
24
17
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
37
22
15
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
22
9
9
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
4
1
1
17
36
21
14
55
68
41
27
75
100
61
40
109
3
80
52
12
23
10
35
20
13
40
47
52
29
21
67
40
26
72
43
62
78
87
Name
VCC
Power
N/A
VCC. Connect to 3.3V power source.
VCC
Power
N/A
VCC. Connect to 3.3V power source.
VCC
Power
N/A
VCC. Connect to 3.3V power source.
VCC
Power
N/A
VCC. Connect to 3.3V power source.
VCC
Power
N/A
VCC. Connect to 3.3V power source.
VCC
Power
N/A
VCC. Connect to 3.3V power source.
VCC
Power
N/A
VCC. Connect to 3.3V power source.
VCC
Power
N/A
VCC. Connect to 3.3V power source.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
99
60
39
GND
Ground
N/A
Ground.
119
72
47
GND
Ground
N/A
Ground.
42
79
NC
N/A
N/A
No-connect. This pin must be left open.
43
44
NC
N/A
N/A
No-connect. This pin must be left open.
45
NC
N/A
N/A
No-connect. This pin must be left open.
46
NC
N/A
N/A
No-connect. This pin must be left open.
55
NC
N/A
N/A
No-connect. This pin must be left open.
56
NC
N/A
N/A
No-connect. This pin must be left open.
66
NC
N/A
N/A
No-connect. This pin must be left open.
67
NC
N/A
N/A
No-connect. This pin must be left open.
77
NC
N/A
N/A
No-connect. This pin must be left open.
78
NC
N/A
N/A
No-connect. This pin must be left open.
Document #: 38-08005 Rev. *B
Page 22 of 42
CY7C64613
4.0
Addr
Register Summary
Name
Description
D7
D6
D5
D4
D3
D2
D1
D0
FIFO A-IN
7800 AINDATA
Read Data from FIFO A
D7
D6
D5
D4
D3
D2
D1
D0
7801 AINBC
Input FIFO A Byte Count
0
D6
D5
D4
D3
D2
D1
D0
7802 AINPF
FIFO A-IN Programmable
Flag (internal bit)
LTGT
D6
D5
D4
D3
D2
D1
D0
7803 AINPFPIN
FIFO A-IN Prorammable
Flag (external pin)
LTGT
D6
D5
D4
D3
D2
D1
D0
Read Data from FIFO B
D7
D6
D5
D4
D3
D2
D1
D0
7804 (reserved)
FIFO B-IN
7805 BINDATA
7806 BINBC
Input FIFO B Byte Count
0
D6
D5
D4
D3
D2
D1
D0
7807 BINPF
FIFO B-IN Programmable
Flag (internal bit)
LTGT
D6
D5
D4
D3
D2
D1
D0
7808 BINPFPIN
FIFO B-IN Programmable
Flag (external pin)
LTGT
D6
D5
D4
D3
D2
D1
D0
INTOG
INSEL
AINPF
AINEF
AINFF
BINPF
BINEF
BINFF
7809 (reserved)
FIFO A/B-IN Control
780A ABINCS
Input FIFOs Toggle control
and flags
780B ABINIE
Input FIFO Interrupt Enables
0
0
AINPFIE AINEFIE
780C ABINIRQ
Input FIFO Interrupt
Requests
0
0
AINPFIR AINEFIR AINFFIR BINPFIR BINEFIR BINFFIR
AINFFIE
BINPFIE BINEFIE
BINFFIE
780E AOUTDATA
Load Output FIFO A
D7
D6
D5
D4
D3
D2
D1
D0
780F AOUTBC
Output FIFO A Byte Count
0
D6
D5
D4
D3
D2
D1
D0
7810 AOUTPF
FIFO A-OUT Programmable
Flag (internal bit)
LTGT
D6
D5
D4
D3
D2
D1
D0
7811 AOUTPFPIN
FIFO A-OUT Programmable
Flag (external pin)
LTGT
D6
D5
D4
D3
D2
D1
D0
780D (reserved)
FIFO A-OUT
7812 (reserved)
FIFO B-OUT
7813 BOUTDATA
Load Output FIFO B
7814 BOUTBC
Output FIFO B Byte Count
D7
D6
D5
D4
D3
D2
D1
D0
0
D6
D5
D4
D3
D2
D1
D0
7815 BOUTPF
FIFO B-OUT Programmable
(internal bit)
LTGT
D6
D5
D4
D3
D2
D1
D0
7816 BOUTPFPIN
FIFO B-OUT Programmable
Flag (external pin)
LTGT
D6
D5
D4
D3
D2
D1
D0
7817 (reserved)
FIFO A/B OUT Control
7818 ABOUTCS
Output FIFOs Toggle
control and flags
OUTTOG OUTSEL AOUTPF AOUTEF AOUTFF BOUTPF BOUTEF BOUTFF
7819 ABOUTIE
Output FIFO Interrupt
Enables
0
0
AOUTPFIE
AOUTEFIE
AOUTFFIE
BOUTPFIE
BOUTEFIE
BOUTFFIE
781A ABOUTIRQ
Output FIFO Interrupt
Requests
0
0
AOUTPFIR
AOUTEFIR
AOUTFFIR
BOUTPFIR
BOUTEFIR
BOUTFFIR
781B (reserved)
FIFO A/B Global Control
781C ABSETUP
FIFO Setup
0
0
ASYNC
DBLIN
0
OUTDLY
0
DBLOUT
781D ABPOLAR
FIFO Control Signals
Polarity
0
0
BOE
AOE
SLRD
SLWR
ASEL
BSEL
781E ABFLUSH
Write (data=x) to reset all
flags
*[2]
*
*
*
*
*
*
*
Document #: 38-08005 Rev. *B
Page 23 of 42
CY7C64613
4.0
Register Summary (continued)
Addr
Name
Description
D7
D6
D5
D4
D3
D2
D1
D0
781F-7823 (reserved)
7824 WFSELECT
Waveform Selector
SINGLEWR
SINGLERD
FIFOWR
FIFORD
7825 IDLECS
GPIF IDLE State control
DONE
0
0
0
0
0
0
IDLEDRV
7826 IDLECTLOUT
GPIF IDLE CTL states
IOE3
IOE2
IOE1/
CTL5
IOE0/
CTL4
CTL3
CTL2
CTL1
CTL0
7827 CTLOUTCFG
GPIF CTL Drive mode
TRICTL
0
CTL5
CTL4
CTL3
CTL2
CTL1
CTL0
*
*
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
*
*
*
7828-7829 (reserved)
782A GPIFADRL
GPIF Address
782B (reserved)
782C AINTC
FIFO A In Transfer Count
FITC
Transfer Count
782D AOUTTC
FIFO A Out Transfer Count
FITC
Transfer Count
782E ATRIG
Trigger a FIFO A RD/WR
*
*
*
*
*
782F (reserved)
7830 BINTC
FIFO B In Transfer Count
FITC
Transfer Count
7831 BOUTTC
FIFO B Out Transfer Count
FITC
Transfer Count
7832 BTRIG
Trigger a FIFO B RD/WR
*
*
*
*
*
*
*
*
7833 (reserved)
7834 SGLDATH
D15
D14
D13
D12
D11
D10
D9
D8
7835 SGLDATLTRIG GPIF Data Low and Trigger
GPIF Data High
D7
D6
D5
D4
D3
D2
D1
D0
7836 SGLDATLNTRIG
D7
D6
D5
D4
D3
D2
D1
D0
GPIF Data Low and No
Trigger
7837(reserved)
7838 READY
GPIF Ready flags
INTRDY
SAS
RDY5
RDY4
RDY3
RDY2
RDY1
RDY0
7839 ABORT
Abort current GPIF cycle
*
*
*
*
*
*
*
*
783B GENIE
GPIF/DMA Interrupt Enable
0
0
0
0
0
DMADN
GPWR
GPDONE
783C GENIRQ
GPIF/DMA Interrupt
Request
0
0
0
0
0
DMADN
GPWR
GPDONE
783A (reserved)
783D-7840 (reserved)
IO Ports D, E
7841 OUTD
Output Port D
OUTD7
OUTD6
OUTD5
OUTD4
OUTD3
OUTD2
OUTD1
OUTD0
7842 PINSD
Input Port D pins
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
7843 OED
Port D Output Enable
0ED7
0ED6
0ED5
0ED4
0ED3
0ED2
0ED1
0ED0
7844 (reserved)
7845 OUTE
Output Port E
OUTE7
OUTE6
OUTE5
OUTE4
OUTE3
OUTE2
OUTE1
OUTE0
7846 PINSE
Input Port E pins
PINE7
PINE6
PINE5
PINE4
PINE3
PINE2
PINE1
PINE0
7847 OEE
Port E Output Enable
OEE7
OEE6
OEE5
OEE4
OEE3
OEE2
OEE1
OEE0
Timer0 Clock source,
Port-to-SFR mapping
0
0
0
0
0
0
T0CLK
SFRPORT
52ONE
0
0
0
GSTATE
BUS16
IF1
IF0
7848 (reserved)
7849 PORTSETUP
Note:
2. Register bit is not used and undefined if read.
784A IFCONFIG
Select 8/16 bit data bus, configure buses (IF)
784B PORTACF2
Port A Configuration #2
0
0
SLRD
SLWR
0
0
0
0
784C PORTCCF2
Port C Configuration #2
CTL5
CTL4
CTL3
CTL1
RDY3
0
RDY1
RDY0
784D-784E (reserved)
DMA Control
784F DMASRCH
DMA Source H
A15
A14
A13
A12
A11
A10
A9
A8
7850 DMASRCL
DMA Source L
A7
A6
A5
A4
A3
A2
A1
A0
Document #: 38-08005 Rev. *B
Page 24 of 42
CY7C64613
4.0
Addr
Register Summary (continued)
D7
D6
D5
D4
D3
D2
D1
7851 DMADESTH
Name
DMA Destination H
Description
A15
A14
A13
A12
A11
A10
A9
D0
A8
7852 DMADESTL
DMA Destination L
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DONE
*
*
*
*
*
*
*
7853 (reserved)
7854 DMALEN
DMA Transfer Length
7855 DMAGO
Start DMA Transfer
7856 (reserved)
7857 DMABURST
DMA Burst control
7858 DMAEXTFIFO
Dummy data reg for using
RAM as external FIFO
*
*
*
DSTR2
DSTR1
DSTR0
RB
WB
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
7859 - 785C (reserved)
785D INT4IVEC
Interrupt 4 Vector
0
1
I4V3
I4V2
I4V1
I4V0
0
0
785E INT4SETUP
Interrupt 4 Set-up
0
0
0
0
0
INT4SFC
INTERNAL
AV4EN
d0
785F-78FF (reserved)
7900- WFDESC
797F
GPIF Waveform
Descriptors
7980-7B3F (reserved)
Endpoint 0–7 Data Buffers
7B40 OUT7BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
7B80 IN7BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7BC0 OUT6BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7C00 IN6BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7C40 OUT5BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7C80 IN5BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7CC0 OUT4BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7D00 IN4BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7D40 OUT3BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7D80 IN3BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7DC0 OUT2BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7E00 IN2BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7E40 OUT1BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7E80 IN1BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7EC0 OUT0BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7F00 IN0BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
d7
d6
d5
d4
d3
d2
d1
d0
7F40-7F5F (reserved)
Isochronous Data
7F60 OUT8DATA
Endpoint 8 OUT Data
7F61 OUT9DATA
Endpoint 9 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F62 OUT10DATA
Endpoint 10 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F63 OUT11DATA
Endpoint 11 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F64 OUT12DATA
Endpoint 12 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F65 OUT13DATA
Endpoint 13 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F66 OUT14DATA
Endpoint 14 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F67 OUT15DATA
Endpoint 15 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F68 IN8DATA
Endpoint 8 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F69 IN9DATA
Endpoint 9 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F6A IN10DATA
Endpoint 10 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F6B IN11DATA
Endpoint 11 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
Document #: 38-08005 Rev. *B
Page 25 of 42
CY7C64613
4.0
Register Summary (continued)
Name
Description
D7
D6
D5
D4
D3
D2
D1
D0
7F6C IN12DATA
Addr
Endpoint 12 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F6D IN13DATA
Endpoint 13 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F6E IN14DATA
Endpoint 14 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F6F IN15DATA
Endpoint 15 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
Isochronous Byte Counts
7F70 OUT8BCH
EP8 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F71 OUT8BCL
EP8 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F72 OUT9BCH
EP9 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F73 OUT9BCL
EP9 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F74 OUT10BCH
EP10 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F75 OUT10BCL
EP10 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F76 OUT11BCH
EP11 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F77 OUT11BCL
EP11 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F78 OUT12BCH
EP12 Out Byte Count H
0
0
0
0
0
0
d9
d8
d0
7F79 OUT12BCL
EP12 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
7F7A OUT13BCH
EP13 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F7B OUT13BCL
EP13 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F7C OUT14BCH
EP14 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F7D OUT14BCL
EP14 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F7E OUT15BCH
EP15 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F7F OUT15BCL
EP15 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F92 CPUCS
Control & Status
rv3
rv2
rv1
rv0
24/48
CLKINV
7F93 PORTACFG
Port A Configuration
RxD1out
RxD0out
FRD
FWR
CS
OE
T1out
7F94 PORTBCFG
Port B Configuration
T2OUT
INT6
INT5
INT4
TxD1
RxD1
T2EX
T2
7F95 PORTCCFG
Port C Configuration
RD
WR
T1
T0
INT1
INT0
TxD0
RxD0
OUTA7
OUTA6
OUTA5
OUTA4
OUTA3
OUTA2
OUTA1
OUTA0
7F80-7F91 (reserved)
CPU Registers
CLKOUT 8051RES
OE
T0out
Input-Output Port Registers
7F96 OUTA
Output Register A
7F97 OUTB
Output Register B
OUTB7
OUTB6
OUTB5
OUTB4
OUTB3
OUTB2
OUTB1
OUTB0
7F98 OUTC
Output Register C
OUTC7
OUTC6
OUTC5
OUTC4
OUTC3
OUTC2
OUTC1
OUTC0
7F99 PINSA
Port Pins A
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
7F9A PINSB
Port Pins B
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
7F9B PINSC
Port Pins C
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
7F9C OEA
Output Enable A
OEA7
OEA6
OEA5
OEA4
OEA3
OEA2
OEA1
OEA0
7F9D OEB
Output Enable B
OEB7
OEB6
OEB5
OEB4
OEB3
OEB2
OEB1
OEB0
7F9E OEC
Output Enable C
OEC7
OEC6
OEC5
OEC4
OEC3
OEC2
OEC1
OEC0
ISO15
ERR
ISO14
ERR
ISO13
ERR
ISO12
ERR
ISO11
ERR
ISO10
ERR
ISO9
ERR
ISO8
ERR
7F9F (reserved)
Isochronous Control/Status Registers
7FA0 ISOERR
ISO OUT Endpoint Error
7FA1 ISOCTL
Isochronous Control
*
*
*
*
PPSTAT
MBZ
MBZ
ISODISAB
7FA2 ZBCOUT
Zero Byte Count bits
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
7FA3 (reserved)
7FA4 (reserved)
I2C compatible Registers
Document #: 38-08005 Rev. *B
Page 26 of 42
CY7C64613
4.0
Addr
Register Summary (continued)
Name
Description
7FA5 I2CS
Control & Status
7FA6 I2DAT
Data
7FA7 I2CMODE
STOP Int Enable,
patible bus speed
I2C
com-
D7
D6
D5
D4
D3
D2
D1
D0
START
STOP
LASTRD
ID1
ID0
BERR
ACK
DONE
d7
d6
d5
d4
d3
d2
d1
d0
0
0
0
0
0
0
STOPIE
400KHZ
Interrupts
7FA8 IVEC
Interrupt Vector
7FA9 IN07IRQ
EPIN Interrupt Request
7FAA OUT07IRQ
EPOUT Interrupt Request
7FAB USBIRQ
USB Interrupt Request
7FAC IN07IEN
EP0–7IN Int Enables
7FAD OUT07IEN
EP0–7OUT Int Enables
0
IV4
IV3
IV2
IV1
IV0
0
0
IN7IR
IN6IR
IN5IR
IN4IR
IN3IR
IN2IR
IN1IR
IN0IR
OUT7IR
OUT6IR
OUT5IR
OUT4IR
OUT3IR
OUT2IR
OUT1IR
OUT0IR
0
0
IBNIR
URESIR
SUSPIR
SUTOKIR
SOFIR
SUDAVIR
IN7IEN
IN6IEN
IN5IEN
IN4IEN
IN3IEN
IN2IEN
IN1IEN
IN0IEN
OUT7IEN OUT6IEN OUT5IEN OUT4IEN OUT3IEN OUT2IEN OUT1IEN OUT0IEN
7FAE USBIEN
USB Int Enables
0
0
IBNIE
URESIE
SUSPIE SUTOKIE
SOFIE
SUDAVIE
7FAF USBBAV
Breakpoint & Autovector
*
*
*
INT2SFC
BREAK
BPPULSE
BPEN
AVEN
7FB0 IBNIRQ
IN-Bulk-NAK Intr. Request
EP7IR
EP6IR
EP5IR
EP4IR
EP3IR
EP2IR
EP1IR
EP0IR
7FB1 IBNIEN
IN-Bulk-NAK Intr. enable
EP7IE
EP6IE
EP5IE
EP4IE
EP3IE
EP2IE
EP1IE
EP0IE
7FB2 BPADDRH
Breakpoint Address H
A15
A14
A13
A12
A11
A10
A9
A8
7FB3 BPADDRL
Breakpoint Address L
A7
A6
A5
A4
A3
A2
A1
A0
HSNAK
EP0STAL
L
Bulk Endpoints 0–7
7FB4 EP0CS
Control & Status
*
*
*
*
OUTBSY
INBSY
7FB5 IN0BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FB6 IN1CS
Control & Status
*
*
*
*
*
*
in1bsy
in1stl
7FB7 IN1BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FB8 IN2CS
Control & Status
*
*
*
*
*
*
in2bsy
in2stl
7FB9 IN2BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FBA IN3CS
Control & Status
*
*
*
*
*
*
in3bsy
in3stl
7FBB IN3BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FBC IN4CS
Control & Status
*
*
*
*
*
*
in4bsy
in4stl
7FBD IN4BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FBE IN5CS
Control & Status
*
*
*
*
*
*
in5bsy
in5stl
7FBF IN5BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FC0 IN6CS
Control & Status
*
*
*
*
*
*
in6bsy
in6stl
7FC1 IN6BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FC2 IN7CS
Control & Status
*
*
*
*
*
*
in7bsy
in7stl
7FC3 IN7BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FC4 (reserved)
7FC5 OUT0BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FC6 OUT1CS
Control & Status
*
*
*
*
*
*
out1bsy
out1stl
7FC7 OUT1BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FC8 OUT2CS
Control & Status
*
*
*
*
*
*
out2bsy
out2stl
7FC9 OUT2BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FCA OUT3CS
Control & Status
*
*
*
*
*
*
out3bsy
out3stl
7FCB OUT3BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FCC OUT4CS
Control & Status
*
*
*
*
*
*
out4bsy
out4stl
7FCD OUT4BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FCE OUT5CS
Control & Status
*
*
*
*
*
*
out5bsy
out5stl
7FCF OUT5BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
Document #: 38-08005 Rev. *B
Page 27 of 42
CY7C64613
4.0
Addr
Register Summary (continued)
D7
D6
D5
D4
D3
D2
D1
D0
7FD0 OUT6CS
Name
Control & Status
Description
*
*
*
*
*
*
out6bsy
out6stl
7FD1 OUT6BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FD2 OUT7CS
Control & Status
*
*
*
*
*
*
out7bsy
out7stl
7FD3 OUT7BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
WakeSRC
*
*
*
DisCon
DiscOE
ReNum
SIGRSUME
Global USB Registers
7FD4 SUDPTRH
Setup Data Ptr H
7FD5 SUDPTRL
Setup Data Ptr L
7FD6 USBCS
USB Control & Status
7FD7 TOGCTL
Toggle Control
Q
S
R
IO
0
EP2
EP1
EP0
7FD8 USBFRAMEL
Frame Number L
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
7FD9 USBFRAMEH
Frame Number H
0
0
0
0
0
FC10
FC9
FC8
Function Address
0
FA6
FA5
FA4
FA3
FA2
FA1
FA0
7FDD USBPAIR
Endpoint Control
ISOsend
0
*
PR6IN
PR4IN
PR2IN
7FDE IN07VAL
Input Endpoint 0–7 valid
IN7VAL
IN6VAL
IN2VAL
IN1VAL
1
7FDF OUT07VAL
Output Endpoint 0–7 valid
OUT7VA OUT6VA OUT5VA OUT4VA OUT3VA OUT2VA OUT1VA
L
L
L
L
L
L
L
1
7FE0 INISOVAL
Input EP 8–15 valid
IN15VAL IN14VAL IN13VAL IN12VAL
IN11VAL IN10VAL
7FE1 OUTISOVAL
Output EP 8–15 valid
OUT15V
AL
OUT11V
AL
7FDA (reserved)
7FDB FNADDR
7FDC (reserved)
PR6OUT PR4OUT PR2OUT
IN5VAL
IN4VAL
OUT14V OUT13V OUT12V
AL
AL
AL
IN3VAL
IN9VAL
IN8VAL
OUT10V OUT9VA OUT8VA
AL
L
L
7FE2 FASTXFR
Fast Transfer Mode
FISO
FBLK
RPOL
RMOD1
RMOD0
WPOL
WMOD1
7FE3 AUTOPTRH
Auto-Pointer H
A15
A14
A13
A12
A11
A10
A9
WMOD0
A8
7FE4 AUTOPTRL
Auto-Pointer L
A7
A6
A5
A4
A3
A2
A1
A0
7FE5 AUTODATA
Auto Pointer Data
D7
D6
D5
D4
D3
D2
D1
D0
8 bytes of SETUP data
d7
d6
d5
d4
d3
d2
d1
d0
7FE6-7FE7 (reserved)
Setup Data
7FE8 SETUPDAT
Isochronous FIFO Sizes
7FF0 OUT8ADDR
Endpt 8 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF1 OUT9ADDR
Endpt 9 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF2 OUT10ADDR
Endpt 10 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF3 OUT11ADDR
Endpt 11 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF4 OUT12ADDR
Endpt 12 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF5 OUT13ADDR
Endpt 13 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF6 OUT14ADDR
Endpt 14 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF7 OUT15ADDR
Endpt 15 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF8 IN8ADDR
Endpt 8 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF9 IN9ADDR
Endpt 9 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFA IN10ADDR
Endpt 10 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFB IN11ADDR
Endpt 11 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFC IN12ADDR
Endpt 12 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFD IN13ADDR
Endpt 13 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFE IN14ADDR
Endpt 14 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFF IN15ADDR
Endpt 15 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
Document #: 38-08005 Rev. *B
Page 28 of 42
CY7C64613
5.0
Input/Output Pin Special Consideration
The EZ-USB FX has a weak internal pull-up resistor that is present on the inputs and outputs when the external signal level is a
high (above 1.3V). The weak internal pull-up is not present in the circuit when the voltage level of the external signal is low. Since
the weak pull-up is only in the circuit when the external signal level is high, this means that if the last voltage level driven on the
pin was a high, the pull-up resistor will keep it high. However, if the last voltage level driven on the pin was a low then the pull-up
is turned off and the pad can float until it gets to a high logic level. This situation affects both inputs as well as outputs that are
three-stated. Use a 25-K ohms or lower pull-down resistor to bring a pin to a low level if needed.
6.0
Absolute Maximum Ratings
Storage Temperature ..........................................................................................................................................–65°C to +150°C
Ambient Temperature with Power Supplied ...............................................................................................................0°C to +70°C
Supply Voltage on VCC relative to GND.................................................................................................................. –0.5V to +4.0V
DC Input Voltage.................................................................................................................................................... –0.5V to 5.25V
DC Voltage Applied to Outputs in High Z State...............................................................................................–0.5V to VCC + 0.5V
Power Dissipation ..............................................................................................................................................................500 mW
Static Discharge Voltage .......................................................................................................................................................> 2 kV
Latch-up Current ............................................................................................................................................................. > 200 mA
Max Output Sink Current ..................................................................................................................................................... 10 mA
7.0
Operating Conditions
TA (Ambient Temperature Under Bias) ......................................................................................................................0°C to +70°C
Supply Voltage ........................................................................................................................................................ +3.0V to +3.6V
Ground Voltage .......................................................................................................................................................................... 0V
FOSC (Oscillator or Crystal Frequency) ............................................................................................................. 12 MHz ± 0.20%[3]
8.0
DC Characteristics
Parameter
Description
VCC
Supply Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
II
Input Leakage Current
VOH
Output Voltage High
VOL
Output Low Voltage
CIN
Input Pin Capacitance
Suspend Current
ISUSP
ICC
Supply Current
USB Transceiver
VOH
Output Voltage High
VOL
Output Low Voltage
RpH
Output Impedance (HIGH state)
RpL
Output Impedance (LOW state)
Ii
Input Leakage Current
Ioz
Three-State Output OFF-State
Current
Conditions
0< VIN < VCC
IOUT = 1.6 mA
IOUT = –1.6 mA
Min.
3.0
2
–0.5
Max.
3.6
5.25
0.8
±10
120
35
0.4
10
275[5]
50[4]
Unit
V
V
V
µA
V
V
pF
µA
mA
±0.1
3.6
0.3
44
44
±5
V
V
Ω
Ω
µA
±10
µA
2.4
8051 running, connected to USB
IOUT = 1.6 mA
IOUT = –1.6 mA
Includes external 22Ω ±5% resistor
Includes external 22Ω ±5% resistor
VCC = 3.6V; VI = 5.5V or GND; not for
IO pins
VI = VIH or VIL;
VO = VCC or GND
Typ.
2.8
0.0
28
28
Notes:
3. The USB Specification requires that the full-speed data rate when transmitting is 12.000 Mb/s ± 0.25% (2,500 ppm). Hence, the allowed variance of Fosc must
be tighter than 0.25% to guarantee 0.25% when transmitting on the USB.
4. A guideline only. Not guaranteed.
5. Maximum suspend current is not guaranteed.
Document #: 38-08005 Rev. *B
Page 29 of 42
CY7C64613
9.0
9.1
AC Electrical Characteristics
USB Transceiver
Specified Conditions: per Table 7-9 Full-speed Source Electrical Characteristics Revision 2.0 of the USB specification
Parameter
Min.
Max.
Unit
Rise and Fall Times Full Speed
Description
4
20
ns
4
20
ns
tRFM
Rise/Fall Time Matching
90
110
%
Vcr
Crossover Point
1.3
2.0
V
Trise
Condition
Tfall
9.2
Program Memory Read
t CL
CLKO UT
Note 6
tAV
tAV
A[15..0]
t STBL
tSTBH
PSEN#
[7]
t AC C 1
t D SU
D[7..0]
t DH
da ta in
f1_8051_pgm em rd.vsd
Parameter
Description
Min.
Typ.
Max.
Unit
Notes
ns
24 MHz
ns
48 MHz
tCL
1/CLKOUT Frequency
tAV
Delay from Clock to Valid Address
0
10
ns
tSTBL
Clock to PSEN# Low
0
8
ns
tSTBH
Clock to PSEN# High
0
8
ns
tDSU
Data Set-up to Clock
10
ns
tDH
Data Hold Time
0
ns
41.66
20.83
Notes:
6. CLKOUT is shown with positive polarity.
7. tACC1 is computed from the above parameters as follows:
tACC1(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC1(48 Mhz) = 3*tCL – tAV – tDSU = 44 ns.
Document #: 38-08005 Rev. *B
Page 30 of 42
CY7C64613
9.3
Data Memory Read
Stretch=0
tCL
CLKOUT
tAV
tSTBL
tSTBH
tAV
A[15..0]
RD#
tACC2 [8]
tDSU
D[7..0]
tDH
data in
Stretch=1
tCL
CLKOUT
tAV
A[15..0]
RD#
tACC3
[8]
tDSU
D[7..0]
tDH
data in
f2_8051_datamemrd.vsd
Parameter
tCL
Description
Min.
1/CLKOUT Frequency
Typ.
Max.
Unit
41.66
ns
24 MHz
20.83
ns
48 MHz
tAV
Delay from Clock to Valid Address
0
10
ns
tSTBL
Clock to RD Low
0
8
ns
tSTBH
Clock to RD High
0
tDSU
Data Set-up to Clock
tDH
Data Hold Time
0
Notes
8
ns
10
ns
ns
Note:
8. tACC2 and tACC3 are computed from the above parameters as follows:
tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC2(48 Mhz) = 3*tCL – tAV – tDSU = 44 ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 188 ns
tACC3(48 Mhz) = 5*tCL – tAV – tDSU = 85 ns.
Document #: 38-08005 Rev. *B
Page 31 of 42
CY7C64613
9.4
Data Memory Write
S tretch = 0
t CL
C LK OUT
t AV
t AV
t STBH
t STBL
A [15..8]
W R#
tO N 1
tOF F 1
D [7..0]
data out
S tretch = 1
tCL
C LK OUT
tAV
t AV
A [15..8]
W R#
tO F F 1
tO N 1
D [7..0]
data out
Parameter
Description
Min.
Max.
Unit
tAV
Delay from Clock to Valid Address
0
10
ns
tSTBL
Clock to WR Pulse Low
0
8
ns
tSTBH
Clock to WR Pulse High
0
8
ns
tON1
Clock to Data Turn-on
0
7
ns
tOFF1
Clock to Data Hold Time
–2
7
ns
Document #: 38-08005 Rev. *B
Notes
Page 32 of 42
CY7C64613
9.5
DMA Read
non-burst
tCL
CLKOUT
tAV
A[15..0]
Note 9
tSTBL
RD#/FRD#
CS#, OE#
Note 10
tDSU
D[7..0]
tSTBH
tDH
in
in
in
burst
tCL
CLKOUT
tAV
A[15..0]
Note 9
RD#/FRD#
CS#, OE#
tSTBL
tSTBH
tDSU
D[7..0]
tDH
in
in
in
in
in
f4_dmard.vsd
Min.
Max.
Unit
tAV
Parameter
Delay from Clock to Valid Address
Description
0
10
ns
Notes
tSTBL
Clock to Strobe Low
0
8
ns
Non-burst
tSTBH
Clock to Strobe High
0
8
ns
Non-burst
tDSU
Data to Clock Set-up
10
ns
tDH
Clock to Data Hold
0
ns
Notes:
9. The address bus is not used in external FIFO transfers that use FRD#.
10. This is the maximum data rate. The strobes are programmable for longer access times.
Document #: 38-08005 Rev. *B
Page 33 of 42
CY7C64613
9.6
DMA Write
t CL
Non - Burst
CLK OUT
t AV
A [15..0]
Note 11
tSTBL
W R#/FW R#
CS #, OE #
Note 12
t ON 1
tD A
tSTBH
t OFF1
D[7..0]
Burst
t CL
CLK OUT
tAV
A [15..0]
Note 11
tSTBL
tSTBH
W R#/FW R#
CS #, OE #
tD A
D[7..0]
f5_dm awr.v s d
Parameter
Description
Min.
Max.
Unit
Notes
tAV
Clock to Address Valid
0
10
ns
tSTBL
Clock to Strobe Low
0
8
ns
Non-burst
tSTBH
Clock to Strobe High
0
8
ns
Non-burst
tDA
Clock to Valid Data
12
ns
tON1
Clock to Data Turn-on
0
7
ns
tOFF1
Clock to Data Hold Time
–2
7
ns
Notes:
11. The address bus in not used in external FIFO transfers (FWR# strobe).
12. This is the maximum data rate. The WR/FWR pulses are programmable for longer access times.
Document #: 38-08005 Rev. *B
Page 34 of 42
CY7C64613
9.7
Slave FIFOs—Output Enables
AOE
BOE
tON
AFI [7..0]
BFI [7..0]
tOFF
f6_fifo_sync_oe.vsd
Min.
Max.
Unit
tON
Parameter
FIFO Data Bus Turn-on Time
0
10
ns
tOFF
FIFO Data Bus Turn-off Time
0
10
ns
9.8
Description
Slave FIFOs—Synchronous Read
tCL
XCLK
[13]
tSUX
t XH
ASEL/BSEL
SLRD
t XDA
AFI/BFI [7..0]
tXF LAG
FLAGS
f7_fifo_sync_read.vsd
Parameter
Description
tSUX
Strobe and Sel to External Clock Set-up Time
tXH
External Clock to Strobe and Sel Hold Time
tXDA
Clock to A/B FIFO data
tXFLAG
Clock to FIFO flag
Min.
Max.
Unit
9
ns
6
ns
13
ns
2tCL+11
ns
Note:
13. XCLK must be greater than or equal to 5 MHz, and less than (but not equal to) 48 MHz and must be free running.
Document #: 38-08005 Rev. *B
Page 35 of 42
CY7C64613
9.9
Slave FIFOs—Synchronous Write
tCL
XCLK
[13]
t SU X
tXH
ASEL/BSEL
SLWR
AFI/BFI [7..0]
valid
tXFLAG
FLAGS
f8_fifo_sync_write.vsd
Parameter
Description
Min.
tCL
CLKOUT Period
tSUX
Sel, Strobe & Data Set-up to External Clock
9
tXH
External Clock to Sel, Strobe & Data Hold Time
2
tXFLAG
External Clock to FIFO Flag
9.10
Typ.
Max.
Unit
41.66
ns
20.83
ns
ns
ns
2tCL+11
ns
Slave FIFOs—Asynchronous Read[14, 15]
Note 16
A S E L/B S E L
t RDL
t RDH
S LRD
t
AC C A
A FI/B FI [7..0]
t
AFLAG
FLA GS
f9_fifo_as y nc _read.v s d
Parameter
Description
Min.
Max.
Unit
tRDL
SLRD strobe active
30
ns
tRDH
SLRD strobe inactive
70
ns
tACCA
Read active to FIFO data valid
40
ns
tAFLAG
SLRD inactive to FIFO flag
95
ns
90
ns
Notes
double byte mode
Notes:
14. The timing diagram assumes OEA/OEB is active.
15. The read operation begins when both A/BSEL and SLRD are active, and ends when either is inactive.
16. The polarities of ASEL/BSEL and SLRD are programmable. Active-LOW is shown.
Document #: 38-08005 Rev. *B
Page 36 of 42
CY7C64613
Slave FIFOs—Asynchronous Write[14, 15]
9.11
Note 16
ASEL/BSEL
t
t
W RL
W RH
SLW R
t
t
S UA
HA
AFI/BFI [7..0]
t
AFLAG
FLAGS
f10_fi fo_as y nc _wri te.v s d
Parameter
Description
Min.
Max.
Unit
tWRL
Slave Write Strobe Active
30
ns
tWRH
Slave Write Strobe Inactive
70
ns
tSUA
Async Data Set-up Time to Write Strobe Inactive
10
ns
tHA
Async Data Hold Time to Write Strobe Inactive
5
tAFLAG
Async Write Strobe Inactive to FIFO Flag Valid
9.12
ns
95
ns
GPIF – Clocked with Fixed 48-MHz Internal Clock
tCL
Internal
(48MHz )
t SRY
tRY H
R D Yn
G D [15..0] (input)
va lid
t XG D
C T Ln and
GD [15..0] (output)
Parameter
Description
tSRY
Set-up time: RDYn and GPIF Data to External Clock
tRYH
Hold time: External Clock to RDYn and GPIF Data
tXGD
Clock to GPIF Data and CTLn output
tCL
Clock Period
Document #: 38-08005 Rev. *B
Min.
Max.
9
2
20.83
Unit
ns
ns
13
ns
20.83
ns
Page 37 of 42
CY7C64613
9.13
GPIF Signals Externally Clocked – XCLK
tCL
XC LK
(input)
tSR X
t RY X
R D Yn
GD [15..0] (input)
va lid
t XG X
C TLn and
GD [15..0] (output)
Parameter
Description
Min.
tSRX
Set-up Time: RDYn and GPIF Data to External Clock
9
tRYX
Hold Time: External Clock to RDYn and GPIF Data
2
tXGX
Clock to GPIF Data and CTLn output
tCL
XCLK Period
10.0
Max.
Unit
ns
ns
21[17]
13
ns
200[17]
ns
Ordering Information
Part
Number
Package
Type
RAM
Size
Burst I/O Rate
(Bytes/sec)
# Prog
I/Os
CY7C64613-52NC
52 PQFP
8K
48 Mbytes
16
8-bit
Yes
CY7C64613-80NC
80 PQFP
8K
96 Mbytes
32
16-bit
Yes
CY7C64613-128NC
128 PQFP
8K
96 Mbytes
40
16-bit + Addr
Yes
EZ-USB FX Xcelerator
Development Kit
11.0
Dataport
Isochronous
Support
CY3671
Package Diagrams
Key for all package diagrams:
BSC = Basic Standard Configuration
All dimensions are in millimeters (mm).
Note:
17. XCLK must be greater than or equal to 5 MHz, and less than (but not equal to) 48 MHz and must be free running.
Document #: 38-08005 Rev. *B
Page 38 of 42
CY7C64613
11.1
52 PQFP
52-Lead Plastic Quad Flatpack N52
51-85042-**
Document #: 38-08005 Rev. *B
Page 39 of 42
CY7C64613
11.2
80 PQFP
80-Lead Plastic Quad Flatpack (14 x 14 x 2.80 mm) N80A
51-85174-**
Document #: 38-08005 Rev. *B
Page 40 of 42
CY7C64613
11.3
128 PQFP
128-Lead Plastic Quad Flatpack
51-85080-*A
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C standard specification
defined by Philips. EZ-USB is a registered trademark, and EZ-USB FX is a trademark, of Cypress Semiconductor. All product
and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-08005 Rev. *B
Page 41 of 42
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C64613
Document History Page
Document Title: CY7C64613 EZ-USB FX™ USB Microcontroller
Document Number: 38-08005
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110206
11/11/01
SZV
Change from Spec number: 38-00903 to 38-08005
*A
114944
01/08/03
KKU
Corrected pinouts and register names in all sections.
Removed CY7C64601 and CY7C64603 part number and references.
*B
125185
04/23/03
KKU
Correct Figure 1-1, Centered 52 pin package in 11.1, Correct 128 pin
package in 11.3
Document #: 38-08005 Rev. *B
Page 42 of 42