Cypress CY8C24994 Psocâ® programmable system-on-chipâ ¢ Datasheet

CY8C24094, CY8C24794
CY8C24894, CY8C24994
PSoC® Programmable System-on-Chip™
1. Features
■
XRES Pin to Support In-System Serial Programming (ISSP)
and External Reset Control in CY8C24894
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3V to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
❐ USB Temperature Range: -10°C to +85°C
■
Advanced Peripherals (PSoC Blocks)
❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ 4 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
❐ Capacitive Sensing Application Capability
2. Logic Block Diagram
Full Speed USB (12 Mbps)
❐ Four Uni-Directional Endpoints
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required
■
Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase and Write Cycles
❐ 1K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■
Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Drive on all GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to 48 Analog Inputs on GPIO
❐ Two 33 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
■
Precision, Programmable Clocking
❐ Internal ±4% 24 and 48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
❐ 0.25% Accuracy for USB with no External Components
Additional System Resources
2
❐ I C™ Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User Configurable Low Voltage Detection
■
Port 5
Port 7
System Bus
■
Port 4
Port 3
Global Digital Interconnect
Port 2
Port 1
Port 0
Analog
Drivers
Global Analog Interconnect
PSoC CORE
SRAM
1K
SROM
Flash 16K
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
ClockSources
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Digital
2
Decimator
Clocks MACs Type 2
Analog
Block
Array
I2C
Internal
POR and LVD
Voltage
System Resets
Ref.
USB
Analog
Input
Muxing
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 38-12018 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 04, 2008
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The PSoC family consists of many Mixed-Signal Array with
On-Chip Controller devices. All PSoC family devices are
designed to replace traditional MCUs, system ICs, and the
numerous discrete components that surround them. The PSoC
CY8C24x94 devices are unique members of the PSoC family
because it includes a full featured, full speed (12 Mbps) USB
port. Configurable analog, digital, and interconnect circuitry
enable a high level of integration in a host of industrial,
consumer, and communication applications.
3.2 The Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource used alone or combined with
other blocks to form 8, 16, 24, and 32-bit peripherals, which are
called user module references.
Figure 3-1. Digital System Block Diagram
Port 7
This architecture allows the user to create customized peripheral
configurations that match the requirements of each individual
application. Additionally, a fast CPU, Flash program memory,
SRAM data memory, and configurable IO are included in a range
of convenient pinouts and packages.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 8%
over temperature and voltage. The 24 MHz IMO can also be
doubled to 48 MHz for use by the digital system. A low power 32
kHz ILO (internal low speed oscillator) is provided for the Sleep
timer and WDT. The clocks, together with programmable clock
dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC device. In
USB systems, the IMO self tunes to ± 0.25% accuracy for USB
communication.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin is also capable of generating a system interrupt
on high level, low level, and change from last read.
Document Number: 38-12018 Rev. *L
To System Bus
Port 0
ToAnalog
System
DIGITAL SYSTEM
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
GIE[7:0]
GIO[7:0]
GlobalDigital
Interconnect
8
Row Output
Configuration
Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
Port 1
Port 2
Digital PSoC Block Array
3.1 The PSoC Core
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Port 3
Digital Clocks
FromCore
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources including a full-speed USB port. Configurable global busing allows all the device resources to be
combined into a complete custom system. The PSoC
CY8C24x94 devices can have up to seven IO ports that connect
to the global digital and analog interconnects, providing access
to 4 digital blocks and 6 analog blocks.
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
Port 5
Port 4
Row Input
Configuration
3. PSoC Functional Overview
8
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include those listed below.
■
Full-Speed USB (12 Mbps)
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 24 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity
■
SPI master and slave
■
I2C slave and multi-master
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow signal multiplexing and performing logic operations.
This configurability frees the designs from the constraints of a
fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in Table 3-1 on page 4.
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Figure 3-2. Analog System Block Diagram
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are listed below.
■
Filters (2 and 4 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to 2, with 16 selectable thresholds)
■
DACs (up to 2, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
P 0 [6 ]
P 0 [5 ]
P 0 [4 ]
P 0 [3 ]
P 0 [2 ]
P 0 [1 ]
P 0 [0 ]
P 2 [3 ]
AGNDIn RefIn
Analog-to-digital converters (up to 2, with 6 to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
P 0 [7 ]
Analog
■
All IO
(E x c e p t P o r t 7 )
Mux Bus
3.1 The Analog System
P 2 [1 ]
P 2 [6 ]
P 2 [4 ]
P 2 [2 ]
P 2 [0 ]
AC I0 [1 :0 ]
AC I1 [1 :0 ]
Ar r a y In p u t
C o n f ig u r a t io n
B lo c k
Ar r a y
ACB00
ACB01
Modulators
ASC10
ASD11
■
Correlators
ASD20
ASC21
■
Peak Detectors
■
Many other topologies possible
A n a lo g R e fe re n c e
In t e r f a c e t o
D ig it a l S ys t e m
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in Figure 3-2.
R e fHi
R e fL o
A G ND
R e fe re n c e
G e n e r a to rs
A G ND In
R e fIn
Bandgap
M 8 C In t e r f a c e ( Ad d r e s s B u s , D a t a B u s , E t c .)
3.0.1 The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin in ports 0-5.
Pins are connected to the bus individually or in any combination.
The bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. It is split into two
sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
Track pad, finger sensing.
■
Chip-wide mux that allows analog input from up to 48 IO pins.
■
Crosspoint connection between any IO pin combinations.
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which are found under http://www.cypress.com > Design
Resources > Application Notes. In general, and unless otherwise
noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.
Document Number: 38-12018 Rev. *L
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4. Getting Started
3.1 Additional System Resources
System Resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief statements describing the merits of each resource follow.
■
Full-Speed USB (12 Mbps) with 5 configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature USB
operation (-10°C to +85°C).
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks are
generated using digital PSoC blocks as clock dividers.
■
Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.
■
Decimator provides a custom hardware filter for digital signal
processing applications including creation of Delta Sigma
ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, multi-master are supported.
■
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
Versatile analog multiplexer system.
3.2 PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups. The device covered by this data
sheet is shown in the highlighted row of the table
Table 3-1. PSoC Device Characteristics
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on the
web at http://www.cypress.com/psoc.
To determine which PSoC device meets your requirements,
navigate through the PSoC Decision Tree in the Application Note
AN2209 at http://www.cypress.com and select Application Notes
under the Design Resources.
4.1 Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
Order >> Buy Kits at http://www.cypress.com/shop, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
4.2 Technical Training Modules
Free On-Demand PSoC Training modules are available for new
users to PSoC. Training modules cover designing, debugging,
advanced
analog,
and
CapSense.
Go
to
http://www.cypress.com/techtrain.
4.3 Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Support
located at the top of the web page, and select CYPros
Consultants.
Digital
IO
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
4.4 Technical Support
CY8C29x66
up to
64
4
16
12
4
4
12
2K
32K
CY8C27x43
up to
44
2
8
12
4
4
12
256
Bytes
16K
CY8C24x94
56
1
4
48
2
2
6
1K
16K
CY8C24x23A
up to
24
1
4
12
2
2
6
256
Bytes
4K
CY8C21x34
up to
28
1
4
28
0
2
4[1]
512
Bytes
8K
CY8C21x23
16
1
4
8
0
2
4[1]
256
Bytes
4K
CY8C20x34
up to
28
0
0
28
0
0
3[2]
512
Bytes
8K
PSoC Part
Number
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, reference the PSoC
Programmable System-on-Chip Technical Reference Manual.
PSoC application engineers take pride in fast and accurate
response. They are available with a four hour guaranteed
response at http://www.cypress.com/support/.
4.5 Application Notes
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to
http://www.cypress.com and select Application Notes under
Documentation list located in the center of the web page. .
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense.
Document Number: 38-12018 Rev. *L
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5. Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP. (Reference the PSoC Designer
Functional Flow diagram below.)
PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC,
and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 5-1. PSoC Designer Subsystems
Graphical Designer
Interface
Context
Sensitive
Help
Importable
Design
Database
Device
Database
Application
Database
PSoC
Designer
Core
Engine
Project
Database
PSoC
Configuration
Sheet
Manufacturing
Information
File
User
Modules
Library
Emulation
Pod
PSoC Designer sets up power-on initialization tables for selected
PSoC block configurations and creates source code for an application framework. The framework contains software to operate
the selected components and, if the project uses more than one
operating configuration, contains routines to switch between
different sets of PSoC block configurations at run time. PSoC
Designer can print out a configuration sheet for a given project
configuration for use during application programming in
conjunction with the Device Data Sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It’s also possible to change the selected
components and regenerate the framework.
5.1.2 Design Browser
The Design Browser allows users to select and import preconfigured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
5.1.3 Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Results
Commands
PSoC
Designer
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.
Assembler. The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries automatically use absolute addressing or are compiled in relative mode,
and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available that
supports the PSoC family of devices. Even if you have never
worked in the C language before, the product quickly allows you
to create complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
5.1.4 Debugger
In-Circuit
Emulator
Device
Programmer
5.1 PSoC Designer Software Subsystems
5.1.1 Device Editor
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
Document Number: 38-12018 Rev. *L
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
5.1.5 Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
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5.2 Hardware Tools
5.2.1 In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
6. Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware and software. This substantially lowers the risk of
having to select a different part to meet the final design requirements.
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run-time. The API also provides optional interrupt service
routines that you can adapt as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by inter-
Document Number: 38-12018 Rev. *L
connecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and enter
parameter values directly or by selecting values from drop-down
menus. When you are ready to test the hardware configuration
or move on to developing code for the project, you perform the
“Generate Application” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the high-level user module API
functions.
Figure 6-1. User Module/Source Code Development Flows
Device Editor
User
Module
Selection
Placement
and
Parameter
-ization
Source
Code
Generator
Generate
Application
Application Editor
Project
Manager
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (including
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
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7. Document Conventions
7.2 Units of Measure
7.1 Acronyms Used
A units of measure table is located in the Electrical Specifications
section. Table 10-1 on page 20 lists all the abbreviations used to
measure the PSoC devices.
The following table lists the acronyms that are used in this
document.
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
FSR
full scale range
GPIO
general purpose IO
GUI
graphical user interface
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
IO
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
PWM
pulse width modulator
SC
switched capacitor
SRAM
static random access memory
Document Number: 38-12018 Rev. *L
7.3 Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
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8. Pin Information
This section describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration.
The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin
(labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
8.1 56-Pin Part Pinout
Table 8-1. 56-Pin Part Pinout (QFN[4]) See LEGEND details and footnotes in Table 8-2 on page 9.
P5[4]
44
IO
M
P2[6]
External Voltage Reference (VREF) input.
M
P5[6]
45
IO
I, M
P0[0]
Analog column mux input.
33
IO
M
P3[0]
46
IO
I, M
P0[2]
Analog column mux input.
34
IO
M
P3[2]
47
IO
I, M
P0[4]
Analog column mux input VREF.
35
IO
M
P3[4]
48
IO
I, M
P0[6]
Analog column mux input.
36
IO
M
P3[6]
49
Vdd
Supply voltage.
37
IO
M
P4[0]
50
38
IO
M
P4[2]
51
IO
I, M
P0[7]
Analog column mux input,.
39
IO
M
P4[4]
52
IO
IO, M
P0[5]
Analog column mux input and column output.
40
IO
M
P4[6]
53
IO
IO, M
P0[3]
Analog column mux input and column output.
41
IO
I, M
P2[0]
Direct switched capacitor block input.
54
IO
I, M
P0[1]
Analog column mux input.
42
IO
I, M
P2[2]
Direct switched capacitor block input.
55
IO
M
P2[7]
43
IO
M
P2[4]
External Analog Ground (AGND) input.
56
IO
M
P2[5]
Power
P7[0]
44
43
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P2[2], A, I, M
P2[0], A, I, M
P4[6], M
P4[4], M
P4[2], M
P4[0], M
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
M, I2C SDA, P1[0]
M,P1[2]
EXTCLK, M,P1[4]
M, P1[6]
21
22
23
24
M,P1[3]
M, I2C SCL, P1[1]
Vss
D+
DVdd
P7[7]
Vss
46
45
51
50
49
48
47
56
55
54
53
52
QFN
(Top V ie w )
15
16
17
18
19
20
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
Document Number: 38-12018 Rev. *L
Power
P2[4],M
M
IO
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6],M
IO
32
P0[7], A, I, M
Vss
31
P0[5], A, IO, M
56-Pin PSoC Device
P2[5],M
P2[7],M
P0[1], A, I, M
P0[3], A, IO, M
Type
Pin
Figure 8-1. CY8C24794
Description
No. Digital Analog Name
1
IO
I, M
P2[3] Direct switched capacitor block input.
2
IO
I, M
P2[1] Direct switched capacitor block input.
3
IO
M
P4[7]
4
IO
M
P4[5]
5
IO
M
P4[3]
A, I, M , P2[3]
1
6
IO
M
P4[1]
A, I, M , P2[1]
2
7
IO
M
P3[7]
M , P4[7]
3
8
IO
M
P3[5]
M , P4[5]
4
9
IO
M
P3[3]
M , P4[3]
5
10
IO
M
P3[1]
M , P4[1]
6
M , P3[7]
7
11
IO
M
P5[7]
8
M , P3[5]
12
IO
M
P5[5]
M , P3[3]
9
13
IO
M
P5[3]
M , P3[1]
10
14
IO
M
P5[1]
M , P5[7]
11
15
IO
M
P1[7] I2C Serial Clock (SCL).
M , P5[5]
12
M , P5[3]
13
16
IO
M
P1[5] I2C Serial Data (SDA).
M , P5[1]
14
17
IO
M
P1[3]
18
IO
M
P1[1] I2C Serial Clock (SCL), ISSP SCLK[3].
19
Power
Vss Ground connection.
20
USB
D+
21
USB
D22
Power
Vdd Supply voltage.
23
IO
P7[7]
24
IO
P7[0]
25
IO
M
P1[0] I2C Serial Data (SDA), ISSP SDATA[3].
26
IO
M
P1[2]
27
IO
M
P1[4] Optional External Clock Input (EXTCLK).
28
IO
M
P1[6]
29
IO
M
P5[0]
Type
Pin
Name
No. Digital Analog
30
IO
M
P5[2]
Description
Ground connection.
Page 8 of 46
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.1 56-Pin Part Pinout (with XRES)
Table 8-2. 56-Pin Part Pinout (QFN[4])
29
IO
M
P5[0]
30
IO
M
P5[2]
Type
Pin
No. Digital Analog Name
31
IO
M
P5[4]
44
IO
M
P2[6]
External Voltage Reference (VREF) input.
32
IO
M
P5[6]
45
IO
I, M
P0[0]
Analog column mux input.
33
IO
M
P3[0]
46
IO
I, M
P0[2]
Analog column mux input.
34
IO
M
P3[2]
47
IO
I, M
P0[4]
Analog column mux input VREF.
35
IO
M
P3[4]
48
IO
I, M
P0[6]
Analog column mux input.
49
Vdd
Supply voltage.
36
Input
I,
I,
I,
I,
A,
A,
A,
A,
M
M
48
47
46
45
44
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
QFN
(Top View)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P2[2],
P2[0],
P4[6],
P4[4],
P4[2],
P4[0],
XRES
P3[4],
P3[2],
P3[0],
P5[6],
P5[4],
P5[2],
P5[0],
A, I, M
A, I, M
M
M
M
M
M
M
M
M
M
M
M
M, I2C SCL,
M, I2C SDA,
M,
M, I2C SCL,
P1[7]
P1[5]
P1[3]
P1[1]
Vss
D+
DVdd
P7[7]
P7[0]
M, I2C SDA, P1[0]
M, P1[2]
EXTCLK, M, P1[4]
M, P1[6]
A, I, M,
A, I, M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
56
55
54
53
52
51
50
49
P2[5],
P2[7],
P0[1],
P0[3],
P0[5],
P0[7],
Vss
Vdd
P0[6],
P0[4],
P0[2],
P0[0],
P2[6],
P2[4],
M
M
A,
A,
A,
A,
M
M
M
M
Figure 8-2. CY8C24894 56-Pin PSoC Device
I, M
IO, M
IO, M
I, M
Type
Pin
Description
No. Digital Analog Name
1
IO
I, M
P2[3] Direct switched capacitor block input.
2
IO
I, M
P2[1] Direct switched capacitor block input.
3
IO
M
P4[7]
4
IO
M
P4[5]
5
IO
M
P4[3]
6
IO
M
P4[1]
7
IO
M
P3[7]
8
IO
M
P3[5]
9
IO
M
P3[3]
10
IO
M
P3[1]
11
IO
M
P5[7]
12
IO
M
P5[5]
13
IO
M
P5[3]
14
IO
M
P5[1]
15
IO
M
P1[7] I2C Serial Clock (SCL).
16
IO
M
P1[5] I2C Serial Data (SDA).
17
IO
M
P1[3]
18
IO
M
P1[1] I2C Serial Clock (SCL), ISSP SCLK[3].
19
Power
Vss Ground connection.
20
USB
D+
21
USB
D22
Power
Vdd Supply voltage.
23
IO
P7[7]
24
IO
P7[0]
25
IO
M
P1[0] I2C Serial Data (SDA), ISSP SDATA[3].
26
IO
M
P1[2]
27
IO
M
P1[4] Optional External Clock Input (EXTCLK).
28
IO
M
P1[6]
Power
Description
37
IO
M
XRES Active high external reset with internal
pull down.
P4[0]
38
IO
M
P4[2]
51
IO
I, M
P0[7]
Analog column mux input,.
39
IO
M
P4[4]
52
IO
IO, M
P0[5]
Analog column mux input and column output.
40
IO
M
P4[6]
53
IO
IO, M
P0[3]
Analog column mux input and column output.
41
IO
I, M
P2[0]
Direct switched capacitor block input.
54
IO
I, M
P0[1]
Analog column mux input.
42
IO
I, M
P2[2]
Direct switched capacitor block input.
55
IO
M
P2[7]
43
IO
M
P2[4]
External Analog Ground (AGND) input.
56
IO
M
P2[5]
50
Power
Vss
Ground connection.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Notes
3. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
4. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
Document Number: 38-12018 Rev. *L
Page 9 of 46
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CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.1 68-Pin Part Pinout
The 68-pin QFN part table and drawing below is for the CY8C24994 PSoC device.
Table 8-3. 68-Pin Part Pinout (QFN[4])
M
M
M
P4[0]
P4[2]
P4[4]
P2[6], M, Ext. VREF
P2[4], M, Ext. AGND
P2[2], M, AI
53
52
P0[2], M, AI
P0[0], M, AI
55
54
58
57
56
P0[7], M, AI
Vss
Vdd
P0[6], M, AI
P0[4], M, AI
P0[1], M, AI
P0[3], M, AIO
P0[5], M, AIO
63
62
61
60
59
64
P2[3], M, AI
P2[5], M
P2[7], M
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Vss
P0[7]
P0[5]
63
64
65
IO
IO
IO
IO,M
I,M
M
P0[3]
P0[1]
P2[7]
66
67
68
IO
IO
IO
M
I,M
I,M
P2[5]
P2[3]
P2[1]
50
51
52
Optional External Clock Input (EXTCLK). 53
54
55
56
57
58
59
60
61
62
I2C Serial Data (SDA), ISSP SDATA[3].
No connection.
No connection.
Active high pin reset with internal pull
down.
66
65
Type
Digital Analog
IO
M
IO
I,M
IO
I,M
IO
M
IO
M
IO
I,M
IO
I,M
IO
I,M
IO
I,M
Power
Power
IO
I,M
IO
IO,M
Pin
No.
Name
31
32
33
34
38
37
36
35
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
NC
NC
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
EXTCLK, M, P1[4]
Supply voltage.
I2C SDA, M, P1[0]
M, P1[2]
I2C Serial Clock (SCL) ISSP SCLK[3].
Ground connection.
QFN
(Top View)
28
29
30
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
49
48
47
46
45
44
43
42
41
40
39
P7[3]
P7[2]
P7[1]
P7[0]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
51
50
24
25
26
27
M, P4[1]
NC
NC
Vss
M, P3[7]
M, P3[5]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
P7[7]
P7[6]
P7[5]
P7[4]
M, P4[7]
M, P4[5]
M, P4[3]
20
21
22
23
IO
IO
IO
P2[1], M, AI
47
48
49
No connection.
No connection.
Ground connection.
68
67
Input
NC
NC
XRES
Figure 8-3. CY8C24994 68-Pin PSoC Device
18
19
44
45
46
Description
M, P1[3]
P4[7]
P4[5]
P4[3]
P4[1]
NC
NC
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
D+
DVdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
Name
I2C SCL, M, P1[1]
Vss
D+
DVdd
Type
Pin
No. Digital Analog
1
IO
M
2
IO
M
3
IO
M
4
IO
M
5
6
7
Power
8
IO
M
9
IO
M
10 IO
M
11
IO
M
12 IO
M
13 IO
M
14 IO
M
15 IO
M
16 IO
M
17 IO
M
18 IO
M
19 IO
M
20 Power
21 USB
22 USB
23 Power
24 IO
25 IO
26 IO
27 IO
28 IO
29 IO
30 IO
31 IO
32 IO
M
33 IO
M
34 IO
M
35 IO
M
36 IO
M
37 IO
M
38 IO
M
39 IO
M
40 IO
M
41 IO
M
42 IO
M
43 IO
M
Description
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
External Voltage Reference (VREF) input.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Ground connection.
Analog column mux input, integration input #1
Analog column mux input and column output, integration
input #2.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
Document Number: 38-12018 Rev. *L
Page 10 of 46
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CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.1 68-Pin Part Pinout (On-Chip Debug)
The 68-pin QFN part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 8-4. 68-Pin Part Pinout (QFN[4])
Type
Pin
No. Digital Analog
50 IO
M
I2C Serial Data (SDA), ISSP SDATA[3]. 51 IO
I,M
52 IO
I,M
Optional External Clock Input (EXTCLK). 53 IO
M
54 IO
M
55 IO
I,M
56 IO
I,M
57 IO
I,M
58 IO
I,M
59 Power
60 Power
61 IO
I,M
62 IO
IO,M
IO
IO
IO
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Vss
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
47 IO
M
P4[0]
66 IO
M
48 IO
M
P4[2]
67 IO
I,M
49 IO
M
P4[4]
68 IO
I,M
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger.
P2[5]
P2[3]
P2[1]
Document Number: 38-12018 Rev. *L
63
64
65
Name
IO,M
I,M
M
Input
P2[6], M, Ext. VREF
P2[4], M, Ext. AGND
P2[2], M, AI
I2C SDA, M, P1[0]
M, P1[2]
EXTCLK M, P1[4]
28
29
30
31
32
33
34
P7[3]
P7[2]
P7[1]
P7[0]
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
CCLK
HCLK
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
,
55
54
53
52
58
57
56
P0[7], M, AI
Vss
Vdd
P0[6], M, AI
P0[4], M, AI
P0[2], M, AI
P0[0], M, AI
64
63
62
61
60
59
P2[3], M, AI
P2[5], M
P2[7], M
P0[1], M, AI
P0[3], M, AIO
P0[5], M, AIO
QFN
(Top View)
P7[7]
P7[6]
P7[5]
P7[4]
Supply voltage.
OCD high-speed clock output.
OCD CPU clock output.
Active high pin reset with internal pull
down.
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
23
24
25
26
27
I2C Serial Clock (SCL), ISSP SCLK[3].
Ground connection.
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
OCDE
OCDO
Vss
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
20
21
22
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
P2[1], M, AI
HCLK
CCLK
XRES
OCD even data IO.
OCD odd data output.
Ground connection.
Figure 8-4. CY8C24094 68-Pin OCD PSoC Device
68
67
44
45
46
Description
18
19
P4[7]
P4[5]
P4[3]
P4[1]
OCDE
OCDO
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
D+
DVdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
Name
M, P1[3]
I2C SCL, M, P1[1]
Vss
D+
DVdd
Type
Pin
No. Digital Analog
1
IO
M
2
IO
M
3
IO
M
4
IO
M
5
6
7
Power
8
IO
M
9
IO
M
10 IO
M
11
IO
M
12 IO
M
13 IO
M
14 IO
M
15 IO
M
16 IO
M
17 IO
M
18 IO
M
19 IO
M
20 Power
21 USB
22 USB
23 Power
24 IO
25 IO
26 IO
27 IO
28 IO
29 IO
30 IO
31 IO
32 IO
M
33 IO
M
34 IO
M
35 IO
M
36 IO
M
37 IO
M
38 IO
M
39 IO
M
40 IO
M
41 IO
M
42 IO
M
43 IO
M
Description
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
External Voltage Reference (VREF) input.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Ground connection.
Analog column mux input, integration input #1
Analog column mux input and column output,
integration input #2.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Page 11 of 46
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.1 100-Ball VFBGA Part Pinout
The 100-ball VFBGA part is for the CY8C24994 PSoC device.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
Power
Power
Vss
Vss
NC
NC
NC
Power
Vdd
NC
NC
Power
Vss
Power
Vss
Power
Vss
Power
Vss
IO
I,M
P2[1]
IO
I,M
P0[1]
IO
I,M
P0[7]
Power
Vdd
IO
I,M
P0[2]
IO
I,M
P2[2]
Power
Vss
Power
Vss
NC
IO
M
P4[1]
IO
M
P4[7]
IO
M
P2[7]
IO
IO,M P0[5]
IO
I,M
P0[6]
IO
I,M
P0[0]
IO
I,M
P2[0]
IO
M
P4[2]
NC
NC
IO
M
P3[7]
IO
M
P4[5]
IO
M
P2[5]
IO
IO,M P0[3]
IO
I,M
P0[4]
IO
M
P2[6]
IO
M
P4[6]
IO
M
P4[0]
NC
NC
NC
IO
M
P4[3]
IO
I,M
P2[3]
Power
Vss
Power
Vss
IO
M
P2[4]
IO
M
P4[4]
IO
M
P3[6]
NC
Description
Ground connection.
Ground connection.
No connection.
No connection.
No connection.
Supply voltage.
No connection.
No connection.
Ground connection.
Ground connection.
Ground connection.
Ground connection.
Direct switched capacitor block input.
Analog column mux input.
Analog column mux input.
Supply voltage.
Analog column mux input.
Direct switched capacitor block input.
Ground connection.
Ground connection.
No connection.
Pin
No.
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
Analog column mux input and column output. H5
Analog column mux input.
H6
Analog column mux input.
H7
Direct switched capacitor block input.
H8
H9
No connection.
H10
No connection.
J1
J2
J3
J4
Analog column mux input and column output. J5
Analog column mux input.
J6
External Voltage Reference (VREF) input.
J7
J8
J9
No connection.
J10
No connection.
K1
No connection.
K2
K3
Direct switched capacitor block input.
K4
Ground connection.
K5
Ground connection.
K6
External Analog Ground (AGND) input.
K7
K8
K9
No connection.
K10
Analog
Name
Digital
Analog
Pin
No.
Digital
Table 8-5. 100-Ball Part Pinout (VFBGA)
IO M
IO M
IO M
Power
Power
IO M
IO M
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
M
M
M
M
M
M
M
M
IO M
IO M
IO M
IO M
IO M
IO M
IO M
IO M
IO
Power
Power
USB
USB
Power
IO
IO
IO M
Power
Power
Power
Power
Power
IO
IO
IO
Power
Power
Name
NC
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
NC
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
Vss
Vss
D+
DVdd
P7[7]
P7[0]
P5[2]
Vss
Vss
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
Description
No connection.
Ground connection.
Ground connection.
Active high pin reset with internal pull down.
No connection.
I2C Serial Clock (SCL).
I2C Serial Clock (SCL), ISSP SCLK[3].
I2C Serial Data (SDA), ISSP SDATA[3].
No connection.
I2C Serial Data (SDA).
Optional External Clock Input (EXTCLK).
Ground connection.
Ground connection.
Supply voltage.
Ground connection.
Ground connection.
Ground connection.
Ground connection.
No connection.
No connection.
Supply voltage.
Ground connection.
Ground connection.
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection.
Document Number: 38-12018 Rev. *L
Page 12 of 46
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Figure 8-5. CY8C24094 OCD (Not for Production)
1
2
3
4
5
6
7
8
9
10
A
Vss
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
B
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2]
P2[2]
Vss
Vss
C
NC
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
NC
D
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
NC
E
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
NC
F
NC
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
G
NC
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
H
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
J
Vss
Vss
D+
D-
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
K
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
BGA (Top View)
8.1 100-Ball VFBGA Part Pinout (On-Chip Debug)
The 100-pin VFBGA part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
Power
Power
Vss
Vss
NC
NC
NC
Power
Vdd
NC
NC
Power
Vss
Power
Vss
Power
Vss
Power
Vss
IO
I,M P2[1]
IO
I,M P0[1]
IO
I,M P0[7]
Power
Vdd
IO
I,M P0[2]
IO
I,M P2[2]
Power
Vss
Power
Vss
NC
IO
M
P4[1]
IO
M
P4[7]
IO
M
P2[7]
IO
IO,M P0[5]
IO
I,M P0[6]
IO
I,M P0[0]
Description
Ground connection.
Ground connection.
No connection.
No connection.
No connection.
Supply voltage.
No connection.
No connection.
Ground connection.
Ground connection.
Ground connection.
Ground connection.
Direct switched capacitor block input.
Analog column mux input.
Analog column mux input.
Supply voltage.
Analog column mux input.
Direct switched capacitor block input.
Ground connection.
Ground connection.
No connection.
Pin
No.
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
Analog column mux input and column output. H5
Analog column mux input.
H6
Analog column mux input.
H7
Document Number: 38-12018 Rev. *L
Analog
Name
Digital
Analog
Pin
No.
Digital
Table 8-6. 100-Ball Part Pinout (VFBGA)
IO M
IO M
IO M
Power
Power
IO M
IO M
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
M
M
M
M
M
M
M
M
IO
IO
IO
IO
IO
IO
M
M
M
M
M
M
Name
OCDE
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
OCDO
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
Description
OCD even data IO.
Ground connection.
Ground connection.
Active high pin reset with internal pull down.
OCD odd data output.
I2C Serial Clock (SCL).
I2C Serial Clock (SCL), ISSP SCLK[3].
I2C Serial Data (SDA), ISSP SDATA[3].
No connection.
I2C Serial Data (SDA).
Optional External Clock Input (EXTCLK).
Page 13 of 46
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Table 8-6. 100-Ball Part Pinout (VFBGA) (continued)
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
IO
IO
I,M
M
P2[0]
P4[2]
NC
NC
IO
M
P3[7]
IO
M
P4[5]
IO
M
P2[5]
IO
IO,M P0[3]
IO
I,M P0[4]
IO
M
P2[6]
IO
M
P4[6]
IO
M
P4[0]
CCLK
NC
NC
IO
M
P4[3]
IO
I,M P2[3]
Power
Vss
Power
Vss
IO
M
P2[4]
IO
M
P4[4]
IO
M
P3[6]
HCLK
Direct switched capacitor block input.
H8
H9
No connection.
H10
No connection.
J1
J2
J3
J4
Analog column mux input and column output. J5
Analog column mux input.
J6
External Voltage Reference (VREF) input.
J7
J8
J9
OCD CPU clock output.
J10
No connection.
K1
No connection.
K2
K3
Direct switched capacitor block input.
K4
Ground connection.
K5
Ground connection.
K6
External Analog Ground (AGND) input.
K7
K8
K9
OCD high-speed clock output.
K10
IO M
IO M
IO
Power
Power
USB
USB
Power
IO
IO
IO M
Power
Power
Power
Power
P3[2]
P5[4]
P7[3]
Vss
Vss
D+
DVdd
P7[7]
P7[0]
P5[2]
Vss
Vss
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
Power
IO
IO
IO
Power
Power
Ground connection.
Ground connection.
Supply voltage.
Ground connection.
Ground connection.
Ground connection.
Ground connection.
No connection.
No connection.
Supply voltage.
Ground connection.
Ground connection.
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger.
Figure 8-6. CY8C24094 OCD (Not for Production)
1
2
3
4
5
6
7
8
9
10
A
Vss
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
B
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2]
P2[2]
Vss
Vss
C
NC
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
NC
D
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
CClk
E
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
HClk
F
ocde
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
G
ocdo
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
H
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
J
Vss
Vss
D+
D-
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
K
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
BGA (Top View)
Document Number: 38-12018 Rev. *L
Page 14 of 46
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.1 100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
IO
I, M P0[1]
IO
M
P2[7]
IO
M
P2[5]
IO
I, M P2[3]
IO
I, M P2[1]
IO
M
P4[7]
IO
M
P4[5]
IO
M
P4[3]
IO
M
P4[1]
OCDE
OCDO
NC
Power
Vss
IO
M
P3[7]
IO
M
P3[5]
IO
M
P3[3]
IO
M
P3[1]
IO
M
P5[7]
IO
M
P5[5]
IO
M
P5[3]
IO
M
P5[1]
IO
M
P1[7]
NC
NC
NC
IO
P1[5]
IO
P1[3]
IO
P1[1]
IO
NC
Vss
D+
DVdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
NC
NC
NC
NC
P1[0]
IO
IO
P1[2]
P1[4]
Power
USB
USB
Power
IO
IO
IO
IO
IO
IO
IO
IO
Description
No connection.
No connection.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
OCD even data IO.
OCD odd data output.
No connection.
Ground connection.
I2C Serial Clock (SCL).
No connection.
No connection.
No connection.
I2C Serial Data (SDA)
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP SCLK[3].
No connection.
Ground connection.
Supply voltage.
No connection.
No connection.
No connection.
No connection.
Crystal (XTALout), I2C Serial Data (SDA),
ISSP SDATA[3].
Optional External Clock Input (EXTCLK).
Analog
Name
Pin
No.
Digital
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Analog
Pin
No.
Digital
Table 8-7. 100-Pin Part Pinout (TQFP)
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
IO
IO
IO
IO
IO
IO
IO
IO
IO
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
IO I, M
Power
M
M
M
M
M
M
M
M
M
Input
IO M
IO M
Power
IO M
IO M
IO I, M
IO I, M
IO
IO
IO
I
IO
I, M
IO
I, M
Name
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
HCLK
CCLK
XRES
P4[0]
P4[2]
Vss
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
NC
P2[6]
NC
P0[0]
NC
NC
P0[2]
NC
P0[4]
NC
P0[6]
Vdd
NC
Power
Vss
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO I, M P0[7]
NC
IO IO, M P0[5]
NC
99 IO
100
IO, M P0[3]
NC
Description
OCD high-speed clock output.
OCD CPU clock output.
Active high pin reset with internal pull down.
Ground connection.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
No connection.
External Voltage Reference (VREF) input.
No connection.
Analog column mux input.
No connection.
No connection.
Analog column mux input and column output.
No connection.
Analog column mux input and column output.
No connection.
Analog column mux input.
Supply voltage.
No connection.
Ground connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
Analog column mux input.
No connection.
Analog column mux input and column output.
No connection.
Analog column mux input and column output.
No connection.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger.
Document Number: 38-12018 Rev. *L
Page 15 of 46
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. *L
NC
P0[2], M, AI
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
P0[0], M , AI
NC
P2[6], M , External VREF
NC
P2[4], M , External AGND
P2[2], M , AI
P2[0], M , AI
P4[6], M
P4[4], M
Vss
P4[2], M
P4[0], M
XRES
CCLK
HCLK
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
M, P1[2]
EXTCLK, M, P1[4]
46
47
48
49
50
P7[1]
P7[0]
NC
NC
NC
NC
I2C SDA, M, P1[0]
P7[3]
P7[2]
36
37
38
39
40
41
42
43
44
45
P7[7]
P7[6]
P7[5]
P7[4]
31
32
33
34
35
77
76
80
79
78
NC
Vdd
P0[6], M, AI
NC
P0[4], M, AI
NC
NC
Vss
87
86
85
84
83
82
81
90
89
88
NC
NC
NC
NC
NC
NC
NC
NC
P0[7], M, AI
NC
95
94
93
92
91
P0[3], M, AI
NC
P0[5], M, AI
98
97
96
28
29
30
26
27
TQFP
NC
I2C SDA, M, P1[5]
M, P1[3]
I2C SCL, M, P1[1]
NC
Vss
D+
DVdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
NC
AI, M , P0[1]
M , P2[7]
M , P2[5]
AI, M , P2[3]
AI, M , P2[1]
M , P4[7]
M , P4[5]
M , P4[3]
M , P4[1]
OCDE
OCDO
NC
Vss
M , P3[7]
M , P3[5]
M , P3[3]
M , P3[1]
M , P5[7]
M , P5[5]
M , P5[3]
M , P5[1]
I2C SCL, P1[7]
NC
100
99
NC
Figure 8-7. CY8C24094 OCD (Not for Production)
Page 16 of 46
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CY8C24894, CY8C24994
9. Register Reference
This section lists the registers of the CY8C24x94 PSoC device family. For detailed register information, reference the
PSoC Programmable System-on-Chip Technical Reference Manual.
9.1 Register Conventions
9.2 Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 38-12018 Rev. *L
Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.
Page 17 of 46
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CY8C24894, CY8C24994
9.3 Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
Addr (0,Hex) Access
Name
00
RW
PMA0_DR
01
RW
PMA1_DR
02
RW
PMA2_DR
03
RW
PMA3_DR
04
RW
PMA4_DR
05
RW
PMA5_DR
06
RW
PMA6_DR
07
RW
PMA7_DR
08
RW
USB_SOF0
09
RW
USB_SOF1
0A
RW
USB_CR0
0B
RW
USBIO_CR0
0C
RW
USBIO_CR1
0D
RW
0E
RW
EP1_CNT1
0F
RW
EP1_CNT
10
RW
EP2_CNT1
11
RW
EP2_CNT
12
RW
EP3_CNT1
13
RW
EP3_CNT
14
RW
EP4_CNT1
15
RW
EP4_CNT
16
RW
EP0_CR
17
RW
EP0_CNT
18
EP0_DR0
19
EP0_DR1
1A
EP0_DR2
1B
EP0_DR3
PRT7DR
1C
RW
EP0_DR4
PRT7IE
1D
RW
EP0_DR5
PRT7GS
1E
RW
EP0_DR6
PRT7DM2
1F
RW
EP0_DR7
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
AMUXCFG
DBB00DR2
22
RW
DBB00CR0
23
#
ARF_CR
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
ASY_CR
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
DCB02DR0
28
#
DCB02DR1
29
W
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
30
ACB00CR3
31
ACB00CR0
32
ACB00CR1
33
ACB00CR2
34
ACB01CR3
35
ACB01CR0
36
ACB01CR1
37
ACB01CR2
38
39
3A
3B
3C
3D
3E
3F
Blank fields are Reserved and should not be accessed.
Document Number: 38-12018 Rev. *L
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
R
R
RW
#
RW
#
RW
#
RW
#
RW
#
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
MUL1_X
A8
MUL1_Y
A9
MUL1_DH
AA
MUL1_DL
AB
ACC1_DR1
AC
ACC1_DR0
AD
ACC1_DR3
AE
ACC1_DR2
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU_F
DAC_D
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
RW
#
#
Page 18 of 46
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9.4 Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
Addr (1,Hex) Access
Name
00
RW
PMA0_WA
01
RW
PMA1_WA
02
RW
PMA2_WA
03
RW
PMA3_WA
04
RW
PMA4_WA
05
RW
PMA5_WA
06
RW
PMA6_WA
07
RW
PMA7_WA
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
RW
PMA0_RA
11
RW
PMA1_RA
12
RW
PMA2_RA
13
RW
PMA3_RA
14
RW
PMA4_RA
15
RW
PMA5_RA
16
RW
PMA6_RA
17
RW
PMA7_RA
18
19
1A
1B
PRT7DM0
1C
RW
PRT7DM1
1D
RW
PRT7IC0
1E
RW
PRT7IC1
1F
RW
DBB00FN
20
RW
CLK_CR0
DBB00IN
21
RW
CLK_CR1
DBB00OU
22
RW
ABF_CR0
23
AMD_CR0
DBB01FN
24
RW
CMP_GO_EN
DBB01IN
25
RW
DBB01OU
26
RW
AMD_CR1
27
ALT_CR0
DCB02FN
28
RW
DCB02IN
29
RW
DCB02OU
2A
RW
2B
DCB03FN
2C
RW
TMP_DR0
DCB03IN
2D
RW
TMP_DR1
DCB03OU
2E
RW
TMP_DR2
2F
TMP_DR3
30
ACB00CR3
31
ACB00CR0
32
ACB00CR1
33
ACB00CR2
34
ACB01CR3
35
ACB01CR0
36
ACB01CR1
37
ACB01CR2
38
39
3A
3B
3C
3D
3E
3F
Blank fields are Reserved and should not be accessed.
Document Number: 38-12018 Rev. *L
Addr (1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (1,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
USBIO_CR2
USB_CR1
Addr (1,Hex) Access
C0
RW
C1
#
EP1_CR0
EP2_CR0
EP3_CR0
EP4_CR0
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
IMO_TR
ILO_TR
BDG_TR
ECO_TR
MUX_CR4
MUX_CR5
RW
RW
RW
RW
RW
RW
RW
CPU_F
DAC_CR
CPU_SCR1
CPU_SCR0
#
#
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RW
RW
RL
RW
#
#
Page 19 of 46
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10. Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater than
12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC.
Figure 10-1. Voltage versus CPU Frequency
5.25
Vdd Voltage
lid ng
Va rati n
e io
Op Reg
4.75
3.00
93 kHz
12 MHz
24 MHz
CPUFrequency
The following table lists the units of measure that are used in this chapter.
Table 10-1. Units of Measure
Symbol
oC
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Document Number: 38-12018 Rev. *L
Symbol
μW
mA
ms
mV
nA
ns
nV
W
pA
pF
pp
ppm
ps
sps
s
V
Unit of Measure
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 20 of 46
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10.1 Absolute Maximum Ratings
Table 10-2. Absolute Maximum Ratings
Symbol
Description
TSTG
Storage Temperature
Min
-55
Typ
25
Max
+100
TA
Vdd
VIO
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
–
–
–
DC Voltage Applied to Tri-state
IMIO
IMAIO
Maximum Current into any Port Pin
Maximum Current into any Port Pin
Configured as Analog Driver
Electro Static Discharge Voltage
Latch-up Current
–
–
+85
+6.0
Vdd +
0.5
Vdd +
0.5
+50
+50
oC
VIO2
-40
-0.5
Vss 0.5
Vss 0.5
-25
-50
2000
–
–
–
–
200
V
mA
ESD
LU
–
Units
oC
Notes
Higher storage temperatures
reduces data retention time. Recommended storage temperature is
+25oC ± 25oC. Extended duration
storage temperatures above 65oC
degrades reliability.
V
V
V
mA
mA
Human Body Model ESD.
10.2 Operating Temperature
Table 10-3. Operating Temperature
Symbol
Description
TA
Ambient Temperature
TAUSB
Ambient Temperature using USB
TJ
Junction Temperature
Document Number: 38-12018 Rev. *L
Min
-40
-10
-40
Typ
–
–
–
Max
+85
+85
+100
Units
Notes
oC
oC
oC
The temperature rise from ambient to
junction is package specific. See
Thermal Impedance on page 41. The
user must limit the power
consumption to comply with this
requirement.
Page 21 of 46
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10.3 DC Electrical Characteristics
10.3.1 DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-4. DC Chip-Level Specifications
Symbol
Description
Vdd
Supply Voltage
Min
3.0
–
Typ
Max
5.25
Units
V
IDD5
Supply Current, IMO = 24 MHz (5V)
–
14
27
mA
IDD3
Supply Current, IMO = 24 MHz (3.3V)
–
8
14
mA
ISB
Sleep (Mode) Current with POR, LVD, Sleep –
Timer, and WDT.[5]
3
6.5
μA
ISBH
Sleep (Mode) Current with POR, LVD, Sleep –
Timer, and WDT at high temperature.[5]
4
25
μA
Notes
See DC POR and LVD specifications,
Table 10-14 on page 28.
Conditions are Vdd = 5.0V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz, analog power =
off.
Conditions are Vdd = 3.3V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 0.367 kHz, analog power =
off.
Conditions are with internal slow speed
oscillator, Vdd = 3.3V, -40 oC ≤ TA ≤ 55
oC, analog power = off.
Conditions are with internal slow speed
oscillator, Vdd = 3.3V, 55 oC < TA ≤ 85
oC, analog power = off.
10.3.2 DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-5. DC GPIO Specifications
Symbol
Description
RPU
Pull-Up Resistor
RPD
Pull-Down Resistor
VOH
High Output Level
Min
4
4
Vdd 1.0
Typ
5.6
5.6
–
8
8
–
Max
Units
kΩ
kΩ
V
VOL
Low Output Level
–
–
0.75
V
VIL
VIH
VH
IIL
CIN
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
–
10
V
V
mV
nA
pF
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Notes
IOH = 10 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])). 80
mA maximum combined IOH budget.
IOL = 25 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])). 200
mA maximum combined IOL budget.
Vdd = 3.0 to 5.25.
Vdd = 3.0 to 5.25.
Gross tested to 1 μA.
Package and pin dependent.
Temp = 25oC.
Package and pin dependent.
Temp = 25oC.
Note
5. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar
functions enabled.
Document Number: 38-12018 Rev. *L
Page 22 of 46
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10.3.3 DC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-6. DC Full-Speed (12 Mbps) USB Specifications
Symbol
Description
USB Interface
Differential Input Sensitivity
VDI
Differential Input Common Mode Range
VCM
VSE
Single Ended Receiver Threshold
Transceiver Capacitance
CIN
High-Z State Data Line Leakage
IIO
REXT
External USB Series Resistor
Static Output High, Driven
VUOH
Min
Typ
Max
Units
0.2
0.8
0.8
–
-10
23
2.8
–
–
–
–
–
–
–
–
2.5
2.0
20
10
25
3.6
V
V
V
pF
μA
W
V
VUOHI
Static Output High, Idle
2.7
–
3.6
V
VUOL
Static Output Low
–
–
0.3
V
ZO
VCRS
USB Driver Output Impedance
D+/D- Crossover Voltage
28
1.3
–
–
44
2.0
W
V
Notes
| (D+) - (D-) |
0V < VIN < 3.3V.
In series with each USB pin.
15 kΩ ± 5% to Ground. Internal pull-up
enabled.
15 kΩ ± 5% to Ground. Internal pull-up
enabled.
15 kΩ ± 5% to Ground. Internal pull-up
enabled.
Including REXT Resistor.
10.3.4 DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 10-7. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Min
–
–
–
–
TCVOSOA Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins) –
IEBOA
Input Capacitance (Port 0 Analog Pins)
–
CINOA
Typ
Max
Units
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
7.0
20
4.5
35.0
–
9.5
μV/oC
pA
pF
VCMOA
Common Mode Voltage Range
0.0
Common Mode Voltage Range (high power 0.5
or high opamp bias)
–
–
Vdd
Vdd 0.5
V
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
dB
Document Number: 38-12018 Rev. *L
60
60
80
Notes
Gross tested to 1 μA.
Package and pin dependent. Temp =
25oC.
The common-mode input voltage
range is measured through an analog
output buffer. The specification
includes the limitations imposed by
the characteristics of the analog
output buffer.
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Table 10-7. 5V DC Operational Amplifier Specifications (continued)
Symbol
VOHIGHO
Description
Min
High Output Voltage Swing (internal signals)
Vdd Power = Low, Opamp Bias = High
A
0.2
Power = Medium, Opamp Bias = High
Vdd Power = High, Opamp Bias = High
0.2
Vdd 0.5
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
–
Power = Medium, Opamp Bias = High
–
Power = High, Opamp Bias = High
–
ISOA
Supply Current (including associated AGND
–
buffer)
–
Power = Low, Opamp Bias = Low
–
Power = Low, Opamp Bias = High
–
Power = Medium, Opamp Bias = Low
–
Power = Medium, Opamp Bias = High
–
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
PSRROA Supply Voltage Rejection Ratio
65
Typ
Max
Units
–
–
–
–
–
–
V
V
V
–
–
–
0.2
0.2
0.5
V
V
V
400
500
800
1200
2400
4600
800
900
1000
1600
3200
6400
μA
μA
μA
μA
μA
μA
80
–
dB
Notes
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd.
10.3.5 DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 10-8. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference
voltage range
LPC supply current
LPC voltage offset
Document Number: 38-12018 Rev. *L
Min
0.2
–
Typ
Max
Units
Vdd - 1 V
–
–
10
2.5
40
30
Notes
μA
mV
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10.3.6 DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-9. 5V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSO
Description
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
–
–
Min
Typ
3
+6
12
–
Max
Units
mV
μV/°C
0.5
–
Vdd - 1.0
V
–
–
0.6
0.6
–
–
W
W
–
–
V
V
–
–
0.5 x Vdd 1.3
0.5 x Vdd 1.3
V
V
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
–
–
0.5
Typ
3
+6
-
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
–
–
1
1
–
–
W
W
0.5 x Vdd + –
1.0
–
0.5 x Vdd +
1.0
–
–
V
V
–
–
0.5 x Vdd 1.0
0.5 x Vdd 1.0
V
V
0.8
2.0
64
2.0
4.3
–
mA
mA
dB
Notes
B
VCMOB
ROUTOB
VOHIGHO
B
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High
0.5 x Vdd + –
1.1
–
0.5 x Vdd +
1.1
VOLOWOB Low Output Voltage Swing (Load = 32 ohms
to Vdd/2)
–
Power = Low
–
Power = High
ISOB
PSRROB
Supply Current Including Bias Cell (No Load)
–
Power = Low
–
Power = High
Supply Voltage Rejection Ratio
53
(0.5 x Vdd - 1.3) ≤ VOUT ≤
(Vdd - 2.3).
Table 10-10. 3.3V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHO
B
Description
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 1K ohms
to Vdd/2)
Power = Low
Power = High
Min
VOLOWOB Low Output Voltage Swing (Load = 1K ohms
–
to Vdd/2)
–
Power = Low
Power = High
ISOB
PSRROB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
–
Supply Voltage Rejection Ratio
34
Document Number: 38-12018 Rev. *L
Notes
(0.5 x Vdd - 1.0) ≤ VOUT ≤
(0.5 x Vdd + 0.9).
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10.3.7 DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 10-11. 5V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2[6, 7]
AGND = 2 x BandGap[6, 7]
AGND = P2[4] (P2[4] = Vdd/2)[6, 7]
AGND = BandGap[6, 7]
AGND = 1.6 x BandGap[6, 7]
AGND Block to Block Variation (AGND = Vdd/2)[6, 7]
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
Min
1.28
Vdd/2 - 0.04
2 x BG - 0.048
P2[4] - 0.011
BG - 0.009
1.6 x BG - 0.022
-0.034
Vdd/2 + BG - 0.10
3 x BG - 0.06
2 x BG + P2[6] 0.113
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] + BG - 0.130
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] 0.133
RefHi = 3.2 x BandGap
3.2 x BG - 0.112
RefLo = Vdd/2 – BandGap
Vdd/2 - BG - 0.04
RefLo = BandGap
BG - 0.06
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
2 x BG - P2[6] 0.084
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
P2[4] - BG - 0.056
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] 0.057
Typ
1.30
Vdd/2 - 0.01
2 x BG - 0.030
P2[4]
BG + 0.008
1.6 x BG - 0.010
0.000
Vdd/2 + BG
3 x BG
2 x BG + P2[6] 0.018
P2[4] + BG - 0.016
P2[4] + P2[6] 0.016
3.2 x BG
Vdd/2 - BG + 0.024
BG
2 x BG - P2[6] +
0.025
P2[4] - BG + 0.026
P2[4] - P2[6] +
0.026
Max
1.32
Vdd/2 + 0.007
2 x BG + 0.024
P2[4] + 0.011
BG + 0.016
1.6 x BG + 0.018
0.034
Vdd/2 + BG + 0.10
3 x BG + 0.06
2 x BG + P2[6] +
0.077
P2[4] + BG + 0.098
P2[4] + P2[6]+
0.100
3.2 x BG + 0.076
Vdd/2 - BG + 0.04
BG + 0.06
2 x BG - P2[6] +
0.134
P2[4] - BG + 0.107
P2[4] - P2[6] +
0.110
Units
V
V
V
V
V
V
V
V
V
V
Typ
1.30
Vdd/2 - 0.01
Max
1.32
Vdd/2 + 0.005
Units
V
V
P2[4] + 0.001
BG + 0.005
1.6 x BG - 0.010
0.000
P2[4] + 0.009
BG + 0.015
1.6 x BG + 0.018
0.034
V
V
V
V
P2[4] + P2[6] 0.009
P2[4] + P2[6] +
0.057
V
V
V
V
V
V
V
V
V
Table 10-12. 3.3V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2[6, 7]
AGND = 2 x BandGap[6, 7]
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap[6, 7]
AGND = 1.6 x BandGap[6, 7]
AGND Column to Column Variation (AGND =
Vdd/2)[6, 7]
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Document Number: 38-12018 Rev. *L
Min
1.28
Vdd/2 - 0.03
Not Allowed
P2[4] - 0.008
BG - 0.009
1.6 x BG - 0.027
-0.034
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] + P2[6] 0.075
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Table 10-12. 3.3V DC Analog Reference Specifications (continued)
Symbol
–
–
–
–
–
–
Description
RefHi = 3.2 x BandGap
RefLo = Vdd/2 - BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Min
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] - P2[6] 0.048
Typ
P2[4]- P2[6] +
0.022
Max
Units
P2[4] - P2[6] +
0.092
V
10.3.8 DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-13. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switched Capacitor)
Min
–
–
Typ
12.2
80
Max
–
–
Units
kΩ
fF
Notes
Note
6. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
7. Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the
AGND.
Document Number: 38-12018 Rev. *L
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10.3.9 DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are
for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip
Technical Reference Manual for more information on the VLT_CR register.
Table 10-14. DC POR and LVD Specifications
Symbol
Description
VPPOR0R
VPPOR1R
VPPOR2R
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPH0
VPH1
VPH2
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Min
Typ
Max
Units
–
2.91
4.39
4.55
–
V
V
V
–
2.82
4.39
4.55
–
V
V
V
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
92
0
0
–
–
–
mV
mV
mV
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98[8]
3.08
3.20
4.08
4.57
4.74[9]
4.82
4.91
V
V
V
V
V
V
V
V
V
Notes
Notes
8. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
9. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 38-12018 Rev. *L
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10.3.10 DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-15. DC Programming Specifications
Symbol
IDDP
VILP
Description
Supply Current During Programming or Verify
Input Low Voltage During Programming or
Verify
VIHP
Input High Voltage During Programming or
Verify
IILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
VOLV
Output Low Voltage During Programming or
Verify
VOHV
Output High Voltage During Programming or
Verify
FlashENP Flash Endurance (per block)
–
–
Min
Typ
15
–
Max
30
0.8
Units
mA
V
Notes
2.1
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
V
Vdd - 1.0 –
Vss +
0.75
Vdd
50,000
–
–
–
Erase/write cycles per block.
1,800,0
00
10
–
–
–
Erase/write cycles.
–
–
Years
Driving internal pull-down
resistor.
Driving internal pull-down
resistor.
V
B
FlashENT Flash Endurance (total)[10]
FlashDR
Flash Data Retention
Note
10. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks
of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees
more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 38-12018 Rev. *L
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10.4 AC Electrical Characteristics
10.4.1 AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-16. AC Chip-Level Specifications
Symbol
FIMO245V
Description
Internal Main Oscillator Frequency for 24 MHz
(5V)
FIMO243V Internal Main Oscillator Frequency for 24 MHz
(3.3V)
FIMOUSB5 Internal Main Oscillator Frequency with USB
(5V)
V
Frequency locking enabled and USB traffic
present.
FIMOUSB3 Internal Main Oscillator Frequency with USB
(3.3V)
V
Frequency locking enabled and USB traffic
present.
FCPU1
CPU Frequency (5V Nominal)
FCPU2
CPU Frequency (3.3V Nominal)
FBLK5
Digital PSoC Block Frequency (5V Nominal)
Min
23.04
Typ
24
Max
24.96[11,12]
Units
MHz
22.08
24
25.92[12,13]
MHz
23.94
24
24.06[12]
MHz
23.94
24
24.06[12]
MHz
0.93
0.93
0
24
12
48
24.96[11,12]
MHz
12.96[12,13]
MHz
49.92[11,12,14] MHz
FBLK3
F32K1
Jitter32k
Step24M
Fout48M
0
15
–
–
46.08
24
32
100
50
48.0
25.92[12,14]
64
–
300
–
–
12.96
MHz
0
–
–
μs
Digital PSoC Block Frequency (3.3V Nominal)
Internal Low Speed Oscillator Frequency
32 kHz Period Jitter
24 MHz Trim Step Size
48 MHz Output Frequency
Jitter24M 24 MHz Period Jitter (IMO) Peak-to-Peak
1
FMAX
Maximum frequency of signal on row input or
row output.
TRAMP
Supply Ramp Time
–
49.92[11,13]
MHz
kHz
ns
kHz
MHz
Notes
Trimmed for 5V operation
using factory trim values.
Trimmed for 3.3V operation
using factory trim values.
-10°C ≤ TA ≤ 85°C
4.35 ≤ Vdd ≤ 5.15
-0°C ≤ TA ≤ 70°C
3.15 ≤ Vdd ≤ 3.45
Refer to the AC Digital Block
Specifications.
Trimmed. Utilizing factory
trim values.
ps
Figure 10-2. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
Notes
11. 4.75V < Vdd < 5.25V.
12. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
13. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
14. See the individual user module data sheets for information on maximum frequencies for user modules
Document Number: 38-12018 Rev. *L
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10.0.1 AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-17. AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Figure 10-3. GPIO Timing Diagram
90%
GPIO
Pin
O u tp u t
Vo lta g e
10%
TR ise F
TR ise S
TFallF
TF a llS
10.0.1 AC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-18. AC Full-Speed (12 Mbps) USB Specifications
Symbol
TRFS
TFSS
TRFMFS
TDRATEFS
Description
Transition Rise Time
Transition Fall Time
Rise/Fall Time Matching: (TR/TF)
Full-Speed Data Rate
Document Number: 38-12018 Rev. *L
Min
4
4
90
12 0.25%
Typ
–
–
–
12
Max
20
20
111
12 +
0.25%
Units
ns
ns
%
Mbps
Notes
For 50 pF load.
For 50 pF load.
For 50 pF load.
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10.0.2 AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 10-19. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Table 10-20. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Document Number: 38-12018 Rev. *L
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
μs
μs
–
–
–
–
5.41
0.72
μs
μs
0.31
2.7
–
–
–
–
V/μs
V/μs
0.24
1.8
–
–
–
–
V/μs
V/μs
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
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When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 10-4. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 10-5. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 38-12018 Rev. *L
0.01
0.1
Freq (kHz)
1
10
100
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10.0.1 AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 10-21. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC.
10.0.2 AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-22. AC Digital Block Specifications
Function
Description
Min
Typ
Max
Units
Notes
Capture Pulse Width
50[15]
–
–
ns
Maximum Frequency, No Capture
–
–
49.92
MHz
Maximum Frequency, With Capture
–
–
25.92
MHz
Enable Pulse Width
50[15]
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.92
MHz
Maximum Frequency, Enable Input
–
–
25.92
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[15]
–
–
ns
Disable Mode
50[15]
–
–
ns
Maximum Frequency
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
(PRS
Mode)
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
(CRC
Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
Timer
Counter
Dead
Band
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
Maximum data rate at 4.1 MHz due
to 2 x over clocking.
–
4.1
MHz
Width of SS_ Negated Between Transmissions 50[15]
–
–
ns
Transmitter
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Receiver
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Note
15. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 38-12018 Rev. *L
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10.0.3 AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-23. AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency for USB Applications
23.94
24
24.06
MHz
–
Duty Cycle
47
50
53
%
–
Power up to IMO Switch
150
–
–
μs
Notes
10.0.4 AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-24. 5V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1V Step, 100pF
Load
Power = Low
Power = High
TSOB
Falling Settling Time to 0.1%, 1V Step, 100pF
Load
Power = Low
Power = High
SRROB
Rising Slew Rate (20% to 80%), 1V Step, 100
pF Load
Power = Low
Power = High
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100
pF Load
Power = Low
Power = High
BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW,
100 pF Load
Power = Low
Power = High
BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100
pF Load
Power = Low
Power = High
Document Number: 38-12018 Rev. *L
Min
Typ
Max
Units
–
–
–
–
2.5
2.5
μs
μs
–
–
–
–
2.2
2.2
μs
μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Notes
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Table 10-25. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
SRROB
Rising Slew Rate (20% to 80%), 1V Step, 100
pF Load
Power = Low
Power = High
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100
pF Load
Power = Low
Power = High
BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW,
100 pF Load
Power = Low
Power = High
BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100
pF Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
3.8
3.8
μs
μs
–
–
–
–
2.6
2.6
μs
μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Notes
10.0.5 AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-26. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TDSCLK3
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Document Number: 38-12018 Rev. *L
Min
1
1
40
40
0
–
–
–
–
Typ
–
–
–
–
–
10
30
–
–
Max
20
20
–
–
8
–
–
45
50
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
Notes
Vdd > 3.6
3.0 ≤ Vdd ≤ 3.6
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10.0.6 AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-27. AC Characteristics of the I2C SDA and SCL Pins for Vdd
Symbol
FSCLI2C
THDSTAI2
C
TLOWI2C
THIGHI2C
TSUSTAI2
Standard Mode
Fast Mode
Min
Max
Min
Max
SCL Clock Frequency
0
100
0
400
Hold Time (repeated) START Condition. After 4.0
–
0.6
–
this period, the first clock pulse is generated.
LOW Period of the SCL Clock
4.7
–
1.3
–
HIGH Period of the SCL Clock
4.0
–
0.6
–
Set-up Time for a Repeated START Condition 4.7
–
0.6
–
Description
Units
Notes
kHz
μs
μs
μs
μs
C
THDDATI2
Data Hold Time
0
–
0
–
μs
Data Set-up Time
250
–
100[16] –
ns
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
–
–
0
50
ns
C
TSUDATI2
C
TSUSTOI2 Set-up Time for STOP Condition
C
TBUFI2C
TSPI2C
Bus Free Time Between a STOP and START
Condition
Pulse Width of spikes are suppressed by the
input filter.
Figure 10-6. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Note
16. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT Š 250 ns must then be met. This automatically is the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 38-12018 Rev. *L
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11. Packaging Dimensions
This section illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the package
and solder reflow peak temperatures.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 11-1. 56-Pin (8x8 mm) QFN
001-12921 **
Document Number: 38-12018 Rev. *L
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Figure 11-2. 68-Pin (8x8 mm x 0.89 mm) QFN
51-85214 *C
Important Note
■
For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
■
Pinned vias for thermal conduction are not required for the low-power PSoC device.
Document Number: 38-12018 Rev. *L
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Figure 11-3. 100-Ball (6x6 mm) VFBGA
51-85209 *B
Figure 11-4. 100-Pin (14x14 x 1.4 mm) TQFP
51-85048 *C
Document Number: 38-12018 Rev. *L
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11.1 Thermal Impedance
Table 11-1. Thermal Impedance for the Package
Typical θJA [17]
Package
56 QFN[18]
12.93 oC/W
68 QFN[18]
13.05 oC/W
100 VFBGA
65 oC/W
100 TQFP
51 oC/W
11.2 Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 11-2. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[19]
Maximum Peak Temperature
56 QFN
240oC
260oC
68 QFN
240oC
260oC
100 VFBGA
240oC
260oC
Notes
17. TJ = TA + POWER x θJA
18. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
19. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications
Document Number: 38-12018 Rev. *L
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12. Development Tool Selection
12.1 Software
■
110 ~ 240V Power Supply, Euro-Plug Adapter
12.1.1 PSoC Designer™
■
iMAGEcraft C Compiler (Registration Required)
At the core of the PSoC development software suite is PSoC
Designer. Used by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com under DESIGN RESOURCES >>
Software and Drivers.
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
12.1.2 PSoC Express™
As the newest addition to the PSoC development software suite,
PSoC Express is the first visual embedded system design tool
that allows a user to create an entire PSoC project and generate
a schematic, BOM, and data sheet without writing a single line
of code. Users work directly with application objects such as
LEDs, switches, sensors, and fans. PSoC Express is available
free of charge at http://www.cypress.com/psocexpress.
12.1.3 PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of charge at http://www.cypress.com/psocprogrammer.
12.1.4 CY3202-C iMAGEcraft C Compiler
CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
12.2 Development Kits
All development kits can be purchased from the Cypress Online
Store.
12.2.1 CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the content of specific memory locations. Advance
emulation features also supported through PSoC Designer. The
kit includes:
12.2.2 CY3210-ExpressDK PSoC Express Development Kit
The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube
In-Circuit Emulator). It provides access to I2C buses, voltage
reference, switches, upgradeable modules and more. The kit
includes:
■
PSoC Express Software CD
■
Express Development Board
■
4 Fan Modules
■
2 Proto Modules
■
MiniProg In-System Serial Programmer
■
MiniEval PCB Evaluation Board
■
Jumper Wire Kit
■
USB 2.0 Cable
■
Serial Cable (DB9)
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
2 CY8C24423A-24PXI 28-PDIP Chip Samples
■
2 CY8C27443-24PXI 28-PDIP Chip Samples
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
12.3 Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
12.3.1 CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
PSoC Designer Software CD
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
ICE-Cube In-Circuit Emulator
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
ICE Flex-Pod for CY8C29x66 Family
■
PSoC Designer Software CD
■
Cat-5 Adapter
■
Getting Started Guide
■
Mini-Eval Programming Board
■
USB 2.0 Cable
Document Number: 38-12018 Rev. *L
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12.3.2 CY3210-PSoCEval1
12.4 Device Programmers
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
All device programmers can be purchased from the Cypress
Online Store.
12.4.1 CY3216 Modular Programmer
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
Modular Programmer Base
■
PSoC Designer Software CD
■
3 Programming Module Cards
■
Getting Started Guide
■
MiniProg Programming Unit
■
USB 2.0 Cable
■
PSoC Designer Software CD
12.3.3 CY3214-PSoCEvalUSB
■
Getting Started Guide
The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special
features of the board include both USB and capacitive sensing
development and debugging support. This evaluation board also
includes an LCD module, potentiometer, LEDs, an enunciator
and plenty of bread boarding space to meet all of your evaluation
needs. The kit includes:
■
USB 2.0 Cable
12.4.2 CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
■
PSoCEvalUSB Board
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■
LCD Module
■
CY3207 Programmer Unit
■
MIniProg Programming Unit
■
PSoC ISSP Software CD
■
Mini USB Cable
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
PSoC Designer and Example Projects CD
■
USB 2.0 Cable
■
Getting Started Guide
■
Wire Pack
12.5 Accessories (Emulation and Programming)
Table 12-1. Emulation and Programming Accessories
Part #
Pin Package
Flex-Pod Kit[20]
Foot Kit[21]
Adapter[22]
CY8C24794-24LFXI
56 QFN
CY3250-24X94QFN
CY3250-56QFN-FK
AS-56-28
CY8C24894-24LFXI
56 QFN
CY3250-24X94QFN
CY3250-56QFN-FK
AS-28-28-02SS-6ENG-GANG
12.5.1 3rd-Party Tools
12.5.2 Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools
are found at http://www.cypress.com under Design Resources >
Evaluation Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator
into
Your
Board
AN2323”
at
http://www.cypress.com/an2323.
Notes
20. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
21. Foot kit includes surface mount feet that are soldered to the target PCB.
22. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters are found at
http://www.emulation.com.
Document Number: 38-12018 Rev. *L
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13. Ordering Information
XRES Pin
Analog Outputs
Analog Inputs
Digital IO Pins
Analog Blocks
Digital Blocks
SRAM
(Bytes)
Temperature
Range
Flash
(Bytes)
Package
Ordering
Code
Table 13-1. CY8C24x94 PSoC Device’s Key Features and Ordering Information
56 Pin (8x8 mm) QFN
56 Pin (8x8 mm) QFN
(Tape and Reel)
CY8C24794-24LFXI
CY8C24794-24LFXIT
16K
16K
1K
1K
-40°C to +85°C
-40°C to +85°C
4
4
6
6
50
50
48
48
2
2
No
No
56 Pin (8x8 mm) QFN
56 Pin (8x8 mm) QFN
(Tape and Reel)
68 Pin OCD (8x8 mm) QFN[23]
68 Pin (8x8 mm) QFN
68 Pin (8x8 mm) QFN
(Tape and Reel)
CY8C24894-24LFXI
CY8C24894-24LFXIT
16K
16K
1K
1K
-40°C to +85°C
-40°C to +85°C
4
4
6
6
49
49
47
47
2
2
Yes
Yes
CY8C24094-24LFXI
CY8C24994-24LFXI
CY8C24994-24LFXIT
16K
16K
16K
1K
1K
1K
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
4
4
4
6
6
6
56
56
56
48
48
48
2
2
2
Yes
Yes
Yes
100 Ball OCD (6x6 mm)
VFBGA[23]
CY8C24094-24BVXI
16K
1K
-40°C to +85°C
4
6
56
48
2
Yes
100 Ball (6x6 mm) VFBGA
100 Pin OCD TQFP[23]
CY8C24994-24BVXI
CY8C24094-24AXI
16K
16K
1K
1K
-40°C to +85°C
-40°C to +85°C
4
4
6
6
56
56
48
48
2
2
Yes
Yes
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
13.1 Ordering Code Definitions
CY 8 C 24 XXX- SP XX
Package Type:
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX/LKX/LTX = QFN Pb-Free
AX = TQFP Pb-Free
BVX = VFBGA Pb-Free
Speed: 24 MHz
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Note
23. This part may be used for in-circuit debugging. It is NOT available for production.
Document Number: 38-12018 Rev. *L
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14. Document History Page
Document Title: CY8C24094, CY8C24794, CY8C24894 and CY8C24994 PSoC® Programmable System-on-Chip™
Document Number: 38-12018
Rev.
ECN No. Submission
Date
Orig. of
Change
Description of Change
**
133189
01.27.2004
NWJ
New silicon and new document – Advance Data Sheet.
*A
251672
See ECN
SFV
First Preliminary Data Sheet. Changed title to encompass only the CY8C24794
because the CY8C24494 and CY8C24694 are not being offered by Cypress.
*B
289742
See ECN
HMT
Add standard DS items from SFV memo. Add Analog Input Mux on pinouts. 2
MACs. Change 512 bytes of SRAM to 1K. Add dimension key to package. Remove
HAPI. Update diagrams, registers and specs.
*C
335236
See ECN
HMT
Add CY logo. Update CY copyright. Update new CY.com URLs. Re-add ISSP
programming pinout notation. Add Reflow Temp. table. Update features (MAC,
Oscillator, and voltage range), registers (INT_CLR2/MSK2, second MAC), and
specs. (Rext, IMO, analog output buffer...).
*D
344318
See ECN
HMT
Add new color and logo. Expand analog arch. diagram. Fix IO #. Update Electrical
Specifications.
*E
346774
See ECN
HMT
Add USB temperature specifications. Make data sheet Final.
*F
349566
See ECN
HMT
Remove USB logo. Add URL to preferred dimensions for mounting MLF
packages.
*G
393164
See ECN
HMT
Add new device, CY8C24894 56-pin MLF with XRES pin. Add Fimousb3v char. to
specs. Upgrade to CY Perform logo and update corporate address and copyright.
*H
469243
See ECN
HMT
Add ISSP note to pinout tables. Update typical and recommended Storage
Temperature per industrial specs. Update Low Output Level maximum IOL budget.
Add FLS_PR1 to Register Map Bank 1 for users to specify which Flash bank
should be used for SROM operations. Add two new devices for a 68-pin QFN and
100-ball VFBGA under RPNs: CY8C24094 and CY8C24994. Add two packages
for 68-pin QFN. Add OCD non-production pinouts and package diagrams. Update
CY branding and QFN convention. Add new Dev. Tool section. Update copyright
and trademarks.
*I
561158
See ECN
HMT
Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add
CY8C20x34 to PSoC Device Characteristics table. Add detailed dimensions to
56-pin QFN package diagram and update revision. Secure one package
diagram/manufacturing per QFN. Update emulation pod/feet kit part numbers. Fix
pinout type-o per TestTrack.
*J
728238
See ECN
HMT
Add CapSense SNR requirement reference. Update figure standards. Update
Technical Training paragraphs. Add QFN package clarifications and dimensions.
Update ECN-ed Amkor dimensioned QFN package diagram revisions. Reword
SNR reference. Add new 56-pin QFN spec.
*K
2552459 08/14/08
AZIE/PYRS
Add footnote on AGND descriptions to avoid using P2[4] for digital signaling as it
may add noise to AGND. Remove reference to CMP_GO_EN1 in Map Bank 1
Table on Address 65; this register has no functionality on 24xxx. Add footnote on
die sales. Add description 'Optional External Clock Input’ on P1[4] to match
description of P1[4].
*L
2616550 12/05/08
OGNE/PYRS Updated Programmable Pin Configuration detail.
Changed title from PSoC® Mixed-Signal Array to PSoC® Programmable
System-on-Chip™
Document Number: 38-12018 Rev. *L
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
Clocks & Buffers
PSoC Solutions
psoc.cypress.com
clocks.cypress.com
General
Low Power/Low Voltage
psoc.cypress.com/solutions
psoc.cypress.com/low-power
Wireless
wireless.cypress.com
Precision Analog
Memories
memory.cypress.com
LCD Drive
psoc.cypress.com/lcd-drive
image.cypress.com
CAN 2.0b
psoc.cypress.com/can
USB
psoc.cypress.com/usb
Image Sensors
psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12018 Rev. *L
Revised December 04, 2008
Page 46 of 46
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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