NXP CBT3253APW Dual 1-of-4 fet multiplexer/demultiplexer Datasheet

CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
Rev. 02 — 8 February 2007
Product data sheet
1. General description
The CBT3253A is a dual 1-of-4 high-speed TTL-compatible FET
multiplexer/demultiplexer. The low on-resistance of the switch allows inputs to be
connected to outputs without adding propagation delay or generating additional ground
bounce noise.
1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data.
The CBT3253A is characterized for operation from −40 °C to +85 °C.
2. Features
5 Ω switch connection between two ports
TTL-compatible input levels
Minimal propagation delay through the switch
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n
n
n
n
3. Ordering information
Table 1.
Ordering information
Tamb = −40 °C to +85 °C
Type number
Topside
mark
Package
Name
Description
Version
CBT3253AD
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
CBT3253ADB C3253A
SSOP16
plastic shrink small outline package;
16 leads; body width 5.3 mm
SOT338-1
CBT3253ADS CT3253A
SSOP16[1]
plastic shrink small outline package;
16 leads; body width 3.9 mm;
lead pitch 0.635 mm
SOT519-1
CBT3253APW CT3253A
TSSOP16
plastic thin shrink small outline package; SOT403-1
16 leads; body width 4.4 mm
CBT3253AD
[1]
Also known as QSOP16.
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
4. Functional diagram
CBT3253A
1A
7
6
5
4
3
2A
9
10
11
12
13
S0
S1
1OE
2OE
1B1
1B2
1B3
1B4
2B1
2B2
2B3
2B4
14
2
1
15
002aab828
Fig 1. Logic diagram of CBT3253A (positive logic)
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
2 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
5. Pinning information
5.1 Pinning
1OE
1
16 VCC
S1
2
15 2OE
1B4
3
14 S0
1B3
4
1B2
5
13 2B4
CBT3253AD
1B1
1A
GND
12 2B3
6
11 2B2
7
10 2B1
9
8
2A
1OE
1
16 VCC
S1
2
15 2OE
1B4
3
14 S0
1B3
4
1B2
5
1B1
6
11 2B2
1A
7
10 2B1
GND
8
13 2B4
CBT3253ADB
12 2B3
9
2A
002aab825
002aab824
Fig 2. Pin configuration for SO16
Fig 3. Pin configuration for SSOP16
1OE
1
16 VCC
1OE
1
16 VCC
S1
2
15 2OE
S1
2
15 2OE
1B4
3
14 S0
1B4
3
14 S0
1B3
4
13 2B4
1B3
4
1B2
5
12 2B3
1B2
5
1B1
6
11 2B2
1B1
6
11 2B2
1A
7
10 2B1
1A
7
10 2B1
GND
8
GND
8
CBT3253ADS
9
2A
002aab826
CBT3253APW
13 2B4
12 2B3
9
2A
002aab827
Fig 4. Pin configuration for SSOP16
(QSOP16)
Fig 5. Pin configuration for TSSOP16
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1OE
1
output enable (active LOW)
S1
2
select-control input
1B4, 1B3, 1B2, 1B1
3, 4, 5, 6
B outputs[1]
1A
7
A input
GND
8
ground (0 V)
2A
9
A input
2B1, 2B2, 2B3, 2B4
10, 11, 12, 13
B outputs
S0
14
select-control input
2OE
15
output enable (active LOW)
VCC
16
positive supply voltage
[1]
B outputs are inputs if A inputs are outputs.
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
3 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
6. Functional description
Refer to Figure 1 “Logic diagram of CBT3253A (positive logic)”
6.1 Function selection
Table 3.
Function selection
H = HIGH state; L = LOW state; X = Don’t Care
Inputs
Function
1OE
2OE
S1
S0
X
H
X
X
disconnect 1A and 2A
H
X
X
X
disconnect 1A and 2A
L
L
L
L
1A to 1B1 and 2A to 2B1
L
L
L
H
1A to 1B2 and 2A to 2B2
L
L
H
L
1A to 1B3 and 2A to 2B3
L
L
H
H
1A to 1B4 and 2A to 2B4
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
Conditions
Min
Max
Unit
supply voltage
−0.5
+7.0
V
VI
input voltage
−0.5[1]
+7.0
V
ICCC
continuous current through
each VCC or GND pin
-
128
mA
IIK
input clamping current
-
−50
mA
Tstg
storage temperature
−65
+150
°C
[1]
VI < 0 V
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
8. Recommended operating conditions
Table 5.
Operating conditions
All unused control inputs of the device must be held at VCC or GND to ensure proper device
operation.
Symbol
Parameter
Conditions
VCC
supply voltage
VIH
HIGH-level input voltage
2
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
Tamb
ambient temperature
−40
-
+85
°C
operating in free air
CBT3253A_2
Product data sheet
Min
Typ
Max
Unit
4.5
-
5.5
V
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
4 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
9. Static characteristics
Table 6.
Static characteristics
Tamb = −40 °C to +85 °C
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VIK
input clamping voltage
VCC = 4.5 V; II = −18 mA
-
-
−1.2
V
Vpass
pass voltage
VI = VCC = 5.5 V; IO = −100 µA
3.4
3.6
3.9
V
ILI
input leakage current
VCC = 5 V; VI = 5.5 V or GND
-
-
±1
µA
ICC
quiescent supply current
VCC = 5.5 V; IO = 0 mA;
VI = VCC or GND
-
-
3
µA
∆ICC
additional quiescent supply
current (control inputs)
VCC = 5.5 V; one input at 3.4 V;
other inputs at VCC or GND
-
-
2.5
mA
Ci
input capacitance
(control pins)
VI = 3 V or 0 V
-
4.5
-
pF
Cio(off)
off-state input/output
capacitance
A port; VO = 3 V or 0 V; OE = VCC
-
11.4
-
pF
B port; VO = 3 V or 0 V; OE = VCC
-
3.8
-
pF
Cio(on)
on-state input/output
capacitance
A port and B port
-
18.6
-
pF
Ron
ON-state resistance[3]
[1]
[2]
VCC = 4.5 V; VI = 0 V; II = 64 mA
-
5
7
Ω
VCC = 4.5 V; VI = 0 V; II = 30 mA
-
5
7
Ω
VCC = 4.5 V; VI = 2.4 V; II = −15 mA
-
10
15
Ω
All typical values are at VCC = 5 V, Tamb = 25 °C.
[2]
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
[3]
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
VCC = +5.0 V ± 0.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
propagation delay
tPD
Conditions
from input (nA or nBn) to output (nBn or nA)
from input (Sn) to output (nA or nBn)
enable
ten
time[2]
disable time[3]
tdis
[1]
Min
Typ
Max
Unit
-
-
0.25
ns
1.2
-
6.2
ns
from input (Sn) to output (nA or nBn)
1.3
-
6.3
ns
from input (nOE) to output (nA or nBn)
1.4
-
6.4
ns
from input (Sn) to output (nA or nBn)
1.1
-
7.2
ns
from input (nOE) to output (nA or nBn)
1.0
-
7
ns
[1]
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
[2]
Output enable time to HIGH and LOW level.
[3]
Output disable time from HIGH and LOW level.
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
5 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
10.1 AC waveforms
VI = GND to 3.0 V.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
tPLH and tPHL are the same as tPD.
3.0 V
input
1.5 V
1.5 V
tPLH
tPHL
0V
VOH
output
1.5 V
1.5 V
VOL
002aab665
Fig 6. Input to output propagation delay
3V
output control
(LOW-level enabling)
1.5 V
1.5 V
tPZL
tPLZ
0V
3.5 V
output
waveform 1
S1 at 7 V(1)
1.5 V
VOL + 0.3 V
tPZH
output
waveform 2
S1 open(2)
tPHZ
1.5 V
VOL − 0.3 V
002aab666
VOL
VOH
0V
(1) Waveform 1 is for an output with internal conditions such that the output is LOW except when
disabled by the output control.
(2) Waveform 2 is for an output with internal conditions such that the output is HIGH except when
disabled by the output control.
Fig 7. 3-state output enable and disable times
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
6 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
11. Test information
RL
from output under test
500 Ω
CL
50 pF
S1
7V
open
GND
RL
500 Ω
002aab667
Test data are given in Table 8.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns.
The outputs are measured one at a time with one transition per measurement.
CL = load capacitance includes jig and probe capacitance.
RL = load resistance.
Fig 8. Test circuit
Table 8.
Test
Test data
Load
CL
RL
tPD
50 pF
500 Ω
open
tPLZ, tPZL
50 pF
500 Ω
7V
tPHZ, tPZH
50 pF
500 Ω
open
CBT3253A_2
Product data sheet
Switch
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
7 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 9. Package outline SOT109-1 (SO16)
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
8 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
D
SOT338-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
8
1
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.00
0.55
8
o
0
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT338-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Fig 10. Package outline SOT338-1 (SSOP16)
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
9 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm
D
E
SOT519-1
A
X
c
y
HE
v M A
Z
9
16
A2
A
(A 3)
A1
θ
Lp
L
8
1
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
v
w
y
Z (1)
θ
mm
1.73
0.25
0.10
1.55
1.40
0.25
0.31
0.20
0.25
0.18
5.0
4.8
4.0
3.8
0.635
6.2
5.8
1
0.89
0.41
0.2
0.18
0.09
0.18
0.05
8o
o
0
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-05-04
03-02-18
SOT519-1
Fig 11. Package outline SOT519-1 (SSOP16)
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
10 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 12. Package outline SOT403-1 (TSSOP16)
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
11 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
12 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 13) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 10.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 13.
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
13 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged Device Model
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
HBM
Human Body Model
MM
Machine Model
PRR
Pulse Rate Repetition
RC
Resistor-Capacitor network
TTL
Transistor-Transistor Logic
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
14 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
CBT3253A_2
20070208
Product data sheet
-
CBT3253A_1
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Table 5 “Operating conditions”:
– changed (VIH) “HIGH-state input voltage” to “HIGH-level input voltage”
– changed (VIL) “LOW-state input voltage” to “LOW-level input voltage”
•
Table 6 “Static characteristics”:
– Cio(off), A port: changed Typ. value from 23.5 pF to 11.4 pF
– Cio(off), B port: changed Typ. value from 6.5 pF to 3.8 pF
– added Cio(on) specification
CBT3253A_1
(9397 750 12919)
20051024
Product data sheet
-
CBT3253A_2
Product data sheet
-
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
15 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
CBT3253A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 8 February 2007
16 of 17
CBT3253A
NXP Semiconductors
Dual 1-of-4 FET multiplexer/demultiplexer
18. Contents
1
2
3
4
5
5.1
5.2
6
6.1
7
8
9
10
10.1
11
12
13
13.1
13.2
13.3
13.4
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Function selection. . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test information . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Introduction to soldering . . . . . . . . . . . . . . . . . 12
Wave and reflow soldering . . . . . . . . . . . . . . . 12
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 8 February 2007
Document identifier: CBT3253A_2