Sanyo LC662316A Four-bit single-chip microcontrollers with 4, 6, and 8 kb of on-chip rom Datasheet

Ordering number : EN5996
CMOS IC
LC662104A, 662106A, 662108A
Four-Bit Single-Chip Microcontrollers
with 4, 6, and 8 KB of On-Chip ROM
Overview
The LC662104A, LC662106A, and LC662108A are 4-bit
CMOS microcontrollers that integrate on a single chip all
the functions required in a special-purpose telephone
controller, including ROM, RAM, I/O ports, a serial
interface, a DTMF generator, timers, and interrupt
functions. These microcontrollers are available in a 30-pin
package.
Features and Functions
• On-chip ROM capacities of 4, 6, and 8 kilobytes, and an
on-chip RAM capacity of 384 × 4 bits.
• Fully supports the LC66000 Series common instruction
set (128 instructions). (The special-purpose instructions
for TM1 and SI/01 are disabled.)
• I/O ports: 24 pins
• DTMF generator
This microcontroller incorporates a circuit that can
generate two sine wave outputs, DTMF output.
• 8-bit serial interface: one circuit
• Instruction cycle time: 0.95 to 10 µs (at 3.0 to 5.5 V)
• Powerful timer functions and prescalers
— Time limit timer, event counter, pulse width
measurement, and square wave output using a 12-bit
timer.
— Time base function using a 12-bit prescaler.
• Powerful interrupt system with 6 interrupt factors and 6
interrupt vector locations.
— External interrupts: 3 factors/3 vector locations
— Internal interrupts: 3 factors/3 vector locations
• Flexible I/O functions
Selectable options include 20-mA drive outputs, pull-up
and open drain circuits.
• Optional runaway detection function (watchdog timer)
• 8-bit I/O functions
• Power saving functions using halt and hold modes.
• Packages: DIP30SD, MFP30S
• Evaluation ICs: LC665099 (evaluation chip) + EVA86K
- ECB662500
LC66E2108(on-chip EPROM microcontroller)
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
101698RM (OT) No. 5966-1/13
LC662104A, 662106A, 662108A
Package Dimensions
unit: mm
unit: mm
3196-DIP30SD
3216-MFP30S
[LC662104A]
[LC662106A]
SANYO: DIP30SD
Type No.
No. of
pins
ROM capacity
SANYO: MFP30S
RAM
capacity
Package
Features
LC66304A/306A/308A
42
4 K/6 K/8 KB
512 W
DIP42S
QFP48E
LC66404A/406A/408A
42
4 K/6 K/8 KB
512 W
DIP42S
QFP48E
LC66506B/508B/512B/516B
64
6 K/8 K/12 K/16 KB
512 W
DIP64S
QFP64A
LC66354A/356A/358A
42
4 K/6 K/8 KB
512 W
DIP42S
QFP48E
LC66354S/356S/358S
42
4 K/6 K/8 KB
512 W
LC66556A/558A/562A/566A
64
6 K/8 K/12 K/16 KB
512 W
DIP64S
QFP64E
LC66354B/356B/358B
42
4 K/6 K/8 KB
512 W
DIP42S
QFP48E
LC66556B/558B/562B/566B
64
6 K/8 K/12 K/16 KB
512 W
DIP64S
QFP64E
Low-voltage high-speed versions
3.0 to 5.5 V/0.92 µs
LC66354C/356C/358C
42
4 K/6 K/8 KB
512 W
DIP42S
QFP48E
2.5 to 5.5 V/0.92 µs
LC662104A/06A/08A
30
4 K/6 K/8 KB
384 W
DIP30SD
MFP30S
LC662304A/06A/08A/12A/16A
42
4 K/6 K/8 K/12 K/16 KB 512 W
DIP42S
QFP48E
LC662508A/12A/16A
64
8 K/12 K/16 KB
512 W
DIP64S
QFP64E
LC665304A/06A/08A/12A/16A
48
4 K/6 K/8 K/12 K/16 KB 512 W
DIP48S
QFP48E
LC66E308
42
EPROM 8 KB
512 W
DIC42S
with window
QFC48
with window
LC66P308
42
OTPROM 8 KB
512 W
DIP42S
QFP48E
QFC48
with window
QFP44M
LC66E408
42
EPROM 8 KB
512 W
DIC42S
with window
LC66P408
42
OTPROM 8 KB
512 W
DIP42S
QFP48E
QFC64
with window
LC66E516
64
EPROM 16 KB
512 W
DIC64S
with window
LC66P516
64
OTPROM 16 KB
512 W
DIP64S
QFP64E
LC66E2108
30
EPROM 8 KB
384 W
LC66E2316
42
EPROM 16 KB
512 W
DIC42S
with window
QFC48
with window
LC66E2516
64
EPROM 16 KB
512 W
DIC64S
with window
QFC64
with window
LC66E5316
52/48
EPROM 16 KB
512 W
DIC52S
with window
QFC48
with window
LC66P2108
30
OTPROM 8 KB
384 W
DIP30SD
MFP30S
LC66P2316
42
OTPROM 16 KB
512 W
DIP42S
QFP48E
LC66P2516
64
OTPROM 16 KB
512 W
DIP64S
QFP64E
LC66P5316
48
OTPROM 16 KB
512 W
DIP48S
QFP48E
Normal versions
4.0 to 6.0 V/0.92 µs
Low-voltage versions
2.2 to 5.5 V/3.92 µs
On-chip DTMF generator versions
3.0 to 5.5 V/0.95 µs
Dual oscillator support
3.0 to 5.5 V/0.95 µs
Window and OTP evaluation versions
4.5 to 5.5 V/0.92 µs
Window evaluation versions
4.5 to 5.5 V/0.95 µs
OTP
4.0 to 5.5 V/0.95 µs
No. 5996-2/13
LC662104A, 662106A, 662108A
We recommend the use of reflow-soldering techniques to solder-mount MFP packages.
Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly
immersed in a dip-soldering bath (dip-soldering techniques).
No. 5996-3/13
LC662104A, 662106A, 662108A
System Block Diagram
Differences between the LC663XX Series and the LC6621XX Series
Item
LC6630X Series
(Including the LC66599 evaluation chip)
LC6635XB Series
LC6621XX Series
System differences
• Hardware wait time (number of
cycles) when hold mode is cleared
65536 cycles
About 64 ms at 4 MHz (Tcyc = 1 µs)
16384 cycles
About 16 ms at 4 MHz (Tcyc = 1 µs)
16384 cycles
About 16 ms at 4 MHz (Tcyc = 1 µs)
Set to FFC.
Set to FFC.
• Value of timer 0 after a reset
(Including the value after hold mode Set to FF0.
is cleared)
• DTMF generator
None (Tools are handled with
external devices.)
None
Yes
• Inverter array
None (Tools are handled with
external devices.)
None
None
• SIO1
Yes
Yes
None
• Three-value inputs/comparator
inputs
Yes
Yes
None
• Three-state output from P31
and P32
None
None
Yes
• Using P0 to clear halt mode
In 4-bit groups
In 4-bit groups
Can be specified for each bit.
• External extended interrupts
None for INT3, INT4, and INT5.
(Tools are handled with external
devices.)
None for INT3, INT4, and INT5.
INT3, INT4, and INT5 can be used
with the internal functions.
• Other P53 functions
Shared with INT2
(Tools are handled with external
devices.)
Shared with INT2
Shared with INT2
Differences in main characteristics
• Operating power-supply voltage
and operating speed (cycle time)
• LC66304A/306A/308A
4.0 to 6.0 V/0.92 to 10 µs
• LC66E308/P308
4.5 to 5.5 V/0.92 to 10 µs
• 3.0 to 5.5 V/0.92 to 10 µs
• LC6635XA
2.2 to 5.5 V/3.92 to 10 µs
3.0 to 5.5 V/1.96 to 10 µs
3.0 to 5.5 V/0.95 to 10 µs
• Pull-up resistors
P0, P1, P4, and P5: about 3 to 10 kΩ
• Port voltage handling
• P2 to P6 and PC: 15V handling
• P0, P1, PD, PE: Normal voltage
handling
P0, P1, P4, and P5: about 3 to 10 kΩ P0, P1, P4, and P5: about 100 kΩ
• P2 to P6 and PC: 15V handling
• P0, P1, PD, PE: Normal voltage
handling
P2 to P4, P51, and P53: 15V voltage
handling Others: normal voltage
handling
No. 5996-4/13
LC662104A, 662106A, 662108A
Pin Function Overview
Pin
P00
P01
P02
P03
P10
P11
P12
P13
P20/SI0
P21/SO0
P22/SCK0
P23/INT0
P30/INT1
P31/POUT0
P32
P33/HOLD
P40
P41
P42
P43
I/O
Overview
Output driver type
Options
State after a
reset
I/O
I/O ports P00 to P03
• Input or output in 4-bit or 1-bit units
• P00 to P03 support the halt mode
control function (This function can be
specified in bit units.)
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Pull-up MOS or Nch
OD output
• Output level on reset
High or low (option)
I/O
I/O ports P10 to P13
Input or output in 4-bit or 1-bit units
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Pull-up MOS or Nch
OD output
• Output level on reset
High or low (option)
I/O
I/O ports P20 to P23
• Input or output in 4-bit or 1-bit units
• P20 is also used as the serial input SI0
pin.
• P21 is also used as the serial output
SO0 pin.
• P22 is also used as the serial clock
SCK0 pin.
• P23 is also used as the INT0 interrupt
request pin, and also as the timer 0
event counting and pulse width
measurement input.
• Pch: CMOS type
• Nch: Intermediate sink current
type
• Nch: +15V handling when OD
option selected
CMOS or Nch OD
output
H
I/O
I/O ports P30 to P32
• Input or output in 3-bit or 1-bit units
• P30 is also used as the INT1 interrupt
request.
• P31 is also used for the square wave
output from timer 0.
• P31 and P32 also support 3-state
outputs.
• Pch: CMOS type
• Nch: Intermediate sink current
type
• Nch: +15V handling when OD
option selected
CMOS or Nch OD
output
H
I
Hold mode control input
• Hold mode is set up by the HOLD
instruction when HOLD is low.
• In hold mode, the CPU is restarted by
setting HOLD to the high level.
• This pin can be used as input port P33
along with P30 to P32.
• When the P33/HOLD pin is at the low
level, the CPU will not be reset by a
low level on the RES pin. Therefore,
applications must not set P33/HOLD
low when power is first applied.
I/O
I/O ports P40 to P43
• Input or output in 4-bit or 1-bit units
• Input or output in 8-bit units when used
in conjunction with P50 to P53.
• Can be used for output of 8-bit ROM
data when used in conjunction with
P50 to P53.
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Nch: +15V handkling when
OD option selected
• Pull-up MOS or Nch
OD output
• Output level on reset
High or low (option)
Continued on next page.
No. 5996-5/13
LC662104A, 662106A, 662108A
Continued from preceding page.
Pin
I/O
P50
P51/DP
P52/DT
P53/INT2
I/O
OSC1
I
OSC2
O
Overview
I/O ports P50 to P53
• Input or output in 4-bit or 1-bit units
• P51 is also used for dial pulse output
• P52 is also used for DTMF output
• P53 is also used as the INT2 interrupt
request.
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Nch: +15-V handling when
OD option selected (P51 and
P53 only)
System clock oscillator connections
When an external clock is used, leave
OSC2 open and connect the clock signal
to OSC1.
RES
I
System reset input
When the P33/HOLD pin is at the high
level, a low level input to the RES pin will
initialize the CPU.
TEST
I
CPU test pin
This pin must be connected to VSS
during normal operation.
VDD
VSS
Output driver type
Options
State after a
reset
• Pull-up MOS or Nch
OD output
• Output level on reset
• Output level after a
reset
(An external pull-up
resistor must be
supplied when used
for DT output.)
High or low (option)
Ceramic oscillator or
external clock selection
Option selection
Power supply pins
Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD.
CMOS output: Complementary output.
OD output: Open-drain output.
No. 5996-6/13
LC662104A, 662106A, 662108A
User Options
1. Port 0, 1, 4, and 5 output level options a reset
The output levels at reset for I/O ports 0, 1, 4, and 5 in independent 4-bit groups, can be selected from the following
two options.
Option
Conditions and notes
Output high at reset
The four bits of ports 0, 1, 4, or 5 are set in a group
Output low at reset
The four bits of ports 0, 1, 4, or 5 are set in a group
2. Oscillator circuit options
• Main clock
Option
Circuit
OSC1
External clock
C1
Ceramic oscillator
Conditions and notes
The input has Schmitt characteristics
OSC1
Ceramic oscillator
C2
OSC2
Note: There is no RC oscillator option.
3. Watchdog timer option
A runaway detection function (watchdog timer) can be selected as an option.
4. Port output type options
• The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, and P5 can be selected
individually from the following two options.
Option
Circuit
Conditions and notes
Output data
Open-drain output
Input data
The port P2, P3, P5, and P6 inputs have Schmitt
characteristics.
DSB
Output data
Output with built-in pull-up
resistor
Input data
The port P2, P3, and P5 inputs have Schmitt
characteristics.
The CMOS outputs (ports P2 and P3) and the
pull-up MOS outputs (P0, P1, P4, and P5) are
distinguished by the drive capacity of the pchannel transistor.
DSB
No. 5996-7/13
LC662104A, 662106A, 662108A
LC662108 Series Option Data Area and Definitions
ROM area
2000H
Bit
P5
6
P4
Unused
This bit must be set to 0.
Oscillator option
0 = (RC oscillator) external clock, 1 = ceramic oscillator
3
Unused
This bit must be set to 0.
2
P1
1
P0
Output level at reset
Watchdog timer option
7
P13
6
P12
5
P11
4
P10
3
P03
2
P02
1
P01
7
2003H
0 = high level, 1 = low level
4
0
2002H
Output level at reset
Option/data relationship
5
0
2001H
Option specified
7
0 = low level, 1 = high level
0 = none, 1 = yes
Output type
0 = OD, 1 = PU
Output type
0 = OD, 1 = PU
P00
Unused
6
P32
5
P31
4
P30
3
P23
2
P22
1
P21
0
P20
7
P53
6
P52
5
P51
4
P50
3
P43
2
P42
1
P41
0
P40
This bit must be set to 0.
Output type
0 = OD, 1 = PU
Output type
0 = OD, 1 = PU
Output type
0 = OD, 1 = PU
Output type
0 = OD, 1 = PU
7
6
2004H
to
200CH
5
4
3
Unused
This bit must be set to 0.
*: Location 2008H must be set to 7F.
2
1
0
7
6
5
200DH
4
3
Reserved. Must be set to predefined values.
This data is generated by the assmbler (21).
If the assembler is not used, set this data to 00.
2
1
0
7
6
5
200EH
4
3
Reserved. Must be set to predefined values.
This data is generated by the assmbler (0x).
If the assembler is not used, set this data to 00.
2
1
0
Continued on next page.
No. 5996-8/13
LC662104A, 662106A, 662108A
Continued from preceding page.
ROM area
Bit
Option specified
Option/data relationship
7
6
5
4
200FH
3
This data is generated by the assmbler (00).
Reserved. Must be set to predefined values.
If the assembler is not used, set this data to (00).
2
1
0
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input voltage
Symbol
VDD max
VIN1
VIN2
Output voltage
Output current per pin
Total pin current
Allowable power dissipation
Conditions
VDD
P2, P3 (except for the P33/HOLD pin),
P4, P51, and P53
All other inputs
VOUT1
P2 and P3 (except for the P33/HOLD pin)
VOUT2
All other inputs
ION1
P0, P1, P2, P3 (except for the P33/HOLD pin),
P4, P5
Ratings
Unit
–0.3 to +7.0
V
–0.3 to +15.0
V
Note
1
–0.3 to VDD + 0.3
V
2
–0.3 to +15.0
V
1
–0.3 to VDD + 0.3
V
2
20
mA
3
4
–IOP1
P0, P1, P4, P5
2
mA
–IOP2
P2, P3 (except for the P33/HOLD pin)
4
mA
4
Σ ION1
P1, P2, P3 (except for the P33/HOLD pin)
75
mA
3
Σ ION2
P0, P4, P5
75
mA
3
Σ IOP1
P1, P2, P3 (except for the P33/HOLD pin)
25
mA
4
Σ IOP2
P0, P4, P5
25
mA
4
340 (200)
mW
5
Pd max
Ta = –30 to +70°C: DIP30S (MFP30S)
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Note: 1. Applies to pins with open-drain output specifications. For pins with other than open-drain output specifications, the ratings in the pin column for that
pin apply.
2. For the oscillator input and output pins, levels up to the free-running oscillation level are allowed.
3. Sink current
4. Source current
5. We recommend the use of reflow soldering techniques to solder mount MFP packages.
Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering
bath (dip-soldering techniques).
No. 5996-9/13
LC662104A, 662106A, 662108A
Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V, unless otherwise specified.
Parameter
Symbol
Conditions
min
Ratings
typ
Unit
max
VDD
3.0
5.5
V
VDDH
VDD: During hold mode
1.8
5.5
V
VIH1
P2, P3 (except for the P33/HOLD pin),
P4, P51, and P53: N-channel output transistor off
0.8 VDD
13.5
V
VIH2
P33/HOLD, RES, OSC1:
N-channel output transistor off
0.8 VDD
VDD
V
VIH3
P0, P1, P50, P52:
N-channel output transistor off
0.8 VDD
VDD
V
VIL1
P2, P3 (except for the P33/HOLD pin),
RES, and OSC1: N-channel output transistor off
VSS
0.2 VDD
V
VIL2
P33/HOLD: VDD = 1.8 to 5.5 V
VSS
0.2 VDD
V
VIL3
P0, P1, P4, P5, TEST:
N-channel output transistor off
VSS
0.2 VDD
V
fop
(Tcyc)
0.4
(10)
4.20
(0.95)
MHz
(µs)
Frequency
fext
0.4
4.20
MHz
Pulse width
textH, textL
Rise and fall times
textR, textF
Operating supply voltage
Memory retention supply voltage
Input high-level voltage
Input low-level voltage
Operating frequency
(instruction cycle time)
VDD
Note
1
2
[External clock input conditions]
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
100
ns
30
ns
Note: 1. Applies to pins with open-drain specifications. However, VIH2 is applied to the P33/HOLD pin.
When ports P2 and P3 have CMOS output specifications they cannot be used as input pins.
2. Applies to pins with open-drain specifications.
No. 5996-10/13
LC662104A, 662106A, 662108A
Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified.
Parameter
Symbol
Ratings
typ
min
max
Unit
Note
IIH1
P2, P3 (except for the P33/HOLD pin), P4,
P51, and P53: VIN = 13.5 V, with the output
Nch transistor off
5.0
µA
1
IIH2
P0, P1, P50, P52, OSC1, RES, and P33/HOLD:
VIN = VDD, with the output Nch transistor off
1.0
µA
1
IIL1
P0, P1, P2, P3, P4, and P5:
VIN = VSS, with the output Nch transistor off
µA
2
V
3
Input high-level current
Input low-level current
Conditions
–1.0
P2, P3 (except for the
IOH = –1 mA
VDD – 1.0
P33/HOLD pin)
IOH = –0.1 mA
VDD – 0.5
Output high-level voltage
VOH1
Value of the output pull-up resistor
RPO
P0, P1, P4, P5
150
kΩ
VOL1
P0, P1, P2, P3, P4, and P5
(except for the P33/HOLD pin): IOL = 1.6 mA
0.4
V
VOL2
P0, P1, P2, P3, P4, and P5
(except for the P33/HOLD pin): IOL = 8 mA
1.5
V
IOFF1
P2, P3, P4, P51, and P53: VIN = 13.5 V
5.0
µA
6
IOFF2
Does not apply to P2, P3, P4, P51, and P53:
VIN = VDD
1.0
µA
6
0.5 VDD
0.8 VDD
V
0.2 VDD
0.5 VDD
V
Output low-level voltage
Output off leakage current
30
100
5
[Schmitt characteristics]
Hysteresis voltage
VHYS
High-level threshold voltage
VtH
Low-level threshold voltage
VtL
0.1 VDD
P2, P3, P4, P5, and RES
[Ceramic oscillator]
Oscillator frequency
fCF
OSC1, OSC2: See Figure 2. 4 MHz
Oscillator stabilization time
fCFS
See Figure 3. 4 MHz
4.0
MHz
10.0
ms
[Serial clock]
Cycle time
Input
Output
Low-level and high-level Input
pulse widths
Output
Rise an fall times
Output
tCKCY
tCKL
SCK0: With the timing of Figure 4 and the test
load of Figure 5.
tCKH
0.9
µs
2.0
Tcyc
0.4
µs
1.0
Tcyc
tCKR, tCKF
0.1
µs
[Serial input]
Data setup time
tICK
Data hold time
tCKI
SI0: With the timing of Figure 4.
Stipulated with respect to the rising edge (↑) of
SCK0.
0.3
µs
0.3
µs
[Serial output]
Output delay time
tCKO
SO0: With the timing of Figure 4 and the test
load of Figure 5. Stipulated with respect to the
falling edge (↓) of SCK0.
0.3
µs
[Pulse conditions]
INT0: Figure 6, conditions under which the INT0
interrupt can be accepted, conditions under
which the timer 0 event counter or pulse width
measurement input can be accepted
2
Tcyc
tIIH, tIIL
INT1, INT2: Figure 6, conditions under which
the corresponding interrupt can be accepted
2
Tcyc
RES high and low-level
pulse widths
tRSH, tRSL
RES: Figure 6, conditions under which reset
can be applied.
3
Tcyc
Operating current drain
IDD OP
Halt mode current drain
IDDHALT
Hold mode current drain
IDDHOLD
INT0 high and low-level
High and low-level pulse widths
for interrupt inputs other than INT0
tIOH, tIOL
VDD: 4-MHz ceramic oscillator
4.5
8.0
mA
VDD: 4-MHz external clock
4.5
8.0
mA
VDD: 4-MHz ceramic oscillator
2.5
5.5
mA
VDD: 4-MHz external clock
2.5
5.5
mA
0.01
10
µA
VDD: VDD = 1.8 to 5.5 V
8
Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the
CMOS output specifications are selected.
2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is
stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected.
3. With the output Nch transistor off for CMOS output specification pins.
4. With the output Nch transistor off for pull-up output specification pins.
6. With the output Pch transistor off for open-drain output specification pins.
7. Reset state
No. 5996-11/13
LC662104A, 662106A, 662108A
Tone (DTMF) Output Characteristics
DC Characteristics at Ta = –30 to +70°C, VSS = 0 V
Parameter
Symbol
Note*:
min
Ratings
typ
max
Unit
VT1
DT: Single tone, VDD = 3.5 to 5.5 V*
0.9
1.3
2.0
Vp-p
DBCR1
DT: Dual tones, VDD = 3.5 to 5.5 V*
1.0
2.0
3.0
dB
Tone output voltage
Row/column tone output
voltage ratio
Conditions
See Figure 7.
VDD
0.8 VDD
OSC1
0.2 VDD
(OSC2)
VSS
textL
Open
External clock
textF
textH
textR
1/fext
Figure 1 External Clock Input Waveform
OSC1
Operating VDD lower limit
OSC2
0V
C1
Ceramic
oscillator
C2
Oscillator unstable
period tCFS
Figure 2 Ceramic Oscillator Circuit
Stable oscillation
Figure 3 Oscillator Stabilization Period
Table 1 Recomended Ceramic Oscillator Constants
External capacitor type
4 MHz
(Murata Mfg. Co., Ltd.)
CSA4.00MG
C1 = 33 pF
4 MHz
(Kyocera Corporation)
KBR4.0MSB
C1 = 33 pF
Built-in capacitor type
4 MHz
(Murata Mfg. Co., Ltd.)
CST4.00MG
C2 = 33 pF
4 MHz
(Kyocera Corporation)
KBR4.0MKC
C2 = 33 pF
tCKCY
tCKL
SCK0
0.2 VDD (input)
0.4 VDD (output)
tCKR
tCKH
tCKF
0.8 VDD (input)
VDD – 1 (output)
tICK tCKI
SI0
0.8 VDD
0.2 VDD
tCK0
SO0
VDD – 1
0.4 VDD
Figure 4 Serial I/O Timing
Figure 5
Timing Load
No. 5996-12/13
LC662104A, 662106A, 662108A
tI0H
tI1H
tRSH
0.8 VDD
0.2 VDD
tI0L
tI1L
tPINL
tRSL
Figure 6 Input Timing for the INT0, INT1, INT2, and RES pins
Figure 7 Tone Output Pin Load
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of October, 1998. Specifications and information herein are subject
to change without notice.
PS No. 5996-13/13
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