ATMEL ATA5282 Ultra low power 125 khz 3d - wake-up receiver with rssi Datasheet

Features
•
•
•
•
•
•
•
•
•
•
•
•
Three Input Channels for 3D Antennas
2.8 mVPP Sensitivity Typically
Ultra Low Current Operation Consumption
2 µA Standby Current Typically
4 µA Active Current Typically
Power Supply 2V to 3.8V
Carrier Frequency Range from 100 kHz to 150 kHz
Wake-up Function for a Microcontroller
Header Detection
Baud Rate up to 4 kbps (ASK Modulation)
Bi-directional Two-wire Interface
ESD According to Automotive Requirements
Benefits
• Digital RSSI for Field Strength Measurement
• Coils Input Range from 2.8 mVPP to 2.8VPP Typically
• High Sensitivity
Applications
•
•
•
•
Ultra Low Power
125 kHz 3D Wake-up
Receiver with
RSSI
ATA5282
Passive Entry Go (PEG)/Car Access
Position Indicator
Home Access Control
RFID Systems
1. Description
The ATA5282 is a 125-kHz ultra low power receiver IC with three input channels for
Passive Entry Go applications. It includes all circuits for an LF wake-up channel. The
three sensitive input stages of the IC amplifier demodulate and measure the input signal from the antenna coils. The microcontroller interface of the IC outputs the data
signal as well as the measured RSSI values. During standby mode, the header detection unit monitors the incoming signal and generates a wake-up signal for the
microcontroller if the IC receives a valid 125-kHz carrier signal.
By combining the IC with an antenna coil, a microcontroller, an RF transmitter/transceiver and a battery, it is possible to design a complete hands-free key for Passive
Entry Go applications.
4694E–AUTO–08/05
Figure 1-1.
Block Diagram
Battery
TC
VDD
VSS
ATA5282
3 Channel Amplifier
with AGC
L1
Timing
control
L2
NDATA/
NWAKEUP
Signal
conditioner
Header
detection
L3
select
3
Serial
interface
8
Vref
NSCL
field strength
2. Pin Configuration
Figure 2-1.
Pinning TSSOP 8L
COIL1
COIL2
COIL3
VSS
Table 2-1.
2
1
2
3
4
8
7
6
5
VDD
NDATA
NSCL
TC
Pin Description
Pin
Symbol
Function
1
COIL1
Input: Coil channel X
2
COIL2
Input: Coil channel Y
3
COIL3
Input: Coil channel Z
4
VSS
Circuit ground
5
TC
6
NSCL
Input: Clock for serial interface (default high)
Output: Current output for oscillator adjustment
7
NDATA
Input/Output: I/O data for serial interface and field strength measurement/
Wake-up function (default high)
8
VDD
Battery voltage
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ATA5282
3. Functional Description
The ATA5282 is a 3-channel ASK receiver for 125-kHz carrier signals. Its three active input
stages with very low power consumption and high input sensitivity allow to connect up to 3
antennas for direction-independent wake-up function and data transfer.
Without a carrier signal the ATA5282 operates in standby listen mode. In this mode, it monitors the 3 Coil inputs with a very low current consumption. To activate the IC and the
connected control unit, the transmitting end must send a preamble carrier burst and the
header code. When a preamble has been detected, the IC activates the internal oscillator and
the header check. The last gap at the end of a valid header enables the NDATA output.
During data transfer, the NDATA pin outputs the demodulated and merged signal of the 3
input stages.
To achieve data rates up to 4 kbps for input signals from 2.8 mVPP to 2.8VPP it is necessary to
control the gain of the amplifiers. Each of the 3 input stages contain an amplifier with Automatic Gain Control (AGC). It is used to adapt the gain to the incoming signal strength, and is
also used as RSSI for field strength measurements.
The integrated synchronous serial interface uses the NSCL together with the NDATA pin as
clock and data line. It allows to control several functions as well as read out the received signal
field strength. Enabling only single coil inputs, freezing the actual status of the automatic gain
control or resetting the complete circuit to the initial state at any time are built-in features.
When communication is finished or a time out event occurs, the internal watchdog timer or
reset command via the serial interface sets the IC to standby listen mode.
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3.1
Functional State Diagram
This diagram gives an overview of the major tasks performed by the ATA5282. The detailed
function of the automatic gain control that is active during preamble check, header check and
data transfer is not shown here.
Figure 3-1.
ATA5282 State Diagram
Stand by
Waiting for
RF-signal
Signal detected
Count
192 periods
Gap detected
before
192 periods
Preamble
check
No valid header
within 2 ms
Gap detected
after 192 periods
No data received
for 20 ms
360 ms
gone
Oscillator
run
Start watchdog
Check 8 edges of
demodulated signal
Start header
check
Header
timing
check
Header ok
Wake up
microcontroller
360 ms
watchdog
Header
timeout
Stop if
header ok
Start quietness
check
Enable
data output
Switch
demodulated
signal to data
output
4
Start header
timeout
check
20 ms
quietness
check
Restart if
signal
detected
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ATA5282
3.2
AGC Amplifier
Each of the three input stages contain an AGC amplifier to amplify the input signal from the
Coil. The gain is adjusted by the automatic gain control circuit if a preamble signal is detected.
The high dynamic range of the AGC amplifier enables the IC to work with input signals from
2.8 mVPP to 2.8VPP. After the AGC settling time has elapsed, the amplifier output delivers a
125-kHz signal with an amplitude adjusted for the following evaluation circuits (preamble
detection, signal conditioner, wake-up).
3.3
Automatic Gain Control
For correct demodulation, the signal conditioner needs an appropriate internal signal amplitude. To control the input signal, the ATA5282 has a built-in digital AGC for each input
channel. This gain control circuit regulates the internal signal amplitude to the reference level
(Ref2, Figure 3-2 on page 6). The gain control uses the signal of the input channel with the
highest amplitude for the regulation as well as signal for the signal conditioner.
During the preamble, each period of the carrier signal decreases the gain if the internal signal
exceeds the reference level. If the signal does not achieve the reference level, each period
increases the gain. After 192 preamble periods, the standard gain control mode is activated. In
this mode, the gain is decreased every two periods if the internal signal exceeds the reference
level and increased every eight periods if the reference level is not achieved. These measures
assure that the input signal’s envelope deformation will be minimized.
During the gaps between signal bursts, the gain control is frozen to avoid that the gain be
modified by noise signals.
The tuning range of the AGC is subdivided into 256 regulator steps. The settling time for the
full tuning range requires 320 periods (192 + (2 × 64) periods) during a preamble phase.
In standby listen mode, the gain is reset to the maximum value. A proper carrier signal activates the automatic gain control.
The preamble (Figure 3-7 on page 10) with up to 320 periods of the 125 kHz magnetic field is
used to control the gain of the input amplifiers. To detect the starting point of the header, the
start gap should not exceed 256 µs (32 periods of 125 kHz).
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Figure 3-2.
Automatic Gain Control
Transmitted
signal
Coil
input
Gain control
reference
Ref.2
Ref.1
50%
Gaincontrolled
signal
100%
Gap detection
reference
Demodulated
output
6
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ATA5282
3.4
Field Strength RSSI (Received Signal Strength Indicator)
The digital value of the AGC counter is used as an indicator for the corresponding field
strength of the input signal. The digital value can be accessed by the microcontroller via the
serial interface.
Figure 3-3.
Field Strength as a Function of Coil Input Signal
Digital Value of Field Strength
(RSSI_V)
255
224
192
max.
160
Limiter
active
min.
128
96
64
32
0
0,001
0,01
0,1
1
10
Coil Input Signal (V CI ) PP
The characteristic gain control value versus the coil input signal (see Figure 3-3) can be calculated by using the following equation:
RSSI_V = ROUND (32 × Ln(VCI)PP + 190)
RSSI_V:
Digital value of field strength
Ln():
Natural logarithm function
VCI:
Coil input voltage
With the variation of the gain the coil input impedance changes from high impedance to minimal 143 kΩ (Figure 3-4). This impedance variation is an insignificant influence to the quality
factor of the resonant circuits.
Figure 3-4.
Coil Input Impedance
10000
max.
typ.
Z (kΩ)
min.
1000
100
1
10
100
1000
10000
Coil Input Signal (mVpp)
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3.5
Signal Conditioner
The signal conditioner operates on the demodulated output signal of all three channels.
Figure 3-5.
Function of Signal Conditioner
Internal signals
Medium signal strength
Input
Channel 1
Internal GAP
High signal strength
Input
Channel 2
Internal GAP
Low signal strength
Input
Channel 3
Internal GAP
Signal
conditioner
output
(NDATA)
The AGC reduces the gain of all 3 channels with reference to the signal with the highest amplitude. This automatically reduces the gain of channels with medium or low input signal
amplitudes which results in the suppression of further process of these channels. The logical
combination of the 3 demodulated output signals mostly represents the signal with the highest
input amplitude.
3.6
Preamble Detection
To prevent the circuit from unintended operations in a noisy environment, the preamble is
checked to consist of 192 periods minimum. Three consecutive periods missing do not disturb
counting. With this check passed, the circuit starts the internal oscillator at the end of the preamble (Figure 3-9 on page 12). The AGC needs a maximum of 256 steps for full range tuning
of amplifiers.
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ATA5282
Before data transmission occurs the IC remains in standby listen mode. To prevent the circuit
from unintended operations in a noisy environment, the preamble detection circuit checks the
input signal. A valid signal is detected by a counter circuit after 192 carrier periods without
interrupts. Short interrupts which are suppressed by the signal conditioner are tolerated. If a
valid carrier (preamble) has been found, the circuit starts the automatic gain control. It requires
up to 256 carrier periods for settling. The complete preamble should have at least 320 carrier
periods.
3.7
Internal Oscillator
If the end of the preamble is detected, the internal oscillator starts operating. It works as a time
base to generate the time windows for the header detection, the header time-out check, the
20-ms-no-signal check and the data transmission duration watchdog. An external resistor connected to TC selects the oscillators frequency and defines all internal timings.
3.8
Header Detection and Wake-up
The preamble needs to be followed by the specific header. This header ensures that the builtin header detection wakes up the controller only with a valid signal. One possible protocol
used for wake-up and data transmission is shown in Figure 3-7 on page 10 and Figure 3-9 on
page 12.
The standard header information must be transferred in OOK-mode (On-Off-Keying) with a
duty cycle of 50%. The header detection starts with the start gap. A valid header requires 8
consecutive samples of rising and falling edges before the NDATA pin switches from high to
low.
Figure 3-6.
Standard Header
32
End of
periods
preamble of 125 kHz
16
periods
of 125 kHz
16
16
periods periods
off
on
Standard
header
tOFF
1152 µs
Demodulated
internal signal
Internal detection
windows
tON
tSTART_S
tSTART_L
tEND_S
tEND_L
tSTART_S
tEND_S
tSTART_S
tEND_S
If no valid header has been detected within 2 ms, beginning at the end of the preamble, the
header time-out check stops the oscillator and resets the gain control as well as the header
detection circuit to their initial state. The circuit then waits for the next preamble.
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In case of corrupted data or in a noisy environment, the controller also may use the serial
interface to reset the ATA5282 to the initial state. This is performed by shifting a specific command into the internal command register.
Figure 3-7.
Wake-up Protocol for 125-kHz ASK Modulation
Preamble
Header
about 2.5 ms
Synch
about 1 ms
16
16
periods periods
on
off
32
periods
off
320 periods
of 125 kHz
0.5 ms
Input
signal
Internally
demodulated
signal
Header
detection
Header
valid
Internal
wake-up
NDATA/
NWAKEUP
n Bit Data
End of Data
32 periods of
125 kHz
Input
signal
Internal
wake-up
0
1
1
20 ms no
signal
NDATA/
NWAKEUP
10
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3.9
Data Output
The wake-up signal enables the data pin that delivers the received and demodulated data
stream to the controller. Sampling and decoding has to be performed by the controller. An
example for data coding is given in the “n Bit Data” field (Figure 3-7 on page 10). This kind of
modulation requires an indication of the end of data, for example, by a burst that differs from
the other transmitted bits. As the circuit does not check the received data (except the header),
it is up to the base station which kind of modulation (pulse distance, Manchester, bi-phase...)
is used.
The data output signal is derived from the internal GAP detection. Table 3-1 describes how the
timing depends on different conditions of the applied input signal. The Q-factor of the external
LC-tank as well as the signal strength influence the pulse width of the output signal.
Figure 3-8.
Output Timing Conditions
100%
50%
Coil
input
Internal
comporator
output
Internal
NGAP
a
b
c
d
a + b = Data delay time tON
c + d = Data delay time tOFF
Table 3-1.
Typical Output Timing versus Signal Strength at 3.2V Supply Voltage
Input Signal
a, c
(Figure 3-8)
Minimum, 2.8 mVPP
Depends on
Q-factor
b (Periods)
d (Periods)
no Q
Q ≤14
Q ≤20
no Q
Q ≤14
Q ≤20
3 to 5
4 to 6
5 to 7
3 to 5
4 to 6
4 to 6
Medium, VCI < 2.8VPP
3 to 5
4 to 6
5 to 7
3 to 5
4 to 6
4 to 6
Strong, VCI ≥ 2.8VPP
3 to 5
3 to 5
3 to 5
3 to 5
4 to 6
4 to 6
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3.10
Current Profile and Reset Function
As long as the ATA5282 does not receive and recognize a valid preamble, it stays in a lowcurrent listen mode with the gain control and the header detection reset to their initial state.
After the circuit has passed the preamble check, the internal oscillator and the watchdog (for a
360 ms interval) starts. This results in an increased current consumption. The target of the different reset sources is to reduce the current consumption as fast as possible back to the initial
value.
This can take place at the end of the header time-out check at the earliest. If no valid header
has been detected within 2 ms, the circuit switches back to the initial state.
With wake-up activated, three further mechanism are available to control the reset. One under
control of the connected microcontroller, one if no signal is received and one unconditional
after a fixed time.
The controller may shift the SOFTRES-command into the internal command register to force
the circuit into the reset state. This may be useful if the controller detects that the received
data are corrupted.
The ATA5282 itself permanently checks for incoming signals. An interval of 20 ms (no signal
received) also leads to the reset state.
If there is no valid signal within 20 ms, for example, in a noisy environment or due to customer
protocol requirements, the watchdog forces the circuit into the reset state after a fixed time of
360 ms at the latest.
Figure 3-9.
Current Profile and Reset Timing
Protocol
Preamble
Start
gap
Header
n Bit Data
Valid preamble
detected
Valid header
detected
Internal
oscillator
Header time out check
2 ms interval
20 ms no data
20 ms interval
360 ms interval
Current
profile
12
Reset if no
header detected
Data transmission duration watchdog
reset if no data
Unconditional
reset
4 µA
2 µA
2 µA
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ATA5282
4. Serial Interface
4.1
General Description
The serial interface is an easy-to-handle 8-bit 2-wire interface. It always operates as a slave.
The controller uses the NSCL input to shift a command into and data out of the internal shift
register. The interface starts working with the first falling edge of NSCL. NDATA/NWAKEUP
serves as bi-directional DATA I/O for command input and data output. The rising edge of
NSCL is used to clock the command into the register of the ATA5282, while the falling edge is
used to shift out the data. Data changes are always derived from the falling edge of NSCL.
Two operating modes are implemented. One is the command mode that only requires an 8-bit
input and does not prepare a data output. This mode is useful to control different operating
modes of the ATA5282, as described on the following pages. The second mode is used to
read out the current value of the AGC-counter that is related to the field strength of the input
signal. The READ_FS command starts an internal sequence to store the value of the AGC into
the shift register and switches the DATA I/O to output mode. After tACC, the controller must
deliver another 8 shift clocks to clock out the information.
Figure 4-1.
Serial Interface
Command
MSB
DATA I/O
(NDATA)
A
B
C
D
E
MSB
F
G
Data
H
NSCL
tSCL
tACC > 50 µs
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4.2
Command and Data Register
The 8-bit command register is organized as follows:
Table 4-1.
Command Register
MSB
Command
FREEZE CH_SEL 1 CH_SEL 2 READ_FS SOFT_RES not used
not used
LSB
Function
TEST
MOD
Default value after reset: 00 hex
0
Application mode active
1
Test mode active
X
For future use
X
0
No effect
1
Reset circuit to initial state
0
No effect
1
Read AGC-counter (field strength)
0
0
Coil input 1, 2, 3 active
0
1
Select Coil input 1 (disable 2 and 3)
1
0
Select Coil input 2 (disable 1 and 3)
1
1
Select Coil input 3 (disable 1 and 2)
0
1
Note:
For future use
Automatic Gain Control (AGC) active
AGC stopped with actual value
These commands, except FREEZE- and READ_FS, cause a reset of AGC to initial state.
Table 4-2.
Data Register
MSB
Data
LSB
Function
AGC7
AGC6
AGC5
AGC4
AGC3
AGC2
AGC1
AGC0
Default value ’00’hex
Note:
The content of the data register is updated every time a READ_FS command is given via the interface.
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4.3
Command Description
Note:
4.3.1
Every command except FREEZE- and READ_FS causes a reset of the AGC to its initial state.
Between every command should be a delay of 50 µs.
TEST_MOD
Not for customer use, this mode is only used for production tests.
4.3.2
SOFT_RES
In addition to the internal hardware reset and watchdog functions, this bit allows the connected
microcontroller to switch the circuit into the initial low-power state. All internal registers including the serial interface and the gain control counter are reset by this command.
4.3.3
READ_FS
As long as this bit is kept at 0, the interface is in write mode and accepts 8-bit commands only.
Setting Read_FS to 1 enables to read out the digital 8-bit value of the gain control counter
(RSSI), thus requiring two 8-bit accesses. The distance between the two accesses (tACC) must
be > 50 µs to allow proper operating and updating of the internal data register.
4.3.4
CH_SEL0,1
These two bits define the operation mode of the three channels. After reset, all channels are
active. With the CH_SEL-bits, one of the three channels can be selected to be active, while
the other two are disabled. The gain control is reset to the initial value if these bits are modified
and operates only with the selected channel. This feature can be used for three-dimensional
field strength measurements or to suppress the influence of noise from disturbing channels.
4.3.5
FREEZE
When set to 1, this bit disables the automatic gain control and maintains the actual value for
the gain of the input amplifiers. Even when changing the input amplitudes (for example, modulation through noise or movement), the gain is kept constant.
4.3.6
Example
The example shows how to program the circuit to operate on channel 1 only and to measure
the field strength of the Coil 1 input signal.
Figure 4-2 shows the command entry which activates Coil 1 input only. The gain control
counter is set to zero (highest sensitivity) by this command. The information is shifted into the
ATA5282 with the rising edge of the shift clock.
Figure 4-2.
Select Coil Input 1
MSB
Command
0
0
1
0
0
0
0
0
DATA I/O
(NDATA)
NSCL
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Figure 4-3 shows the second step, the read-out of the actual field strength of the signal applied
to Coil 1.
When 128 steps have been passed, the gain control is finished and the value can be read out.
This is performed by providing the command READ_FS with the information of the selected
channel. 50 µs later, the ATA5282 has updated and stored the information into the internal
shift register. Now the microcontroller can read the actual information by generating the next 8
shift clock pulses. The information changes on the falling edge of the clock pulse.
Figure 4-3.
Read Field Strength of Channel 1
Read
Command
Read field strength of
coil 1 input signal
MSB
0
0
1
1
0
1
0
Field strength data
MSB
0
internal operation
DATA I/O
(NDATA)
NSCL
> 50 µs
Up-link
Down-link
4.4
Reset Interface
To prevent the system from hanging or running into a deadlock condition due to disturbances
on the NSCL line (hardware or software), a special function is provided to reset, the interface.
Figure 4-4.
Reset Interface
DATA I/O
(NDATA)
NSCL
Reset
interface
Setting the NSCL to a low level and generating 4 clock pulses at the NDATA pin resets all
interface-relevant registers and flip-flops, thus cancelling the deadlock condition and resynchronizing the interface.
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ATA5282
5. Application
Figure 5-1 shows an application of the ATA5282. Combined with the antenna resonant circuit,
the ATA5282 is used as wake-up receiver for the microcontroller. Additional to the antenna circuits the blocking filter - consisting of a RC element (R1 = 100Ω, C1 = 4.7 µF) - is necessary for
the ATA5282. An additional resistor (R2 = 2 MΩ/1%) should be placed at TC for oscillator tuning (optional: a parallel capacitor C2 with maximum 10 pF).
Figure 5-1.
Application Circuit
R1
C2
VDD
125 kHz
TC
ATA5282
X
C1
R2
GND
Timing
Central
Board
Controller
Antenna
Driver
ATA5278
Y
Header
Detect
Z
UHF
Receiver
ATA5743
Note:
Serial
Interace
433 MHz
NDATA
NSCL
Microcontroller
MARC4
UHF
Module
ATA5757
Unused channels should be connected to VDD.
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Figure 5-2.
Pin Connection and Pin Protection
ATA5282
COIL1
1
8
VDD
Divider impedance
143 kΩ to 5 MΩ
VDD
COIL2
2
7
NDATA
6
NSCL
5
TC
20 kΩ
Divider impedance
143 kΩ to 5 MΩ
2 kΩ
VDD
COIL3
3
1 kΩ
Divider impedance
143 kΩ to 5 MΩ
VDD
VSS
4
18 kΩ
18
1 kΩ
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ATA5282
6. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Value
Unit
Power supply
VDD
–0.3 to +6.5
V
Input voltage (except coil inputs)
VIN
VSS – 0.3 < VIN < VDD + 0.3
V
Input current coil
ICI
±10
mA
VCI
VDD – 3.5 < VCI < VDD + 3.5
V
ESD protection (human body)
Input voltage coil
VESD
4
kV
Operating temperature range
Tamb
–40 to +85
°C
Storage temperature range
Tstg
–40 to +130
°C
Soldering temperature
Tsld
260
°C
Symbol
Value
Unit
Thermal resistance junction-case
RthJC
260
K/W
Thermal resistance junction-ambient
RthJA
240
K/W
Symbol
Value
Unit
7. Thermal Resistance
Parameters
8. Operating Range
Parameters
Power supply range
VDD
2 to 3.8
V
Operating temperature range
TOP
–40 to +85
°C
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9. Electrical Characteristics
VSS = 0V, VDD = 0V to 3.8V, Tamb = –40°C to 85°C unless otherwise specified
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
2
3.2
3.8
V
A
Power Supply and Coil Limiter
1.1
Power supply
8
VDD
1.2
Supply current
(initial state, AGC off)
8
IDD
2
4
µA
A
1.3
Supply current (AGC active)
8
IDD
4
6
µA
A
1.4
Power on reset threshold
1.5
1.9
V
A
100
ms
C
100
µs
C
VPOR
Switch on VDD to circuit
active
1.5
Power up time
1.6
RESET reactivation caused by
tBDN = 500 ns
negative spikes on VDD
Coil input voltage referred to
VDD (Input Coil limiter for
channels X, Y, Z)
ICI = ±1 mA
VDD = 2.0V
VDD = 3.2V
VDD = 3.8V
1.8
TC low current output
VO_TC at 500 mV
1.9
Carrier frequency range
1.71
1.72
1.73
2
1
VPON
7
tRST
10
1, 2, 3
VCI
5
ITC
205
1, 2, 3
fCF
100
7
±1.2
±1.4
±1.55
250
VP
VP
VP
A
280
nA
A
150
kHz
D
4.9
Amplifiers
2.1
Wake-up sensitivity
125-kHz input signal
VSENS
2.8
mVPP
A
2.2
Bandwidth
Without Coil
BW
150
kHz
C
2.3
Upper corner frequency
Without Coil
fu
180
kHz
C
2.4
Lower corner frequency
Without Coil
fo
30
kHz
C
2.5
Gain difference
Maximum/minimum value
(decimal) of channels
RSSI_Vmax – RSSI_Vmin
(see Figure 3-3 on page 7)
1, 2, 3
GDIFF
2.6
Input impedance
VIN ≥ 2.8 mVPP at 125 kHz
1, 2, 3
RIN
2.7
Input capacitance
1, 2, 3
CIN
2.8
3
Coils Input Range
VCI = 2.8 mVPP
VCI = 2.8 VPP
Oscillator frequency
REXT = 2 MΩ and
CEXT maximum 10 pF
3.2
Preamble periods
VCI ≥ 1VPP
1, 2, 3
3.3
3.5
kΩ
A
10
pF
C
60
dB
A
kHz
A
143
1, 2, 3
A
Digital
3.1
3.4
16
Header detection windows
(L = long, S = short)
see Figure 3-6 on page 9
Tolerance included
oscillator tolerance
3.6
6
fOSC
80
90
100
nPAM
320
tSTART_L
160
182
205
µs
D
tEND_L
315
357
400
µs
D
tSTART_S
40
50
60
µs
A
tEND_S
200
225
255
µs
D
tNSCL
10
µs
C
tACC
50
µs
A
A
3.7
Shift clock period
3.8
Data access time
3.9
Data rate (Q < 20)
125 kHz ASK
DRATE
4
kbps
A
3.10
Delay time RF signal to data
125 kHz ASK
tON
40
µs
A
3.11
Delay time RF signal to data
125 kHz ASK
tOFF
40
µs
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
20
ATA5282
4694E–AUTO–08/05
ATA5282
9. Electrical Characteristics (Continued)
VSS = 0V, VDD = 0V to 3.8V, Tamb = –40°C to 85°C unless otherwise specified
No.
4
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Interface
4.1
NSCL input level LOW
6
VIL_NSCL
VSS
0.2 ×
VDD
V
A
4.2
NSCL input level HIGH
6
VIH_NSCL
0.8 ×
VDD
VDD
V
A
4.3
NSCL input leakage current
LOW
VNSCL = VSS
6
IIL_NSCL
–200
0
nA
A
4.4
NSCL input leakage current
HIGH
VNSCL = VDD
6
IIH_NSCL
0
+200
nA
A
4.5
NDATA input level LOW
VNSCL = VSS
7
VIL_NDAT
VSS
0.2 ×
VDD
V
A
4.6
NDATA input level HIGH
VNSCL = VSS
7
VIH_NDAT
0.8 ×
VDD
VDD
V
A
4.7
NDATA input leakage current
LOW
VNDAT = VSS
VNSCL = VSS
7
IIL_NDAT
–200
0
nA
A
4.8
NDATA input leakage current
HIGH
VNDAT = VDD
VNSCL = VSS
7
IIH_NDAT
0
+200
nA
A
4.9
NDATA output level LOW
INDAT = +70 µA
VNSCL = VDD
7
VOL_NDAT
VSS
0.2 ×
VDD
V
A
4.10
NDATA output level HIGH
INDAT = –70 µA
VNSCL = VDD
7
VOL_NDAT
0.8× VDD
VDD
V
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
21
4694E–AUTO–08/05
10. Ordering Information
Extended Type Number
Package
Remarks
ATA5282-6AQH
TSSOP 8L
5000 pcs taped and reeled, Pb-free
ATA5282-6APH
TSSOP 8L
500 pcs taped and reeled, Pb-free
11. Package Information
Figure 11-1. Package TSSOP 8L
22
ATA5282
4694E–AUTO–08/05
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