Features • • • • • • • • • • • • • • • • • • • • • • • • • 80C31 Compatible 8031 pin and instruction compatible Four 8-bit I/O ports Two 16-bit timer/counters 128 bytes scratchpad RAM High-Speed Architecture 40 MHz @ 5V, 30MHz @ 3V X2 Speed Improvement capability (6 clocks/machine cycle) 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V) Dual Data Pointer Asynchronous port reset Interrupt Structure with 5 Interrupt sources, 4 priority level interrupt system Full duplex Enhanced UART Framing error detection Automatic address recognition Power Control modes Idle mode Power-down mode Power-off Flag Once mode (On-chip Emulation) Power supply: 4.5-5.5V, 2.7-5.5V Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC) Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1 (13.9 footprint) 8-bit CMOS Microcontroller ROMless TS80C31X2 AT80C31X2 1. Description TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM, a 5-source, 4 priority level interrupt system, an on-chip oscilator and two timer/counters. In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism. The fully static design of the TS80C31X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C31X2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. 4428E–8051–02/08 TxD RxD 2. Block Diagram (1) (1) XTAL1 EUART XTAL2 ALE/ PROG RAM 128x8 C51 CORE PSEN IB-bus CPU EA Timer 0 Timer 1 (1) INT Ctrl Parallel I/O Ports & Ext. Bus Port 0 Port 1 Port 2 Port 3 P3 P2 P1 (1) (1) P0 T1 T0 RESET (1) (1) INT1 WR (1) INT0 RD (1): Alternate function of Port 3 2 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 4. SFR Mapping The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3 • Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1 • Serial I/O port registers: SADDR, SADEN, SBUF, SCON • Power and clock control registers: PCON • Interrupt system registers: IE, IP, IPH • Others: CKCON Table 4-1. All SFRs with their address and their reset value Bit addressable 0/8 Non Bit addressable 1/9 2/A 3/B 4/C 5/D 6/E 7/F F8h F0h FFh B 0000 0000 F7h E8h E0h EFh ACC 0000 0000 E7h D8h D0h DFh PSW 0000 0000 D7h C8h CFh C0h C7h B8h B0h A8h A0h 98h 90h 88h 80h IP SADEN XXX0 0000 0000 0000 BFh P3 IPH XXX0 0000 1111 1111 IE SADDR 0XX0 0000 0000 0000 AFh P2 AUXR1 1111 1111 XXXX XXX0 SCON SBUF 0000 0000 XXXX XXXX B7h A7h 9Fh P1 97h 1111 1111 TCON TMOD TL0 TL1 TH0 TH1 CKCON 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXXX XXX0 P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 0/8 1/9 2/A 3/B PCON 00X1 0000 4/C 5/D 6/E 8Fh 87h 7/F Reserved 3 4428E–8051–02/08 P0.6 / A6 32 31 30 37 EA/VPP ALE/PROG PSEN P0.6/AD6 RST 10 36 P0.7/AD7 P3.0/RxD 35 34 EA NIC* 11 12 P3.1/TxD 13 33 ALE P3.2/INT0 P3.3/INT1 14 15 32 31 PSEN P3.4/T0 P3.5/T1 16 30 P2.6/A14 17 29 P2.5/A13 P2.7 / A15 P2.6 / A14 P2.5 / A13 17 18 24 23 P2.2 / A10 XTAL1 19 20 22 21 P2.1 / A9 P3.6/WR P1.0 P1.1 P1.2 NIC* P2.7/A15 18 19 20 21 22 23 24 25 26 27 28 P2.0 / A8 P1.3 P1.4 P0.5/AD5 P2.3/A11 P2.4/A12 P3.7/RD XTAL2 P2.2/A10 25 P2.1/A9 16 P2.4 / A12 P2.3 / A11 PLCC44 NIC* P2.0/A8 14 15 VSS P0.2/AD2 P0.3/AD3 9 P3.4/T0 P3.5/T1 P3.6/WR 26 P0.1/AD1 P1.7 VSS 13 P0.7 / A7 XTAL1 29 28 27 39 38 P0.4/AD4 P1.6 7 8 XTAL2 CDIL40 P1.5 P3.7/RD 11 12 PDIL/ 6 5 4 3 2 1 44 43 42 41 40 P0.5 / A5 P0.3/AD3 10 P0.0/AD0 9 P1.4 P0.3 / A3 P0.4 / A4 P0.2/AD2 P3.2/INT0 P3.3/INT1 36 35 34 33 P0.1/AD1 P3.0/RxD P3.1/TxD 6 7 8 5 P0.0/AD0 P1.7 RST P0.1 / A1 P0.2 / A2 VCC P1.6 37 VSS1/NIC* P1.4 P1.5 3 4 VCC P0.0 / A0 VSS1/NIC* VCC 39 38 P1.0 40 2 P1.1 1 P1.2 P1.0 / T2 P1.1 / T2EX P1.2 P1.3 P1.3 5. Pin Configuration 44 43 42 41 40 39 38 37 36 35 34 P1.5 1 P1.6 2 P1.7 RST 3 4 P3.0/RxD 5 NIC* 6 7 8 P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 33 32 P0.4/AD4 31 P0.6/AD6 30 P0.7/AD7 29 28 27 EA 26 25 PSEN 9 10 24 P2.6/A14 11 23 P2.5/A13 PQFP44 VQFP44 P0.5/AD5 NIC* ALE P2.7/A15 P2.3/A11 P2.4/A12 P2.2/A10 P2.1/A9 NIC* P2.0/A8 VSS XTAL1 XTAL2 P3.7/RD P3.6/WR 12 13 14 15 16 17 18 19 20 21 22 *NIC: No Internal Connection 4 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 Pin Number Mnemonic VSS DIL LCC VQFP 1.4 Type 20 22 16 I Ground: 0V reference 1 39 I Optional Ground: Contact the Sales Office for ground connection. Power Supply: This is the power supply voltage for normal, idle and power-down operation Vss1 Name And Function VCC 40 44 38 I P0.0-P0.7 3932 43-36 37-30 I/O P1.0-P1.7 1-8 2-9 40-44 1-3 I/O P2.0-P2.7 2128 24-31 18-25 I/O P3.0-P3.7 1017 11, 13-19 5, 7-13 I/O 10 11 5 I RXD (P3.0): Serial input port 11 13 7 O TXD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 0 13 15 9 I INT1 (P3.3): External interrupt 1 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. ALE 30 33 27 O (I) Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. 5 4428E–8051–02/08 EA 31 35 29 I External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier 6 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 6. TS80C31X2 Enhanced Features In comparison to the original 80C31, the TS80C31X2 implements some new features, which are: • The X2 option. • The Dual Data Pointer. • The 4 level interrupt priority system. • The power-off flag. • The ONCE mode. • Enhanced UART 6.1 X2 Feature The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. • Save power consumption while keeping same CPU power (oscillator power saving). • Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. • Increase CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. 6.1.1 Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 6-1. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 6-2. shows the mode switching waveforms. Figure 6-1. Clock Generation Diagram 2 XTAL1 FXTAL XTAL1:2 0 1 state machine: 6 clock cycles. CPU control FOSC X2 CKCON reg 7 4428E–8051–02/08 Figure 6-2. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode X2 Mode STD Mode The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode). CAUTION In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate. Table 6-1. CKCON Register CKCON - Clock Control Register (8Fh) 7 6 5 4 3 2 1 0 - - - - - - - X2 Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 X2 Description CPU and peripheral clock bit Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2). Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL). Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com) 8 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 7. Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 7-1). Figure 7-1. Use of Dual Pointer External Data Memory 7 0 DPS DPTR1 DPTR0 AUXR1(A2H) DPH(83H) DPL(82H) Table 7-1. AUXR1: Auxiliary Register 1 7 6 5 4 3 2 1 0 - -3 - - - - - DPS Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 DPS Description Data Pointer Selection Clear to select DPTR0. Set to select DPTR1. Reset Value = XXXX XXX0 Not bit addressable 9 4428E–8051–02/08 8. Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer. ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000 MOV DPTR,#SOURCE 0003 05A2 INC AUXR1 0005 90A000 MOV DPTR,#DEST 0008 LOOP: 0008 05A2 INC AUXR1 000A E0 MOVX A,@DPTR 000B A3 INC DPTR 000C 05A2 INC AUXR1 000E F0 MOVX @DPTR,A 000F A3 INC DPTR 0010 70F6 JNZ LOOP 0012 05A2 INC AUXR1 ; address of SOURCE ; switch data pointers ; address of DEST ; switch data pointers ; get a byte from SOURCE ; increment SOURCE address ; switch data pointers ; write the byte to DEST ; increment DEST address ; check for 0 terminator ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. 10 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 9. TS80C31X2 Serial I/O Port The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: • Framing error detection • Automatic address recognition 9.1 Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1). Figure 9-1. Framing Error Block Diagram SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h) Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD = 0) SMOD1 SMOD0 - POF GF1 GF0 PD IDL PCON (87h) To UART framing error control When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 9-3.) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 92. and Figure 9-3.). Figure 9-2. UART Timings in Mode 1 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 Stop bit RI SMOD0=X FE SMOD0=1 11 4428E–8051–02/08 Figure 9-3. UART Timings in Modes 2 and 3 RXD D0 D1 D2 Start bit D3 D4 Data byte D5 D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 9.2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). 9.3 Given Address Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR SADEN Given 0101 0110b 1111 1100b 0101 01XXb The following is an example of how to use given addresses to address different slaves: 12 Slave A: SADDR SADEN Given 1111 0001b 1111 1010b 1111 0X0Xb Slave B: SADDR SADEN Given 1111 0011b 1111 1001b 1111 0XX1b AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 Slave C: SADDR SADEN Given 1111 0010b 1111 1101b 1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). 9.4 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR SADEN Broadcast =SADDR OR SADEN 0101 0110b 1111 1100b 1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A: SADDR 1111 0001b SADEN 1111 1010b Broadcast 1111 1X11b, Slave B: SADDR 1111 0011b SADEN 1111 1001b Broadcast 1111 1X11B, Slave C: SADDR= 1111 0010b SADEN 1111 1101b Broadcast 1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. 9.5 Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. Table 9-1. 7 SADEN - Slave Address Mask Register (B9h) 6 5 4 3 2 1 0 Reset Value = 0000 0000b Not bit addressable 13 4428E–8051–02/08 Table 9-2. 7 SADDR - Slave Address Register (A9h) 6 5 4 3 2 1 0 Reset Value = 0000 0000b Not bit addressable 14 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 Table 9-3. SCON Register -- SCON - Serial Control Register (98h) 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic 7 FE Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 bit 6 SM1 Serial port Mode bit 1 SM0 SM1 Mode Description Baud Rate 0 0 1 1 FXTAL/12 (/6 in X2 mode) Variable FXTAL/64 or FXTAL/32 (/32, /16 in X2 mode) Variable 0 1 0 1 0 1 2 3 Shift Register 8-bit UART 9-bit UART 9-bit UART 5 SM2 Serial port Mode 2 bit / Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0. 4 REN Reception Enable bit Clear to disable serial reception. Set to enable serial reception. 3 TB8 Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3. 2 RB8 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8 / Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. 1 TI Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0 RI Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 9-2. and Figure 9-3. in the other modes. Reset Value = 0000 0000b Bit addressable 15 4428E–8051–02/08 Table 9-4. PCON Register -- PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Bit Number Mnemonic 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2 GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. 16 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 10. Interrupt System The TS80C31X2 has a total of 5 interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (timers 0 and 1) and the serial port interrupt. These interrupts are shown in Figure 10-1. Figure 10-1. Interrupt Control System High priority interrupt IPH, IP 3 INT0 IE0 0 3 TF0 0 Interrupt polling sequence, decreasing from high to low priority 3 INT1 IE1 0 3 TF1 0 3 RI TI 0 Individual Enable Global Disable Low priority interrupt Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 10-2.Table 10-3.). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 10-3.) and in the Interrupt Priority High register (See Table 10-4.). shows the bit values and priority levels associated with each combination. Table 10-1. Priority Level Bit Values IPH.x IP.x Interrupt Level Priority 0 0 0 (Lowest) 0 1 1 1 0 2 1 1 3 (Highest) 17 4428E–8051–02/08 A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 10-2. IE Register -- IE - Interrupt Enable Register (A8h) 7 6 5 4 3 2 1 0 EA - - ES ET1 EX1 ET0 EX0 Bit Bit Number Mnemonic Description Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit. 7 EA 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 ES Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. 3 ET1 Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. 2 EX1 External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. 1 ET0 Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. 0 EX0 External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0XX0 0000b Bit addressable 18 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 Table 10-3. IP Register -- IP - Interrupt Priority Register (B8h) 7 6 5 4 3 2 1 0 - - - PS PT1 PX1 PT0 PX0 Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 PS Serial port Priority bit Refer to PSH for priority level. 3 PT1 Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. 2 PX1 External interrupt 1 Priority bit Refer to PX1H for priority level. 1 PT0 Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. 0 PX0 External interrupt 0 Priority bit Refer to PX0H for priority level. Description Reset Value = XXX0 0000b Bit addressable 19 4428E–8051–02/08 Table 10-4. IPH Register -- IPH - Interrupt Priority High Register (B7h) 7 6 5 4 3 2 1 0 - - - PSH PT1H PX1H PT0H PX0H Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 3 2 1 0 Description PSH Serial port Priority High bit PS Priority Level PSH 0 0 Lowest 0 1 1 0 1 1 Highest PT1H Timer 1 overflow interrupt Priority High bit PT1H PT1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PX1H External interrupt 1 Priority High bit PX1H PX1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PT0H Timer 0 overflow interrupt Priority High bit PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PX0H External interrupt 0 Priority High bit PX0H PX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Reset Value = XXX0 0000b Not bit addressable 20 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 11. Idle mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give and indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The over way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. 11.1 Power-Down Mode To save maximum power, a power-down mode can be invoked by software (Refer to Table 9-4., PCON register). In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from power-down. To properly terminate powerdown, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 11-1. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. In this case the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put TS80C31X2 into power-down mode. 21 4428E–8051–02/08 Figure 11-1. Power-Down Exit Waveform INT0 INT1 XTAL1 Active phase Power-down phase Oscillator restart phase Active phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content. Note: NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. Table 11-1. The state of ports during idle and power-down modes Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle External 1 1 Floating Port Data Address Port Data Power Down External 0 0 Floating Port Data Port Data Port Data 22 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 12. ONCETM Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C31X2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C31X2; the following sequence must be exercised: • Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the TS80C31X2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26. shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. Table 12-1. External Pin Status during ONCE Mode ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1/2 Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up Active 23 4428E–8051–02/08 13. Power-Off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. The power-off flag (POF) is located in PCON register (See Table 13-1.). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type of reset. The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will return indeterminate value. Table 13-1. PCON Register -- PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Bit Number Mnemonic 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2 GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X1 0000b Not bit addressable 24 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 14. Electrical Characteristics 14.1 Absolute Maximum Ratings (1) Ambiant Temperature Under Bias: C = commercial0°C to 70°C I = industrial -40°C to 85°C Storage Temperature-65°C to + 150°C Voltage on VCC to VSS-0.5 V to + 7 V Voltage on VPP to VSS-0.5 V to + 13 V Voltage on Any Pin to VSS-0.5 V to VCC + 0.5 V Power Dissipation1 W(2) Note: 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package. 14.2 Power consumption measurement Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was running under reset. In Atmel Wireless & Microcontrollers new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That’s why, while keeping measurements under Reset, Atmel Wireless & Microcontrollers presents a new way to measure the operating Icc: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc. 25 4428E–8051–02/08 14.3 DC Parameters for Standard Voltage TA = 0°C to +70°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. Table 14-1. Symbol DC Parameters in Standard Voltage Parameter Min VIL Input Low Voltage VIH Input High Voltage except XTAL1, RST VIH1 Input High Voltage, XTAL1, RST VOL VOL1 VOL2 VOH VOH1 VOH2 RRST Output Low Voltage, ports 1, 2, 3 Output Low Voltage, port 0 Typ Max Unit -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V 0.3 V IOL = 100 µA(4) 0.45 V IOL = 1.6 mA(4) 1.0 V IOL = 3.5 mA(4) 0.3 V IOL = 200 µA(4) 0.45 V IOL = 3.2 mA(4) 1.0 V IOL = 7.0 mA(4) 0.3 V IOL = 100 µA(4) 0.45 V IOL = 1.6 mA(4) 1.0 V IOL = 3.5 mA(4) (6) (6) Output Low Voltage, ALE, PSEN Output High Voltage, ports 1, 2, 3 Output High Voltage, port 0 Output High Voltage,ALE, PSEN RST Pulldown Resistor VCC - 0.3 V VCC - 0.7 V VCC - 1.5 V VCC - 0.3 V VCC - 0.7 V VCC - 1.5 V VCC - 0.3 V VCC - 0.7 V VCC - 1.5 V 50 90 (5) 200 kΩ Test Conditions IOH = -10 µA IOH = -30 µA IOH = -60 µA VCC = 5 V ± 10% IOH = -200 µA IOH = -3.2 mA IOH = -7.0 mA VCC = 5 V ± 10% IOH = -100 µA IOH = -1.6 mA IOH = -3.5 mA VCC = 5 V ± 10% IIL Logical 0 Input Current ports 1, 2 and 3 -50 µA Vin = 0.45 V ILI Input Leakage Current ±10 µA 0.45 V < Vin < VCC ITL Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 µA Vin = 2.0 V CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz TA = 25°C IPD Power Down Current 50 µA 2.0 V < VCC < 5.5 V(3) ICC under RESET ICC operating Power Supply Current Maximum values, X1 mode: (7) 20 (5) 1 + 0.4 Freq (MHz) @12MHz 5.8 @16MHz 7.4 Power Supply Current Maximum values, X1 mode: (7) 3 + 0.6 Freq (MHz) @12MHz 10.2 mA mA VCC = 5.5 V(1) VCC = 5.5 V(8) @16MHz 12.6 26 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 Symbol ICC Parameter Min Typ Unit Test Conditions 0.25+0.3 Freq (MHz) Power Supply Current Maximum values, X1 mode: (7) idle Max @12MHz 3.9 VCC = 5.5 V(2) mA @16MHz 5.1 14.4 DC Parameters for Low Voltage TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. Table 14-2. Symbol DC Parameters for Low Voltage Parameter Min Typ Max Unit -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V Test Conditions VIL Input Low Voltage VIH Input High Voltage except XTAL1, RST VIH1 Input High Voltage, XTAL1, RST VOL Output Low Voltage, ports 1, 2, 3 (6) 0.45 V IOL = 0.8 mA(4) VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 0.45 V IOL = 1.6 mA(4) VOH Output High Voltage, ports 1, 2, 3 0.9 VCC V IOH = -10 µA VOH1 Output High Voltage, port 0, ALE, PSEN 0.9 VCC V IOH = -40 µA IIL Logical 0 Input Current ports 1, 2 and 3 -50 µA Vin = 0.45 V ILI Input Leakage Current ±10 µA 0.45 V < Vin < VCC ITL Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 µA Vin = 2.0 V 200 kΩ 10 pF RRST RST Pulldown Resistor CIO Capacitance of I/O Buffer IPD Power Down Current ICC under RESET ICC operating 50 90 20 (5) 50 (5) 30 10 Power Supply Current Maximum values, X1 mode: (7) (5) 1 + 0.2 Freq (MHz) @12MHz 3.4 idle mA VCC = 2.0 V to 5.5 V(3) VCC = 2.0 V to 3.3 V(3) VCC = 3.3 V(1) @16MHz 4.2 Power Supply Current Maximum values, X1 mode: (7) 1 + 0.3 Freq (MHz) @12MHz 4.6 @16MHz 5.8 ICC µA Fc = 1 MHz TA = 25°C Power Supply Current Maximum values, X1 mode: (7) mA VCC = 3.3 V(8) 0.15 Freq (MHz) + 0.2 @12MHz 2 mA VCC = 3.3 V(2) @16MHz 2.6 Note: 1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 14-5.), VIL = VSS + 0.5 V, 27 4428E–8051–02/08 VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used.. 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 143.). 3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 14-4.). 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. 8. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 14-5.), VIL = VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case. VCC ICC VCC P0 VCC RST (NC) CLOCK SIGNAL VCC EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 14-1. ICC Test Condition, under reset 28 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 VCC ICC VCC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST EA XTAL2 XTAL1 (NC) CLOCK SIGNAL All other pins are disconnected. VSS Figure 14-2. Operating ICC Test Condition VCC ICC VCC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST EA XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL All other pins are disconnected. Figure 14-3. ICC Test Condition, Idle Mode VCC ICC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) VCC EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 14-4. ICC Test Condition, Power-Down Mode 29 4428E–8051–02/08 VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1 Figure 14-5. Clock Signal Waveform for ICC Tests in Active and Idle Modes 14.5 14.5.1 AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = 0 to +70°C (commercial temperature range); VSS = 0 V; VCC = 5 V ± 10%; -M and -V ranges. TA = -40°C to +85°C (industrial temperature range); VSS = 0 V; VCC = 5 V ± 10%; -M and -V ranges. TA = 0 to +70°C (commercial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range. TA = -40°C to +85°C (industrial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range. Table 14-3. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals. Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings will then be degraded. Table 14-3. Load Capacitance versus speed range, in pF Port 0 Port 1, 2, 3 ALE / PSEN -M 100 80 100 -V 50 50 30 -L 100 80 100 Table 8-5., Table 8-8. and Table 8-11. give the description of each AC symbols. Table 14-6., Table 14-9. and Table 14-12. give for each range the AC parameter. 30 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 Table 14-7., Table 14-10. and Table 14-13. give the frequency derating formula of the AC parameter. To calculate each AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value in the formula. Values of the frequency must be limited to the corresponding speed grade: Table 14-4. Max frequency for derating formula regarding the speed grade Freq (MHz) T (ns) -M X1 mode -M X2 mode -V X1 mode -V X2 mode -L X1 mode -L X2 mode 40 20 40 30 30 20 25 50 25 33.3 33.3 50 Example: TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns): x= 25 (Table 14-7.) T= 50ns TLLIV= 2T - x = 2 x 50 - 25 = 75ns Table 14-5. External Program Memory Characteristics Symbol T Parameter Oscillator clock period TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction FloatAfter PSEN TPXAV PSEN to Address Valid TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float 31 4428E–8051–02/08 Table 14-6. AC Parameters for Fix Clock -V X2 mode Speed -M 30 MHz 40 MHz 60 MHz equiv. Max -L standard mode 40 MHz standard mode 20 MHz 30 MHz 40 MHz equiv. T 25 33 25 50 33 ns TLHLL 40 25 42 35 52 ns TAVLL 10 4 12 5 13 ns TLLAX 10 4 12 5 13 ns 70 Max Min 45 Max Min 78 Max Units Min Min Max 65 98 ns TLLPL 15 9 17 10 18 ns TPLPH 55 35 60 50 75 ns TPLIV TPXIX 35 25 0 50 0 30 0 0 55 0 ns ns TPXIZ 18 12 20 10 18 ns TAVIV 85 53 95 80 122 ns TPLAZ 10 10 10 10 10 ns Table 14-7. 32 -L X2 mode Symbol TLLIV Min -V AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock X2 Clock -M -V -L Units TLHLL Min 2T-x T-x 10 8 15 ns TAVLL Min T-x 0.5 T - x 15 13 20 ns TLLAX Min T-x 0.5 T - x 15 13 20 ns TLLIV Max 4T-x 2T-x 30 22 35 ns TLLPL Min T-x 0.5 T - x 10 8 15 ns TPLPH Min 3T-x 1.5 T - x 20 15 25 ns TPLIV Max 3T-x 1.5 T - x 40 25 45 ns TPXIX Min x x 0 0 0 ns TPXIZ Max T-x 0.5 T - x 7 5 15 ns TAVIV Max 5T-x 2.5 T - x 40 30 45 ns TPLAZ Max x x 10 10 10 ns AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 14.5.2 External Program Memory Read Cycle 12 TCLCL TLHLL TLLIV ALE TLLPL TPLPH PSEN PORT 0 TLLAX TAVLL INSTR IN TPLIV TPLAZ A0-A7 TPXAV TPXIZ TPXIX INSTR IN A0-A7 INSTR IN TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 Figure 14-6. External Program Memory Read Cycle Table 14-8. External Data Memory Characteristics Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high 33 4428E–8051–02/08 Table 14-9. AC Parameters for a Fix Clock -V X2 mode Speed -M 30 MHz 40 MHz 60 MHz equiv. standard mode 40 MHz equiv. 30 MHz 85 135 125 175 ns TWLWH 130 85 135 125 175 ns 0 Min 60 0 Max Min 102 0 Max Min Units 130 95 0 Max 137 0 ns ns TRHDZ 30 18 35 25 42 ns TLLDV 160 98 165 155 222 ns TAVDV 165 100 175 160 235 ns 130 ns TLLWL 50 TAVWL 75 47 80 70 103 ns TQVWX 10 7 15 5 13 ns TQVWH 160 107 165 155 213 ns TWHQX 15 9 17 10 18 ns TRLAZ TWHLH 34 -L 20 MHz TRLRH 100 Max standard mode 40 MHz Min TRHDX Min -L X2 mode Symbol TRLDV Max -V 100 30 0 10 40 70 55 0 7 27 95 45 0 15 35 105 70 0 5 45 13 0 ns 53 ns AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 Table 14-10. AC Parameters for a Variable Clock: derating formula 14.5.3 Symbol Type Standard Clock X2 Clock -M -V -L Units TRLRH Min 6T-x 3T-x 20 15 25 ns TWLWH Min 6T-x 3T-x 20 15 25 ns TRLDV Max 5T-x 2.5 T - x 25 23 30 ns TRHDX Min x x 0 0 0 ns TRHDZ Max 2T-x T-x 20 15 25 ns TLLDV Max 8T-x 4T -x 40 35 45 ns TAVDV Max 9T-x 4.5 T - x 60 50 65 ns TLLWL Min 3T-x 1.5 T - x 25 20 30 ns TLLWL Max 3T+x 1.5 T + x 25 20 30 ns TAVWL Min 4T-x 2T-x 25 20 30 ns TQVWX Min T-x 0.5 T - x 15 10 20 ns TQVWH Min 7T-x 3.5 T - x 15 10 20 ns TWHQX Min T-x 0.5 T - x 10 8 15 ns TRLAZ Max x x 0 0 0 ns TWHLH Min T-x 0.5 T - x 15 10 20 ns TWHLH Max T+x 0.5 T + x 15 10 20 ns External Data Memory Write Cycle TWHLH ALE PSEN TLLWL TWLWH WR TLLAX PORT 0 TQVWX A0-A7 TQVWH TWHQX DATA OUT TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 Figure 14-7. External Data Memory Write Cycle 35 4428E–8051–02/08 14.5.4 External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL TRLRH TRLDV RD TLLAX PORT 0 TRHDZ TAVDV TRHDX A0-A7 DATA IN TRLAZ TAVWL ADDRESS OR SFR-P2 PORT 2 ADDRESS A8-A15 OR SFR P2 Figure 14-8. External Data Memory Read Cycle Table 14-11. Serial Port Timing - Shift Register Mode Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid Table 14-12. AC Parameters for a Fix Clock -V X2 mode Speed 30 MHz 40 MHz 60 MHz equiv. Max Max standard mode 40 MHz -L 20 MHz standard mode 40 MHz equiv. 30 MHz TXLXL 300 200 300 300 400 ns TQVHX 200 117 200 200 283 ns TXHQX 30 13 30 30 47 ns TXHDX 0 0 0 0 0 ns 34 Min Max 117 Min Max 117 Min Units Min 117 Min -L X2 mode Symbol TXHDV 36 -M -V Max 200 ns AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 Table 14-13. AC Parameters for a Variable Clock: derating formula 14.5.5 Symbol Type Standard Clock X2 Clock TXLXL Min 12 T 6T TQVHX Min 10 T - x 5T-x 50 50 50 ns TXHQX Min 2T-x T-x 20 20 20 ns TXHDX Min x x 0 0 0 ns TXHDV Max 10 T - x 5 T- x 133 133 133 ns -M -V -L Units ns Shift Register Timing Waveforms INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE TXLXL CLOCK TXHQX TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA 0 1 2 3 4 5 6 7 TXHDX TXHDV VALID VALID VALID SET TI VALID VALID VALID VALID VALID SET RI CLEAR RI Figure 14-9. Shift Register Timing Waveforms Table 14-14. External Clock Drive Characteristics (XTAL1) Symbol Parameter Min TCLCL Oscillator Period 25 ns TCHCX High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns TCHCX/TCLCX Cyclic ratio in X2 mode 60 % 40 Max Units 37 4428E–8051–02/08 14.5.6 External Clock Drive Waveforms VCC-0.5 V 0.45 V 0.7VCC 0.2VCC-0.1 V TCHCL TCHCX TCLCH TCLCX TCLCL Figure 14-10. External Clock Drive Waveforms 14.5.7 AC Testing Input/Output Waveforms VCC-0.5 V INPUT/OUTPUT 0.2VCC+0.9 0.2VCC-0.1 0.45 V Figure 14-11. AC Testing Input/Output Waveforms AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. 14.5.8 Float Waveforms FLOAT VOH-0.1 V VLOAD VOL+0.1 V VLOAD+0.1 V VLOAD-0.1 V Figure 14-12. Float Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA. 14.5.9 38 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 Figure 14-13. Clock Waveforms INTERNAL CLOCK STATE4 STATE5 STATE6 STATE1 STATE2 P1P2 P1P2 P1P2 P1P2 P1P2 STATE3 P1P2 STATE4 P1P2 STATE5 P1P2 XTAL2 ALE THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLE FLOAT PCL OUT DATA SAMPLE FLOAT PCL OUT DATA SAMPLE FLOAT PCL OUT INDICATES ADDRESS P2 (EXT) READ CYCLE RD PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt FLOAT P2 INDICATES DPH OR P2 SFR TO PCH WRITE CYCLE WR PCL OUT (EVEN IF MEMORY IS INTERNAL) P0 DPL OR Rt DATA OUT P2 PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) INDICATES DPH OR P2 SFR TO PCH PORT OPERATION OLD DATA P0 PINS SAMPLED NEW DATA P0 PINS SAMPLED MOV DEST P0 MOV DEST PORT (P1, P2, (INCLUDES INT0, INT1, TO, T1) P1, P2, P3 PINS SERIAL PORT SHIFT CLOCK TXD (MODE 0) RXD SAMPLED P1, P2, P3 PINS RXD SAMPLED This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. 39 4428E–8051–02/08 15. Ordering Information Part Number(3) Memory Size Supply Voltage Temperature Range Max Frequency Package Packing TS80C31X2-MCA TS80C31X2-MCB TS80C31X2-MCC TS80C31X2-MCE TS80C31X2-LCA TS80C31X2-LCB TS80C31X2-LCC TS80C31X2-LCE TS80C31X2-VCA TS80C31X2-VCB TS80C31X2-VCC TS80C31X2-VCE OBSOLETE TS80C31X2-MIA TS80C31X2-MIB TS80C31X2-MIC TS80C31X2-MIE TS80C31X2-LIA TS80C31X2-LIB TS80C31X2-LIC TS80C31X2-LIE TS80C31X2-VIA TS80C31X2-VIB TS80C31X2-VIC TS80C31X2-VIE AT80C31X2-3CSUM ROMLess 5V ±10% Industrial & Green 40 MHz(1) PDIL40 Stick AT80C31X2-SLSUM ROMLess 5V ±10% Industrial & Green 40 MHz(1) PLCC44 Stick AT80C31X2-RLTUM ROMLess 5V ±10% Industrial & Green 40 MHz(1) VQFP44 Tray AT80C31X2-3CSUL ROMLess 2.7 to 5.5V Industrial & Green 30 MHz(1) PDIL40 Stick AT80C31X2-SLSUL ROMLess 2.7 to 5.5V Industrial & Green 30 MHz(1) PLCC44 Stick AT80C31X2-RLTUL ROMLess 2.7 to 5.5V Industrial & Green 30 MHz(1) VQFP44 Tray 40 AT/TS80C31X2 4428E–8051–02/08 AT/TS80C31X2 Part Number(3) Memory Size Supply Voltage Temperature Range Max Frequency Package AT80C31X2-3CSUV ROMLess 5V ±10% Industrial & Green 60 MHz(3) PDIL40 Stick AT80C31X2-SLSUV ROMLess 5V ±10% Industrial & Green 60 MHz(3) PLCC44 Stick AT80C31X2-RLTUV ROMLess 5V ±10% Industrial & Green 60 MHz(3) VQFP44 Tray Notes: Packing 1. 20 MHz in X2 Mode. 2. Tape and Reel available for SL, PQFP and RL packages. 3. 30 MHz in X2 Mode. 41 4428E–8051–02/08 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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