Renesas ISL9000IRGCZ Dual ldo with low noise, very high psrr and low iq Datasheet

W DESIGNS
D E D FO R N E
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N OT R
D REPLACE
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REC
ISL9000A
ISL9000
DATASHEET
FN9217
Rev 4.00
March 11, 2008
Dual LDO with Low Noise, Very High PSRR and Low IQ
ISL9000 is a high performance dual LDO capable of
sourcing 300mA current from each output. It has a low
standby current and very high PSRR and is stable with
output capacitance of 1µF to 10µF with ESR of up to 200m.
Features
The device integrates an individual Power-On-Reset (POR)
function for each output. The POR delay for VO2 can be
externally programmed by connecting a timing capacitor to
the CPOR pin. The POR delay for VO1 is internally fixed at
approximately 2ms. A reference bypass pin is also provided
for connecting a noise filtering capacitor for low noise and
high-PSRR applications.
• ±1.8% accuracy over all operating conditions
The quiescent current is typically only 42µA with both LDOs
enabled and active. Separate enable pins control each
individual LDO output. When both enable pins are low, the
device is in shutdown, typically drawing less than 0.1µA.
Several combinations of voltage outputs are standard.
Output voltage options for each LDO range are from 1.5V to
3.3V. Other output voltage options may be available upon
request.
• Integrates two 300mA high performance LDOs
• Excellent transient response to large current steps
• Excellent load regulation:
< 0.1% voltage change across full range of load current
• Low output noise: typically 30µVRMS @ 100µA (1.5V)
• Very high PSRR: 90dB @ 1kHz
• Extremely low quiescent current: 42µA (both LDOs active)
• Wide input voltage capability: 2.3V to 6.5V
• Low dropout voltage: typically 200mV @ 300mA
• Stable with 1µF to 10µF ceramic capacitors
• Separate enable and POR pins for each LDO
• Soft-start and staged turn-on to limit input current surge
during enable
• Current limit and overheat protection
Pinout
• Tiny 10 Ld 3mmx3mm DFN package
ISL9000
(10 LD 3X3 DFN)
TOP VIEW
• -40°C to +85°C operating temperature range
• Pb-free (RoHS compliant)
VIN 1
10 VO1
Applications
EN1 2
9
VO2
• PDAs, Cell Phones and Smart Phones
EN2 3
8
POR2
• Portable Instruments, MP3 Players
CBYP 4
7
POR1
• Handheld Devices including Medical Handhelds
CPOR 5
6
GND
FN9217 Rev 4.00
March 11, 2008
Page 1 of 11
ISL9000
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
VO1 VOLTAGE
(V)
VO2 VOLTAGE
(V)
TEMP RANGE (°C)
PACKAGE
(Pb-Free)
PKG DWG. #
ISL9000IRNNZ
DCGA
3.3
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRNJZ
DAAA
3.3
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRNFZ
DBAA
3.3
2.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRNCZ
DABH
3.3
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRMNZ
DCHA
3.0
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRMMZ
DSAA
3.0
3.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRMGZ
DCJA
3.0
2.7
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRLLZ
DRAA
2.9
2.9
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRKNZ
DABF
2.85
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRKKZ
DCAA
2.85
2.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRKJZ
DDAA
2.85
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRKFZ
DEAA
2.85
2.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRKPZ
DABG
2.85
1.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRKCZ
DHAA
2.85
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRJNZ
DCKA
2.8
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRJMZ
DPAA
2.8
3.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRJRZ
DNAA
2.8
2.6
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRJCZ
DMAA
2.8
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRJBZ
DFAA
2.8
1.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRGPZ
DABE
2.7
1.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRGCZ
DLAA
2.7
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRFJZ
DGAA
2.5
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRFDZ
DCLA
2.5
2.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRFCZ
DCMA
2.5
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRPLZ
DKAA
1.85
2.9
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRPPZ
DABJ
1.85
1.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRCJZ
DCNA
1.8
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRCCZ
DCPA
1.8
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRBLZ
DABD
1.5
2.9
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRBJZ
DJAA
1.5
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRBCZ
DABC
1.5
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000IRBBZ
DABB
1.5
1.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. For other output voltages, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
FN9217 Rev 4.00
March 11, 2008
Page 2 of 11
ISL9000
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V
VO1, VO2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V
Thermal Resistance (Notes 4, 5)
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
JA (°C/W)
JC (°C/W)
10 Ld 3x3 DFN Package . . . . . . . . . . .
50
10
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
CBYP = 0.01µF; CPOR = 0.01µF.
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
6.5
V
DC CHARACTERISTICS
Supply Voltage
2.3
VIN
Ground Current
Quiescent condition: IO1 = 0µA; IO2 = 0µA
IDD1
One LDO active
25
32
µA
IDD2
Both LDO active
42
52
µA
Shutdown Current
IDDS
@ +25°C
0.1
1.0
µA
UVLO Threshold
VUV+
1.9
2.1
2.3
V
VUV-
1.6
1.8
2.0
V
Regulation Voltage Accuracy
Maximum Output Current
IMAX
Internal Current Limit
ILIM
Dropout Voltage (Note 7)
Thermal Shutdown Temperature
Initial accuracy at VIN = VO + 0.5V, IO = 10mA, TJ = +25°C
-0.7
+0.7
%
VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = +25°C
-0.8
+0.8
%
VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA,
TJ = -40°C to +125°C
-1.8
+1.8
%
Continuous
300
350
mA
475
600
mA
VDO1
IO = 300mA; VO  2.5V
300
500
mV
VDO2
IO = 300mA; 2.5V  VO  2.8V
250
400
mV
VDO3
IO = 300mA; VO > 2.8V
200
325
mV
TSD+
145
°C
TSD-
110
°C
@ 1kHz
90
dB
@ 10kHz
70
dB
@ 100kHz
50
dB
IO = 100µA, VO = 1.5V, TA = +25°C, CBYP = 0.1µF
BW = 10Hz to 100kHz
30
µVRMS
AC CHARACTERISTICS
Ripple Rejection (Note 6)
Output Noise Voltage (Note 6)
IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1µF
DEVICE START-UP CHARACTERISTICS
FN9217 Rev 4.00
March 11, 2008
Page 3 of 11
ISL9000
Electrical Specifications
PARAMETER
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
CBYP = 0.01µF; CPOR = 0.01µF. (Continued)
TYP
MAX
(Note 8)
UNITS
Time from assertion of the ENx pin to when the output
voltage reaches 95% of the VO(nom)
250
500
µs
Slope of linear portion of LDO output voltage ramp during
start-up
30
60
µs/V
SYMBOL
Device Enable Time
tEN
LDO Soft-Start Ramp Rate
tSSR
MIN
(Note 8)
TEST CONDITIONS
EN1, EN2 PIN CHARACTERISTICS
Input Low Voltage
VIL
-0.3
0.5
V
Input High Voltage
VIH
1.4
VIN +
0.3
V
0.1
µA
Input Leakage Current
IIL, IIH
Pin Capacitance
CPIN
Informative
5
pF
POR1, POR2 PIN CHARACTERISTICS
POR1, POR2 Thresholds
POR1 Delay
VPOR+
As a percentage of nominal output voltage
91
94
97
%
VPOR-
87
90
93
%
tP1LH
1.0
2.0
3.0
ms
tP1HL
POR2 Delay
tP2LH
25
CPOR = 0.01µF
100
POR1, POR2 Pin Internal Pull-Up
Resistance
VOL
300
25
tP2HL
POR1, POR2 Pin Output Low
Voltage
200
µs
@IOL = 1.0mA
RPOR
78
100
ms
µs
0.2
V
180
k
NOTES:
6. Limits established by characterization and are not production tested.
7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.
8. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
EN1
EN2
tEN
VPOR+
VPOR-
VPOR+
VPOR-
<tP1HL
VO1
VO2
<tP2HL
tP1LH
tP1HL
tP2LH
tP2HL
POR1
POR2
FIGURE 1. TIMING PARAMETER DEFINITION
FN9217 Rev 4.00
March 11, 2008
Page 4 of 11
ISL9000
Typical Performance Curves
0.10
0.8
VO = 3.3V
ILOAD = 0mA
0.4
0.2
-40°C
0.0
+25°C
-0.2
+85°C
-0.4
VIN = 3.8V
VO = 3.3V
0.08
OUTPUT VOLTAGE CHANGE (%)
OUTPUT VOLTAGE, VO (%)
0.6
-0.6
0.06
0.04
-40°C
0.02
+25°C
0.00
-0.02
+85°C
-0.04
-0.06
-0.08
-0.8
3.4
3.8
4.6
4.2
5.0
5.4
5.8
6.2
-0.10
6.6
0
50
100
FIGURE 2. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V
OUTPUT)
250
300
400
350
FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
0.10
3.4
VIN = 3.8V
VO = 3.3V
ILOAD = 0mA
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
VO = 3.3V
IO = 0mA
3.3
OUTPUT VOLTAGE, VO (V)
OUTPUT VOLTAGE CHANGE (%)
200
150
LOAD CURRENT - IO (mA)
INPUT VOLTAGE (V)
3.2
IO = 150mA
3.1
IO = 300mA
3.0
2.9
-0.08
-0.10
-40
2.8
-25
5
-10
20 35 50 65
TEMPERATURE (°C)
80
95
110 125
DROPOUT VOLTAGE, VDO (mV)
OUTPUT VOLTAGE, VO (V)
2.7
IO = 150mA
2.6
IO = 300mA
2.5
2.4
3.6
4.1
4.6
5.1
5.6
6.1
INPUT VOLTAGE (V)
FIGURE 6. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V
OUTPUT)
FN9217 Rev 4.00
March 11, 2008
4.6
5.1
5.6
6.1
6.5
350
VO = 2.8V
2.8
3.1
4.1
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V
OUTPUT)
2.9
2.3
2.6
3.6
INPUT VOLTAGE (V)
FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
IO = 0mA
3.1
6.5
300
250
VO = 2.8V
200
VO = 3.3V
150
100
50
0
0
50
100
150
200
250
OUTPUT LOAD (mA)
300
350
FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT
Page 5 of 11
400
ISL9000
Typical Performance Curves
(Continued)
55
350
VO = 3.3V
50
GROUND CURRENT (µA)
DROPOUT VOLTAGE, VDO (mV)
300
250
+85°C
+25°C
-40°C
200
150
100
+125°C
+25°C
45
-40°C
40
35
VO1 = 3.3V
VO2 = 2.8V
30
50
IO(BOTH CHANNELS) = 0µA
0
0
50
100
150
200
250
OUTPUT LOAD (mA)
300
350
25
400
3.0
3.5
4.58
4.0
5.5
5.0
6.0
6.5
INPUT VOLTAGE (V)
FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
55
200
180
50
GROUND CURRENT (µA)
GROUND CURRENT (µA)
160
+25°C
140
+85°C
120
-40°C
100
80
60
40
VIN = 3.8V
VO1 = 3.3V
VO2 = 2.8V
20
0
0
50
100
150
200
250
300
45
40
35
VIN
V
IN = 3.8V
V
VO
O = 3.3V
ILOAD = 0µA
30
BOTH OUTPUTS ON
25
-40
400
350
-25
-10
5
LOAD CURRENT (mA)
FIGURE 10. GROUND CURRENT vs LOAD
VIN
VO1
3.5
2.5
3
2
95
110 125
VO2
VO1 = 3.3V
VO2 = 2.8V
IL1 = 300mA
POR1
3.0
IL2 = 300mA
VOLTAGE (V)
VOLTAGE (V)
4
80
FIGURE 11. GROUND CURRENT vs TEMPERATURE
VO1 = 3.3V
VO2 = 2.8V
IL1 = 300mA
5
20 35 50 65
TEMPERATURE (°C)
POR2
IL2 = 300mA
CPOR = 0.1µF
2.0
VO1
1.5
1
1.0
0
0.5
VO2
0
0
1
2
3
4
5
TIME (s)
6
7
8
FIGURE 12. POWER-UP/POWER-DOWN
FN9217 Rev 4.00
March 11, 2008
9
10
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME (s)
3.5
4.0
4.5
5.0
FIGURE 13. POWER-UP/POWER-DOWN WITH POR SIGNALS
Page 6 of 11
ISL9000
Typical Performance Curves
(Continued)
VO = 3.3V
ILOAD = 300mA
VO2 (10mV/DIV)
2
VO1 (V)
CLOAD = 1µF
CBYP = 0.01µF
VIN = 5.0V
VO1 = 3.3V
VO2 = 2.8V
IL1 = 300mA
IL2 = 300mA
CL1, CL2 = 1µF
CBYP = 0.01µF
3
1
4.3V
3.6V
0
VEN (V)
5
10mV/DIV
0
0
100
200
300
400
500
600
700
800
900 1000
400µs/DIV
TIME (µs)
FIGURE 14. TURN ON/TURN OFF RESPONSE
FIGURE 15. LINE TRANSIENT RESPONSE (3.3V OUTPUT)
VO = 2.8V
ILOAD = 300mA
CLOAD = 1µF
CBYP = 0.01µF
VO (25mV/DIV)
4.2V
3.5V
VO = 1.8V
VIN = 2.8V
300mA
10mV/DIV
ILOAD
100µA
100µs/DIV
400µs/DIV
FIGURE 16. LINE TRANSIENT RESPONSE (2.8V OUTPUT)
100
1000
80
CBYP = 0.1µF
70
PSRR (dB)
SPECTRAL NOISE DENSITY (nV/Hz)
VIN = 3.6V
VO = 1.8V
IO = 10mA
90
CLOAD = 1µF
60
50
40
30
20
10
0
0.1k
FIGURE 17. LOAD TRANSIENT RESPONSE
1k
10k
FREQUENCY (Hz)
100k
FIGURE 18. PSRR vs FREQUENCY
FN9217 Rev 4.00
March 11, 2008
1M
100
10
1
VIN = 3.6V
VO = 1.8V
ILOAD = 10mA
CBYP = 0.1µF
CIN = 1µF
CLOAD = 1µF
0.1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 19. SPECTRAL NOISE DENSITY vs FREQUENCY
Page 7 of 11
ISL9000
Pin Description
PIN
NUMBER
PIN
NAME
TYPE
1
VIN
Analog I/O
2
EN1
Low Voltage Compatible
CMOS Input
LDO-1 Enable.
3
EN2
Low Voltage Compatible
CMOS Input
LDO-2 Enable.
4
CBYP
Analog I/O
Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the
desired noise and PSRR performance.
5
CPOR
Analog I/O
POR2 Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR2 output release after LDO-2
output reaches 94% of its specified voltage level. (200ms delay per 0.01µF).
6
GND
Ground
7
POR1
Open Drain Output (1mA) Open-drain POR Output for LDO-1 (active-low):
Internally connected to VO1 through 100k resistor.
8
POR2
Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low):
Internally connected to VO2 through 100k resistor.
9
VO2
Analog I/O
LDO-2 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
10
VO1
Analog I/O
LDO-1 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
DESCRIPTION
Supply Voltage/LDO Input:
Connect a 1µF capacitor to GND.
GND is the connection to system ground. Connect to PCB Ground plane.
Typical Application
ISL9000
VIN (2.3 TO 6.5V)
1
ON
2
ENABLE1
OFF ON
ENABLE2
OFF
3
4
5
C1
C2
VIN
VO1
EN1
EN2
VO2
POR2
CBYP
POR1
CPOR
GND
C3
10
VOUT 1
9
VOUT 2
VOUT 2 OK
8
RESET 2
VOUT 2 TOO LOW (200ms delay,
C3 = 0.01µF)
VOUT 1 OK
7
6
C4
C5
RESET 1
VOUT 1 TOO LOW (2ms delay)
C1, C4, C5: 1µF X5R ceramic capacitor
C2: 0.1µF X7R ceramic capacitor
C3: 0.01µF X7R ceramic capacitor
FN9217 Rev 4.00
March 11, 2008
Page 8 of 11
ISL9000
Block Diagram
VIN
VO1
VO2
LDO
VO1
ERROR
AMPLIFIER
~1.0V
VO2
VREF
TRIM
IS1
POR
COMPARATOR
QEN1
VOK1
1V
POR1
LDO-1
POR2
QEN2
VO1
100k
QEN1
IS2
LDO-2
IS1
VOK2
EN1
CONTROL
LOGIC
EN2
POR2
VOK2
POR2
DELAY
CBYP
VO2
BANDGAP AND
TEMPERATURE
SENSOR
VOLTAGE
REFERENCE
GENERATOR
100k
UVLO
1.00V
VOK1
0.94V
POR1
0.90V
CPOR
Functional Description
The ISL9000 contains two high performance LDOs. High
performance is achieved through a circuit that delivers fast
transient response to varying load conditions. In a quiescent
condition, the ISL9000 adjusts its biasing to achieve the
lowest standby current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, staged turn-on and soft-start.
Smart thermal shutdown protects the device against
overheating. Staged turn-on and soft-start minimize start-up
input current surges without causing excessive device
turn-on time.
Power Control
The ISL9000 has two separate enable pins, EN1 and EN2,
to individually control power to each of the LDO outputs.
When both EN1 and EN2 are low, the device is in shutdown
FN9217 Rev 4.00
March 11, 2008
POR1
DELAY
GND
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When one or both of the enable pins are asserted, the
device first polls the output of the UVLO detector to ensure
that VIN voltage is at least about 2.1V. Once verified, the
device initiates a start-up sequence. During the start-up
sequence, trim settings are first read and latched. Then,
sequentially, the bandgap, reference voltage and current
generation circuitry power-up. Once the references are
stable, a fast-start circuit quickly charges the external
reference bypass capacitor (connected to the CBYP pin) to
the proper operating voltage. After the bypass capacitor has
been charged, the LDOs power-up in their specified
sequence.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge.
Page 9 of 11
ISL9000
If EN1 is brought high, and EN2 goes high before the VO1
output stabilizes, the ISL9000 delays the VO2 turn-on until
the VO1 output reaches its target level.
The resistor division ratio is programmed in the factory to
one of the following output voltages: 1.5V, 1.8V, 1.85V, 2.5V,
2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, and 3.3V.
If EN2 is brought high, and EN1 goes high before VO2 starts
its output ramp, then VO1 turns on first and, the ISL9000
delays the VO2 turn-on until the VO1 output reaches its
target level.
Power-On Reset Generation
If EN2 is brought high, and EN1 goes high after VO2 starts
its output ramp, then the ISL9000 immediately starts to ramp
up the VO1 output.
If both EN1 and EN2 are brought high at the same time, the
VO1 output has priority, and is always powered up first.
During operation, whenever the VIN voltage drops below
about 1.8V, the ISL9000 immediately disables both LDO
outputs. When VIN rises back above 2.1V, the device
re-initiates its start-up sequence and LDO operation will
resume automatically.
Reference Generation
The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter. The filter
includes the external capacitor connected to the CBYP pin.
A 0.01µF capacitor connected CBYP implements a 100Hz
lowpass filter, and is recommended for most high
performance applications. For the lowest noise application, a
0.1µF or greater CBYP capacitor should be used. This filters
the reference noise below the 10Hz to 1kHz frequency band,
which is crucial in many noise-sensitive applications.
The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider
provides the regulation reference, POR detection thresholds,
and other voltage references required for current generation
and over-temperature detection.
The current generator provides the references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9000 provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200m. The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not normally needed as LDO
performance improvement is minimal.
Each LDO uses an independently trimmed 1V reference. An
internal resistor divider drops the LDO output voltage down
to 1V. This is compared to the 1V reference for regulation.
FN9217 Rev 4.00
March 11, 2008
Each LDO has a separate Power-on Reset signal generation
circuit which outputs to the respective POR pins. The POR
signal is generated as follows:
A POR comparator continuously monitors the output of each
LDO. The LDO enters a power-good state when the output
voltage is above 94% of the expected output voltage for a
period exceeding the LDO PGOOD entry delay time (see the
following). In the power-good state, the open-drain PORx
output is in a high-impedance state. An internal 100k
pull-up resistor pulls the pin up to the respective LDO output
voltage. An external resistor can be added between the
PORx output and the LDO output for a faster rise time,
however, the PORx output should not connect through an
external resistor to a supply greater than the associated
LDO voltage.
The power-good state is exited when the LDO output falls
below 90% of the expected output voltage for a period longer
than the PGOOD exit delay time. While power-good is false,
the ISL9000 pulls the respective POR pin low.
For LDO-1, the PGOOD entry delay time is fixed at about
2ms while the PGOOD exit delay is about 25µs. For LDO-2,
the PGOOD entry and exit delays are determined by the
value of the external capacitor connected to the CPOR pin.
For a 0.01µF capacitor, the entry and exit delays are 200ms
and 25µs respectively. Larger or smaller capacitor values will
yield proportionately longer or shorter delay times. The POR
exit delay should never be allowed to be less than 10µs to
ensure sufficient immunity against transient induced false
POR triggering.
Overheat Detection
The bandgap provides a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +145°C, one or both of the
LDOs momentarily shut down until the die cools sufficiently.
In the overheat condition, only the LDO sourcing more than
50mA will be shut off. This does not affect the operation of
the other LDO. If both LDOs source more than 50mA and an
overheat condition occurs, both LDO outputs are disabled.
Once the die temperature falls back below about +110°C,
the disabled LDO(s) are re-enabled and soft-start
automatically takes place.
The ISL9000 provides short-circuit protection by limiting the
output current to about 475mA. If short circuited, an output
current of 475mA will cause die heating. If the short circuit
lasts long enough, the overheat detection circuit will turn off
the output.
Page 10 of 11
ISL9000
Dual Flat No-Lead Plastic Package (DFN)
L10.3x3C
2X
0.10 C A
A
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
E
NOMINAL
MAX
NOTES
A
0.85
0.90
0.95
-
A1
-
-
0.05
-
b
B
D2
//
A
C
SEATING
PLANE
0.10 C
D2
0.08 C
7
8
D2/2
1
0.20
0.25
0.30
5, 8
3.00 BSC
2.33
E
E2
A3
SIDE VIEW
(DATUM B)
0.20 REF
D
TOP VIEW
2.38
2.43
7, 8
1.69
7, 8
3.00 BSC
1.59
e
1.64
-
0.50 BSC
-
k
0.20
-
-
-
L
0.35
0.40
0.45
8
N
10
2
Nd
5
3
Rev. 1 4/06
2
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k
2. N is the number of terminals.
(DATUM A)
3. Nd refers to the number of terminals on D.
E2
E2/2
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
NX L
N
8
MIN
A3
6
INDEX
AREA
6
INDEX
AREA
SYMBOL
N-1
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
0.10 M C A B
(A1)
9 L
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
CL
NX (b)
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN9217 Rev 4.00
March 11, 2008
Page 11 of 11