FEATURES TYPICAL APPLICATION CIRCUIT NEUTRAL PHASE PHASE PHASE B A C ISOLATION BARRIER 3.3V V1P VM IM PHASE A IP ADE7912/ ADE7913 V2P GNDISO_A GNDMCU 3.3V V1P VM 3.3V IM PHASE B ADE7912/ ADE7913 IP V2P GNDISO_B GNDMCU 3.3V V1P VM APPLICATIONS IM PHASE C IP ADE7912/ ADE7913 GNDMCU V2P GNDISO_C GNDMCU 3.3V V1P VM NEUTRAL LINE IM ADE7903 IP LOAD V2P GNDMCU 12458-001 3-phase shunt-based polyphase meters with neutral channel measurement Single-phase meters Power quality monitoring Solar inverters Process monitoring Standalone ADCs Protective devices Isolated sensor interfaces Industrial programmable logic controllers (PLCs) SYSTEM MICROCONTROLLER One (ADE7903) 24-bit, Σ-Δ ADC (simultaneously sampling with three ADE7912/ADE7913 ADCs) On-chip temperature sensor 4-wire SPI serial interface Standalone 24-bit, Σ-Δ ADC Up to four ADE7903 and ADE7912/ADE7913 devices clocked from a single crystal or an external clock Synchronization of multiple ADE7903 and ADE7912/ADE7913 devices ±31.25 mV peak input range for current channel ±500 mV peak input range for voltage channels Single 3.3 V supply 20-lead, wide body SOIC package Operating temperature: −40°C to +85°C SPI INTERFACE Data Sheet 3-Channel, Sigma-Delta ADC with SPI ADE7903 Figure 1. GENERAL DESCRIPTION The ADE7903 is a nonisolated, 3-channel, Σ-Δ analog-to-digital converter (ADC) for the neutral line of polyphase energy metering applications using shunt current sensors. The ADE7903 can also be used for single-phase energy metering and other standalone ADC applications. The ADE7903 features three 24-bit ADCs. The current ADC provides a 67 dBFS signal-to-noise ratio (SNR) over a 3.3 kHz signal bandwidth, whereas the voltage ADCs provide an SNR of 72 dBFS over the same bandwidth. One channel is dedicated to measuring the voltage across a shunt when the shunt is used for current sensing. Up to two additional channels are dedicated to measuring voltages, which are usually sensed using resistor dividers. One voltage channel can be used to measure the temperature of the die via an internal sensor. The ADE7903 includes three channels: one current channel and two voltage channels. Together with the ADE7912/ADE7913, the ADE7903 provides a small form factor, 3-phase isolated solution with a neutral Rev. 0 measurement. The three phases are isolated with ADE7912/ ADE7913 devices, while the neutral line is not isolated with the ADE7903. The ADE7903 configuration and status registers are accessed via a bidirectional SPI serial port for easy interfacing with microcontrollers. The ADE7903 can be clocked from a crystal or an external clock signal. To minimize the system bill of materials, the master ADE7912/ADE7913 can drive the clocks of up to three additional ADE7912/ADE7913 or ADE7903 devices. Multiple ADE7912/ADE7913 and ADE7903 devices can be synchronized to sample at the same moment and provide coherent outputs. The ADE7903 can also be used individually as a standalone ADC. The ADE7903 is available in a 20-lead, Pb-free, wide body SOIC package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADE7903 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Protecting the Integrity of Configuration Registers .............. 17 Applications ....................................................................................... 1 CRC of Configuration Registers............................................... 17 Typical Application Circuit ............................................................. 1 ADE7903 Status .......................................................................... 17 General Description ......................................................................... 1 Applications Information .............................................................. 18 Revision History ............................................................................... 2 ADE7903 in Polyphase Energy Meters ................................... 18 Functional Block Diagram .............................................................. 3 ADE7903 in Single-Phase Energy Meters ............................... 19 Specifications..................................................................................... 4 ADE7903 Clock .......................................................................... 20 Timing Characteristics ................................................................ 6 SPI-Compatible Interface .......................................................... 20 Absolute Maximum Ratings ............................................................ 7 Thermal Resistance ...................................................................... 7 Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices....................................................................... 22 ESD Caution .................................................................................. 7 Power Management ........................................................................ 23 Pin Configuration and Function Descriptions ............................. 8 Power-Up and Initialization Procedures ................................. 23 Typical Performance Characteristics ............................................. 9 Hardware Reset ........................................................................... 24 Test Circuit ...................................................................................... 11 Software Reset ............................................................................. 24 Terminology .................................................................................... 12 Power-Down Mode .................................................................... 24 Theory of Operation ...................................................................... 14 Layout Guidelines ........................................................................... 25 Analog Inputs .............................................................................. 14 ADE7903 Evaluation Board ...................................................... 25 Analog-to-Digital Conversion .................................................. 14 ADE7903 Version ....................................................................... 25 Reference Circuit ........................................................................ 16 Register List ..................................................................................... 26 CRC of ADC Output Values ..................................................... 16 Outline Dimensions ....................................................................... 28 Temperature Sensor ................................................................... 16 Ordering Guide .......................................................................... 28 REVISION HISTORY 12/14—Revision 0: Initial Version Rev. 0 | Page 2 of 28 Data Sheet ADE7903 FUNCTIONAL BLOCK DIAGRAM GND LDO V2P VM V1P IM IP REF GND 1 ADE7903 19 2 8 3 5 4 20 VDD GND LDO TEMPERATURE SENSOR 18 ADC DIGITAL BLOCK AND SPI PORT ADC 6 17 16 15 14 7 ADC 9 VOLTAGE REFERENCE 13 10 Figure 2. Rev. 0 | Page 3 of 28 CS SCLK MOSI MISO XTAL2 XTAL1 12 CLKOUT/ DREADY 11 GND 12458-002 VDD ADE7903 Data Sheet SPECIFICATIONS VDD = 3.3 V ± 10%, GND = 0 V, on-chip reference, XTAL1 = 4.096 MHz, TMIN to TMAX = −40°C to +85°C, TA = 25°C (typical), unless otherwise noted. Table 1. Parameter ANALOG INPUTS 1 Pseudo Differential Signal Voltage Range Between IP and IM Pins Pseudo Differential Signal Voltage Range Between V1P and VM Pins and Between V2P and VM Pins Maximum VM and IM Voltage Crosstalk Input Impedance to Ground (DC) IP, IM, V1P, and V2P Pins VM Pin Current Channel ADC Offset Error Voltage Channels ADC Offset Error ADC Offset Drift over Temperature Gain Error Gain Drift over Temperature Min Typ Max Unit Test Conditions/Comments −31.25 +31.25 mV peak IM pin connected to GND −500 +500 mV peak Pseudo differential inputs between V1P and VM pins and between V2P and VM pins; VM pin connected to GND +25 −90 mV dB −105 dB IP and IM inputs set to 0 V (GND) when V1P and V2P inputs at full scale V2P and VM inputs set to 0 V (GND) when IP and V1P inputs at full scale; V1P and VM inputs set to 0 V (GND) when IP and V2P inputs at full scale V1 channel only −25 AC Power Supply Rejection, PSR −90 kΩ kΩ mV mV ppm/°C % ppm/°C ppm/°C dB DC Power Supply Rejection, PSR −80 dB ±5 °C 67 68 72 74 66 68 72 73 −79 −78 −82 −82 83 83 85 85 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS TEMPERATURE SENSOR Accuracy WAVEFORM SAMPLING—CURRENT CHANNEL1 Signal-to-Noise Ratio, SNR Signal-to-Noise-and-Distortion Ratio, SINAD Total Harmonic Distortion, THD Spurious-Free Dynamic Range, SFDR 480 240 −2 −35 ±200 −4 −135 −85 +4 +135 +85 Rev. 0 | Page 4 of 28 Current channel V1 and V2 channels VDD = 3.3 V + 120 mV rms (50 Hz/100 Hz), IP = V1P = V2P = GND VDD = 3.3 V ± 330 mV dc, IP = 6.25 mV rms, V1P = V2P = 100 mV rms ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz Data Sheet Parameter VOLTAGE CHANNELS1 Signal-to-Noise Ratio, SNR ADE7903 Min Total Harmonic Distortion, THD Spurious-Free Dynamic Range, SFDR Supply Current (IDD) 5 Max 72 74 77 79 72 74 77 78 −83 −83 −85 −85 86 86 87 87 Signal-to-Noise-and-Distortion Ratio, SINAD CLKIN 2 Input Clock Frequency CLKIN Duty Cycle XTAL1 Logic Inputs Input High Voltage, VINH Input Low Voltage, VINL XTAL1 Total Capacitance 3 XTAL2 Total Capacitance3 CLKOUT Delay from XTAL1 4 LOGIC INPUTS—MOSI, SCLK, CS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS—CLKOUT/DREADY AND MISO Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY VDD Pin Typ 3.6 45 4.096 50 4.21 55 2.4 ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz All specifications for CLKIN = 4.096 MHz MHz % 0.8 1 10 V V µA pF 0.4 V V 3.63 V 6.2 mA mA 2.4 2.5 5.1 2 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 100 40 40 2.97 Test Conditions/Comments V V pF pF ns 0.8 0.015 Unit ISOURCE = 800 µA ISINK = 2 mA For specified performance Minimum = 3.3 V − 10%; maximum = 3.3 V + 10% No CLKIN signal at XTAL1 pin See the Terminology section for a definition of the parameters. CLKIN is the internal clock of the ADE7903. It is the frequency at which the device is clocked at the XTAL1 pin. XTAL1/XTAL2 total capacitances refer to the net capacitances on each pin. Each capacitance is the sum of the parasitic capacitance at the pin and the capacitance of the ceramic capacitor connected between the pin and GND. See the ADE7903 Clock section for more details. 4 CLKOUT delay from XTAL1 is the delay that occurs from a high to low transition at the XTAL1 pin to a synchronous high to low transition at the CLKOUT/DREADY pin when CLKOUT functionality is enabled. 5 Supply current specified with the two VDD pins connected externally from the same power supply (see the Pin Configuration and Function Descriptions section). 1 2 3 Rev. 0 | Page 5 of 28 ADE7903 Data Sheet TIMING CHARACTERISTICS VDD = 3.3 V ± 10%, GND = 0 V, on-chip reference, CLKIN = 4.096 MHz, TMIN to TMAX = −40°C to +85°C. Table 2. SPI Interface Timing Parameters Parameter CS to SCLK Positive Edge SCLK Frequency 1 SCLK Low Pulse Width SCLK High Pulse Width Data Output Valid After SCLK Edge Data Input Setup Time Before SCLK Edge Data Input Hold Time After SCLK Edge Data Output Fall Time Data Output Rise Time SCLK Rise Time SCLK Fall Time MISO Disable After CS Rising Edge CS High After SCLK Edge Min 50 250 80 80 tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDIS tSFS Max 5600 80 70 20 20 20 20 20 40 5 0 Minimum and maximum specifications are guaranteed by design. CS tSS tSFS SCLK tSL tSH tDAV tSR tSF tDIS MSB MISO INTERMEDIATE BITS LSB tDF tDR INTERMEDIATE BITS MSB IN MOSI LSB IN 12458-003 tDSU tDHD Figure 3. SPI Interface Timing 2mA TO OUTPUT PIN IOL 1.6V CL 50pF 800µA IOH 12458-004 1 Symbol tSS Figure 4. Load Circuit for Timing Specifications Rev. 0 | Page 6 of 28 Unit ns kHz ns ns ns ns ns ns ns ns ns ns ns Data Sheet ADE7903 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA and θJC are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter VDD to GND Analog Input Voltage to GND, IP, IM, V1P, V2P, VM Reference Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Operating Temperature Industrial Range Storage Temperature Range Lead Temperature (Soldering, 10 sec)1 1 Rating −0.3 V to +3.7 V −2 V to +2 V Table 4. Thermal Resistance −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V Package Type 20-Lead SOIC_W ESD CAUTION −40°C to +85°C −65°C to +150°C 260°C Analog Devices, Inc., recommends that reflow profiles used in soldering RoHS compliant devices conform to J-STD-020D.1 from JEDEC. Refer to JEDEC for the latest revision of this standard. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 7 of 28 θJA 79 θJC 24.7 Unit °C/W ADE7903 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 20 GND GND 2 19 VDD V1P 4 ADE7903 17 SCLK VM 5 TOP VIEW (Not to Scale) 16 MOSI IM 6 15 MISO IP 7 14 XTAL2 LDO 8 13 XTAL1 REF 9 12 CLKOUT/DREADY GND 10 11 GND 12458-005 18 CS V2P 3 Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 19 Mnemonic VDD 2, 10, 11, 20 3, 4, 5 GND V2P, V1P, VM 6, 7 IM, IP 8 LDO 9 REF 12 CLKOUT/DREADY 13 XTAL1 14 XTAL2 15 16 17 MISO MOSI SCLK 18 CS Description Supply Voltage. These pins provide the supply voltage for the ADE7903. Maintain the supply voltage at 3.3 V ± 10% for specified operation. Decouple each VDD pin to GND with a ceramic 100 nF capacitor and a single 10 µF capacitor in parallel. Connect the VDD pins externally. Ground Reference. Connect the GND pins externally. Analog Inputs for the Voltage Channels. The voltage channels are used with the voltage transducers. V2P and V1P are pseudo differential voltage inputs with a maximum signal level of ±500 mV with respect to VM for specified operation. Use these pins with the related input circuitry, as shown in Figure 18. If V1P or V2P is not used, connect it to the VM pin. Analog Inputs for the Current Channel. The current channel is used with shunts. IM and IP are pseudo differential voltage inputs with a maximum differential level of ±31.25 mV. Use these pins with the related input circuitry, as shown in Figure 18. 2.5 V Output of the Analog Low Dropout (LDO) Regulator. Decouple this pin with a 4.7 µF capacitor in parallel with a ceramic 100 nF capacitor to GND. Do not connect external load circuitry to this pin. Voltage Reference. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.2 V. Decouple this pin to GND with a 4.7 µF capacitor in parallel with a ceramic 100 nF capacitor. Clock Output (CLKOUT). When CLKOUT functionality is selected (see the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for details), the ADE7903 generates a digital signal synchronous to the master clock at the XTAL1 pin. Use CLKOUT to provide a clock to other ADE7912/ ADE7913 and ADE7903 devices on the board. Data Ready, Active Low (DREADY). When the DREADY functionality is selected (see the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for details), the ADE7903 generates an active low signal synchronous to the ADC output frequency. Use this signal to start reading the ADC outputs of the ADE7903. Master Clock Input. An external clock can be provided at this logic input. The CLKOUT/DREADY signal of another appropriately configured ADE7903 (see the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for details) can be provided at this pin. Alternatively, a crystal with a maximum drive level of 0.5 mW and an equivalent series resistance (ESR) of 20 Ω can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE7903. The clock frequency for specified operation is 4.096 MHz, but lower frequencies down to 3.6 MHz can be used. See the ADE7903 Clock section for more details. Crystal, Second Input. A crystal with a maximum drive level of 0.5 mW and an ESR of 20 Ω can be connected across XTAL2 and XTAL1 to provide a clock source for the ADE7903. Data Output for SPI Port. Pull up this pin with a 10 kΩ resistor (see the ADE7903 Clock section for details). Data Input for SPI Port. Serial Clock Input for SPI Port. All serial data transfers are synchronized to this clock (see the ADE7903 Clock section). Chip Select for SPI Port. Rev. 0 | Page 8 of 28 Data Sheet ADE7903 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 –20 –40 AMPLITUDE (dB) –60 –80 –100 –120 –100 –120 –160 –160 0 500 1000 1500 2000 2500 3000 3500 4000 4500 FREQUENCY (Hz) Figure 6. Current Channel Fast Fourier Transform (FFT), ±31.25 mV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz 0 –180 0 500 1000 1500 2000 2500 3000 3500 4000 4500 FREQUENCY (Hz) Figure 9. Voltage Channel V1 FFT, ±500 µV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz 0 SNR = 6.43dB THD = –36.07dB SINAD = 6.43dB SFDR = 41.28dB –20 SNR = 74.99dB THD = –79.47dB SINAD = 73.66dB SFDR = 79.561dB –20 –40 AMPLITUDE (dB) –40 –60 –80 –100 –120 –60 –80 –100 –120 –140 –140 0 500 1000 1500 2000 2500 3000 3500 4000 4500 FREQUENCY (Hz) –180 12458-007 –160 Figure 7. Current Channel FFT, ±31.25 µV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz 0 500 1000 1500 2000 2500 3000 0 SNR = 75.11dB THD = –79.55dB SINAD = 73.78dB SFDR = 79.62dB –40 –40 AMPLITUDE (dB) –80 –100 –120 –60 –80 –100 –120 –140 –140 –160 –160 0 500 1000 1500 2000 2500 3000 FREQUENCY (Hz) 3500 4000 4500 –180 12458-008 –180 Figure 8. Voltage Channel V1 FFT, ±500 mV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz 4500 SNR = 15.27dB THD = –45.83dB SINAD = 15.27dB SFDR = 53.59dB –20 –60 4000 Figure 10. Voltage Channel V2 FFT, ±500 mV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz 0 –20 3500 FREQUENCY (Hz) 12458-010 –160 0 500 1000 1500 2000 2500 3000 FREQUENCY (Hz) 3500 4000 4500 12458-011 AMPLITUDE (dB) –80 –140 –180 AMPLITUDE (dB) –60 –140 12458-006 AMPLITUDE (dB) –40 SNR = 15.32dB THD = –47.02dB SINAD = 15.32dB SFDR = 53.71dB –20 12458-009 SNR = 66.55dB THD = –88.71dB SINAD = 66.53dB SFDR = 91.2dB Figure 11. Voltage Channel V2 FFT, ±500 µV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz Rev. 0 | Page 9 of 28 Data Sheet 100 100 90 90 PERCENTAGE OF DISTRIBUTION (%) 80 70 60 50 40 30 20 –80 –60 –40 –20 0 20 40 60 80 100 TEMPERATURE COEFFICIENT (ppm/°C) 50 40 30 20 0 –100 100 90 90 70 60 50 40 30 20 –20 0 20 40 60 80 100 80 70 60 50 40 30 20 10 –60 –40 –20 0 20 40 60 80 100 0 –100 12458-013 –80 TEMPERATURE COEFFICIENT (ppm/°C) Figure 13. Cumulative Histogram of the Current Channel ADC Gain Temperature Coefficient for Temperatures Between 25°C and 85°C –80 –60 –40 –20 0 20 40 60 80 100 TEMPERATURE COEFFICIENT (ppm/°C) Figure 16. Cumulative Histogram of the Voltage Channel V2 ADC Gain Temperature Coefficient for Temperatures Between −40°C and +25°C 100 90 90 PERCENTAGE OF DISTRIBUTION (%) 100 80 70 60 50 40 30 20 10 80 70 60 50 40 30 20 10 –80 –60 –40 –20 0 20 40 60 TEMPERATURE COEFFICIENT (ppm/°C) 80 100 0 –100 12458-014 0 –100 –40 12458-016 10 0 –100 –60 Figure 15. Cumulative Histogram of the Voltage Channel V1 ADC Gain Temperature Coefficient for Temperatures Between 25°C and 85°C 100 80 –80 TEMPERATURE COEFFICIENT (ppm/°C) PERCENTAGE OF DISTRIBUTION (%) PERCENTAGE OF DISTRIBUTION (%) Figure 12. Cumulative Histogram of the Current Channel ADC Gain Temperature Coefficient for Temperatures Between −40°C and +25°C PERCENTAGE OF DISTRIBUTION (%) 60 10 12458-012 0 –100 70 12458-015 10 80 Figure 14. Cumulative Histogram of the Voltage Channel V1 ADC Gain Temperature Coefficient for Temperatures Between −40°C and +25°C –80 –60 –40 –20 0 20 40 60 TEMPERATURE COEFFICIENT (ppm/°C) 80 100 12458-017 PERCENTAGE OF DISTRIBUTION (%) ADE7903 Figure 17. Cumulative Histogram of the Voltage Channel V2 ADC Gain Temperature Coefficient for Temperatures Between 25°C and 85°C Rev. 0 | Page 10 of 28 Data Sheet ADE7903 TEST CIRCUIT 1 10µF 150Ω FERRITE 100nF 1kΩ TP3 150Ω FERRITE 7 33nF 150Ω FERRITE TP5 6 TP2 330kΩ 330kΩ 1kΩ 1kΩ XTAL2 14 IP VDD GND V1P TS4148 33nF TS4148 5 33nF 3.3V 20 100nF 4.096MHz 10µF 22pF 22pF IM 1kΩ 4 19 ADE7912A/ ADE7913A CS 18 TO MCU MISO 15 MOSI 16 VM TS4148 330kΩ 330kΩ TS4148 3 330kΩ SCLK V2P 8 1kΩ 33nF 4.7µF 4.7µF 100nF 100nF SAME AS IN ADE7912 A/ ADE7913 A LDO 10 9 CLKOUT/DREADY GNDISO GND REF 12 18 3 15 4 16 ADE7912B/ ADE7913B 5 6 17 19 7 13 8 14 9 11 10 20 1 2 12 18 15 16 5 6 7 19 13 9 14 11 10 20 1 2 7 6 4 5 3 8 4.7µF 4.7µF 100nF 100nF 10 9 VDD VDD GND GND GND IP IM ADE7903N V1P VM 10kΩ TO MCU TO MCU TO MCU SAME AS IN ADE7912 A/ ADE7913 A TO MCU TO MCU TO MCU 17 ADE7912C/ ADE7913C 8 SAME AS IN ADE7912 A/ ADE7913 A 11 1 2 4 100nF 12 3.3V 3 SAME AS IN ADE7912 A/ ADE7913 A 17 CS MISO MOSI V2P SCLK LDO XTAL1 GND XTAL2 REF CLKOUT/DREADY 19 3.3V 20 100nF Rev. 0 | Page 11 of 28 10µF 11 18 TO MCU 15 16 17 13 14 12 NOTES 1. ADE7912 X/ADE7913 X = PHASE X ADE7912/ADE7913, WHERE X = A, B, OR C. Figure 18. Test Circuit SAME AS IN ADE7912 A/ ADE7913 A 12458-018 TP4 XTAL1 13 GNDISO TS4148 150Ω FERRITE 330kΩ VDDISO 33nF TP1 150Ω FERRITE 2 ADE7903 Data Sheet TERMINOLOGY Pseudo Differential Signal Voltage Range Between IP and IM, V1P and VM, and V2P and VM Pins This range represents the peak-to-peak pseudo differential voltage that must be applied to the ADCs to generate a full-scale response when the IM and VM pins are connected to GND. The IM and VM pins are connected to GND using antialiasing filters (see Figure 18). Figure 19 illustrates the input voltage range between IP and IM. Figure 20 illustrates the input voltage range between V1P and VM and between V2P and VM. +31.25mV IP 0V –31.25mV IM 0V IP – IM Input Impedance to Ground (DC) The input impedance to ground represents the impedance measured at each ADC input pin (IP, IM, V1P, V2P, and VM) with respect to GND. +31.25mV –31.25mV 12458-019 0V Figure 19. Pseudo Differential Input Voltage Range Between IP and IM Pins +500mV ADC Offset Error ADC offset error is the difference between the average measured ADC output code with both inputs connected to GND and the ideal ADC output code. The magnitude of the offset depends on the input range of each channel. ADC Offset Drift over Temperature The ADC offset drift is the change in offset over temperature. It is measured at −40°C, +25°C, and +85°C. The offset drift over temperature is computed as follows: V1P, V2P 0V Drift = –500mV VM Crosstalk Crosstalk represents leakage of signals, usually via capacitance between circuits. Crosstalk is measured in the current channel by setting the IP and IM pins to GND, supplying a full-scale alternate differential voltage between the V1P and VM pins and between the V2P and VM pins of the voltage channel, and measuring the output of the current channel. It is measured in the V1P voltage channel by setting the V1P and VM pins to GND, supplying a full-scale alternate differential voltage at the IP and V2P pins, and measuring the output of the V1P channel. Crosstalk is measured in the V2P voltage channel by setting the V2P and VM pins to GND, supplying a full-scale alternate differential voltage at the IP and V1P pins, and measuring the output of the V2P channel. The crosstalk is equal to the ratio between the grounded ADC output value and its ADC full-scale output value. The ADC outputs are acquired for 2 sec. Crosstalk is expressed in decibels. Offset (−40 ) − Offset (25) Offset (85) − Offset (25) max , Offset (25) × (−40 − 25) Offset (25) × (85 − 25) 0V V1P – VM, V2P – VM +500mV Offset drift is expressed in ppm/°C. –500mV 12458-020 0V Figure 20. Pseudo Differential Input Voltage Range Between V1P and VM Pins and Between V2P and VM Pins Maximum VM and IM Voltage Range This range represents the maximum allowed voltage at the VM and IM pins relative to GND. Gain Error The gain error in the ADCs represents the difference between the measured ADC output code (minus the offset) and the ideal output code when the internal voltage reference is used (see the Analog-to-Digital Conversion section). The difference is expressed as a percentage of the ideal code. It represents the overall gain error of one current or voltage channel. Rev. 0 | Page 12 of 28 Data Sheet ADE7903 Gain Drift over Temperature This temperature coefficient includes the temperature variation of the ADC gain and of the internal voltage reference. It represents the overall temperature coefficient of one current or voltage channel. With the internal voltage reference in use, the ADC gain is measured at −40°C, +25°C, and +85°C. Then, the temperature coefficient is computed as follows: Gain (−40 ) − Gain (25) Gain (85) − Gain (25) Drift = max , Gain (25) × (− 40 − 25) Gain (25) × (85 − 25) Gain drift is measured in ppm/°C. Power Supply Rejection (PSR) PSR quantifies the measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken when the voltage at the input pins is 0 V. A second reading is obtained with the same input signal levels when an ac signal (120 mV rms at 50 Hz or 100 Hz) is introduced onto the supply. Any error introduced by this ac signal is expressed as a percentage of the reading (power supply rejection ratio, PSRR). PSR = 20log10 (PSRR). For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken when the voltage between the IP and IM pins is 6.25 mV rms, and the voltages between the V1P and VM pins and between the V2P and VM pins are 100 mV rms. A second reading is obtained with the same input signal levels when the power supplies are varied by ±10%. Any error introduced is expressed as a percentage of the reading (PSRR). Then PSR = 20log10 (PSRR). Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The spectral components are calculated over a 2 sec window. The value for SNR is expressed in decibels relative to full scale (dBFS). Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The spectral components are calculated over a 2 sec window. The value for SINAD is expressed in decibels relative to full scale (dBFS). Total Harmonic Distortion (THD) THD is the ratio of the rms sum of all harmonics (excluding the noise components) to the rms value of the fundamental. The spectral components are calculated over a 2 sec window. The value for THD is expressed in decibels relative to full scale (dBFS). Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the rms value of the actual input signal to the rms value of the peak spurious component over the measurement bandwidth of the waveform samples. The spectral components are calculated over a 2 sec window. The value of SFDR is expressed in decibels relative to full scale (dBFS). Rev. 0 | Page 13 of 28 ADE7903 Data Sheet THEORY OF OPERATION ANALOG INPUTS The ADE7903 has three analog inputs: one current channel and two voltage channels. The current channel has two fully differential voltage input pins, IP and IM, that accept a maximum differential signal of ±31.25 mV. The maximum VIP signal level is also ±31.25 mV. The maximum VIM signal level allowed at the IM input is ±25 mV. Figure 21 shows a schematic of the input for the current channel and its relation to the maximum IM pin voltage. VIP = ±31.25mV MAX PEAK VIM = ±25mV MAX VIP +31.25mV VIP IP 0V 12458-021 IM VIM –31.25mV Figure 21. Maximum Input Level, Current Channel Note that the current channel is used to sense the voltage across a shunt. In this case, one pole of the shunt becomes the ground of the meter (see Figure 28) and, therefore, the current channel is used in a pseudo differential configuration, similar to the voltage channel configuration (see Figure 22). The voltage channel has two pseudo differential, single-ended voltage input pins: V1P and V2P. These single-ended voltage inputs have a maximum input voltage of ±500 mV with respect to VM. The maximum signal allowed at the VM input is ±25 mV. Figure 22 shows a schematic of the voltage channel inputs and their relation to the maximum VM voltage. A Σ-Δ modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. In the ADE7903, the sampling clock is equal to CLKIN/4 (1.024 MHz when CLKIN = 4.096 MHz). The 1-bit digital-toanalog converter (DAC) in the feedback loop is driven by the serial stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC output (and, therefore, the bit stream) can approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. A meaningful result is obtained only when a large number of samples is averaged. This averaging is completed in the second part of the ADC, the digital low-pass filter, after the data is passed through the digital isolators. By averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit data-words that are proportional to the input signal level. The Σ-Δ converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first technique is oversampling. Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. For example, when CLKIN = 4.096 MHz, the sampling rate in the ADE7903 is 1.024 MHz, and the bandwidth of interest is 40 Hz to 3.3 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the bandwidth of interest is lowered, as shown in Figure 24. ANTIALIAS FILTER (RC) V1 = ±500mV MAX PEAK VM = ±25mV MAX V1 +500mV V1 DIGITAL FILTER SIGNAL V1P OR V2P SHAPED NOISE SAMPLING FREQUENCY NOISE 0V VM 0 12458-022 The ADE7903 has three second-order Σ-Δ ADCs. For simplicity, the block diagram in Figure 23 shows a first-order Σ-Δ ADC. The converter is composed of the Σ-Δ modulator and the digital low-pass filter (LPF). C 0 + + – – 24 VREF .....10100101..... 1-BIT DAC Figure 23. First-Order Σ-Δ ADC 3.3 4 512 FREQUENCY (kHz) 1024 Figure 24. Noise Reduction Due to Oversampling and Noise Shaping in the Analog Modulator DIGITAL LOW-PASS FILTER 12458-023 R NOISE CLKIN/4 LATCHED COMPARATOR 1024 SIGNAL ANALOG-TO-DIGITAL CONVERSION INTEGRATOR 512 FREQUENCY (kHz) HIGH RESOLUTION OUTPUT FROM DIGITAL LPF Figure 22. Maximum Input Level, Voltage Channels ANALOG LOW-PASS FILTER 3.3 4 12458-024 VM –500mV However, oversampling alone is not sufficient to improve the SNR in the band of interest. For example, an oversampling factor of four is required to increase the SNR by a mere 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. Noise shaping is the second technique used to achieve high resolution. In the Σ-Δ modulator, Rev. 0 | Page 14 of 28 Data Sheet ADE7903 The bandwidth of interest is a function of the input clock frequency, the ADC output frequency (selectable by Bits[5:4] (ADC_FREQ) in the CONFIG register; see the ADC Output Values section for details), and Bit 7 (BW) of the CONFIG register. When CLKIN is 4.096 MHz and the ADC output frequency is 8 kHz, if BW is cleared to 0 (the default value), the ADC bandwidth is 3.3 kHz. If BW is set to 1, the ADC bandwidth is 2 kHz. Table 6 shows the ADC output frequencies and the ADC bandwidth as a function of the input clock (CLKIN) frequency. Three cases are shown: one for CLKIN = 4.096 MHz, the typical clock input frequency value; one for CLKIN = 4.21 MHz, the maximum clock input frequency; and one for CLKIN = 3.6 MHz, the minimum clock input frequency. Antialiasing Filter Figure 23 also shows an analog low-pass filter (RC) on the input to the ADC. This filter is placed outside the ADE7903, and its role is to prevent aliasing. Aliasing is an artifact of all sampled systems, as shown in Figure 25. Aliasing refers to the frequency components in the input signal to the ADC that are higher than half the sampling rate of the ADC and appear in the sampled signal at a frequency below half the sampling rate. Frequency components above half the sampling frequency (also known as the Nyquist frequency, that is, 512 kHz) are imaged or folded back down below 512 kHz. This folding happens with all ADCs, regardless of the architecture. In Figure 25, only frequencies near the sampling frequency of 1.024 MHz move into the bandwidth of interest for metering, that is, 40 Hz to 3.3 kHz or 40 Hz to 2 kHz. To attenuate the high frequency noise (near 1.024 MHz) and prevent the distortion of the bandwidth of interest, a low-pass filter must be introduced. It is recommended that one RC filter with a corner frequency of 5 kHz be used for the attenuation to be sufficiently high at the sampling frequency of 1.024 MHz. The 20 dB per decade attenuation of this filter is usually sufficient to eliminate the effects of aliasing. ALIASING EFFECTS 0 2 4 512 FREQUENCY (kHz) IMAGE FREQUENCIES SAMPLING FREQUENCY 1024 12458-025 the noise is shaped by the integrator, which has a high-pass type response for the quantization noise. The result is that most of the noise is at higher frequencies where it can be removed by the digital low-pass filter. This noise shaping is shown in Figure 24. Figure 25. Aliasing Effects ADC Transfer Function All ADCs in the ADE7903 produce 24-bit signed output codes. With a full-scale input signal of 31.25 mV on the current channel and 0.5 V on the voltage channels, and with an internal reference of 1.2 V, the ADC output code is nominally 5,320,000 and usually varies for each ADE7903 around this value. The code from the ADC can vary between 0x800000 (−8,388,608) and 0x7FFFFF (+8,388,607), which is equivalent to an input signal level of ±49.27 mV on the current channel and ±0.788 V on the voltage channels. However, for specified performance, do not exceed the nominal range of ±31.25 mV for the current channel and ±500 mV for the voltage channels; ADC performance is guaranteed only for input signals within these limits. ADC Output Values The ADC output values are stored in three 24-bit signed registers, IWV, V1WV, and V2WV, at a rate defined by Bits[5:4] (ADC_FREQ) in the CONFIG register. The output frequency is 8 kHz (CLKIN/512), 4 kHz (CLKIN/1024), 2 kHz (CLKIN/2048), or 1 kHz (CLKIN/4096) based on ADC_FREQ being equal to 00, 01, 10, or 11, respectively, when CLKIN is 4.096 MHz. The microcontroller reads the ADC output registers one at a time or in burst mode. See the SPI Read Operation section and the SPI Read Operation in Burst Mode section for more information. Table 6. ADC Output Frequency and ADC Bandwidth as a Function of CLKIN Frequency CLKIN (MHz) 4.096 4.21 3.6 ADC_FREQ Bits in CONFIG Register 00 01 10 11 00 01 10 11 00 01 10 11 ADC Output Frequency (Hz) 8000 4000 2000 1000 8222 4111 2055 1027 7031 3515 1757 878 ADC Bandwidth When BW Bit in CONFIG Register Cleared to 0 (Hz) 3300 1650 825 412 3391 1695 847 423 2900 1450 725 362 Rev. 0 | Page 15 of 28 ADC Bandwidth When BW Bit in CONFIG Register Set to 1 (Hz) 2000 1000 500 250 2055 1027 513 256 1757 878 439 219 ADE7903 Data Sheet REFERENCE CIRCUIT All other gi coefficients are equal to 0. The nominal reference voltage at the REF pin is 1.2 V. This reference voltage is used for the ADCs in the ADE7903. Because the on-chip dc-to-dc converter cannot supply external loads, the REF pin cannot be overdriven by a standalone external voltage reference. Every output cycle, the ADE7903 computes the cyclic redundancy check (CRC) of the ADC output values stored in the IWV, V1WV, and V2WV registers. Bits[5:4] (ADC_FREQ) in the CONFIG register determine the ADC output frequency and, therefore, the update rate of the CRC. The CRC algorithm is based on the CRC-16-CCITT algorithm. The registers are introduced into a linear feedback shift register (LFSR) based generator one byte at a time, least significant byte first, as shown in Figure 26. Each byte is then used with the MSB first. The 16-bit result is written in the ADC_CRC register. 16 23 8 8 7 15 0 0 23 16 15 7 16 23 8 8 7 15 0 23 16 15 7 16 23 8 8 7 0 15 0 7 + a71 a48 a47 a24 a23 a0 LFSR GENERATOR g1 g3 g2 g15 FB b0 b1 b2 (5) The ADE7903 contains a temperature sensor that is multiplexed with the V2P input of the voltage channel. Bit 3 (TEMP_EN) of the CONFIG register selects what the third ADC of the ADE7903 measures. If the TEMP_EN bit is 0, its default value, the ADC measures the voltage between the V2P and VM pins. If the TEMP_EN bit is 1, the ADC measures the temperature sensor. In the ADE7903, the conversion result is stored in the V2WV register. The time it takes for the temperature sensor measurement to settle after the TEMP_EN bit is set to 1 is 5 ms. temp = 8.72101 × 10−5 × (V2WV + TEMPOS × 211) − 306.47 where temp is the temperature value measured in degrees Celsius. Figure 26. CRC Calculation of ADC Output Values g0 bi(j) = FB(j) AND gi XOR bi − 1(j − 1), i = 1, 2, 3, …, 15 The expression used to calculate the temperature in the microcontroller, when Bit 7 (BW) in the CONFIG register is set to the default value of 0, is IWV REGISTER 0 (4) TEMPERATURE SENSOR 12458-026 23 16 15 b0(j) = FB(j) AND g0 The ADC_CRC register can be read by executing an SPI register read access or as part of the SPI burst mode read operation. See the SPI Read Operation and the SPI Read Operation in Burst Mode sections for more details. CRC OF ADC OUTPUT VALUES V1WV REGISTER (3) Equation 3, Equation 4, and Equation 5 must be repeated for j = 1, 2, …, 72. The value written into the ADC_CRC register contains Bit bi(72), i = 0, 1, …, 15. The voltage of the ADE7903 reference drifts slightly with temperature. Table 1 lists the gain drift over temperature specification of each ADC channel. This value includes the temperature variation of the ADC gain, together with the temperature variation of the internal voltage reference. V2WV REGISTER FB(j) = aj − 1 XOR b15(j − 1) b15 12458-027 LFSR a71, a70,....,a2, a1, a0 Figure 27. LFSR Generator Used for ADC_CRC Calculation Figure 27 shows how the LFSR works. The IWV, V1WV, and V2WV registers form the [a71, a70,…, a0] bits used by the LFSR. Bit a0 is Bit 7 of the first register to enter the LFSR; Bit a71 is Bit 16 of V2WV, the last register to enter the LFSR. The formulas that govern the LFSR are as follows: bi(0) = 1, where i = 0, 1, 2, …, 15, the initial state of the bits that form the CRC. Bit b0 is the LSB, and Bit b15 is the MSB. gi, where i = 0, 1, 2, …, 15 are the coefficients of the generating polynomial defined by the CRC-16-CCITT algorithm as follows: G(x) = x16 + x12 + x5 + 1 (1) g0 = g5 = g12 = 1 (2) The gain value is different depending on the value of Bit 7 (BW) in the CONFIG register. When Bit 7 (BW) is set to 0, the gain used to convert the bit information provided by the ADE7903 into degrees Celsius has a default value of 8.72101 × 10−5°C/LSB; when Bit 7 (BW) is set to 1, this gain value is 9.26171 × 10−5°C/LSB. The temperature measurement accuracy is ±5°C. TEMPOS is the 8-bit, signed, read-only register in which the temperature sensor offset is stored. The offset information is calculated during the manufacturing process, and it is stored with the opposite sign. For example, if the offset is 5, −5 is written into the ADE7903. One LSB of the TEMPOS register is equivalent to 211 LSBs of the V2WV register. Instead of using the default gain value, the gain can be calibrated as part of the overall meter calibration process. Measure the temperature, TEMP, of the ADE7903, read the V2WV register containing the temperature sensor reading of the ADE7903, and compute the gain as follows: Rev. 0 | Page 16 of 28 Temperature gain = TEMP V 2WV + TEMPOS × 211 (6) Data Sheet ADE7903 PROTECTING THE INTEGRITY OF CONFIGURATION REGISTERS The configuration registers of the ADE7903 are either user accessible registers (CONFIG, SYNC_SNAP, COUNTER0, and COUNTER1) or internal registers. The internal registers are not user accessible, and they must remain at their default values. To protect the integrity of all configuration registers, a write protection mechanism is available. By default, the write protection is disabled and the user accessible configuration registers can be written without restriction. When the protection is enabled, no writes to any configuration register are allowed. The registers can always be read, without restriction, independent of the write protection state. To enable the protection, write 0xCA to the 8-bit lock register (Address 0xA). To disable the protection, write 0x9C to the 8-bit lock register. It is recommended that the write protection be enabled after the CONFIG register is initialized. If any user accessible register must be changed, for example, during the synchronization process of multiple ADE7912/ADE7913 and ADE7903 devices, disable the protection, change the value of the register, and then reenable the protection. CRC OF CONFIGURATION REGISTERS Every output cycle, the ADE7903 computes the CRC of the CONFIG and TEMPOS registers, as well as Bit 2 (IC_PROT) of the STATUS0 register, and Bit 7 of the STATUS1 register. The CRC algorithm is called CRC-16-CCITT. The 16-bit result is written in the CTRL_CRC register. The input registers to the CRC circuit form a 64-bit array that is introduced bit by bit into an LFSR-based generator, similar to Figure 26 and Figure 27, one byte at a time, least significant byte first. Each byte is then processed with the MSB first. The formulas that govern the LFSR are as follows: bi(0) = 1, where i = 0, 1, 2, …, 15, the initial state of the bits that form the CRC. Bit b0 is the LSB, and Bit b15 is the MSB. gi, where i = 0, 1, 2, …, 15 are the coefficients of the generating polynomial defined by the CRC-16-CCITT algorithm in Equation 1 and Equation 2. FB(j) = aj − 1 XOR b15(j − 1) (7) b0(j) = FB(j) AND g0 (8) bi(j) = FB(j) AND gi XOR bi − 1(j − 1), i = 1, 2, 3, … , 15 (9) Equation 7, Equation 8, and Equation 9 must be repeated for j = 1, 2, … , 64. The value written into the CTRL_CRC register contains Bit bi(64), i = 0, 1, …, 15. Because each ADE7903 has a particular TEMPOS register value, each ADE7903 has a different CTRL_CRC register default value. ADE7903 STATUS The bits in the STATUS0 and STATUS1 registers of the ADE7903 characterize the state of the device. If the value of the CTRL_CRC register changes, Bit 1 (CRC_STAT) in the STATUS0 register is set to 1. This bit clears to 0 when the STATUS0 register is read. After the configuration registers are protected by writing 0xCA into the lock register, Bit 2 (IC_PROT) in the STATUS0 register is set to 1. It clears to 0 when the STATUS0 register is read, and it is set back to 1 at the next ADC output cycle. At power-up, or after a hardware or software reset, the ADE7903 signals the end of the reset period by clearing Bit 0 (RESET_ON) in the STATUS0 register to 0. If the ADC output values of IWV, V1WV, and V2WV are not read during an output cycle, Bit 3 (ADC_NA) in the STATUS1 register becomes 1. It clears to 0 when the STATUS1 register is read. The STATUS0 and STATUS1 registers can be read by executing an SPI register read. STATUS0 can also be read as part of the SPI burst mode read operation. See the SPI Read Operation and the SPI Read Operation in Burst Mode sections for more information. Rev. 0 | Page 17 of 28 ADE7903 Data Sheet PHASE C PHASE A ADE7912/ADE7913 NEUTRAL LINE XTAL2 VM XTAL1 IM CS SCLK IP MOSI MISO CLKOUT/ DREADY V2P ADE7903 V1P GNDMCU GNDISO_A VM 4.096MHz CRYSTAL MICROCONTROLLER IM PHASE B ADE7912/ADE7913 GND V1P XTAL2 CS_B IP VM XTAL1 CS_C IM CS SCLK CS_N IP MOSI MISO CLKOUT/ DREADY MOSI V2P 12458-028 IN V1P Figure 28. Neutral Line with the ADE7903 V2P Figure 28 shows how the ADE7903 inputs are connected on the neutral line of a 3-phase system. The neutral current is sensed using a shunt, and the voltage across the shunt is measured at the fully differential inputs, IP and IM. SCLK MISO I/O GNDMCU GNDISO_B PHASE C ADE7912/ADE7913 V1P A pole of the shunt is connected to the IM pin of the ADE7903 and becomes the ground, GND. Pin V1P and Pin VM are connected to the IM pin if they are not in use. The V1P and V2P voltage channels are used to measure auxiliary voltages. If V1P or V2P is not used, connect it to VM. Figure 29 shows a block diagram of a 3-phase energy meter that uses three ADE7912/ADE7913 devices, one ADE7903 on the neutral line, and a microcontroller. One 4.096 MHz crystal provides the clock to the ADE7912/ADE7913 that senses the Phase A current and voltage. The ADE7912/ADE7913 devices that sense the Phase B and Phase C currents and voltages and the ADE7903 device that senses the neutral current are clocked by a signal generated at the CLKOUT/DREADY pin of the ADE7912/ADE7913 that is placed to sense the Phase A current and voltage. As an alternative configuration, the microcontroller can generate a 4.096 MHz clock to all ADE7912/ADE7913 and ADE7903 devices at the XTAL1 pin (see Figure 30). Note that the XTAL1 pin can receive a clock with a frequency within the 3.6 MHz to 4.21 MHz range, as specified in Table 1. CS_A VM IM IP V2P CS SCLK MOSI MISO CLKOUT/ DREADY GNDMCU ISOLATION BARRIER GNDISO_C V1P XTAL2 VM XTAL1 IM IP CS PHASE N ADE7903 SCLK V2P LOAD XTAL2 XTAL1 MOSI MISO CLKOUT/ DREADY GNDMCU Figure 29. 3-Phase Energy Meter Using Three ADE7912/ADE7913 Devices and One ADE7903 Device The microcontroller uses the SPI port to communicate with the ADE7912/ADE7913 and ADE7903 devices. Four of its input/ output pins, CS_A, CS_B, CS_C, and CS_N, are used to generate the SPI CS signals. The SCLK, MOSI, and MISO pins of the microcontroller are directly connected to the corresponding SCLK, MOSI, and MISO pins of each ADE7912/ADE7913 device (see Figure 31). To simplify Figure 29 to Figure 31, these connections are not shown. Rev. 0 | Page 18 of 28 12458-029 NEUTRAL PHASE B The ADE7903 is designed for use in a 3-phase energy metering systems in which three ADE7912/ADE7913 devices and one ADE7903 device are managed by a master device containing an SPI interface, usually a microcontroller. PHASE A ADE7903 IN POLYPHASE ENERGY METERS NEUTRAL APPLICATIONS INFORMATION ADE7903 PHASE A ADE7912/ADE7913 V1P XTAL2 VM XTAL1 IM CS SCLK IP MOSI V2P GNDISO_A CS PHASE B ADE7912/ADE7913 VDD 10kΩ CS_A CS_A XTAL2 CS_B VM XTAL1 CS_C IM CS SCLK MOSI CS_N MISO CLKOUT/ DREADY MISO GNDISO_B GNDMCU XTAL2 VM XTAL1 IM CS SCLK MOSI IP V2P GNDISO_C MISO CS_C SCLK MOSI CS CLK I/O ADE7912/ ADE7913 SCLK ADE7903 SCLK MOSI PHASE C MISO CS MISO CLKOUT/ DREADY NEUTRAL MOSI MISO 12458-031 XTAL2 XTAL1 Figure 31. SPI Connections Between Three ADE7912/ADE7913 Devices, One ADE7903 Device, and a Microcontroller CS PHASE N ADE7903 SCLK ADE7903 IN SINGLE-PHASE ENERGY METERS MISO CLKOUT/ DREADY GNDMCU Figure 30. Microcontroller Generating Clock to Three ADE7912/ADE7913 Devices and One ADE7903 Device In Figure 30, the CLKOUT/DREADY pin of the ADE7912/ ADE7913 used to sense the Phase C current and voltage is connected to the input/output pin of the microcontroller. CLKOUT/DREADY provides an active low pulse for 64 CLKIN cycles (15.625 μs at CLKIN = 4.096 MHz) when the ADC conversion data is available. It signals when the ADC outputs of all ADE7912/ADE7913 and ADE7903 devices become available and when the microcontroller starts to read them. See the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for more information about synchronizing multiple ADE7912/ADE7913 and ADE7903 devices. The ADE7903 is also designed for use in a single-phase energy metering system in which one ADE7903 device or an ADE7903 and ADE7912/ADE7913 combination is managed by a master device containing an SPI interface, usually a microcontroller. Figure 32 shows a block diagram of a single-phase energy meter that uses an ADE7903 on the phase and a microcontroller. One 4.096 MHz crystal provides the clock to the ADE7903 that senses the phase current and voltage. Unlike the isolated solution, this setup means that the ADE7903 is floating at the line voltage. Other combinations of the ADE7903 and the ADE7912/ADE7913 are possible in a single-phase application for monitoring both the phase and the neutral. At power-up, or after a hardware or software reset, follow the procedure described in the Power-Up Procedure for Systems with Multiple Devices Using a Single Crystal section or the Power-Up Procedure for Systems with Multiple Devices Using Clock Generated from Microcontroller section to ensure that the ADE7912/ADE7913 and ADE7903 devices function appropriately. PHASE MOSI 12458-030 V2P LOAD MOSI PHASE B MISO CS_N NEUTRAL VM IP SCLK MOSI GNDMCU ISOLATION BARRIER V1P IM CS_B SCLK MICROCONTROLLER PHASE C ADE7912/ADE7913 V1P CS ADE7912/ ADE7913 MICROCONTROLLER V1P V2P MOSI PHASE A MISO MISO CLKOUT/ DREADY GNDMCU IP SCLK ADE7912/ ADE7913 V1P XTAL2 XTAL1 VM CS ADE7903 SCLK IP MOSI MISO CLKOUT/ DREADY V2P LOAD PHASE IM 4.096MHz CRYSTAL MICROCONTROLLER CS SCLK MOSI MISO I/O GNDMCU Figure 32. Single-Phase Energy Meter Using an ADE7903 Device Rev. 0 | Page 19 of 28 12458-032 PHASE C PHASE B PHASE A NEUTRAL Data Sheet ADE7903 Data Sheet ADE7903 CLOCK SPI-COMPATIBLE INTERFACE Provide a digital clock signal at the XTAL1 pin to clock the ADE7903. The frequency at which the ADE7903 is clocked at XTAL1 is called CLKIN. The ADE7903 is specified for CLKIN = 4.096 MHz, but frequencies between 3.6 MHz and 4.21 MHz are acceptable. The SPI of the ADE7903 is the slave of the communication and consists of four pins: SCLK, MOSI, MISO, and CS. The serial clock for a data transfer is applied at the SCLK logic input. All data transfer operations synchronize to the serial clock. Data shifts into the ADE7903 at the MOSI logic input on the falling edge of SCLK, and the ADE7903 samples the data on the rising edge of SCLK. Data shifts out of the ADE7903 at the MISO logic output on the falling edge of SCLK and can be sampled by the master device on the rising edge of SCLK. The MSB of the word is shifted in and out first. The maximum and minimum serial clock frequencies supported by this interface are 5.6 MHz and 250 kHz, respectively. MISO stays in high impedance when no data is transmitted from the ADE7903. At power-up or during hardware or software reset, the microcontroller reads the STATUS0 register to detect when Bit 0 (RESET_ON) clears to 0. See Figure 31 for details of the connections between the SPI ports of three ADE7912/ADE7913 devices and one ADE7903 device, and a microcontroller containing an SPI interface. Alternatively, a 4.096 MHz crystal with a typical drive level of 0.5 mW and an ESR of 20 Ω can be connected across the XTAL1 and XTAL2 pins to provide a clock source for the ADE7903 (see Figure 33). The total capacitance (TC) at the XTAL1 and XTAL2 pins is TC = C1 + CP1 = C2 + CP2 where: C1 and C2 are the ceramic capacitors between XTAL1 and GND and between XTAL2 and GND, respectively. CP1 and CP2 are the parasitic capacitors of the wires connecting the crystal to the ADE7903. The load capacitance (LC) of the crystal is equal to half the total capacitance because it is the capacitance of the series circuit composed by C1 + CP1 and C2 + CP2. LC = C1 + CP1 C2 + CP2 TC = = 2 2 2 Therefore, the value of the C1 and C2 capacitors as a function of the load capacitance of the crystal is C1 = C2 = 2 × LC − CP1 = 2 × LC − CP2 In the case of the ADE7903, the typical total capacitance of the XTAL1 and XTAL2 pins is 40 pF (see Table 1). Select a crystal with a load capacitance of LC = TC = 20 pF 2 Assuming that the parasitic capacitances, CP1 and CP2, are equal to 20 pF, select the C1 and C2 capacitors equal to 20 pF. CP1 ADE7903 XTAL1 TC C1 C2 CP2 SPI Read Operation The read operation using the ADE7903 SPI interface is initiated when the master sets the CS pin low and begins sending one command byte on the MOSI line. The master places data on the MOSI line starting with the first high to low transition of SCLK. The bit composition of the command byte is shown in Table 7. Bits[1:0] are don’t care bits, and they can have any value. The examples presented throughout this section show them set to 00. Bit 2 (READ_EN) determines the type of the operation. For a read, READ_EN must be set to 1. For a write, READ_EN must be cleared to 0. Bits[7:3] (ADDR) represent the address of the register to be read or written. Table 7. Command Byte for SPI Read/Write Operations TC 12458-033 XTAL2 The CS logic input is the chip select input. Drive the CS input low for the entire data transfer operation. Bringing CS high during a data transfer operation leaves the ADE7903 register that is the object of the data transfer unaffected; however, it aborts the transfer and places the serial bus in a high impedance state. A new transfer can then be initiated by returning the CS logic input to low. Bit Location 1:0 2 Bit Name Reserved READ_EN 7:3 ADDR Figure 33. Crystal Circuitry Rev. 0 | Page 20 of 28 Description These bits can have any value. Set this bit to 1 if a SPI read operation is executed. Clear this bit to 0 if a SPI write operation is executed. Address of the register to be read or written. Data Sheet ADE7903 For example, if the IWV register is not required, but V1WV is, set the ADDR bits to the V1WV address, 00001, in the command byte, and execute the burst mode operation. CS SCLK 0 0 0 0 0 1 0 0 MOSI 23 0 15 0 CS IWV MISO CNT_SNAPSHOT 12458-035 The ADE7903 SPI samples data on the low to high transitions of SCLK. After the ADE7903 device receives the last bit of the command byte on a low to high transition of SCLK, it begins to transmit its contents on the MISO line when the next SCLK high to low transition occurs; thus, the master can sample the data on a low to high SCLK transition. After the master receives the last bit, it sets the CS and SCLK lines high and the communication ends. The data lines, MOSI and MISO, go into a high impedance state. Figure 34 shows an 8-bit register read operation; 16-bit and 32-bit registers are read in the same manner. Figure 35. SPI Read Operation in Burst Mode SCLK SPI Write Operation 1 0 0 7 MISO 6 1 0 REGISTER VALUE Figure 34. SPI Read Operation of an 8-Bit Register SPI Read Operation in Burst Mode All ADE7903 output registers (IWV, V1WV, V2WV, ADC_CRC, STATUS0, and CNT_SNAPSHOT) can be read in one of two ways: one register at a time (see the SPI Read Operation section) or by reading multiple consecutive registers simultaneously in burst mode. Burst mode is initiated when the master sets the CS pin low and begins sending the command byte (see Table 7) on the MOSI line with Bits[7:3] (ADDR) set to the IWV register address, 00000. This means a command byte set to 0x04. The master places data on the MOSI line starting with the first high to low transition of SCLK. The SPI of the ADE7903 samples data on the low to high transitions of SCLK. After the ADE7903 device receives the last bit of the command byte on a low to high transition of SCLK, it begins to transmit the 24-bit IWV register on the MISO line when the next SCLK high to low transition occurs; thus, the master can sample the data on a low to high SCLK transition. After the master receives the last bit of the IWV register, the ADE7903 device sends V1WV, which is placed at the next location, and continues in this manner until the master sets the CS and SCLK lines high and the communication ends. The data lines, MOSI and MISO, go into a high impedance state. See Figure 35 for details of the SPI read operation in burst mode. If a register does not need to be read, for example, the 16-bit CNT_SNAPSHOT register, the master sets the CS and SCLK lines high after the STATUS0 register is received. CS SCLK 7 MOSI ADDR[4:0] 0 0 0 6 1 0 REGISTER VALUE 12458-036 ADDR[4:0] 12458-034 MOSI The SPI write operation is initiated when the master sets the CS pin low and begins sending one command byte (see Table 7). Bit 2 (READ_EN) must be cleared to 0. The master places data on the MOSI line starting with the first high to low transition of SCLK. The SPI of the ADE7903 samples data on the low to high transitions of SCLK. Next, the master sends the 8-bit value of the register without losing any SCLK cycles. After the last bit is transmitted, at the end of the SCLK cycle, the master sets the CS and SCLK lines high, and the communication ends. The data lines, MOSI and MISO, go into a high impedance state. See Figure 36 for details of the SPI write operation. Figure 36. SPI Write Operation Note that the SPI write operation can execute 8-bit writes only. The 16-bit synchronization counter register (composed of COUNTER0 and COUNTER1) is written by executing the write operation twice: the least significant byte is written first, followed by the most significant byte. See the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for details on the functionality controlled by the synchronization counter register. Because the ADE7903 does not need to acknowledge a write command in any way, this operation can be broadcast to multiple ADE7912/ADE7913 and ADE7903 devices when the same register must be initialized with the same value. After executing a write operation, it is recommended to read back the register to ensure that it was initialized correctly. Rev. 0 | Page 21 of 28 ADE7903 Data Sheet SYNCHRONIZING MULTIPLE ADE7912/ADE7913 AND ADE7903 DEVICES The ADE7912/ADE7913 and ADE7903 allow the user to sample all currents and voltages simultaneously and to provide coherent ADC output samples, which is a highly desired feature in polyphase metering systems. The ADE7903 in Polyphase Energy Meters section describes how a polyphase energy meter containing multiple ADE7912/ ADE7913 and ADE7903 devices can use one crystal to clock all the ADE7912/ADE7913 and ADE7903 devices. At power-up, only one ADE7912/ADE7913 or ADE7903 device is clocked from the crystal, while the other devices are set to receive the clock from the CLKOUT/DREADY pin of the first ADE7912/ADE7913 device. This pin has DREADY functionality enabled by default. In Figure 29 and Figure 30, the ADE7912/ADE7913 device on Phase A is clocked from the crystal or the microcontroller, and the CLKOUT/DREADY pin generates the DREADY signal. The other ADE7912/ ADE7913 and ADE7903 devices are clocked by the DREADY signal because the CLKOUT signal has not yet been received by their XTAL1 pins. The microcontroller enables CLKOUT functionality when Bit 0 (CLKOUT_EN) in the CONFIG register is set to 1. This operation ensures that the other ADE7912/ ADE7913 and ADE7903 devices in the system receive the same clock as the ADE7912/ADE7913 on Phase A and that all ADCs within all ADE7912/ADE7913 and ADE7903 devices in the system sample data at the same exact moment. As an alternative to using one crystal, the microcontroller can generate a clock signal to the XTAL1 pins of every ADE7912/ ADE7913 and ADE7903, ensuring precise ADC sampling synchronization (see Figure 30). To configure all ADE7912/ADE7913 and ADE7903 devices in an energy meter to provide coherent ADC output samples, that is, samples obtained in the same output cycle, all ADE7912/ ADE7913 and ADE7903 devices must have the same ADC output frequency and the outputs must be synchronized. Bits[5:4] (ADC_FREQ) in the CONFIG register select the ADC output frequency; therefore, they must be initialized to the same value (see the ADC Output Values section for more details). To synchronize the ADC outputs, that is, to set all ADE7912/ ADE7913 and ADE7903 devices to generate ADC outputs at the same exact moment, after power-up, the microcontroller must broadcast a write to the 8-bit SYNC_SNAP register with the value 0x01. All ADE7912/ADE7913 and ADE7903 devices then start a new ADC output period simultaneously when Bit 0 (sync) of the SYNC_SNAP register is written. The sync bit clears itself to 0 after one CLKIN cycle. As shown in Figure 29 and Figure 30, the CLKOUT/ DREADY pin of one ADE7912/ADE7913 or ADE7903 is connected to an I/O input of the microcontroller. This ADE7912/ADE7913 or ADE7903 device has Bit 0 (CLKOUT_EN) in the CONFIG register set to the default value, 0, to enable the DREADY functionality. When the ADC output period starts, the CLKOUT/DREADY pin goes low for 64 CLKIN cycles (15.625 µs when CLKIN = 4.096 MHz), signaling that all ADC outputs from all ADE7912/ADE7913 and ADE7903 devices are available and the microcontroller must start reading them. It is recommended that the SPI read in burst mode be used to ensure that all data is read in the shortest amount of time. For more information on the synchronization procedure of ADE7912/ADE7913 devices, refer to the ADE7912/ADE7913 data sheet. The same synchronization procedure applies to the ADE7903. Rev. 0 | Page 22 of 28 Data Sheet ADE7903 POWER MANAGEMENT POWER-UP AND INITIALIZATION PROCEDURES 5. At power-up or after a hardware or software reset, execute the following steps for a microcontroller managing a system formed by one or multiple ADE7912/ADE7913 and ADE7903 devices. 6. Protect the user accessible and internal configuration registers by setting the lock register to 0xCA. See the Protecting the Integrity of Configuration Registers section. When the ADC conversion data is available, the ADE7903 device begins generating a signal that is active low at the CLKOUT/DREADY pin for 64 CLKIN cycles (15.625 µs for CLKIN = 4.096 MHz). The DREADY functionality is enabled by default at the CLKOUT/DREADY pin. The microcontroller reads the IWV, V1WV, V2WV, ADC_CRC, CNT_SNAPSHOT, and STATUS0 registers in SPI burst mode (see the SPI Read Operation in Burst Mode section for more information). Power-Up Procedure for Systems with a Single ADE7903 For a standalone ADE7903 device managed by a microcontroller, the power-up procedure is as follows (see Figure 37): 3. 4. Connect a crystal between the XTAL1 and XTAL2 pins. Supply VDD to the ADE7903 device. To ensure that the ADE7903 device starts functioning correctly, the supply must reach 3.3 V − 10% in fewer than 23 ms from approximately a 2.6 V level. The ADE7903 device starts to function. To determine when the ADE7903 device is ready to accept commands, read the STATUS0 register until Bit 0 (RESET_ON) is cleared to 0, which happens approximately 20 ms after the ADE7903 starts to function and indicates that the ADE7903 is fully functional using the default settings. Initialize the CONFIG register. 7. Note that this power-up procedure also applies in the same way to systems that have multiple ADE7903 devices, each clocked from its own crystal. Every ADE7903 device is powered up and started independently. 3.3V – 10% ≈2.6V ADE7903 AND ADE7912/ADE7913 NONISOLATED SIDE READY ADE7912/ADE7913 ISOLATED SIDE READY 0V 20ms 23ms ADE7912/ADE7913 POWERED UP POR TIMER TURNED ON 100ms ADE7903 AND ADE7912/ADE7913 START FUNCTIONING BIT STATUS0[0] (RESET_ON) CLEARED TO 0 DC-TO-DC CONVERTER POWERED UP AND Σ-Δ MODULATORS FUNCTIONAL (ADE7912/ADE7913 ONLY) 12458-037 1. 2. Figure 37. Power-Up Procedure for Systems with One or Multiple ADE7903 and ADE7912/ADE7913 Devices, Each Clocked from Its Own Crystal Rev. 0 | Page 23 of 28 ADE7903 Data Sheet Power-Up Procedure for Systems with Multiple Devices Using a Single Crystal For polyphase energy meters using the ADE7912/ADE7913 and ADE7903 devices, shown in Figure 29 and Figure 30, in which a single crystal is used, see the ADE7912/ADE7913 data sheet for additional details on the power-up procedure. Power-Up Procedure for Systems with Multiple Devices Using Clock Generated from Microcontroller For polyphase energy meters in which the microcontroller generates the clock signal used by all ADE7912/ADE7913 and ADE7903 devices (see Figure 30), see the ADE7912/ADE7913 data sheet for additional details on the power-up procedure. HARDWARE RESET The ADE7903 does not have a dedicated reset pin. Instead, while the SCLK pin is receiving the serial clock, the CS and MOSI pins can be kept low by executing a SPI broadcast write operation in which the lines are kept low for 64 SCLK cycles. This is equivalent to sending eight bytes equal to 0x00 to the ADE7903 to accomplish a hardware reset. During a hardware reset, all the registers are set to their default values. This procedure can be done simultaneously for an ADE7903 device in a polyphase or single-phase energy meter. At the end of the reset period, the ADE7903 clears Bit 0 (RESET_ON) in the STATUS0 register to 0. At this point, follow one of the procedures described in the Power-Up and Initialization Procedures section to initialize the ADE7903 correctly. SOFTWARE RESET Bit 6 (SWRST) in the CONFIG register manages the software reset functionality. The default value of this bit is 0. If this bit is set to 1, the ADE7903 enters the software reset state. In this state, all the internal registers are reset to their default values. When the software reset ends, Bit 6 (SWRST) in the CONFIG register clears automatically to 0, and Bit 0 (RESET_ON) in the STATUS0 register is cleared to 0. If the configuration registers are protected using a lock = 0xCA register write, first unlock the registers by writing lock = 0x9C, and then write to the CONFIG register by setting Bit 6 (SWRST) to 1 to start a software reset. At this point, follow one of the procedures described in the Power-Up and Initialization Procedures section to initialize the ADE7903 correctly. POWER-DOWN MODE If the microcontroller generates the clock to all ADE7912/ ADE7913 and ADE7903 devices (see Figure 30), the current consumption can be reduced by shutting down the clock. The ADE7903 stops functioning. When the clock is restarted, as a good programming practice, execute a hardware reset to restart the ADE7903. In systems in which the CLKOUT/DREADY pin of one ADE7912/ ADE7913 device is used to clock other ADE7912/ADE7913 and ADE7903 devices (see Figure 29 and Figure 30), lower current consumption of the ADE7903 device can be achieved by clearing Bit 0 (CLKOUT_EN) in the CONFIG register to 0. Rev. 0 | Page 24 of 28 Data Sheet ADE7903 LAYOUT GUIDELINES Figure 18 shows the test circuit of the ADE7903. The test circuit contains three ADE7912/ADE7913 devices and one ADE7903 device together with the surrounding circuitry required to sense the phase current and voltages in a 3-phase system. The ADE7912/ ADE7913 and ADE7903 devices are managed by a microcontroller using the SPI interface. The microcontroller is not shown in the schematic. For the layout of that schematic, refer to the Layout Guidelines section of the ADE7912/ADE7913 data sheet, in addition to the guidelines in this section for the ADE7903 on the neutral channel. 12458-039 Figure 38 and Figure 39 show a proposed layout of the printed circuit board (PCB) with two layers that have the components placed on the top layer of the board only. Follow these layout guidelines to create a low noise design. Figure 39. 2-Layer Circuit Board, Bottom Layer ADE7903 EVALUATION BOARD The EVAL-ADE7903EBZ evaluation board allows users to quickly evaluate the ADE7903. This evaluation board is used in conjunction with the EVAL-SDP-CB1Z system demonstration platform. Order both the EVAL-ADE7903EBZ evaluation board and the system demonstration platform to evaluate the ADE7903. See the EVAL-ADE7903EBZ product page for details. ADE7903 VERSION 12458-038 Bits[2:0] (Version) in the STATUS1 register identify the version of the ADE7903. Figure 38. 2-Layer Circuit Board, Top Layer Rev. 0 | Page 25 of 28 ADE7903 Data Sheet REGISTER LIST In Table 8 to Table 14, R means a register can be read, and W means a register can be written. U means an unsigned register, and S means a signed register in twos complement format. Table 8. Register List Address 0x0 0x1 0x2 0x3 0x4 Register Name IWV V1WV V2WV Reserved ADC_CRC R/W R R R R R Bit Length 24 24 24 24 16 Type S S S S U Default Value1 0x000000 0x000000 0x000000 0x000000 N/A 0x5 CTRL_CRC R 16 U N/A 0x6 0x7 Reserved CNT_SNAPSHOT R R 16 16 S U 0x0000 0x00 0x8 0x9 0xA CONFIG STATUS0 Lock R/W R W 8 8 8 U U U 0 0x01 0x00 0xB 0xC SYNC_SNAP COUNTER0 W R/W 8 8 U U 0x00 N/A 0xD COUNTER1 R/W 8 U N/A 0xE 0xF 0x10, 0x11 0x12, 0x13 0x14 0x15, 0x16, 0x17 0x18 Reserved STATUS1 Reserved Reserved Reserved Reserved R/W R R/W R 8 8 8 8 U U U U 0xFF 0x00 0x00 0x00 R 8 U 0x00 TEMPOS R 8 S N/A 1 Description Instantaneous value of Current I. Instantaneous value of Voltage V1. Instantaneous value of Voltage V2. Reserved. This location always reads 0x000000. CRC value of IWV, V1WV, and V2WV registers. See the CRC of ADC Output Values section for details. CRC value of configuration registers. See the CRC of Configuration Registers section for details. Reserved. This location always reads 0x0000. Snapshot value of the counter used in synchronization operation. See Table 9 and the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for details. Configuration register. See Table 10 for details. Status register. See Table 11 for details. Memory protection register. See the Protecting the Integrity of Configuration Registers section and Table 12 for details. Synchronization register. See Table 13 for details. Contains the eight LSBs of the internal synchronization counter. COUNTER1[3:0] bits contain the four MSBs of the internal synchronization counter. See the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for details. Reserved registers. Status register. See Table 14 for details. For proper operation, do not write to these registers. Reserved registers. No functionality assigned at this address. Reserved registers. Temperature sensor offset. See the Temperature Sensor section for more information. N/A means not applicable. Table 9. CNT_SNAPSHOT Register (Address 0x7) Bit(s) [11:0] [15:12] Name Counter Reserved Default Value 0x000 0000 Description Snapshot value of the counter used in synchronization operation. Reserved. These bits do not represent any functionality. Rev. 0 | Page 26 of 28 Data Sheet ADE7903 Table 10. CONFIG Register (Address 0x8) Bit(s) 0 Name CLKOUT_EN Default Value 0 Description Enables CLKOUT functionality at the CLKOUT/DREADY pin. When CLKOUT_EN = 0, the default value, DREADY functionality is enabled. When CLKOUT_EN = 1, CLKOUT functionality is enabled. 1 2 3 Reserved Reserved TEMP_EN 0 0 0 [5:4] ADC_FREQ 00 6 7 SWRST BW 0 0 Reserved. This bit does not represent any functionality. Reserved bit. This bit selects the second voltage channel measurement. When the TEMP_EN bit is set to 0, the default value, the voltage between the V2P and VM pins is measured. When this bit is 1, the internal temperature sensor is measured (see the Temperature Sensor section for more information). These bits select the ADC output frequency. 00 = 8 kHz, 125 µs period. 01 = 4 kHz, 250 µs period. 10 = 2 kHz, 500 µs period. 11 = 1 kHz, 1 ms period. When this bit is set to 1, a software reset is initiated. This bit clears itself to 0 after one CLKIN cycle. Selects the bandwidth of the digital low-pass filter of the ADC. When BW = 0, the default value, the bandwidth is 3.3 kHz. When BW = 1, the bandwidth is 2 kHz. The bandwidth data is for CLKIN = 4.096 MHz and an ADC output frequency of 8 kHz. See the Analog-to-Digital Conversion section for details on how CLKIN and the ADC output frequency influence the bandwidth selection. Table 11. STATUS0 Register (Address 0x9) Bit(s) 0 Name RESET_ON Default Value 1 1 2 CRC_STAT IC_PROT 0 0 [7:3] Reserved 0 Description During reset, the RESET_ON bit is set to 1. When the reset ends and the ADE7903 is ready to be configured, the RESET_ON bit is cleared to 0. If the CRC of the configuration registers changes value, the CRC_STAT bit is set to 1. If the configuration registers are not protected, this bit is 0. After the configuration registers are protected (lock register = 0xCA), this bit is set to 1. Reserved. These bits do not represent any functionality. Table 12. Lock Register (Address 0xA) Bit(s) [7:0] Name LOCK_KEY Default Value 00000000 Description When the LOCK_KEY bits are equal to 0xCA, protection of the configuration registers is enabled. When the LOCK_KEY bits are equal to 0x9C, the protection is disabled, and the configuration registers can be written. This is a write only register. If the address location is read, the value is 0x00. Table 13. SYNC_SNAP Register (Address 0xB) Bit(s) 0 Name Sync Default Value 0 1 Snap 0 [7:2] Reserved 0 Description When the sync bit is set to 1 via a broadcast SPI write operation, the ADE7912/ADE7913 devices in the system generate ADC outputs in the same exact moment. The bit clears itself back to 0 after one CLKIN cycle. See the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for more details. When snap is set to 1 via a broadcast SPI write operation, the internal counters of the ADE7912/ADE7913 devices in the system are latched. The bit clears itself back to 0 after one CLKIN cycle. See the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for more details. Reserved. These bits do not represent any functionality. Table 14. STATUS1 Register (Address 0xF) Bit(s) [2:0] 3 Name Version ADC_NA Default Value 0 0 [6:4] 7 Reserved Reserved 0 0 Description The ADE7903 version number. If the ADC outputs are not accessed during one ADC output period, the ADC_NA bit is set to 1. When the STATUS1 register is read, the bit is cleared to 0. Reserved. These bits do not represent any functionality. Reserved. Internal functionality is associated with this bit. Rev. 0 | Page 27 of 28 ADE7903 Data Sheet OUTLINE DIMENSIONS 13.00 (0.5118) 12.60 (0.4961) 11 20 7.60 (0.2992) 7.40 (0.2913) 10 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 45° 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 06-07-2006-A 1 Figure 40. 20-Lead Standard Small Outline Package, [SOIC_W] Wide Body (RW-20) Dimensions shown in millimeters (and inches) ORDERING GUIDE Model 1, 2 ADE7903ARWZ ADE7903ARWZ-RL EVAL-ADE7903EBZ EVAL-SDP-CB1Z 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 20-Lead Standard Small Outline Package [SOIC_W] 20-Lead Standard Small Outline Package [SOIC_W], 13” Tape and Reel Evaluation Board Evaluation System Controller Board Z = RoHS Compliant Part. The EVAL-SDP-CB1Z is the controller board that manages the EVAL-ADE7903EBZ evaluation board. Both boards must be ordered together. ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12458-0-12/14(0) Rev. 0 | Page 28 of 28 Package Option RW-20 RW-20