Megawin MLC061B Single chip 8-bit cpu Datasheet

MLC0xxB Series
8-bit I/O type micro-controller with voice function
Features
• Single chip 8-bit CPU
• Operation voltage: 2.4V to 5.5V
• Memory:
♦
• Dual-channel melody with programmable
envelope
• Programmable sample rate for
voice/melody function
ROM (shared by program and data):
• One serial input port and voltage
1024K ~ 48KBytes
♦
comparator built-in
Data RAM: 256 Bytes
• 24 input/output pins with wake-up function
• Two power-down modes for saving power
• Three re-loadable 16-bit timers
• One watchdog timer built-in
• Oscillator
consumption:
♦
Sleep mode: micro-controller no
♦
operation (main- and sub-oscillator still
selected by code option
oscillating)
♦
Single or dual clock operation is
♦
Stop mode: micro-controller no operation
Main oscillator operation at crystal or
RC mode is selected by code option
(all oscillators stop oscillating)
♦
• Two current DAC output for voice
Crystal/Ceramic oscillator up to 4MHz
@ 2.4V and 8MHz @ 3.6V
synthesizer
♦
RC oscillator up to 4MHz @ 2.4V
Selection Information
ROM
(Program ROM)
I/O
Voice
Duration
6KHz 4-bit ADPCM
8KHz 4-bit ADPCM
ROM
(Program ROM)
I/O
Voice
Duration
6KHz 4-bit ADPCM
8KHz 4-bit ADPCM
MLC331B
1024K x 8-bit
(32K x 8-bit)
MLC241B
768K x 8-bit
(32K x 8-bit)
MLS161B
512K x 8-bit
(32K x 8-bit)
MLC121B
384K x 8-bit
(32K x 8-bit)
24
340 sec
250 sec
24
250 sec
190 sec
24
165 sec
125 sec
24
125 sec
90 sec
MLC081B
256K x 8-bit
(32K x 8-bit)
MLC061B
192K x 8-bit
(32K x 8-bit)
MLC041B
128K x 8-bit
(32K x 8-bit)
MLC031B
96K x 8-bit
(32K x 8-bit)
MLC021B
64K x 8-bit
(32K x 8-bit)
MLC017B
48K x 8-bit
(32K x 8-bit)
24
80 sec
60 sec
24
60 sec
45 sec
24
40 sec
30 sec
24
30 sec
22 sec
24
20 sec
16 sec
24
16 sec
12 sec
This document contains information on a new product under development by MEGAWIN. MEGAWIN reserves the right to change or discontinue
this product without notice.
 MEGAWIN Technology Co., Ltd. 2007 All rights reserved.
2007/05 version 0.60
MEGAWIN
Application Field
General voice synthesizer
Toy controller
General IR controller
General Description
MLC0xxB series integrates an 8-bit CPU core,
melody function with programmable envelope,
SRAM, timer, D/A and system control circuits
which can perform harmonic music with
by a CMOS silicon gate technology. The ROM
different timbres.
can store voice, melody, data table and
program.
This chip is very suitable for instruments,
speech products, and intelligent educational
Twenty-four I/O pins can be used for keypad
toys, etc.
control, motor control, IR application, LED
indicators or communication with other
systems. This chip can implement a dual tone
Pad Description
2
Pad No.
33, 4
Pad Name
AGND, GND
I/O
P
35, 1
AVDD, VDD
P
2, 3
7, 8
5
6
36
34
9 ~ 16
25 ~ 32
OSCO, OSCI
X32O, X32I
/RES
TEST
SPK2
SPK1
P0.0 ~ P0.7
P1.0 ~ P1.7
O, I
O, I
I
O
O
I/O
I/O
17 ~ 24
P2.0 ~ P2.7
I/O
Description
Ground pins, the two ground pins should be connected at
the outside individually
Positive power pins, the two power pins should be
connected at the outside individually
RC or crystal oscillator pins
32.768KHz crystal oscillator pins
System reset pin (low active)
For test mode only
DAC 2 output
DAC 1 output
Programmable I/O ports with interrupt function
Programmable I/O ports. Port P1.3, P1.4, P1.5 can be I/O
or serial input port. Port1.6, 1.7 can be output with IR
carrier.
Programmable I/O ports. Port 2.4~2.6 can be I/O or
voltage comparator.
MLC0xxB Series Technical Summary
MEGAWIN
Block Diagram
Tone gatting logic
Port 0.0 ~ 0.7
Port 1.0 ~ 1.7
Port 2.0 ~ 2.7
SPK1
SPK2
I/O, DAC
TM0, 1, 2
SRAM/Register
CPU
ROM
Divider 0, 1
MLC0xxB Series Technical Summary
AGND
AVDD
GND
VDD
OSCO
OSCI
X32I
MEGAWIN
X32O
System Clock Generator
3
Function Description
Registers
PCH
1
A
Y
X
P
PCL
S
Accumulator
The accumulator is a general-purpose 8-bit register, which stores the results of most arithmetic and
logic operations. In addition, the accumulator usually contains one of two data words, which are used
in these operations.
Index Register (X, Y)
There are two 8-bit index registers (X and Y), which may be used to count program steps or to provide
an index value to be used in generating an effective address. When executing an instruction, which
specifies indexed addressing, the CPU fetches the OP Code and the base address, and modifies the
address by adding the index register to it prior to performing the desired operation. Pre- or post-index
of index address is possible.
Processor Status Register (P)
The 8-bit processor status register contains seven status flags. Some of the flags are controlled by
the program, others may be controlled both the program and the CPU.
Bit 7
N
Bit 6
V
Bit 5
1
Bit 4
B
Bit 3
D
Bit 2
I
Bit 1
Z
Bit 0
C
N: Signed flag, 1 = negative, 0 = positive
V: Overflow flag, 1 = true, 0 = false
B: BRK interrupt command, 1 = BRK, 0 = IRQB
D: Decimal mode, 1 = true, 0 = false
I: IRQB disable flag, 1 = disable, 0 = enable
Z: Zero flag, 1 = true, 0 = false
C: Carry flag, 1 = true, 0 = false
4
MLC0xxB Series Technical Summary
MEGAWIN
Program Counter (PC)
The 16-bit program counter register provides the addresses, which step the micro-controller through
sequential program instructions. Each time the micro-controller fetches an instruction from program
memory, the lower byte of the program counter (PCL) is placed on the low-order 8 bits of the address
bus and the higher byte of the program counter (PCH) is placed on the high-order 8 bits. The counter
is incremented each time an instruction or data is fetched from program memory.
Stack Pointer (S)
The stack pointer is an 8-bit register, which is used to control the addressing of the variable-length
stack. The stack pointer is automatically incremented and decremented under control of the
micro-controller to perform stack manipulations under direction of either the program or interrupts
(/NMI or /IRQ). The stack allows simple implementation of nested subroutines and multiple level
interrupts. The stack pointer is initialized by the user’s software.
MEGAWIN
MLC0xxB Series Technical Summary
5
Memory Map
There are 256 bytes SRAM in MLC0xxB series. They are working RAM (0000H to 007FH) and stacks
(0180H to 01FFH). The address 0100H to 17FH are shared with address 0000H to 007FH. The
address 00C0H to 00FFH and 0200H to 027FH are special function registers area.
The bank select function, ranged from 4000H to 7FFFH, is used for extending memories if the ROM
size is more than 32K bytes in MLC0xxB series. The default bank number is 00H after power on or
reset.
There are 1024K ~ 48K bytes program/data ROM in MLC0xxB series. It is combined with 32K
program/data ROM and bank switching data ROM. The ROM address from 4000H to FFFFH can
store program, voice data, melody notes and other data. The address mapping of MLC0xxB series is
shown as below.
MLC0xxB Series Memory Map
0000H
007FH
0080H~00BFH
00C0H~00FFH
0100H
017FH
0180H
01FFH
0200H
027FH
Zero Page WR
Share area
SFR
...
Stack Area
...
Special Function
Register
...
0300H
3FFFH
4000H
7FFFH
Table
Bank
0
(017)
Table
Bank
1
(021)
2
3
(031)
Table
Bank
5
(041)
Table
Bank
45
(241)
Table
Bank
61
(331)
8000H
Program/Table
BFFFH
C000H
Program/Table
FFEDH
FFEEH ~ FFEFH
FFFEH ~ FFFFH
6
Interrupt Vector
Area
MLC0xxB Series Technical Summary
MEGAWIN
Special Function Register (SFR)
The address 00C0H to 00FFH and 0200H to 027FH are reserved for special function registers (SFR).
The SFR is used to control or store the status of I/O, timers, system clock and other peripheral.
SFR (special function register): 00C0H ~ 00FFH (page 0 area)
Address
00C0
00C1
00C2
00C3
00C4
00C5
00C6
00C7
00C8
00C9
00CA
00CB
00CC
00CD
00CE
00CF
Address
00E0
00E1
00E2
00E3
00E4
00E5
00E6
00E7
00E8
00E9
00EA
00EB
00EC
00ED
00EE
00EF
Content
NMI_SEL
IRQ_EN / IRQ_ST
IRQ_CLR
TM0L
TM0H
TM0_CTL
TM0_MOD
TM1L
TM1H
TM1_CTL
DIV0_ST / DIV0x_SEL
DIV1_STL/ DIV1x_SEL
DIV1_STH
Content
CH1
CH2
CH3
TM2_L
TM2_H
TM2_CTL
MEGAWIN
Default Address
Content
00
00D0 BANK
X
00D1
00
00D2
00
00D3
00
00D4
00
00D5 P1_MFR
00
00D6 P2_MFR
00
00D7
00
00D8 P0
00
00D9 P1
00
00DA P2
X
00DB
00
00DC
X
00DD
00
00DE WDT_CTL
00
00DF WDT_CLR
Default
00
X
X
X
X
00
00
X
00
00
00
X
X
X
00
00
Default Address
Content
X
00F0
00
00F1
X
00F2
00
00F3
X
00F4
00
00F5
X
00F6
X
00F7
00
00F8 CMP_CTL
00
00F9 DB_TC
00
00FA VT_CTL
X
00FB
X
00FC
X
00FD DAC_DRV
X
00FE
X
00FF
Default
X
X
X
X
X
X
X
X
00
00
00
X
X
00
X
X
MLC0xxB Series Technical Summary
7
SFR (special function register): 0200H ~ 027FH
Address
Content
0200 PWR_CR
0201 FCPU_SR
0202 RLH_EN
0203
0204
0205
0206
0207
0208
0209
020A
020B
020C
020D
020E
020F
Default Address
00
0210
00
0211
00
0212
X
0213
X
0214
X
0215
X
0216
X
0217
X
0218
X
0219
X
021A
X
021B
X
021C
X
021D
X
021E
X
021F
Content
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Address
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229
022A
022B
022C
022D
022E
022F
Default Address
X
0230
X
0231
X
0232
X
0233
X
0234
X
0235
X
0236
X
0237
X
0238
X
0239
X
023A
X
023B
X
023C
X
023D
X
023E
X
023F
Content
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8
Content
MLC0xxB Series Technical Summary
MEGAWIN
Special Function Register, Continued
Address
0240
0241
0242
0243
0244
0245
0246
0247
0248
0249
024A
024B
024C
024D
024E
024F
Content
Default Address
00
0250
00
0251
X
0252
X
0253
00
0254
00
0255
X
0256
X
0257
00
0258
00
0259
X
025A
X
025B
X
025C
X
025D
X
025E
X
025F
Content
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Content
Default Address
X
0270
X
0271
X
0272
X
0273
X
0274
X
0275
X
0276
X
0277
X
0278
X
0279
X
027A
X
027B
X
027C
X
027D
X
027E
X
027F
Content
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
P0CR
P0MR
P1CR
P1MR
P2CR
P2MR
Address
0260
0261
0262
0263
0264
0265
0266
0267
0268
0269
026A
026B
026C
026D
026E
026F
MEGAWIN
MLC0xxB Series Technical Summary
9
Interrupt Vectors
Vector Address
FFFCH, FFFDH
FFFAH, FFFBH
FFF8H, FFF9H
FFF6H, FFF7H
FFF4H, FFF5H
FFF2H, FFF3H
FFF0H, FFF1H
FFEEH, FFEFH
Item
RESET
NMI
DIV0x
TM0
P0
TM1
TM2
DIV1x
Priority
1
2
3
4
5
6
7
8
Properties
Ext.
Int./Ext.
Int.
Int.
Ext.
Int.
Int.
Int.
Memo
Initial reset
Non-maskable interrupt vector
Selectable divider 0 carry out interrupt
Timer 0 overflow interrupt
Port P0 interrupt vector
Timer 1 overflow interrupt
Timer 2 overflow interrupt
Selectable divider 1 carry out interrupt
There are eight kinds of interrupt sources are provided in MLC0xxB series. The flag IRQ_EN and
IRQ_ST are used to control the interrupts. When flag IRQ_ST is set to ‘1’ by hardware and the
corresponding bits of flag IRQ_EN has been set by software, an interrupt is generated. When an
interrupt occurs, all of the interrupts are inhibited until the CLI or STA IRQ_EN, #I instruction is
invoked. Executing the SEI instruction can also disable the interrupts.
Selectable
NMI
NMI
Process
Logic
S Q
R
NMI_EV
STA IRQ_EN, #I
Divider0
overflow signal
S Q
.
.
.
Divider1
overflow signal
S Q
R
FFFCH, FFFDH
FFFAH, FFFBH
FFF8H, FFF9H
FFF6H, FFF7H
IRQ_ST.1
IRQ_EN.1
FFF4H, FFF5H
Interrupt
Process
Logic
FFF2H, FFF3H
FFF0H, FFF1H
FFEEH, FFEFH
IRQ_ST.5
IRQ_EN.5
Initial Reset
STA IRQ_CLR, #I
10
Interrupt
Vector
Generator
Logic
IRQ_EN.0
R
S Q
Enable
IRQ_ST.0
R
Timer0
underflow signal
Initial Reset
CLI instruction
Disable
MLC0xxB Series Technical Summary
SEI instruction
MEGAWIN
Interrupt Registers
NMI select flag
Address
00C0H
Register
NMI_SEL
NIS2
0
0
0
0
1
1
1
1
NIS1
0
0
1
1
0
0
1
1
7
-
6
-
5
-
4
-
3
-
2
NIS2
1
NIS1
0
NIS0
R
W
√
√
Selected NMI source
None (default)
TM0
DIV0x
P0
TM1
TM2
DIV1x
(None)
NIS0
0
1
0
1
0
1
0
1
This register is used to select the NMI trigger source. The NMI is a rare resource of this system.
Only one trigger source is selected at one application is recommended. If over one trigger source is
needed in some special applications, program must to distinguish the additional interrupter. After NMI
occurs, program has to read NMI_SEL register to know which source triggering NMI.
IRQ enable flag
Address
00C2H
Name
IRQ_EN
Bit 7
-
Bit 6
-
Bit 5
DIV1x
Bit 4
TM2
Bit 3
TM1
Bit 2
P0
Bit 1
TM0
Bit 0
DIV0x
R
W
-
√
Bit 0
DIV0x
R
W
√
-
R
W
-
√
Program can enable or disable the ability of triggering IRQ through this register.
0: Disable (default “0” at initialization)
1: Enable
P0: Raising or falling edge occurs at port 0 input mode
TM0, TM1, TM2: Timer 0/1/2 underflow
DIV0x, DIV1x: Divider 0/1 selected interrupt frequency occurred
IRQ status flag (same address with IRQ_EN)
Address
00C2H
Name
IRQ_ST
Bit 7
-
Bit 6
-
Bit 5
DIV1x
Bit 4
TM2
Bit 3
TM1
Bit 2
P0
Bit 1
TM0
When IRQ occurs, program can read this register to know which source triggering IRQ.
IRQ clear flag
Address
00C3H
Name
IRQ_CLR
Bit 7
-
Bit 6
-
Bit 5
DIV1x
Bit 4
TM2
Bit 3
TM1
Bit 2
P0
Bit 1
TM0
Bit 0
DIV0x
Program can clear the interrupt event by writing ‘1’ into the corresponding bit.
MEGAWIN
MLC0xxB Series Technical Summary
11
DIV0 interrupt selector (clock source: FOSC)
Address
00CCH
Name
DIV0_ST
00CCH
DIV0x_SEL
Bit 7
FOSC
/256
-
Bit 6
FOSC
/128
-
Bit 5
FOSC
/64
-
Bit 4
FOSC
/32
-
Bit 3
FOSC
/16
-
Bit 2
FOSC
/8
-
Bit 1
FOSC
/4
CKO1
Bit 0
FOSC
/2
CKO0
R
W
√
-
-
√
The divider 0 is organized as an 8-bit binary up counter, which is designed to generate periodic
interrupts. When the main oscillator starts action, the divider 0 is incremented by each clock (FOSC).
The contents of divider 0 can be reset to 00H by POR, reset, waken from STOP mode and change the
contents of DIV0x_SEL.
CKO1
0
0
1
1
Selected DIV0x frequency
FOSC / 32
FOSC / 64
FOSC / 128
FOSC / 256
CKO0
0
1
0
1
Fcpu
DIV0x
DIV0
DIV0x_SEL.0
DIV0x_SEL.1
FCPU_SR.2
Fx32
FCPU_SR.0
FCPU_SR.1
Fosc/32, /64, /128, /256
(for DIV0x)
Fosc/1, /2, /4, /8
(for TM0)
Fosc/1, /2, /4, /8
Vdd
P1.4
DIV1x_SEL.6
DIV1x_SEL.5
DIV1x_SEL.4
Fosc
Fosc/1, /2, /4, /8, /16,
/32, /64, /128
(for DIV1)
DIV0_ST (8-bit)
DIV0
Rst
To TM2
Fosc/1, /2, /4, /8
(for TM2)
TM1_UV
TM1_CTL.0
TM1_CTL.1
TM1_CTL.2
/P1.4
Vss
TM0_UV
Fx32
Fosc/1, /2, /4, /8
(for TM1)
To TM1
To DIV1
DIV1x
DIV1x_SEL.0
DIV1x_SEL.1
DIV1x_SEL.2
DIV1x_SEL.3
16K, 8K, 4K, 2K, 1K, 512,
256, 128
DIV1
TM2_CTL.0
TM2_CTL.1
TM2_CTL.2
To TM0
TM0_CTL.0
TM0_CTL.1
TM0_CTL.2
64, 32, 16, 8, 4, 2, 1, 0.5
Fx32
DIV1
Rst
DIV1_STL (8-bit)
Fosc/1, /2, /4, /8,
/16, 32, /64, /128
DIV1_STH (8-bit)
DIV1x SEL 7
12
MLC0xxB Series Technical Summary
MEGAWIN
DIV1 interrupt selector (If the frequency of divider 1 clock source is 32.768KHz)
Address
00CEH
Name
DIV1_STL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
W
128
Hz
256
Hz
512
Hz
1024
Hz
2048
Hz
4096
Hz
8192
Hz
16384
Hz
√
-
00CFH
00CEH
DIV1_STH
DIV1x_SEL
0.5Hz
CKI7
1Hz
CKI6
2Hz
CKI5
4Hz
CKI4
8Hz
CKO3
16Hz
CKO2
32Hz
CKO1
64Hz
CKO0
√
-
√
The divider 1 contents can be reset to 00H by POR, reset, waken from STOP mode and writing
DIV1x_SEL register any value.
CKI7: select the input clock source of divider 1. 0: FOSC/x (00CE H), 1: FX32
CKI6
0
0
0
0
1
1
1
1
CKI5
0
0
1
1
0
0
1
1
CKI4
0
1
0
1
0
1
0
1
CKO3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CKO2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CKO1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MEGAWIN
Selected DIV1 input frequency
FOSC / 1
FOSC / 2
FOSC / 4
FOSC / 8
FOSC / 16
FOSC / 32
FOSC / 64
FOSC / 128
CKO0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Selected DIV1x frequency
FDIV1 / 2 (16384 Hz)
FDIV1 / 4
(8192 Hz)
(4096 Hz)
FDIV1 / 8
FDIV1 / 16 (2048 Hz)
FDIV1 / 32 (1024 Hz)
(512 Hz)
FDIV1 / 64
FDIV1 / 128 (256 Hz)
FDIV1 / 256 (128 Hz)
(64 Hz)
FDIV1 / 512
FDIV1 / 1024 (32 Hz)
FDIV1 / 2048 (16 Hz)
(8 Hz)
FDIV1 / 4096
(4 Hz)
FDIV1 / 8192
FDIV1 / 16384 (2 Hz)
FDIV1 / 32768 (1 Hz)
FDIV1 / 65536 (0.5 Hz)
MLC0xxB Series Technical Summary
13
Watchdog Timer (WDT)
Address
00DEH
00DFH
Name
WDT_CTL
WDT_CLR
Bit 7
RSTS
CLR
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
Bit 3
Bit 2
RSEL
Bit 2
Bit 1
CKI1
Bit 1
Bit 0
CKI0
Bit 0
R
W
√
√
√
√
RSTS: WDT reset status, set by hardware when WDT overflows, clear by hardware reset or set WDT_CLR.7 to
one to clear this bit (this bit is read only)
RSEL: WDT reset selector, = 0 Reset whole chip except RSTS (WDT_CTL.7)
= 1 Reset PC and IRQ_EN only
CKI1, CKI0: WDT clock selector, = 00 FDIV1/16384 selected (8 S @ FDIV1 = 32K)
= 01 FDIV1/4096 selected (2 S @ FDIV1 = 32K)
= 10 FDIV1/1024 selected (0.5 S @ FDIV1 = 32K)
= 11 FDIV1/128 selected (62.5 mS @ FDIV1 = 32K)
CLR: RSTS clear control bit, program can clear RSTS by program "1" into this bit (this bit is write only)
The watchdog timer (WDT), which is organized as a 4-bit counter, is designed to prevent the program
from unknown errors. The WDT is enabling by code option. If the WDT overflows, the WDT reset
function will be performed. The watchdog timer control register (WDT_CTL) controls the WDT reset
function. RSTS (WDT_CTL.7) is set by hardware when the WDT overflows and is cleared by store
one to the bit 7 of WDT_CLR register or hardware reset. There are two types of WDT reset, which is
selected by RSEL (bit2 of WDT_CTL). WDT overflow will cause two types reset depending on the
setting of RSEL  if RSEL is equal to 0, the reset is the same as hardware reset except the setting of
WDT_CTL and WDT_CLR; If RSEL is equal to 1, the reset only acts on program counter (PC) and
IRQ_EN. The WDT clock frequency is decided by bit1 and bit0 of WDT_CTL register. Store one to the
bit 7 of WDT_CLR register will also reset the contents of the WDT. In normal operation, the
application program must reset WDT before it overflows. The organization of the divider1 and
watchdog timer is shown as below.
WDT_CTL.0
WDT_CTL.1
Fdiv1/128
(Option code = 0)
WDT
Disable
Fdiv1/1024
WDT_CTL.2
Qw1 Qw2 Qw3 Qw4
Fdiv1/4096
R
Fdiv1/16384
R
R
Enable
(Option code = 1)
Overflow signal
PC & IRQ_EN reset
(other peripheral unchanged)
R
S
R
System Reset
except WDT_CTL.7
Q
WDT_CTL.7
Hardware reset
WDT_CLR <- 8XH
Fdiv1
Q1
Q2
...
Q7
Q8
Q9
Q10 Q11 Q12 Q13 Q14 Q15 Q16
Divider1
14
MLC0xxB Series Technical Summary
MEGAWIN
System Control Registers
Bank select
Address
00D0H
Name
BANK
Bit 7
-
Bit 6
BK6
Bit 5
BK5
Bit 4
BK4
Bit 3
BK3
Bit 2
BK2
Bit 1
BK1
Bit 0
BK0
R
W
√
√
Program can switch the memory bank through this register. After power on reset, this register in
initialized as 00H. The maximum bank numbers in MLC0xxB series are show as below:
Part No.
Max. Bank
Part No.
Max. Bank
MLC331B
11 1101b
MLC081B
00 1101b
MLC241B
10 1101b
MLC061B
00 1001b
MLC161B
01 1101b
MLC041B
00 0101b
MLC121B
01 0101b
MLC031B
00 0011b
MLC021B
00 0001b
MLC017B
00 0000b
For more detailed information, please refer to memory map description.
Power saving control
Address
0200H
CKC1
0
0
1
1
Name
PWR_CR
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
CKC1
Bit 1
CKC0
Bit 0
HALT
R
W
-
√
System clock control
FOSC enable, FX32 enable (Dual mode)
FOSC enable, FX32 disable (Single mode)
FOSC disable, FX32 enable (Slow mode)
FOSC disable, FX32 disable (Stop mode)
CKC0
0
1
0
1
Note: PWR_CR.CKC0 is inhibited when single clock mode is selected.
HALT: FCPU off-line control bit. 1: FCPU off-line, 0: FCPU on-line
Program can switch the normal operation mode to the power-saving mode for saving power
consumption through this register. There are three power saving modes in this system.
Slow mode: (PWR_CR.CKC1 = 1, PWR_CR.CKC0 = 0)
The main uC clock (FOSC) stops oscillating. Only very low power is needed for uC to keep running.
Stop mode: (PWR_CR.CKC1 = 1, PWR_CR.CKC0 = 1)
All system clocks stop oscillating. The uC can be awakened from stop mode by 3-ways: port 0
interrupt, hardware reset, or power-on reset.
Halt mode: (PWR_CR.HALT = 1)
The FCPU clock in off-line status. The oscillator(s) still oscillating if the PWR_CR.CKC1, PWR_CR.CKC0
keep low. The uC can be awakened from halt mode by 3-ways: all interrupt events (DIV0x, DIV1x,
timer 0, timer 1, timer 2, port 0), hardware reset, or power-on reset.
MEGAWIN
MLC0xxB Series Technical Summary
15
FCPU selector
Address
0201H
Name
FCPU_SR
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
R
W
-
√
Bit 2
P0
Bit 1
TM0
Bit 0
DIV0x
R
W
-
√
CKS2: FCPU clock source select. 0: FOSC/x (0201 H), 1:FX32
CKS1
0
0
1
1
Selected FOSC/x (0201H) frequency
FOSC / 1 (default)
FOSC / 2
FOSC / 4
FOSC / 8
CKS0
0
1
0
1
Release halt mode enable flag
Address
0202H
Name
RLH_EN
Bit 7
-
Bit 6
-
Bit 5
DIV1x
Bit 4
TM2
Bit 3
TM1
Set IRQ_CLR register to clear the halt release event.
Release halt status flag is the IRQ_ST register.
16
MLC0xxB Series Technical Summary
MEGAWIN
Timers/Counters
Timer0
Address
00C4H
00C5H
00C6H
00C7H
Name
TM0L
TM0H
TM0_CTL
TM0_MOD
Bit 7
T7
T15
STC
-
Bit 6
T6
T14
RL/S
-
Bit 5
T5
T13
TKES
-
Bit 4
T4
T12
TMS1
TKPS
Bit 3
T3
T11
TMS0
SRS
Bit 2
T2
T10
TKI2
-
Bit 1
T1
T9
TKI1
TDI1
Bit 0
T0
T8
TKI0
TDI0
R
W
√
√
√
√
√
√
√
√
STC: Start/Stop counting. 1: start and pre-load the value to counter, 0: stop timer clock (set this bit to 1 will be
ignored when this bit already set to 1)
RL/S: Auto-reload disable/enable. 1: disable auto-reload, 0: enable auto-reload
TKES: Event or series input clock-in trigger edge selector; 0: rising edge, 1: falling edge
TMS1
0
0
1
1
TMS0
0
1
0
1
Select TM0 operation mode
16-bit counter (default)
Reserved
16-bit shift register (the FTM0_UV/2 circuit will be bypassed)
16-bit rotate register (the FTM0_UV/2 circuit will be bypassed)
TKI2
0
0
0
0
1
1
1
1
TKI1
0
0
1
1
0
0
1
1
TKI0
0
1
0
1
0
1
0
1
Selected TM0 input clock source
FOSC / 1
FOSC / 2
FOSC / 4
FOSC / 8
VDD
FX32
P1.4
VSS
TKPS: Exchange the clock and data path of timer 0. 0:default path, 1: exchanged path
SRS: Shift register selector. 0: shift left, 1: shift right
TDI1
0
0
1
1
MEGAWIN
TDI0
0
1
0
1
Selected TM0 shift-in data source
VDD
P1.5
DIV0x
DIV1x
MLC0xxB Series Technical Summary
17
Timer1
Address
00C8H
00C9H
00CAH
Name
TM1L
TM1H
TM1_CTL
Bit 7
T7
T15
STC
Bit 6
T6
T14
RL/S
Bit 5
T5
T13
TKES
Bit 4
T4
T12
TMS1
Bit 3
T3
T11
-
Bit 2
T2
T10
TKI2
Bit 1
T1
T9
TKI1
Bit 0
T0
T8
TKI0
R
W
√
√
√
√
√
√
STC: Start/Stop counting. 1: start and pre-load the value to counter, 0: stop timer clock
RL/S: Auto-reload disable/enable. 1: disable auto-reload, 0: enable auto-reload
TKES: Event or series input clock-in trigger edge selector; 0: rising edge, 1: falling edge
TMS1
0
1
Select TM1 operation mode
16-bit counter
16-bit shift right register (the FTM1_UV/2 circuit will be bypassed)
TKI2
0
0
0
0
1
1
1
1
TKI1
0
0
1
1
0
0
1
1
TKI0
0
1
0
1
0
1
0
1
Selected TM1input clock source
FOSC / 1
FOSC / 2
FOSC / 4
FOSC / 8
TM0 underflow
FX32
/P1.4
VSS
Timer 1 is a 16-bit down-count counter. The counter underflow frequency of timer 1 can be calculated
with the equation:
FTM1_UV = FTM1 / (TM1+1)
For example: (if FTM1 = 4.096MHz)
TM1
00 00H
00 01H
00 02H
…
00 FFH
…
FF FFH
Frequency
Invalid
2.048MHz
1.365MHz
…
16KHz
…
62.5Hz
The timer 1 also can be used as tone generator. It generates specific frequency of tone with square
wave, but the frequency of specific tone is half of the overflow frequency. The example frequency
table is shown as below:
18
MLC0xxB Series Technical Summary
MEGAWIN
Set TM1_CTL to be 80H (enable counting and auto reload, source clock = 4.00MHz)
TM1H
3BH
38H
35H
…
1DH
…
0EH
…
07H
…
03H
03H
Underflow frequency
261.609
277.200
293.643
…
523.286
…
1046.572
…
2093.144
…
3952.569
4184.100
TM1L
BAH
5EH
36H
…
DCH
…
EEH
…
77H
…
F4H
BCH
Tone frequency
130.804
138.600
146.821
…
261.643
…
523.286
…
1046.572
…
1976.284
2092.050
Relative scale of tone
C3 (130.813)
C3# (138.591)
D3 (146.832)
…
C4 (261.626)
…
C5 (523.251)
…
C6 (1046.502)
…
B6 (1975.533)
C7 (2093.005)
Fosc/1
Fosc/2
Fosc/4
Fosc/8
Fx32
P1.4
Vdd
Vss
TM0_CTL.0
MUX
TM0_CTL.1
TM0_CTL.2
reload
TM0L re-load buffer (W)
TM0H re-load buffer (W)
reload
Control
Logic
TM0_MOD.4
TM0_CTL.6
TM0_CTL.7
TM0_MOD.0
TM0_MOD.1
FTM0_UV/ 2
TM0_CTL.4
TM0_CTL.3
Vdd
P1.5
DIV0x
DIV1x
MUX
Fx32
Fosc/1
Fosc/2
Fosc/4
Fosc/8
TM0
Underflow
TM0
TM1L re-load buffer (W)
reload
TM1H re-load buffer (W)
reload
Control
Logic
TM1_CTL.6
TM1_CTL.7
TM1L (R)
MUX
Vdd
TM1_CTL.1
TM1_CTL.0
P1.3
TM0_CTL.4
/P1.4
Vss
TM1_CTL.2
TM0
Underflow
TM0H (R)
TM0L (R)
MUX
MUX
TM1H (R)
TM1
Underflow
CH1
Tone
FTM1_UV/ 2
TM1_CTL.4
TM1
P1.6
TM1_CTL.4
P1.7
CH2
Tone
FTM2_UV/ 2
TM2L (R)
TM2H (R)
TM2_CTL.6
TM2_CTL.7
MUX
Fx32
Fosc/1
Fosc/2
Fosc/4
Fosc/8
TM0
Underflow
TM1
Underflow
Vss
TM2_CTL.2
TM2
Underflow
Control
Logic
TM2L re-load buffer (W)
reload
TM2H re-load buffer (W)
reload
TM2
TM2_CTL.1
TM2_CTL.0
MEGAWIN
MLC0xxB Series Technical Summary
19
Timer2
Address
00E8H
00E9H
00EAH
Name
TM2_L
TM2_H
TM2_CTL
Bit 7
T7
T15
STC
Bit 6
T6
T14
RL/S
Bit 5
T5
T13
-
Bit 4
T4
T12
-
Bit 3
T3
T11
-
Bit 2
T2
T10
TKI2
Bit 1
T1
T9
TKI1
Bit 0
T0
T8
TKI0
R
W
√
√
√
√
√
√
STC: Start/Stop counting. 1: start and pre-load the value to counter, 0: stop timer clock
RL/S: Auto-reload disable/enable. 1: disable auto-reload, 0: enable auto-reload
TKI2
0
0
0
0
1
1
1
1
TKI1
0
0
1
1
0
0
1
1
Selected TM2 input clock source
FOSC / 1
FOSC / 2
FOSC / 4
FOSC / 8
TM0 underflow
FX32
TM1 underflow
VSS
TKI0
0
1
0
1
0
1
0
1
Input/Output Pin of the P0
Vdd
P0MR.1
Enable
Output
Buffer
DATA
BUS
I/O PIN
P0.n
Enable
P0CR.x
STA P0,#data
Instruction
P0MR.0
Enable
20
LDA buffer, P0
Instruction
MLC0xxB Series Technical Summary
MEGAWIN
I/O Ports
Port 0
Address
00D8H
0240H
0241H
Name
P0
P0CR
P0MR
Bit 7
P07
CP07
-
Bit 6
P06
CP06
MP06
Bit 5
P05
CP05
MP05
Bit 4
P04
CP04
MP04
Bit 3
P03
CP03
-
Bit 2
P02
CP02
MP02
Bit 1
P01
CP01
MP01
Bit 0
P00
CP00
MP00
R
W
√
√
√
√
√
√
Port 0 is an 8-bit I/O port; each pin can be programmed as input or output individually.
P0CR: p0.0~p0.7 is input or output. 0: input, 1: output
P0MR: p0.0~p0.7, pull-high, CMOS/NMOS and pull-high value setting
P0MR.0: P0.0 ~ P0.3 Pull-high control, 0: disable, 1:enable
P0MR.1: P0.0 ~ P0.3 CMOS/NMOS selector, 0: CMOS, 1:NMOS
P0MR.2: P0.0 ~ P0.3 Pull-high resistor value control, 0: large, 1: small
P0MR.4: P0.4 ~ P0.7 Pull-high control, 0: disable, 1: enable
P0MR.5: P0.4 ~ P0.7 CMOS/NMOS selector, 0: CMOS, 1:NMOS
P0MR.6: P0.4 ~ P0.7 Pull-high resistor value control, 0: large, 1: small (350K or 50K selector)
At initial reset, the port P0 is all in input mode. Each pin of port P0 can be specified as input or output
mode independently by the P0CR registers. When P0 is used as output port, CMOS or NMOS open
drain output type can be selected by the P0MR register. Port P0 has the internal pull-high resistors
that can be enabled/disabled by specifying the P0MR.0 and P0MR.4 respectively. The pull-high
resistors will be temporarily disable if the port is specified as output mode. The read value will be the
contents of output buffer in output mode. When P0 port is used as input mode and the RLH_EN, and
IRQ_EN corresponding to the P0 port are set, a signal change at the port P0 (any pin) will execute the
halt mode release or interrupt subroutine. Both the raising or falling signal will set the port P0 event.
The Schmitt trigger circuit is added in the input port part of all I/O pins.
Please set port 0 as output high before set it as input mode, if speeds up the internal pull-high effect is
needed. If the I/O ports are not used in your application, please set them as input with pull-high or
output mode to avoid unnecessary power consumption.
MEGAWIN
MLC0xxB Series Technical Summary
21
Port 1
Address
00D9H
0244H
0245H
Name
P1
P1CR
P1MR
Bit 7
P17
CP17
-
Bit 6
P16
CP16
-
Bit 5
P15
CP15
MP15
Bit 4
P14
CP14
MP14
Bit 3
P13
CP13
-
Bit 2
P12
CP12
-
Bit 1
P11
CP11
MP11
Bit 0
P10
CP10
MP10
R
W
√
√
√
√
√
√
Bit 3
PS3
Bit 2
-
Bit 1
-
Bit 0
-
R
W
√
√
Port 1 is an 8-bit I/O port; refer to port 0 for more information.
P1CR: P1.0 ~ P1.7 is input or output. 0: input, 1: output
P1MR: P1.0 ~ P1.7, pull-high and CMOS/NMOS
Port 1 multi-function selector
Address
00D5H
Name
P1_MFR
Bit 7
PS7
Bit 6
PS6
Bit 5
-
Bit 4
-
The port 1 can be programmed to special function via P1_MFR register. The serial input port is multiplex with
P1.4 and P1.5 (P1.4/CLK and P1.5/Din), the event counter input port is multiplex with P1.4 and P1.5, and the
Infrared control is multiplex with P1.3, P1.6 or P1.7
PS7, PS6, PS3: Normal I/O or TM2/TM1/TM0 carrier output selector. 0:normal I/O, 1: carrier output
Port 2
Address
00DAH
0248H
0249H
Name
P2
P2CR
P2MR
Bit 7
P27
CP27
-
Bit 6
P26
CP26
-
Bit 5
P25
CP25
MP25
Bit 4
P24
CP24
MP24
Bit 3
P23
CP23
-
Bit 2
P22
CP22
-
Bit 1
P21
CP21
MP21
Bit 0
P20
CP20
MP20
R
W
√
√
√
√
√
√
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
R
W
√
√
Port 2 is an 8-bit I/O port; refer to port 0 for more information.
P2CR: P2.0 ~ P2.7 is input or output. 0: input, 1: output
P2MR: P2.0 ~ P2.7, pull-high and CMOS/NMOS
Port 2 multi-function selector (P2.4/V-, P2.5/V+, P2.6/Vo)
Address
00D6H
Name
P2_MFR
Bit 7
-
Bit 6
PS6
Bit 5
-
Bit 4
-
PS6: Normal I/O or voltage comparator output selector of port 2.6. 0:normal I/O, 1: comparator output
22
MLC0xxB Series Technical Summary
MEGAWIN
Voltage comparator (P2.4/V-, P2.5/V+, P2.6/Vo)
Address
00F8H
Name
CMP_CTL
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
PWR
Bit 1
-
Bit 0
RLT
R
W
√
√
PWR: Voltage comparator power control. 0: power-off, 1: power-on
RLT: The voltage compare result. 0: V+ < V-, 1: V+ > VFosc/1
Fosc/2
Fosc/4
Fosc/8
FX32
P1.4
Vdd
Vss
MUX
TM0_CTL.0
TM0_CTL.1
TM0_CTL.2
TM0L re-load buffer (W)
reload
TM0H re-load buffer (W)
reload
Control
Logic
TM0_MOD.4
TM0L (R)
MUX
MUX
TM0_MOD.0
TM0_MOD.1
TM1_CTL.6
TM1_CTL.7
TM0H (R)
TM0
Underflow
FTM0_UV/ 2
Vdd
P1.5
DIV0x
DIV1x
TM0_CTL.4
TM0_CTL.3
TM0
TM0_CTL.4
P1.3
Use TM0 as series input buffer
Input/Output Pin of the P2
Vdd
P2MR.1
Enable
Output
Buffer
DATA
BUS
Enable
P2CR.x
STA P2,#data
Instruction
Analog
Switch
I/O PIN
P2.4
P2MR.0
LDA buffer, P2
Instruction
SEL
_
Store the
compare
result to a
register bit
+
Power
control
bit
Analog
Switch
I/O PIN
P2.5
Analog
Switch
I/O PIN
P2.6
To P2.5 I/O
Vdd
SEL
MEGAWIN
MLC0xxB Series Technical Summary
23
CH1 Buffer
Address
00E1H
Name
CH1
Bit 7
DA7
Bit 6
DA6
Bit 5
DA5
Bit 4
DA4
Bit 3
DA3
Bit 2
DA2
Bit 1
DA1
Bit 0
DA0
R
W
√
√
Temporary speech data output buffer. For playing a voice, the program could be coded as below:
LDA
STA
PCM
E1H
; Load PCM data into DAC buffer
; Latch 8-bit data (CH1) into DAC1 if directly mode is selected.
CH2, CH3 Buffer
Address
00E3H
00E5H
Name
CH2/ENV2
CH3/ENV3
Bit 7
DA7
DA7
Bit 6
DA6
DA6
Bit 5
DA5
DA5
Bit 4
DA4
DA4
Bit 3
DA3
DA3
Bit 2
DA2
DA2
Bit 1
DA1
DA1
Bit 0
DA0
DA0
R
W
√
√
√
√
Temporary speech data output buffer.
SPK1
Voice (L ch)
TM1H re-load buffer (W)
CH1 Buffer
Control
Logic
Voice (R ch)
TM1_CTL.6
TM1_CTL.7
Shift
TM1
Underflow
TM1H (R)
TM1
TM1_CTL.4
P1.6
VT_CTL.1
Data Bus
CH2
Tone
CH2 Buffer
Envelope
Process
Vss
CH3
Tone
VT_CTL.2
CH3 Buffer
TM2
Underflow
TM2H (R)
SPK2
Mixer
Vss
FTM2_UV/ 2
TM2_CTL.6
TM2_CTL.7
Control
Logic
Load
Data Latch Control Logic:
1. TM0 int. load
2. TM1 int. load
3. TM2 int. load
4. Directly
FTM1_UV/ 2
TM2H re-load buffer (W)
DAC1
reload
P1.7
Envelope
Process
DAC2
Load
Shift
Data Latch Control Logic:
1. TM0 int. load
2. TM1 int. load
3. TM2 int. load
4. Directly
reload
TM2
24
MLC0xxB Series Technical Summary
MEGAWIN
The CH2 and CH3 buffers could work as envelope setting registers that designed to control the output
level of tone. When they are set to be 80H, the output is at the lowest – no any tone output. After
stopping playing tone, the VT_CTL register should be set to voice mode and progress the fade out
subroutine to avoid the noise burst. Changing the envelope of a tone can create various timbre of
music. The waveform of normal square wave is like:
Program can create such waveforms as below through the envelope setting register.
(Envelope A)
(Envelope B)
The same tone with envelope A and B sounds very different. The tones with envelope-A sounds like
piano and envelope-B sounds like harmonica.
MEGAWIN
MLC0xxB Series Technical Summary
25
DAC buffer transfer control
Address
00F9H
Name
DB_TC
Bit 7
-
Bit 6
TC6
Bit 5
TC5
Bit 4
TC4
Bit 3
-
Bit 2
TC2
Bit 1
TC1
Bit 0
TC0
R
W
√
√
TC6 ~ TC4 control Ch2/Ch3, TC2 ~ TC0 control Ch1. Before disable all the DAC output, user must
progress the fade out subroutine to avoid the noise burst.
TC6: DAC2 enable control. 0: disable, 1:enable
TC5
0
0
1
1
DAC 2 buffer transfer control
Ch 2 / Ch3 buffer data transfer to DAC 2 after TM0 underflow
Ch 2 / Ch3 buffer data transfer to DAC 2 after TM1 underflow
Ch 2 / Ch3 buffer data transfer to DAC 2 after TM2 underflow
Ch 2 / Ch3 buffer data transfer to DAC 2 directly
TC4
0
1
0
1
TC2: DAC1 enable control. 0: disable, 1:enable
TC1
0
0
1
1
DAC 1 buffer transfer control
Ch 1 buffer data transfer to DAC 1 after TM0 underflow
Ch 1 buffer data transfer to DAC 1 after TM1 underflow
Ch 1 buffer data transfer to DAC 1 after TM2 underflow
Ch 1 buffer data transfer to DAC 1 directly
TC0
0
1
0
1
Voice/Tone control
Address
00FAH
Name
VT_CTL
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
VTS3
Bit 1
VTS2
Bit 0
-
R
W
√
√
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
DRV1
Bit 0
DRV0
R
W
√
√
Ch3, Ch2 voice/tone path control register.
VTS3: Ch 3 voice/tone control. 0: voice, 1:tone
VTS2: Ch 2 voice/tone control. 0: voice, 1:tone
DAC output current
Address
00FDH
Name
DAC_DRV
Bit 7
-
Bit 6
-
Program can select the driving current of DAC output to fit different bipolar junction transistor for
generating appropriate sound quality.
DRV1
0
0
1
1
26
DRV0
0
1
0
1
DAC output drive current (VDD = 3.0V)
1.30 mA (default)
1.84 mA
2.60 mA
3.67 mA
MLC0xxB Series Technical Summary
MEGAWIN
Programming Notice
The status after different reset condition is listed below:
Power on reset
Unknown
Unknown
Default value
SRAM Data
CPU Register
Special Function Register
CPU /RST pin reset
Unchanged
Unknown
Default value
Mask Option
Clock source
Fosc
WDT
Single / Dual
RC / Crystal
Enable / Disable
Application Circuit
1
2
3
4
VCC
VCC
SPK2
SPK1
U1
MLC0xxB_COB
D
D
8 Ohm
8 Ohm
SPK1
R6
620
VCC
SPK2
Q1
8050S
Q2
8050S
R7
620
VCC
32.768KHz
P0.0
36
35
34
33
32
31
30
29
28
27
SPK2
SPK1
C6
0.1uF
C5
20pF
VCC
Q3
8550
R8
P1.2
M1
470
VCC
+
P0.1
P0.2
P0.3
C10
47uF
A
R10
560
-
R14
100
Q4
8550
R9
P1.2
470
C
M2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
C4
20pF
X1
SPK2
AVDD
SPK1
AGND
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
VDD
OSCO
OSCI
GND
RES
TEST
X32O
X32I
P0.0
-
R12
750K
C
1
2
3
4
5
6
7
8
9
+
R1
430K
@4MHz
A
C1
47uF
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P1.0
P1.1
AA x 3
4.5V
C7
C8
0.1u
0.1u
R11
560
R5
200
VCC
R4
200
B
P0.0
P0.1
S00
S01
P0.0
P0.1
S02
P0.2
P0.3
S04
S05
P0.1
S06
P0.2
S03
P0.0
P0.3
S08
S09
P0.1
S10
P0.2
S07
P0.0
P0.3
Q8
8050S
S13
R3
200
Q5
8050S
Q6
8050S
B
S12
R15
1
LED 3
S14
P0.2
S11
LED 4
P0.3
S15
R2
200
LED 2
LED 1
Title
A
Size
MLC0xxB Series Typical Application Circuit
Number
Revision
A4
Date:
File:
1
MEGAWIN
2
3
MLC0xxB Series Technical Summary
A
16-May-2007
Sheet of
E:\User\Feng\SCH\MLC081 series\C081BSAP.ddb
Drawn By:
4
27
A
Pad Assignment
Vdd
1
OSCO
2
OSCI(R)
GND
3
4
SPK2
35
AVdd
34
SPK1
33
AGND
32
P1.7
5
31
P1.6
TEST
6
30
P1.5
X32O
7
29
P1.4
X32I
8
28
P1.3
P0.0
9
27
P1.2
/RES
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
25
26
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P1.0
P1.1
28
(0,0)
36
MLC0xxB Series Technical Summary
MEGAWIN
Absolute Maximum Rating
PARAMETER
Supply Voltage to Ground Potential
Applied Input / Output Voltage
Power Dissipation
Ambient Operating Temperature
Storage Temperature
RATING
-0.3 to +5.0
-0.3 to +5.0
60
0 to +70
-55 to +150
UNIT
V
V
mW
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC Characteristics
(VDD-VSS = 3.0 V, FOSC = 4MHz, Ta = 25° C; unless otherwise specified)
PARAMETER
Op. Voltage
Op. Current
SYM.
VDD
CONDITIONS
-
MIN.
2.4
TYP.
-
MAX.
5.5
UNIT
V
IOP
No load (Ext.-V)
-
1.5
5.1
mA
In normal operation
Standby Current
ISTB
No load (Ext.-V)
-
1
3
µA
DAC output driving current
IDAC
DAC_DRV = 00H
-
1.30
-
mA
DAC_DRV = 01H
-
1.84
-
Input High Voltage
VIH
DAC_DRV = 02H
-
2.60
-
DAC_DRV = 03H
-
3.67
-
-
0.8 VDD
-
VDD
V
Input Low Voltage
VIL
-
0
-
Port 0, 1, 2 drive current
IOH
VOH = 2.7V, VDD = 3.0V
-
1.5
0.2VDD
-
mA
V
Port 0, P1.4~1.7, P2.4~2.7
sink current
IOL0
VOL = 0.4V, VDD = 3.0V
-
3.0
-
mA
Port 1.0~1.3, 2.0~2.3
sink current
IOL1
VOL = 0.4V, VDD = 3.0V
-
9.0
-
mA
Internal Pull-high Resistor (L)
RPH0
VIL = 0V
-
350K
-
Ω
Internal Pull-high Resistor (S)
RPH1
VIL = 0V, port 0 only
-
50K
-
Ω
AC Characteristics
PARAMETER
CPU Op. Frequency
Frequency Deviation by
Voltage Drop for RC Oscillator
POR duration
MEGAWIN
SYM.
FCPU
CONDITIONS
RC/Crystal, VDD = 3.0V
MIN.
0.5
TYP.
4
MAX.
-
RC/Crystal, VDD = 5.0V
0.5
8
-
-
2
4
%
10
15
50
mS
∆f
f(3.0V) - f(2.4V)
f
TPOR
f(3.0V)
FOSC = 4 MHz
MLC0xxB Series Technical Summary
UNIT
MHz
29
History:
V0.10: Original
V0.20: Add FFEDH on the memory map diagram (page 6)
V0.30: Correct the SRS function definition (page 17, set this bit to 1 should be shift right)
V0.40: Add the description about the output mode of I/O port (page 21)
V0.50: Modify the typing error of page 21 (change 100K to 350K)
V0.60: Modify some typing mistakes
30
MLC0xxB Series Technical Summary
MEGAWIN