MOTOROLA Order this document by MJL16218/D SEMICONDUCTOR TECHNICAL DATA SCANSWITCH MJL16218* NPN Bipolar Power Deflection Transistor For High and Very High Resolution Monitors *Motorola Preferred Device POWER TRANSISTOR 15 AMPERES 1500 VOLTS — VCES 170 WATTS The MJL16218 is a state–of–the–art SWITCHMODE bipolar power transistor. It is specifically designed for use in horizontal deflection circuits for 20 mm diameter neck, high and very high resolution, full page, monochrome monitors. • • • • 1500 Volt Collector–Emitter Breakdown Capability Typical Dynamic Desaturation Specified (New Turn–Off Characteristic) Application Specific State–of–the–Art Die Design Fast Switching: 175 ns Inductive Fall Time (Typ) 2000 ns Inductive Storage Time (Typ) • Low Saturation Voltage: 0.2 Volts at 5.0 Amps Collector Current and 2.0 A Base Drive • Low Collector–Emitter Leakage Current — 250 µA Max at 1500 Volts — VCES • High Emitter–Base Breakdown Capability For High Voltage Off Drive Circuits — 8.0 Volts (Min) CASE 340G–02, STYLE 2 TO–3PBL MAXIMUM RATINGS Rating Collector–Emitter Breakdown Voltage Collector–Emitter Sustaining Voltage Emitter–Base Voltage Collector Current — Continuous — Pulsed (1) Base Current — Continuous — Pulsed (1) Maximum Repetitive Emitter–Base Avalanche Energy Total Power Dissipation @ TC = 25°C @ TC = 100°C Derated above TC = 25°C Operating and Storage Temperature Range Symbol Value Unit VCES VCEO(sus) VEBO 1500 Vdc 650 Vdc 8.0 Vdc IC ICM IB IBM W (BER) 15 20 Adc 7.0 14 Adc 0.2 mJ PD 170 39 1.49 Watts TJ, Tstg – 55 to 125 °C Symbol Max Unit RθJC 0.67 °C/W TL 275 °C W/°C THERMAL CHARACTERISTICS Characteristic Thermal Resistance — Junction to Case Lead Temperature for Soldering Purposes 1/8″ from the case for 5 seconds (1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle ≤ 10%. (2) Proper strike and creepage distance must be provided. Designer’s and SCANSWITCH are trademarks of Motorola, Inc. Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. Preferred devices are Motorola recommended choices for future use and best overall value. Motorola, Inc. 1997 Motorola Bipolar Power Transistor Device Data 1 MJL16218 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit ICES — — — — 250 25 µAdc IEBO V(BR)EBO VCEO(sus) — — 25 µAdc 8.0 11 — Vdc 650 — — Vdc OFF CHARACTERISTICS (2) Collector Cutoff Current (VCE = 1500 V, VBE = 0 V) (VCE = 1200 V, VBE = 0 V) Emitter–Base Leakage (VEB = 8.0 Vdc, IC = 0) Emitter–Base Breakdown Voltage (IE = 1.0 mA, IC = 0) Collector–Emitter Sustaining Voltage (Table 1) (IC = 10 mAdc, IB = 0) ON CHARACTERISTICS (2) Collector–Emitter Saturation Voltage (IC = 5.0 Adc, IB = 2.0 Adc) (IC = 3.0 Adc, IB = 0.6 Adc) Base–Emitter Saturation Voltage (IC = 5.0 Adc, IB = 1.0 Adc) VCE(sat) — — 0.17 0.14 1.0 0.5 Vdc VBE(sat) hFE — 0.9 1.5 Vdc DC Current Gain — 4.0 24 6.0 — — — tds Cob — 350 — ns — 300 500 pF fT — 0.8 — MHz (IC = 1.0 A, VCE = 5.0 Vdc) (IC = 12 A, VCE = 5.0 Vdc) DYNAMIC CHARACTERISTICS Dynamic Desaturation Interval (IC = 5.5 A, IB1 = 2.2 A, LB = 1.5 µH) Output Capacitance (VCE = 10 Vdc, IE = 0, ftest = 100 kHz) Gain Bandwidth Product (VCE = 10 Vdc, IC = 0.5 A, ftest = 1.0 MHz) SWITCHING CHARACTERISTICS Inductive Load (IC = 6.0 A, IB = 2.0 A), High Resolution Deflection Simulator Circuit Table 2 Storage Fall Time ns tsv tfi — — 2000 175 3000 250 (2) Pulse Test: Pulse Width = 300 µs, Duty Cycle ≤ 2.0%. SAFE OPERATING AREA 100 IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A) 18 10 10 ms 50 ms 1.0 100 ms 250 ms 0.1 IC/IB = 5 TJ ≤ 100°C 14 10 6 2 0.01 1.0 10 100 VCE, COLLECTOR–EMITTER VOLTAGE (V) Figure 1. Maximum Forward Bias Safe Operating Area 2 1000 0 300 600 900 1200 1500 VCE, COLLECTOR–EMITTER VOLTAGE (V) Figure 2. Maximum Reverse Bias Safe Operating Area Motorola Bipolar Power Transistor Device Data MJL16218 SAFE OPERATING AREA (continued) FORWARD BIAS 1 POWER DERATING FACTOR There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC – VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 1 is based on TC = 25_C; T J(pk) is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to 10% but must be derated when TC ≥ 25 _C. Second breakdown limitations do not derate the same as thermal limitations. Allowable current at the voltages shown on Figure 1 may be found at any case temperature by using the appropriate curve on Figure 3. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. SECOND BREAKDOWN DERATING 0.8 0.6 THERMAL DERATING 0.4 0.2 0 45 25 85 65 125 105 TC, CASE TEMPERATURE (°C) Figure 3. Power Derating REVERSE BIAS For inductive loads, high voltage and high current must be sustained simultaneously during turn–off, in most cases, with the base–to–emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe level at or below a specific value of collector current. This can be accomplished by several means such as active clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as Reverse Biased Safe Operating Area and represents the voltage– current condition allowable during reverse biased turnoff. This rating is verified under clamped conditions so that the device is never subjected to an avalanche mode. Figure 2 gives the RBSOA characteristics. Table 1. RBSOA/V(BR)CEO(SUS) Test Circuit 0.02 µF H.P. 214 OR EQUIV. P.G. 100 + V ≈ 11 V 2N6191 + 0 – 20 10 µF RB1 ≈ – 35 V A RB2 0.02 µF + – 50 2N5337 1 µF 500 100 T1 –V IC(pk) +V IC 0V *IC –V VCE(pk) L T1 (ICpk) [ LcoilVCC T1 adjusted to obtain IC(pk) T.U.T. A VCE MR856 50 *IB Vclamp IB1 VCC IB V(BR)CEO L = 10 mH RB2 = ∞ VCC = 20 Volts *Tektronix *P–6042 or *Equivalent Motorola Bipolar Power Transistor Device Data RBSOA L = 200 µH RB2 = 0 VCC = 20 Volts RB1 selected for desired IB1 IB2 Note: Adjust – V to obtain desired VBE(off) at Point A. 3 MJL16218 TYPICAL ELECTRICAL CHARACTERISTICS 1.0 1.0 IC/IB = 2.5 IC/IB = 5.0 100°C V, VOLTAGE (V) V, VOLTAGE (V) 100°C 25°C 0.1 0.01 25°C 0.1 0.01 0.1 1.0 0.1 10 IC, COLLECTOR CURRENT (A) Figure 4. Typical Collector–Emitter Saturation Voltage Figure 5. Typical Collector–Emitter Saturation Voltage IC/IB = 2.5 1.0 V BE , BASE–EMITTER VOLTAGE (V) V BE , BASE–EMITTER VOLTAGE (V) 10 10 10 25°C 100°C IC/IB = 5.0 1.0 25°C 100°C 0.1 0.1 0.1 4 1.0 IC, COLLECTOR CURRENT (A) 1.0 10 0.1 1.0 IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A) Figure 6. Typical Emitter–Base Saturation Voltage Figure 7. Typical Emitter–Base Saturation Voltage Motorola Bipolar Power Transistor Device Data 10 MJL16218 TYPICAL ELECTRICAL CHARACTERISTICS (continued) 100 100 HFE = 5.0 V H FE , DC CURRENT GAIN H FE , DC CURRENT GAIN HFE = 2.0 V 100°C 25°C 10 1.0 100°C 25°C 10 1.0 0.01 0.1 10 1.0 0.01 100 0.1 1.0 100 10 IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A) Figure 8. DC Current Gain Figure 9. DC Current Gain 1.0 25°C V, VOLTAGE (V) 100°C VBE(on) = 5.0 V 0.1 0.1 1.0 10 IC, COLLECTOR CURRENT (A) Figure 10. “On” Voltages Motorola Bipolar Power Transistor Device Data 5 MJL16218 DYNAMIC DESATURATION The SCANSWITCH series of bipolar power transistors are specifically designed to meet the unique requirements of horizontal deflection circuits in computer monitor applications. Historically, deflection transistor design was focused on minimizing collector current fall time. While fall time is a valid figure of merit, a more important indicator of circuit performance as scan rates are increased is a new characteristic, “dynamic desaturation.” In order to assure a linear collector current ramp, the output transistor must remain in hard saturation during storage time and exhibit a rapid turn–off transition. A sluggish transition results in serious consequences. As the saturation voltage of the output transistor increases, + 24 V Table 2. High Resolution Deflection Application Simulator U2 MC7812 VI G VO N D + R7 2.7 k R8 9.1 k C5 0.1 R3 250 SYNC Q1 (DC) R6 1k 8 7 OSC 6 VCC % OUT 1 GND R10 47 (IC) R5 1k (IB) + R9 470 C4 0.005 R2 R510 Q2 MJ11016 + C2 10 µF Q5 MJ11016 R1 1k 6.2 V C3 10 µF C6 100 µF + LY 100 V R11 470 1W Q3 MJE 15031 T1 U1 MC1391P 2 R12 470 1W BS170 T1: Ferroxcube Pot Core #1811 P3C8 Primary/Sec. Turns Ratio = 18:6 Gapped for LP = 30 µH CY D2 MUR460 VCE LB Q4 DUT R4 22 D1 MUR110 LB = 1.5 µH CY = 0.01 µF LY = 13 µH IB1 = 2.2 A IB2 = 4.5 A VCE , COLLECTOR–EMITTER VOLTAGE (V) C1 100 µF IB, BASE CURRENT (A) the voltage across the yoke drops. Roll off in the collector current ramp results in improper beam deflection and distortion of the image at the right edge of the screen. Design changes have been made in the structure of the SCANSWITCH series of devices which minimize the dynamic desaturation interval. Dynamic desaturation has been defined in terms of the time required for the VCE to rise from 1.0 to 5.0 volts (Figures 9 and 10) and typical performance at optimized drive conditions has been specified. Optimization of device structure results in a linear collector current ramp, excellent turn–off switching performance, and significantly lower overall power dissipation. 5 DYNAMIC DESATURATION TIME IS MEASURED FROM VCE = 1 V TO VCE = 5 V 4 3 2 1 tds 0 0 6 2 4 6 8 TIME (2 µs/DIV) TIME (ns) Figure 11. Deflection Simulator Circuit Base Drive Waveform Figure 12. Definition of Dynamic Desaturation Measurement Motorola Bipolar Power Transistor Device Data 10 MJL16218 PACKAGE DIMENSIONS 0.25 (0.010) M T B M –Q– –B– –T– C E U N A 1 R 2 L 3 –Y– P K W F 2 PL G J H D 3 PL 0.25 (0.010) M Y Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. DIM A B C D E F G H J K L N P Q R U W MILLIMETERS MIN MAX 2.8 2.9 19.3 20.3 4.7 5.3 0.93 1.48 1.9 2.1 2.2 2.4 5.45 BSC 2.6 3.0 0.43 0.78 17.6 18.8 11.0 11.4 3.95 4.75 2.2 2.6 3.1 3.5 2.15 2.35 6.1 6.5 2.8 3.2 INCHES MIN MAX 1.102 1.142 0.760 0.800 0.185 0.209 0.037 0.058 0.075 0.083 0.087 0.102 0.215 BSC 0.102 0.118 0.017 0.031 0.693 0.740 0.433 0.449 0.156 0.187 0.087 0.102 0.122 0.137 0.085 0.093 0.240 0.256 0.110 0.125 S STYLE 2: PIN 1. BASE 2. COLLECTOR 3. EMITTER CASE 340G–02 TO–3PBL ISSUE F Motorola reserves the right to make changes without further notice to any products herein. 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