TI1 CDCVF2505PW 3.3-v clock phase-lock loop clock driver Datasheet

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CDCVF2505
SCAS640G – JULY 2000 – REVISED AUGUST 2016
CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver
1 Features
3 Description
•
The CDCVF2505 is a high-performance, low-skew,
low-jitter, phase-lock loop (PLL) clock driver. This
device uses a PLL to precisely align the output clocks
(1Y[0-3] and CLKOUT) to the input clock signal
(CLKIN) in both frequency and phase. The
CDCVF2505 operates at 3.3 V and also provides
integrated series-damping resistors that make it ideal
for driving point-to-point loads.
1
•
•
•
•
•
•
•
•
•
•
•
Phase-Lock Loop Clock Driver for Synchronous
DRAM and General-Purpose Applications
Spread Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
Low Jitter (Cycle-to-Cycle): < |150 ps|
(Over 66 MHz to 200 MHz Range)
Distributes One Clock Input to One Bank of Five
Outputs (CLKOUT Used to Tune the Input-Output
Delay)
Three-States Outputs When There Is No Input
Clock
Operates From Single 3.3-V Supply
Available in 8-Pin TSSOP and 8-Pin SOIC
Packages
Consumes Less Than 100 mA (Typical) in PowerDown Mode
Internal Feedback Loop Is Used to Synchronize
the Outputs to the Input Clock
25-Ω On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates the
Need for External Components
One bank of five outputs provides low-skew, low-jitter
copies of CLKIN. Output duty cycles are adjusted to
50 percent, independent of duty cycle at CLKIN. The
device automatically goes into power-down mode
when no input signal is applied to CLKIN.
The loop filter for the PLLs is included on-chip. This
minimizes the component count, space, and cost.
The CDCVF2505 is characterized for operation from
–40°C to 85°C.
Device Information(1)
PART NUMBER
CDCVF2505
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.90 mm
TSSOP (8)
4.40 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
Synchronous DRAMs
Industrial Applications
General-Purpose Zero-Delay Clock Buffers
Functional Block Diagram
8
CLKIN
1
PLL
25 W
3
25 W
CLKOUT
1Y0
2
1Y1
25 W
Power Down
5
25 W
7
25 W
Edge Detect
Typical <10 MHz
1Y2
1Y3
3-State
B0246-01
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCVF2505
SCAS640G – JULY 2000 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
9.1 Overview ................................................................... 8
9.2 Functional Block Diagram ......................................... 8
9.3 Feature Description................................................... 8
9.4 Device Functional Modes.......................................... 9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ................................................ 10
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2012) to Revision G
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Changed RθJA value for D package from 165.5 : to 112.3°C/W ............................................................................................. 4
•
Changed RθJA value for PW package from 230.5112.3°C/W : to 175.8°C/W......................................................................... 4
•
Updated values in the Thermal Information table to align with JEDEC standards. ............................................................... 4
2
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5 Description (continued)
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of
the feedback signal to the reference signal. This stabilization is required following power up and application of a
fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
6 Pin Configuration and Functions
D or PW Package
8-Pin SOIC or TSSOP
Top View
CLKIN
1
8
CLKOUT
1Y1
2
7
1Y3
1Y0
3
6
VDD3.3V
GND
4
5
1Y2
Not to scale
Pin Functions
PIN
NAME
NO.
1Y[0–3]
2, 3, 5, 7
TYPE (1)
DESCRIPTION
O
Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated
25-Ω series damping resistor.
CLKIN
1
I
Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock
driver. CLKIN is used to provide the reference signal to the integrated PLL that generates the
clock output signals. CLKIN must have a fixed frequency and fixed phase for the PLL to
obtain phase lock. Once the circuit is powered up and a valid signal is applied, a stabilization
time (100 µs) is required for the PLL to phase lock the feedback signal to CLKIN.
CLKOUT
8
O
Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection
is made inside the chip and an external feedback loop should NOT be connected. CLKOUT
can be loaded with a capacitor to achieve zero delay between CLKIN and the Y outputs.
GND
4
P
Ground
VDD3.3V
6
P
3.3-V supply
(1)
I = Input, O = Output, and P = Power
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage
(2) (3)
MIN
MAX
UNIT
–0.5
4.3
V
–0.5
VDD + 0.5
V
–0.5
VDD + 0.5
V
VI
Input voltage
VO
Output voltage (2) (3)
IIK
Input clamp current (VI < 0 or VI > VDD)
±50
mA
IOK
Output clamp current (VO < 0 or VO > VDD)
±50
mA
IO
Continuous total output current (VO = 0 to VDD)
±50
mA
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.3 V maximum.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±300
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
3
3.3
3.6
UNIT
VDD
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VDD
V
IOH
High-level output current
–12
mA
IOL
Low-level output current
12
mA
TA
Operating free-air temperature
85
°C
0.7 VDD
V
V
0.3 VDD
0
–40
V
7.4 Thermal Information
CDCVF2505
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
8 PINS
8 PINS
UNIT
175.8
°C/W
RθJA
Junction-to-ambient thermal resistance (2)
112.3
RθJC(top)
Junction-to-case (top) thermal resistance
55.8
61.8
°C/W
RθJB
Junction-to-board thermal resistance
53.1
104.3
°C/W
ψJT
Junction-to-top characterization parameter
12.8
7.7
°C/W
ψJB
Junction-to-board characterization parameter
52.5
102.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input voltage
MIN
II = –18 mA, VDD = 3 V
IOH = –100 µA, VDD = MIN to MAX
VOH
TYP (1)
High-level output voltage
Low-level output voltage
IOH = –12 mA, VDD = 3 V
2.1
IOH = –6 mA, VDD = 3 V
2.4
V
0.2
0.8
0.55
VO = 1 V, VDD = 3 V
IOL
Low-level output current
II
Input current
VI = 0 V or VDD
CI
Input capacitance
VI = 0 V or VDD, VDD = 3.3 V
(1)
V
IOH = 6 mA, VDD = 3 V
High-level output current
Output capacitance
–1.2
IOH = 12 mA, VDD = 3 V
IOH
Co
UNIT
VDD – 0.2
IOH = 100 µA, VDD = MIN to MAX
VOL
MAX
–27
VO = 1.65 V, VDD = 3.3 V
mA
–36
VO = 2 V, VDD = 3 V
27
VO = 1.65 V, VDD = 3.3 V
VI = 0 V or VDD, VDD = 3.3 V
V
mA
40
±5
µA
4.2
Yn
2.8
CLKOUT
5.2
pF
pF
All typical values are at respective nominal VDD and 25°C
7.6 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
MHz
SUPPLY VOLTAGE, VDD = 3.3 V ±0.3 V
fclk
Clock frequency
Input clock duty cycle
24
200
24 MHz to 85 MHz (1)
30%
85%
86 MHz to 200 MHz
40%
50%
Stabilization time (2)
60%
100
µs
MHz
SUPPLY VOLTAGE, VDD = 2.7 V
fclk
Clock frequency
Input clock duty cycle
Stabilization time
(1)
(2)
42
166
42 MHz to 85 MHz (1)
30%
70%
86 MHz to 166 MHz
40%
(2)
50%
60%
100
µs
Assured by design but not 100% production tested
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for
propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not
apply for input modulation under SSC application.
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7.7 Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF, VDD = 3.3 V ±0.3 V (1)
PARAMETER
TEST CONDITIONS
Propagation delay, normalized
(see Figure 2)
tpd
tsk(o)
Output skew
CLKIN to Yn, f = 66 MHz to 200 MHz
(3)
MAX
UNIT
150
ps
150
ps
f = 66 MHz to 200 MHz
70
150
f = 24 MHz to 50 MHz
200
400
Jitter (cycle-to-cycle)
(see Figure 4)
odc
Output duty cycle
(see Figure 3)
f = 24 MHz to 200 MHz at 50% VDD
tr
Rise time
tf
Fall time
(2)
(3)
–150
Yn to Yn
tc(jit_cc)
(1)
TYP (2)
MIN
ps
45%
55%
VO = 0.4 V to 2 V
0.5
2
ns
VO = 2 V to 0.4 V
0.5
2
ns
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for
propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not
apply for input modulation under SSC application.
All typical values are at respective nominal VDD and 25°C
The tsk(o) specification is only valid for equal loading of all outputs.
7.8 Typical Characteristics
at 3.3 V, 25°C (unless otherwise noted)
500
150
tpd − Propagation Delay Time − ps
tpd − Propagation Delay Time − ps
Load: CLKOUT = 12 pF || 500 W,
Yn = 25 pF || 500 W
400
300
200
100
0
Load: CLKOUT = 21 pF || 500 W,
Yn = 25 pF || 500 W
100
50
0
−50
−100
−150
25
50
75
100
125
150
175
200
0
50
f − Frequency − MHz
200
Figure 2. tpd, Typical Propagation Delay Time
vs Frequency (Tuned for Minimum Delay)
500
55.0
Typical Values @ 3.3 V,
TA = 25°C
tc(jit_CC) − Cycle-to-Cycle Jitter − ps
Load: CLKOUT = 12 pF || 500 W,
Yn = 25 pF || 500 W
52.5
Duty Cycle − %
150
G003
Figure 1. tpd, Propagation Delay Time vs Frequency
50.0
47.5
400
300
200
100
0
45.0
25
50
75
100
125
150
175
200
25
50
75
100
125
150
175
200
f − Frequency − MHz
f − Frequency − MHz
G004
Figure 3. Duty Cycle vs Frequency
6
100
f − Frequency − MHz
G002
G005
Figure 4. Cycle-Cycle Jitter vs Frequency
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8 Parameter Measurement Information
From Output Under Test
Yn = 25 pF || 500 W
CLKOUT = 12 pF || 500 W
500 W
S0283-01
Figure 5. Test Load Circuit
3V
50% VDD
CLKIN
0V
tpd
2V
1Y0–1Y3
0.4 V
tr
VOH
2V
50% VDD
0.4 V
VOL
tf
T0262-01
Figure 6. Voltage Threshold for Measurements, Propagation Delay (Tpd)
Any Y
50 % VDD
tsk(o)
Any Y
50 % VDD
T0263-01
Figure 7. Output Skew
tc1
tc2
tc(jit_CC) = tc1 – tc2
T0264-01
Figure 8. Cycle-to-Cycle Jitter
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9 Detailed Description
9.1 Overview
The CDCVF2505 is designed for synchronous DRAM in server systems. This makes the device ideal for
applications which require the lowest possible skew between a provided reference clock and the clock copies
generated from the internal oscillator. At the same time, the phase-locked-loop has a high enough bandwidth to
track a spread-spectrum reference clock.
9.2 Functional Block Diagram
8
CLKIN
1
PLL
25 W
3
25 W
CLKOUT
1Y0
2
1Y1
25 W
Power Down
5
25 W
7
25 W
Edge Detect
Typical <10 MHz
1Y2
1Y3
3-State
B0246-01
Copyright © 2016, Texas Instruments Incorporated
9.3 Feature Description
The CDCVF2505 provides a single high-impedance reference input to a phase-locked-loop circuit (PLL). The
reference is directly fed to a phase comparator. The control circuit loop filter is integrated into the device. The
oscillator output is fed to a clock tree with five output buffers. One of them is used as feedback to close the loop
of the PLL circuit. (4) The feedback path is designed for lowest phase difference or skew seen between reference
input and outputs. With respect to the supported reference frequency range the seen phase difference is
negligible to the clock period. Thus the CDCVF2505 is categorized as a Zero Delay PLL.
The CDCVF2505 contains an reference clock detector. This edge detector connected to CLKIN pin automatically
powers down the PLL and tri-states the output buffers to save power, as soon as the input reference frequency
goes below the minimum operating frequency range.
(4)
8
The CLKOUT pin shall not be used to drive a trace, but only for delay tuning.
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9.4 Device Functional Modes
The device has two functional modes: active and power down.
The CDCVF2505 automatically switches from active to power down, and vice versa, when the detected CLKIN
reference frequency is low. The PLL automatically switches on and tries to lock to the reference clock as soon as
the input frequency exceeds 20 MHz (typical). The PLL switches off and tri-states the output buffers when the
input frequency goes below 12 MHz (typical).
Table 1. Function Table
INPUT
(1)
OUTPUTS
CLKIN
1Y (0:3)
L
L
CLKOUT
L
H
H
H
≤1 MHz (1)
Z
Z
Full device functionality is specified for frequencies equal to or higher
than 24 MHz. Below 1 MHz, the device goes in power-down mode in
which the PLL is turned off and the outputs enter into Hi-Z mode.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The CDCVF2505 is designed for ease of use. The internal PLL operates without additional configuration required
by the user.
10.2 Typical Application
Data
SDRAM
Memory
Controller
Clock
Data
SDRAM
CDCVF2505
SDRAM
SDRAM
Copyright © 2016, Texas Instruments Incorporated
Figure 9. Typical SDRAM Application
10.2.1 Design Requirements
The CLKOUT pin can be used to optimize the feedback delay using discrete capacitors placed at the pin to
introduce additional delay on the feedback signal.
10.2.2 Detailed Design Procedure
The following steps describe how to optimize the propagation delay of the PLL:
• Determine the average output load seen by all clock outputs Y[3:0].
• Decide how the phase relationship between the CLKIN reference and the clock outputs shall be:
– zero delay
– leading CLKIN phase with respect to Y[3:0].
– lagging CLKIN phase with respect to Y[3:0].
• Look up an initial typical value for the delta load using Figure 10:
– for zero delay: match the loading
– for leading CLKIN phase: load CLKOUT less than Y[3:0]
– for lagging CLKIN phase: load CLKOUT more than Y[3:0]
10
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Typical Application (continued)
10.2.3 Application Curves
1400
120
Yn = 25 pF
Yn = 3 pF
Worst Case @ VCC = 3.6 V, TA = 85°C,
Load: Y and CLKOUT = 25 pF || 500 W
CLKOUT = Yn =
25 pF || 500 W
3 pF || 500 W
700
100
ICC − Supply Current − mA
tpd − Propagation Delay Time − ps
1050
350
CLKOUT
3 pF to 25 pF
0
−13
−4
−350
CLKOUT
3 pF to 25 pF
−700
80
60
40
20
−1050
−1400
−30
0
−20
−10
0
10
20
30
0
Delta Load − pF
20
40
60
80 100 120 140 160 180 200
f − Frequency − MHz
G001
G006
Delta load = CLKOUT load – Yn load
Clock frequency, f = 100 MHz
Figure 10. tpd, Propagation Delay Time vs Delta Load
Figure 11. ICC, Supply Current vs Frequency
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11 Power Supply Recommendations
The power supply decoupling can be optimized to the power plane capacitance and resonance, which is
determined by the circuit board size and dielectric material for the buffered frequency of interest. Details can be
found in Design and Layout Guidelines for the CDCVF2505 Clock Driver (SCAA045). For basic functionality, the
device shall receive at least 100 nF as local decoupling capacitor.
12 Layout
12.1 Layout Guidelines
TI recommends the following layout guidelines for designing in the CDCVF2505 on a printed-circuit board:
• Provide a full ground or reference plane for the clock traces and the decoupling section.
• Ground floods including stitching using VIAs help prevent the clock injecting spectral lines to surrounding
components.
• The decoupling must be placed very close to the device package. The decoupling capacitors can also be
placed on the bottom layer of the board. See Design and Layout Guidelines for the CDCVF2505 Clock Driver
(SCAA045) for detailed recommendations.
• The CLKOUT pin can have a very short connection to tuning capacitors for the internal feedback.
12.2 Layout Example
Place delay tuning
capacitors, depending
on the clock output
loading.
Provide full reference plane for clock
signals until receiver. (grey plane)
Provide
low
inductance and
resistance
connection for
supply
and
reference pins.
VDD3.3V
1 nF
2.2 nF 10 nF
47 nF
1 PF
Place
decoupling
capacitors
on
bottom layer of
PCB between
pin 4 and 6. On
top layer next
to pin 4 and 5.
Figure 12. Layout Illustration
12
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
Design and Layout Guidelines for the CDCVF2505 Clock Driver (SCAA045)
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CDCVF2505D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV05
CDCVF2505DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV05
CDCVF2505DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV05
CDCVF2505DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV05
CDCVF2505PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV05
CDCVF2505PWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV05
CDCVF2505PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV05
CDCVF2505PWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV05
HPA00771PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV05
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCVF2505DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
CDCVF2505PWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCVF2505DR
SOIC
D
8
2500
367.0
367.0
38.0
CDCVF2505PWR
TSSOP
PW
8
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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