Renesas H8S2649 Renesas 16-bit single-chip microcomputer h8s family/h8s/2600 sery Datasheet

REJ09B0200-0200
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2649 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2600 Series
H8S/2649
Rev.2.00
Revision Date: Dec. 05, 2005
HD64F2649
HD6432649
Rev. 2.00 Dec. 05, 2005 Page ii of xxxviii
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 2.00 Dec. 05, 2005 Page iii of xxxviii
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 2.00 Dec. 05, 2005 Page iv of xxxviii
Configuration of This Manual
This manual comprises the following items:
1.
2.
3.
4.
5.
6.
General Precautions on Handling of Product
Configuration of This Manual
Preface
Contents
Overview
Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 2.00 Dec. 05, 2005 Page v of xxxviii
Preface
The H8S/2649 Group single-chip microcomputer is made up of the high-speed H8S/2600 CPU as
its core, and the peripheral functions required configuring a system. The H8S/2600 CPU has an
instruction set that is compatible with the H8/300 and H8/300H CPUs.
Target Users: This manual was written for users who will be using the H8S/2649 Group in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2649 Group to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions, and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 22,
List of Registers.
Examples: Register name:
The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev. 2.00 Dec. 05, 2005 Page vi of xxxviii
H8S/2649 Group manuals:
Document Title
Document No.
H8S/2649 Group Hardware Manual
This manual
H8S/2600 Series, H8S/2000 Series Programming Manual
REJ09B0139
User's manuals for development tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
REJ10B0058
Microcomputer Development Environment System H8S, H8/300 Series
Simulator/Debugger User's Manual
ADE-702-282
H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial
REJ10B0024
H8S, H8/300 Series High-performance Embedded Workshop 3 User's
Manual
REJ10B0026
Rev. 2.00 Dec. 05, 2005 Page vii of xxxviii
Rev. 2.00 Dec. 05, 2005 Page viii of xxxviii
Contents
Section 1 Overview................................................................................................1
1.1
1.2
1.3
Features.................................................................................................................................. 1
Internal Block Diagram.......................................................................................................... 2
Pin Assignments..................................................................................................................... 3
1.3.1 Pin Assignments ....................................................................................................... 3
1.3.2 Pin Functions in Each Operating Mode .................................................................... 4
1.3.3 Pin Functions .......................................................................................................... 10
Section 2 CPU......................................................................................................15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Features................................................................................................................................ 15
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 16
2.1.2 Differences from H8/300 CPU ............................................................................... 17
2.1.3 Differences from H8/300H CPU............................................................................. 17
CPU Operating Modes......................................................................................................... 18
2.2.1 Normal Mode.......................................................................................................... 18
2.2.2 Advanced Mode...................................................................................................... 20
Address Space...................................................................................................................... 22
Registers............................................................................................................................... 23
2.4.1 General Registers.................................................................................................... 24
2.4.2 Program Counter (PC) ............................................................................................ 25
2.4.3 Extended Control Register (EXR) .......................................................................... 25
2.4.4 Condition-Code Register (CCR)............................................................................. 26
2.4.5 Multiply-Accumulate Register (MAC)................................................................... 27
2.4.6 Initial Values of CPU Registers .............................................................................. 27
Data Formats........................................................................................................................ 28
2.5.1 General Register Data Formats ............................................................................... 28
2.5.2 Memory Data Formats ............................................................................................ 30
Instruction Set ...................................................................................................................... 31
2.6.1 Table of Instructions Classified by Function .......................................................... 32
2.6.2 Basic Instruction Formats ....................................................................................... 42
Addressing Modes and Effective Address Calculation........................................................ 43
2.7.1 Register DirectRn ............................................................................................... 43
2.7.2 Register Indirect@ERn ....................................................................................... 43
2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)................. 44
2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn..... 44
2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32....................................... 44
Rev. 2.00 Dec. 05, 2005 Page ix of xxxviii
2.8
2.9
2.7.6 Immediate#xx:8, #xx:16, or #xx:32.................................................................... 45
2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC) ...................................... 45
2.7.8 Memory Indirect@@aa:8 ................................................................................... 45
2.7.9 Effective Address Calculation ................................................................................ 46
Processing States.................................................................................................................. 49
Usage Note........................................................................................................................... 51
2.9.1 Notes on Using the Bit Operation Instruction......................................................... 51
Section 3 MCU Operating Modes ....................................................................... 53
3.1
3.2
3.3
3.4
3.5
Operating Mode Selection ................................................................................................... 53
Register Descriptions........................................................................................................... 54
3.2.1 Mode Control Register (MDCR) ............................................................................ 54
3.2.2 System Control Register (SYSCR)......................................................................... 55
Operating Mode Descriptions .............................................................................................. 56
3.3.1 Mode 4.................................................................................................................... 56
3.3.2 Mode 5.................................................................................................................... 56
3.3.3 Mode 6.................................................................................................................... 56
3.3.4 Mode 7.................................................................................................................... 56
Pin Functions in Each Operating Mode ............................................................................... 57
Address Map ........................................................................................................................ 58
Section 4 Exception Handling ............................................................................. 59
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Exception Handling Types and Priority............................................................................... 59
Exception Sources and Exception Vector Table .................................................................. 60
Reset .................................................................................................................................... 61
4.3.1 Reset Exception Handling ...................................................................................... 61
4.3.2 Interrupts after Reset............................................................................................... 64
4.3.3 State of On-Chip Peripheral Modules after Reset Release ..................................... 64
Traces................................................................................................................................... 64
Interrupts.............................................................................................................................. 65
Trap Instruction.................................................................................................................... 66
Stack Status after Exception Handling................................................................................. 67
Usage Note........................................................................................................................... 68
Section 5 Interrupt Controller.............................................................................. 69
5.1
5.2
5.3
Features................................................................................................................................ 69
Input/Output Pins................................................................................................................. 71
Register Descriptions........................................................................................................... 72
5.3.1 Interrupt Priority Registers A to H, J, K, M, and O
(IPRA to IPRH, IPRJ, IPRK, IPRM, and IPRO) .................................................... 73
Rev. 2.00 Dec. 05, 2005 Page x of xxxviii
5.4
5.5
5.6
5.7
5.3.2 IRQ Enable Register (IER) ..................................................................................... 74
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)........................................ 75
5.3.4 IRQ Status Register (ISR)....................................................................................... 77
Interrupt Sources.................................................................................................................. 78
5.4.1 External Interrupts .................................................................................................. 78
5.4.2 Internal Interrupts ................................................................................................... 79
Interrupt Exception Handling Vector Table......................................................................... 79
Interrupt Control Modes and Interrupt Operation ................................................................ 83
5.6.1 Interrupt Control Mode 0 ........................................................................................ 83
5.6.2 Interrupt Control Mode 2 ........................................................................................ 85
5.6.3 Interrupt Exception Handling Sequence ................................................................. 87
5.6.4 Interrupt Response Times ....................................................................................... 89
5.6.5 DTC Activation by Interrupt................................................................................... 90
Usage Notes ......................................................................................................................... 91
5.7.1 Conflict between Interrupt Generation and Disabling ............................................ 91
5.7.2 Instructions that Disable Interrupts ......................................................................... 92
5.7.3 When Interrupts Are Disabled ................................................................................ 92
5.7.4 Interrupts during Execution of EEPMOV Instruction............................................. 92
Section 6 PC Break Controller (PBC) .................................................................93
6.1
6.2
6.3
6.4
Features................................................................................................................................ 93
Register Descriptions ........................................................................................................... 94
6.2.1 Break Address Register A (BARA) ........................................................................ 94
6.2.2 Break Address Register B (BARB) ........................................................................ 95
6.2.3 Break Control Register A (BCRA) ......................................................................... 95
6.2.4 Break Control Register B (BCRB).......................................................................... 96
Operation ............................................................................................................................. 96
6.3.1 PC Break Interrupt Due to Instruction Fetch .......................................................... 96
6.3.2 PC Break Interrupt Due to Data Access.................................................................. 97
6.3.3 PC Break Operation at Consecutive Data Transfer................................................. 97
6.3.4 Operation in Transitions to Power-Down Modes ................................................... 97
6.3.5 When Instruction Execution Is Delayed by One State............................................ 99
Usage Notes ....................................................................................................................... 100
6.4.1 Module Stop Mode Setting ................................................................................... 100
6.4.2 PC Break Interrupts .............................................................................................. 100
6.4.3 CMFA and CMFB ................................................................................................ 100
6.4.4 PC Break Interrupt when DTC Is Bus Master ...................................................... 100
6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP,
TRAPA, RTE, or RTS Instruction ........................................................................ 100
6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction ........................................ 100
Rev. 2.00 Dec. 05, 2005 Page xi of xxxviii
6.4.7
6.4.8
PC Break Set for Instruction Fetch at Address Following Bcc Instruction........... 101
PC Break Set for Instruction Fetch at Branch Destination Address
of Bcc Instruction ................................................................................................. 101
Section 7 Bus Controller (BSC) ........................................................................ 103
7.1
7.2
7.3
Features.............................................................................................................................. 103
Input/Output Pins............................................................................................................... 105
Register Descriptions......................................................................................................... 105
7.3.1 Bus Width Control Register (ABWCR) ............................................................... 106
7.3.2 Access State Control Register (ASTCR) .............................................................. 106
7.3.3 Wait Control Registers H and L (WCRH and WCRL)......................................... 107
7.3.4 Bus Control Register H (BCRH) .......................................................................... 109
7.3.5 Bus Control Register L (BCRL) ........................................................................... 110
7.3.6 Pin Function Control Register (PFCR) ................................................................. 111
7.4 Bus Control........................................................................................................................ 112
7.4.1 Area Division........................................................................................................ 112
7.4.2 Bus Specifications ................................................................................................ 113
7.4.3 Memory Interfaces................................................................................................ 114
7.5 Basic Bus Interface ............................................................................................................ 115
7.5.1 Data Size and Data Alignment.............................................................................. 115
7.5.2 Valid Strobes ........................................................................................................ 117
7.5.3 Basic Timing......................................................................................................... 118
7.5.4 Wait Control ......................................................................................................... 125
7.6 Burst ROM Interface ......................................................................................................... 127
7.6.1 Basic Timing......................................................................................................... 127
7.6.2 Wait Control ......................................................................................................... 129
7.6.3 Write Access......................................................................................................... 129
7.7 Idle Cycle........................................................................................................................... 130
7.7.1 Operation .............................................................................................................. 130
7.7.2 Pin States in Idle Cycle......................................................................................... 132
7.8 Write Data Buffer Function ............................................................................................... 133
7.9 Bus Arbitration .................................................................................................................. 134
7.9.1 Operation .............................................................................................................. 134
7.9.2 Bus Transfer Timing............................................................................................. 134
7.10 Bus Controller Operation in Reset ..................................................................................... 135
Section 8 Data Transfer Controller (DTC)........................................................ 137
8.1
8.2
Features.............................................................................................................................. 137
Register Descriptions......................................................................................................... 139
8.2.1 DTC Mode Register A (MRA) ............................................................................. 140
Rev. 2.00 Dec. 05, 2005 Page xii of xxxviii
8.3
8.4
8.5
8.6
8.7
8.8
8.2.2 DTC Mode Register B (MRB).............................................................................. 141
8.2.3 DTC Source Address Register (SAR)................................................................... 142
8.2.4 DTC Destination Address Register (DAR)........................................................... 142
8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 142
8.2.6 DTC Transfer Count Register B (CRB)................................................................ 142
8.2.7 DTC Enable Registers A to G, and I (DTCERA to DTCERG, and DTCERI) ..... 143
8.2.8 DTC Vector Registers A to G (DTVECRA to DTVECRG)................................. 144
Activation Sources ............................................................................................................. 145
Location of Register Information and DTC Vector Table ................................................. 146
Operation ........................................................................................................................... 149
8.5.1 Normal Mode........................................................................................................ 150
8.5.2 Repeat Mode ......................................................................................................... 151
8.5.3 Block Transfer Mode ............................................................................................ 152
8.5.4 Chain Transfer ...................................................................................................... 154
8.5.5 Interrupts............................................................................................................... 155
8.5.6 Operation Timing.................................................................................................. 155
8.5.7 Number of DTC Execution States ........................................................................ 156
Procedures for Using DTC................................................................................................. 158
8.6.1 Activation by Interrupt.......................................................................................... 158
8.6.2 Activation by Software ......................................................................................... 158
Examples of Use of the DTC ............................................................................................. 159
8.7.1 Normal Mode........................................................................................................ 159
8.7.2 Chain Transfer ...................................................................................................... 160
8.7.3 Software Activation .............................................................................................. 161
Usage Notes ....................................................................................................................... 162
8.8.1 Module Stop Mode Setting ................................................................................... 162
8.8.2 On-Chip RAM ...................................................................................................... 162
8.8.3 DTCE Bit Setting.................................................................................................. 162
Section 9 I/O Ports .............................................................................................163
9.1
9.2
Port 1.................................................................................................................................. 168
9.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 168
9.1.2 Port 1 Data Register (P1DR)................................................................................. 169
9.1.3 Port 1 Register (PORT1)....................................................................................... 169
9.1.4 Pin Functions ........................................................................................................ 170
Port 2.................................................................................................................................. 178
9.2.1 Port 2 Data Direction Register (P2DDR).............................................................. 178
9.2.2 Port 2 Data Register (P2DR)................................................................................. 179
9.2.3 Port 2 Register (PORT2)....................................................................................... 179
9.2.4 Pin Functions ........................................................................................................ 180
Rev. 2.00 Dec. 05, 2005 Page xiii of xxxviii
9.3
9.4
9.5
9.6
9.7
9.8
9.9
Port 3.................................................................................................................................. 188
9.3.1 Port 3 Data Direction Register (P3DDR).............................................................. 188
9.3.2 Port 3 Data Register (P3DR) ................................................................................ 189
9.3.3 Port 3 Register (PORT3)....................................................................................... 189
9.3.4 Port 3 Open-Drain Control Register (P3ODR) ..................................................... 190
9.3.5 Pin Functions ........................................................................................................ 190
Port 4.................................................................................................................................. 193
9.4.1 Port 4 Register (PORT4)....................................................................................... 193
9.4.2 Pin Functions ........................................................................................................ 193
Port 5.................................................................................................................................. 194
9.5.1 Port 5 Data Direction Register (P5DDR).............................................................. 194
9.5.2 Port 5 Data Register (P5DR) ................................................................................ 194
9.5.3 Port 5 Register (PORT5)....................................................................................... 195
9.5.4 Pin Functions ........................................................................................................ 195
Port 9.................................................................................................................................. 196
9.6.1 Port 9 Register (PORT9)....................................................................................... 196
9.6.2 Pin Functions ........................................................................................................ 196
Port A................................................................................................................................. 197
9.7.1 Port A Data Direction Register (PADDR)............................................................ 197
9.7.2 Port A Data Register (PADR)............................................................................... 198
9.7.3 Port A Register (PORTA)..................................................................................... 198
9.7.4 Port A Pull-Up MOS Control Register (PAPCR) ................................................. 199
9.7.5 Port A Open-Drain Control Register (PAODR) ................................................... 199
9.7.6 Pin Functions ........................................................................................................ 200
9.7.7 MOS Input Pull-Up Function ............................................................................... 201
Port B ................................................................................................................................. 202
9.8.1 Port B Data Direction Register (PBDDR) ............................................................ 202
9.8.2 Port B Data Register (PBDR) ............................................................................... 203
9.8.3 Port B Register (PORTB) ..................................................................................... 203
9.8.4 Port B Pull-Up MOS Control Register (PBPCR) ................................................. 204
9.8.5 Port B Open-Drain Control Register (PBODR).................................................... 204
9.8.6 Pin Functions ........................................................................................................ 205
9.8.7 MOS Input Pull-Up Function ............................................................................... 205
Port C ................................................................................................................................. 206
9.9.1 Port C Data Direction Register (PCDDR) ............................................................ 206
9.9.2 Port C Data Register (PCDR) ............................................................................... 207
9.9.3 Port C Register (PORTC) ..................................................................................... 207
9.9.4 Port C Pull-Up MOS Control Register (PCPCR) ................................................. 208
9.9.5 Port C Open-Drain Control Register (PCODR).................................................... 208
9.9.6 Pin Functions ........................................................................................................ 209
Rev. 2.00 Dec. 05, 2005 Page xiv of xxxviii
9.10
9.11
9.12
9.13
9.14
9.15
9.9.7 MOS Input Pull-Up Function................................................................................ 209
Port D................................................................................................................................. 210
9.10.1 Port D Data Direction Register (PDDDR) ............................................................ 210
9.10.2 Port D Data Register (PDDR)............................................................................... 211
9.10.3 Port D Register (PORTD)..................................................................................... 211
9.10.4 Port D Pull-Up MOS Control Register (PDPCR) ................................................. 212
9.10.5 Pin Functions ........................................................................................................ 212
9.10.6 MOS Input Pull-Up Function................................................................................ 213
Port E ................................................................................................................................. 214
9.11.1 Port E Data Direction Register (PEDDR)............................................................. 214
9.11.2 Port E Data Register (PEDR)................................................................................ 215
9.11.3 Port E Register (PORTE)...................................................................................... 215
9.11.4 Port E Pull-Up MOS Control Register (PEPCR) .................................................. 216
9.11.5 Pin Functions ........................................................................................................ 216
9.11.6 MOS Input Pull-Up Function................................................................................ 217
Port F ................................................................................................................................. 218
9.12.1 Port F Data Direction Register (PFDDR) ............................................................. 218
9.12.2 Port F Data Register (PFDR) ................................................................................ 219
9.12.3 Port F Register (PORTF) ...................................................................................... 219
9.12.4 Pin Functions ........................................................................................................ 220
Port H................................................................................................................................. 223
9.13.1 Port H Data Direction Register (PHDDR) ............................................................ 223
9.13.2 Port H Data Register (PHDR)............................................................................... 224
9.13.3 Port H Register (PORTH)..................................................................................... 224
9.13.4 Pin Functions ........................................................................................................ 225
Port J .................................................................................................................................. 225
9.14.1 Port J Data Direction Register (PJDDR)............................................................... 225
9.14.2 Port J Data Register (PJDR) ................................................................................. 226
9.14.3 Port J Register (PORTJ)........................................................................................ 226
9.14.4 Pin Functions ........................................................................................................ 227
Port K................................................................................................................................. 227
9.15.1 Port K Data Direction Register (PKDDR) ............................................................ 227
9.15.2 Port K Data Register (PKDR)............................................................................... 228
9.15.3 Port K Register (PORTK)..................................................................................... 228
9.15.4 Pin Functions ........................................................................................................ 228
Section 10 16-Bit Timer Pulse Unit (TPU) .......................................................229
10.1 Features.............................................................................................................................. 229
10.2 Input/Output Pins ............................................................................................................... 234
10.3 Register Descriptions ......................................................................................................... 235
Rev. 2.00 Dec. 05, 2005 Page xv of xxxviii
10.4
10.5
10.6
10.7
10.8
10.9
10.3.1 Timer Control Register (TCR).............................................................................. 237
10.3.2 Timer Mode Register (TMDR)............................................................................. 242
10.3.3 Timer I/O Control Register (TIOR)...................................................................... 244
10.3.4 Timer Interrupt Enable Register (TIER)............................................................... 261
10.3.5 Timer Status Register (TSR)................................................................................. 263
10.3.6 Timer Counter (TCNT)......................................................................................... 266
10.3.7 Timer General Register (TGR) ............................................................................. 266
10.3.8 Timer Start Register (TSTR) ................................................................................ 266
10.3.9 Timer Synchro Register (TSYR) .......................................................................... 267
Operation ........................................................................................................................... 268
10.4.1 Basic Functions..................................................................................................... 268
10.4.2 Synchronous Operation......................................................................................... 274
10.4.3 Buffer Operation................................................................................................... 276
10.4.4 Cascaded Operation .............................................................................................. 280
10.4.5 PWM Modes......................................................................................................... 282
10.4.6 Phase Counting Mode........................................................................................... 287
Interrupt Sources................................................................................................................ 293
DTC Activation.................................................................................................................. 295
A/D Converter Activation.................................................................................................. 295
Operation Timing............................................................................................................... 296
10.8.1 Input/Output Timing............................................................................................. 296
10.8.2 Interrupt Signal Timing ........................................................................................ 300
Usage Notes ....................................................................................................................... 304
10.9.1 Module Stop Mode Setting ................................................................................... 304
10.9.2 Input Clock Restrictions ....................................................................................... 304
10.9.3 Caution on Period Setting ..................................................................................... 305
10.9.4 Conflict between TCNT Write and Clear Operations .......................................... 305
10.9.5 Conflict between TCNT Write and Increment Operations ................................... 306
10.9.6 Conflict between TGR Write and Compare Match............................................... 307
10.9.7 Conflict between Buffer Register Write and Compare Match.............................. 308
10.9.8 Conflict between TGR Read and Input Capture ................................................... 309
10.9.9 Conflict between TGR Write and Input Capture .................................................. 310
10.9.10 Conflict between Buffer Register Write and Input Capture.................................. 311
10.9.11 Conflict between Overflow/Underflow and Counter Clearing ............................. 312
10.9.12 Conflict between TCNT Write and Overflow/Underflow .................................... 313
10.9.13 Multiplexing of I/O Pins ....................................................................................... 313
10.9.14 Interrupts in Module Stop Mode........................................................................... 313
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Section 11 Programmable Pulse Generator (PPG) ............................................315
11.1 Features.............................................................................................................................. 315
11.2 Input/Output Pins ............................................................................................................... 317
11.3 Register Descriptions ......................................................................................................... 317
11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ......................................... 318
11.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 319
11.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 320
11.3.4 PPG Output Control Register (PCR) .................................................................... 323
11.3.5 PPG Output Mode Register (PMR) ...................................................................... 324
11.4 Operation ........................................................................................................................... 325
11.4.1 Overview............................................................................................................... 325
11.4.2 Output Timing....................................................................................................... 326
11.4.3 Sample Setup Procedure for Normal Pulse Output............................................... 327
11.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)........... 328
11.4.5 Non-Overlapping Pulse Output............................................................................. 329
11.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output ............................... 331
11.4.7 Example of Non-Overlapping Pulse Output
(Example of Four-Phase Complementary Non-Overlapping Output)................... 332
11.4.8 Inverted Pulse Output ........................................................................................... 334
11.4.9 Pulse Output Triggered by Input Capture ............................................................. 335
11.5 Usage Notes ....................................................................................................................... 336
11.5.1 Module Stop Mode Setting ................................................................................... 336
11.5.2 Operation of Pulse Output Pins............................................................................. 336
Section 12 Watchdog Timer (WDT)..................................................................337
12.1 Features.............................................................................................................................. 337
12.2 Register Descriptions ......................................................................................................... 339
12.2.1 Timer Counter (TCNT)......................................................................................... 339
12.2.2 Timer Control/Status Register (TCSR)................................................................. 339
12.2.3 Reset Control/Status Register (RSTCSR)............................................................. 343
12.3 Operation ........................................................................................................................... 344
12.3.1 Watchdog Timer Mode ......................................................................................... 344
12.3.2 Interval Timer Mode............................................................................................. 346
12.4 Interrupt Sources................................................................................................................ 346
12.5 Usage Notes ....................................................................................................................... 347
12.5.1 Notes on Register Access...................................................................................... 347
12.5.2 Contention between Timer Counter (TCNT) Write and Increment ...................... 348
12.5.3 Changing Value of CKS2 to CKS0....................................................................... 348
12.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 348
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12.5.5 Internal Reset in Watchdog Timer Mode.............................................................. 349
12.5.6 OVF Flag Clearing in Interval Timer Mode ......................................................... 349
Section 13 Serial Communication Interface (SCI)............................................ 351
13.1 Features.............................................................................................................................. 351
13.2 Input/Output Pins............................................................................................................... 353
13.3 Register Descriptions......................................................................................................... 354
13.3.1 Receive Shift Register (RSR) ............................................................................... 354
13.3.2 Receive Data Register (RDR)............................................................................... 354
13.3.3 Transmit Data Register (TDR).............................................................................. 355
13.3.4 Transmit Shift Register (TSR) .............................................................................. 355
13.3.5 Serial Mode Register (SMR) ................................................................................ 355
13.3.6 Serial Control Register (SCR) .............................................................................. 358
13.3.7 Serial Status Register (SSR) ................................................................................. 361
13.3.8 Smart Card Mode Register (SCMR)..................................................................... 365
13.3.9 Bit Rate Register (BRR) ....................................................................................... 366
13.4 Operation in Asynchronous Mode ..................................................................................... 373
13.4.1 Data Transfer Format............................................................................................ 373
13.4.2 Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode......................................................................................... 375
13.4.3 Clock..................................................................................................................... 376
13.4.4 SCI Initialization (Asynchronous Mode).............................................................. 377
13.4.5 Data Transmission (Asynchronous Mode) ........................................................... 378
13.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 380
13.5 Multiprocessor Communication Function.......................................................................... 384
13.5.1 Multiprocessor Serial Data Transmission ............................................................. 386
13.5.2 Multiprocessor Serial Data Reception .................................................................. 388
13.6 Operation in Clocked Synchronous Mode ......................................................................... 391
13.6.1 Clock..................................................................................................................... 391
13.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 392
13.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 393
13.6.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 396
13.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) .............................................................................. 398
13.7 Operation in Smart Card Interface ..................................................................................... 400
13.7.1 Pin Connection Example ...................................................................................... 400
13.7.2 Data Format (Except for Block Transfer Mode)................................................... 401
13.7.3 Block Transfer Mode ............................................................................................ 402
13.7.4 Receive Data Sampling Timing and Reception Margin
in Smart Card Interface Mode .............................................................................. 403
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13.7.5 Initialization .......................................................................................................... 404
13.7.6 Data Transmission (Except for Block Transfer Mode)......................................... 405
13.7.7 Serial Data Reception (Except for Block Transfer Mode) .................................... 408
13.7.8 Clock Output Control............................................................................................ 410
13.8 Interrupt Sources................................................................................................................ 412
13.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 412
13.8.2 Interrupts in Smart Card Interface Mode .............................................................. 413
13.9 Usage Notes ....................................................................................................................... 414
13.9.1 Module Stop Mode Setting ................................................................................... 414
13.9.2 Break Detection and Processing ........................................................................... 414
13.9.3 Mark State and Break Detection ........................................................................... 414
13.9.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ..................................................................... 414
13.9.5 Restrictions on Using DTC................................................................................... 415
13.9.6 SCI Operations during Mode Transitions ............................................................. 415
13.9.7 Notes when Switching from SCK Pin to Port Pin................................................. 419
Section 14 Controller Area Network (HCAN) ..................................................421
14.1 Features.............................................................................................................................. 421
14.2 Input/Output Pins ............................................................................................................... 423
14.3 Register Descriptions ......................................................................................................... 424
14.3.1 Master Control Register (MCR) ........................................................................... 425
14.3.2 General Status Register (GSR) ............................................................................. 426
14.3.3 Bit Configuration Register (BCR) ........................................................................ 427
14.3.4 Mailbox Configuration Register (MBCR) ............................................................ 430
14.3.5 Transmit Wait Register (TXPR) ........................................................................... 431
14.3.6 Transmit Wait Cancel Register (TXCR)............................................................... 432
14.3.7 Transmit Acknowledge Register (TXACK) ......................................................... 433
14.3.8 Abort Acknowledge Register (ABACK) .............................................................. 434
14.3.9 Receive Complete Register (RXPR)..................................................................... 435
14.3.10 Remote Request Register (RFPR)......................................................................... 436
14.3.11 Interrupt Register (IRR)........................................................................................ 437
14.3.12 Mailbox Interrupt Mask Register (MBIMR)......................................................... 441
14.3.13 Interrupt Mask Register (IMR) ............................................................................. 442
14.3.14 Receive Error Counter (REC)............................................................................... 443
14.3.15 Transmit Error Counter (TEC).............................................................................. 443
14.3.16 Unread Message Status Register (UMSR)............................................................ 444
14.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)............................................ 444
14.3.18 Message Control (MC0 to MC15) ........................................................................ 447
14.3.19 Message Data (MD0 to MD15) ............................................................................ 449
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14.4
14.5
14.6
14.7
14.8
14.3.20 HCAN Monitor Register (HCANMON)............................................................... 450
Operation ........................................................................................................................... 451
14.4.1 Hardware and Software Resets ............................................................................. 451
14.4.2 Initialization after Hardware Reset ....................................................................... 451
14.4.3 Message Transmission.......................................................................................... 457
14.4.4 Message Reception ............................................................................................... 461
14.4.5 HCAN Sleep Mode............................................................................................... 464
14.4.6 HCAN Halt Mode................................................................................................. 467
Interrupt Sources................................................................................................................ 468
DTC Interface .................................................................................................................... 469
CAN Bus Interface............................................................................................................. 470
Usage Notes ....................................................................................................................... 471
14.8.1 Module Stop Mode Setting ................................................................................... 471
14.8.2 Reset ..................................................................................................................... 471
14.8.3 HCAN Sleep Mode............................................................................................... 471
14.8.4 Interrupts............................................................................................................... 471
14.8.5 Error Counters ...................................................................................................... 472
14.8.6 Register Access..................................................................................................... 472
14.8.7 HCAN Medium-Speed Mode ............................................................................... 472
14.8.8 Register Hold in Standby Modes .......................................................................... 472
14.8.9 Use on Bit Manipulation Instructions ................................................................... 472
14.8.10 HCAN TXCR Operation ...................................................................................... 473
14.8.11 HCAN Transmit Procedure .................................................................................. 474
14.8.12 Note on Releasing the HCAN Reset or HCAN Sleep........................................... 474
14.8.13 Note on Accessing Mailbox during the HCAN Sleep .......................................... 474
Section 15 A/D Converter ................................................................................. 475
15.1 Features.............................................................................................................................. 475
15.2 Input/Output Pins............................................................................................................... 477
15.3 Register Description .......................................................................................................... 478
15.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 478
15.3.2 A/D Control/Status Register (ADCSR) ................................................................ 479
15.3.3 A/D Control Register (ADCR) ............................................................................. 481
15.4 Operation ........................................................................................................................... 482
15.4.1 Single Mode.......................................................................................................... 482
15.4.2 Scan Mode ............................................................................................................ 482
15.4.3 Input Sampling and A/D Conversion Time .......................................................... 483
15.4.4 External Trigger Input Timing.............................................................................. 485
15.5 Interrupt Source ................................................................................................................. 485
15.6 A/D Conversion Accuracy Definitions .............................................................................. 486
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15.7 Usage Notes ....................................................................................................................... 488
15.7.1 Module Stop Mode Setting ................................................................................... 488
15.7.2 Permissible Signal Source Impedance .................................................................. 488
15.7.3 Influences on Absolute Accuracy ......................................................................... 488
15.7.4 Range of Analog Power Supply and Other Pin Settings....................................... 489
15.7.5 Notes on Board Design ......................................................................................... 489
15.7.6 Notes on Noise Countermeasures ......................................................................... 490
Section 16 Motor Control PWM Timer (PWM)................................................493
16.1 Features.............................................................................................................................. 493
16.2 Input/Output Pins ............................................................................................................... 495
16.3 Register Descriptions ......................................................................................................... 496
16.3.1 PWM Control Register (PWCR) .......................................................................... 497
16.3.2 PWM Output Control Register (PWOCR)............................................................ 498
16.3.3 PWM Polarity Register (PWPR)........................................................................... 499
16.3.4 PWM Counter (PWCNT) ..................................................................................... 499
16.3.5 PWM Cycle Register (PWCYR)........................................................................... 499
16.3.6 PWM Duty Registers A, C, E, G
(PWDTRA, PWDTRC, PWDTRE, PWDTRG) ................................................... 500
16.3.7 PWM Buffer Registers A, C, E, G
(PWBFRA, PWBFRC, PWBFRE, PWBFRG) ..................................................... 503
16.3.8 PWM Buffer Transfer Control Register (PWBTCR)............................................ 504
16.4 Bus Master Interface .......................................................................................................... 505
16.4.1 16-Bit Data Registers............................................................................................ 505
16.4.2 8-Bit Data Registers.............................................................................................. 505
16.5 Operation ........................................................................................................................... 506
16.5.1 PWM Operation.................................................................................................... 506
16.5.2 Buffer Transfer Control ........................................................................................ 507
16.6 Usage Note......................................................................................................................... 508
Section 17 LCD Controller/Driver ....................................................................509
17.1 Features.............................................................................................................................. 509
17.2 Input/Output Pins ............................................................................................................... 511
17.3 Register Descriptions ......................................................................................................... 512
17.3.1 LCD Port Control Register (LPCR)...................................................................... 512
17.3.2 LCD Control Register (LCR)................................................................................ 515
17.3.3 LCD Control Register 2 (LCR2)........................................................................... 517
17.4 Operation ........................................................................................................................... 518
17.4.1 Settings up to LCD Display .................................................................................. 518
17.4.2 Relationship between LCD RAM and Display..................................................... 520
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17.4.3 Operation in Power-Down Modes ........................................................................ 525
17.4.4 Boosting the LCD Drive Power Supply................................................................ 526
Section 18 RAM ................................................................................................ 527
Section 19 ROM ................................................................................................ 529
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
19.10
19.11
19.12
19.13
Features.............................................................................................................................. 529
Mode Transitions ............................................................................................................... 530
Block Configuration .......................................................................................................... 534
Input/Output Pins............................................................................................................... 536
Register Descriptions......................................................................................................... 536
19.5.1 Flash Memory Control Register 1 (FLMCR1) ..................................................... 537
19.5.2 Flash Memory Control Register 2 (FLMCR2) ..................................................... 538
19.5.3 Erase Block Register 1 (EBR1) ............................................................................ 539
19.5.4 Erase Block Register 2 (EBR2) ............................................................................ 540
19.5.5 RAM Emulation Register (RAMER).................................................................... 540
19.5.6 Flash Memory Power Control Register (FLPWCR)............................................. 541
On-Board Programming Modes......................................................................................... 542
19.6.1 Boot Mode ............................................................................................................ 542
19.6.2 Programming/Erasing in User Program Mode...................................................... 545
Flash Memory Emulation in RAM .................................................................................... 546
Flash Memory Programming/Erasing................................................................................ 549
19.8.1 Program/Program-Verify ...................................................................................... 549
19.8.2 Erase/Erase-Verify................................................................................................ 551
19.8.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 551
Program/Erase Protection .................................................................................................. 553
19.9.1 Hardware Protection ............................................................................................. 553
19.9.2 Software Protection .............................................................................................. 553
19.9.3 Error Protection .................................................................................................... 553
Interrupt Handling when Programming/Erasing Flash Memory........................................ 554
Programmer Mode ............................................................................................................. 554
Power-Down States for Flash Memory.............................................................................. 555
Usage Notes ....................................................................................................................... 556
Section 20 Clock Pulse Generator..................................................................... 559
20.1 Register Descriptions......................................................................................................... 560
20.1.1 System Clock Control Register (SCKCR) ............................................................ 560
20.2 Oscillator............................................................................................................................ 562
20.2.1 Connecting a Crystal Resonator............................................................................ 562
20.2.2 External Clock Input............................................................................................. 563
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20.3
20.4
20.5
20.6
PLL Circuit ........................................................................................................................ 565
Medium-Speed Clock Divider ........................................................................................... 565
Bus Master Clock Selection Circuit................................................................................... 565
Subclock Oscillator............................................................................................................ 566
20.6.1 Connecting 32.768-kHz Crystal Resonator........................................................... 566
20.6.2 Handling Pins when Subclock is not Used ........................................................... 567
20.7 Subclock Waveform Generation Circuit............................................................................ 567
20.8 Usage Notes ....................................................................................................................... 567
20.8.1 Note on Crystal Resonator .................................................................................... 567
20.8.2 Note on Board Design........................................................................................... 568
Section 21 Power-Down Modes ........................................................................569
21.1 Register Descriptions ......................................................................................................... 573
21.1.1 Standby Control Register (SBYCR) ..................................................................... 573
21.1.2 Low-Power Control Register (LPWRCR) ............................................................ 576
21.1.3 Module Stop Control Registers A to D (MSTPCRA to MSTPCRD) ................... 578
21.2 Medium-Speed Mode......................................................................................................... 580
21.3 Sleep Mode ........................................................................................................................ 581
21.4 Software Standby Mode..................................................................................................... 582
21.5 Hardware Standby Mode ................................................................................................... 584
21.6 Watch Mode....................................................................................................................... 585
21.7 Subsleep Mode................................................................................................................... 586
21.8 Subactive Mode ................................................................................................................. 586
21.9 Module Stop Mode ............................................................................................................ 587
21.10 Direct Transitions............................................................................................................... 588
21.10.1 Overview of Direct Transitions ............................................................................ 588
21.11 φ Clock Output Disabling Function ................................................................................... 588
21.12 Usage Notes ....................................................................................................................... 589
21.12.1 I/O Port Status....................................................................................................... 589
21.12.2 Current Consumption during Oscillation Stabilization Wait Period..................... 589
21.12.3 DTC Module Stop Setting .................................................................................... 589
21.12.4 On-Chip Peripheral Module Interrupts ................................................................. 589
21.12.5 Writing to MSTPCR ............................................................................................. 589
Section 22 List of Registers ...............................................................................591
22.1 Register Addresses (Address Order).................................................................................. 592
22.2 Register Bits....................................................................................................................... 620
22.3 Register States in Each Operating Mode ........................................................................... 648
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Section 23 Electrical Characteristics [Preliminary] .......................................... 675
23.1 Absolute Maximum Ratings .............................................................................................. 675
23.2 DC Characteristics ............................................................................................................. 676
23.3 AC Characteristics ............................................................................................................. 681
23.3.1 Clock Timing ........................................................................................................ 682
23.3.2 Control Signal Timing .......................................................................................... 683
23.3.3 Bus Timing ........................................................................................................... 685
23.3.4 Timing of On-Chip Peripheral Modules ............................................................... 691
23.4 A/D Conversion Characteristics ........................................................................................ 696
23.5 LCD Characteristics........................................................................................................... 697
23.6 Flash Memory Characteristics ........................................................................................... 698
Appendix
A.
B.
C.
......................................................................................................... 701
I/O Port States in Each Operating State ............................................................................. 701
Product Code Lineup ......................................................................................................... 706
Package Dimensions .......................................................................................................... 707
Main Revisions and Additions in this Edition..................................................... 709
Index
......................................................................................................... 719
Rev. 2.00 Dec. 05, 2005 Page xxiv of xxxviii
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ................................................................................................. 2
Figure 1.2 Pin Assignments (FP-144G).......................................................................................... 3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 19
Figure 2.2 Stack Structure in Normal Mode ................................................................................. 19
Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 20
Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 21
Figure 2.5 Memory Map............................................................................................................... 22
Figure 2.6 CPU Registers ............................................................................................................. 23
Figure 2.7 Usage of General Registers ......................................................................................... 24
Figure 2.8 Stack............................................................................................................................ 25
Figure 2.9 General Register Data Formats (1).............................................................................. 28
Figure 2.9 General Register Data Formats (2).............................................................................. 29
Figure 2.10 Memory Data Formats............................................................................................... 30
Figure 2.11 Instruction Formats (Examples) ................................................................................ 42
Figure 2.12 Branch Address Specification in Memory Indirect Mode ......................................... 46
Figure 2.13 State Transitions ........................................................................................................ 50
Section 3 MCU Operating Modes
Figure 3.1 Address Map ............................................................................................................... 58
Section 4
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Exception Handling
Reset Sequence (Advanced Mode with On-chip ROM Enabled)................................ 62
Reset Sequence (Advanced Mode with On-chip ROM Disabled)............................... 63
Stack Status after Exception Handling ........................................................................ 67
Operation when SP Value Is Odd................................................................................ 68
Section 5
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Interrupt Controller
Block Diagram of Interrupt Controller........................................................................ 70
Block Diagram of Interrupts IRQ0 to IRQ5 ................................................................ 78
Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0...... 84
Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2..................... 86
Interrupt Exception Handling ...................................................................................... 88
Conflict between Interrupt Generation and Disabling................................................. 91
Section 6 PC Break Controller (PBC)
Figure 6.1 Block Diagram of PC Break Controller ...................................................................... 94
Figure 6.2 Operation in Power-Down Mode Transitions.............................................................. 98
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Section 7 Bus Controller (BSC)
Figure 7.1 Block Diagram of Bus Controller.............................................................................. 104
Figure 7.2 Area Divisions........................................................................................................... 112
Figure 7.3 Access Sizes and Data Alignment Control (8-Bit Access Space) ............................. 115
Figure 7.4 Access Sizes and Data Alignment Control (16-bit Access Space) ............................ 116
Figure 7.5 Bus Timing for 8-Bit, 2-State Access Space ............................................................. 118
Figure 7.6 Bus Timing for 8-Bit, 3-State Access Space ............................................................. 119
Figure 7.7 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)............. 120
Figure 7.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access).............. 121
Figure 7.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) .................................. 122
Figure 7.10 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)........... 123
Figure 7.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)............ 124
Figure 7.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ................................ 125
Figure 7.13 Example of Wait State Insertion Timing................................................................. 126
Figure 7.14 Example of Burst ROM Access Timing (AST0 = 1 and BRSTS0 = 1) .................. 128
Figure 7.15 Example of Burst ROM Access Timing (AST0 = 0 and BRSTS1 = 0) .................. 129
Figure 7.16 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) ............ 130
Figure 7.17 Example of Idle Cycle Operation (Write after Read) .............................................. 131
Figure 7.18 Relationship between Chip Select (CS) and Read (RD) ......................................... 132
Figure 7.19 Example of Timing when Write Data Buffer Function is Used .............................. 133
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC ............................................................................................. 138
Figure 8.2 Block Diagram of DTC Activation Source Control .................................................. 145
Figure 8.3 Location of DTC Register Information in Address Space......................................... 146
Figure 8.4 Flowchart of DTC Operation .................................................................................... 149
Figure 8.5 Memory Mapping in Normal Mode .......................................................................... 150
Figure 8.6 Memory Mapping in Repeat Mode ........................................................................... 151
Figure 8.7 Memory Mapping in Block Transfer Mode .............................................................. 153
Figure 8.8 Chain Transfer Operation.......................................................................................... 154
Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ..................... 155
Figure 8.10 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2) ...................................... 156
Figure 8.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 156
Section 10
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
16-Bit Timer Pulse Unit (TPU)
Block Diagram of TPU............................................................................................ 233
Example of Counter Operation Setting Procedure .................................................. 268
Free-Running Counter Operation ............................................................................ 269
Periodic Counter Operation..................................................................................... 270
Example of Setting Procedure for Waveform Output by Compare Match.............. 270
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Figure 10.6 Example of 0 Output/1 Output Operation ............................................................... 271
Figure 10.7 Example of Toggle Output Operation ..................................................................... 271
Figure 10.8 Example of Input Capture Operation Setting Procedure ......................................... 272
Figure 10.9 Example of Input Capture Operation....................................................................... 273
Figure 10.10 Example of Synchronous Operation Setting Procedure ........................................ 274
Figure 10.11 Example of Synchronous Operation...................................................................... 275
Figure 10.12 Compare Match Buffer Operation......................................................................... 276
Figure 10.13 Input Capture Buffer Operation............................................................................. 277
Figure 10.14 Example of Buffer Operation Setting Procedure................................................... 277
Figure 10.15 Example of Buffer Operation (1)........................................................................... 278
Figure 10.16 Example of Buffer Operation (2)........................................................................... 279
Figure 10.17 Cascaded Operation Setting Procedure ................................................................. 280
Figure 10.18 Example of Cascaded Operation (1)...................................................................... 281
Figure 10.19 Example of Cascaded Operation (2)...................................................................... 281
Figure 10.20 Example of PWM Mode Setting Procedure .......................................................... 284
Figure 10.21 Example of PWM Mode Operation (1) ................................................................. 285
Figure 10.22 Example of PWM Mode Operation (2) ................................................................. 285
Figure 10.23 Example of PWM Mode Operation (3) ................................................................. 286
Figure 10.24 Example of Phase Counting Mode Setting Procedure........................................... 287
Figure 10.25 Example of Phase Counting Mode 1 Operation .................................................... 288
Figure 10.26 Example of Phase Counting Mode 2 Operation .................................................... 289
Figure 10.27 Example of Phase Counting Mode 3 Operation .................................................... 290
Figure 10.28 Example of Phase Counting Mode 4 Operation .................................................... 291
Figure 10.29 Phase Counting Mode Application Example......................................................... 293
Figure 10.30 Count Timing in Internal Clock Operation............................................................ 296
Figure 10.31 Count Timing in External Clock Operation........................................................... 296
Figure 10.32 Output Compare Output Timing ........................................................................... 297
Figure 10.33 Input Capture Input Signal Timing........................................................................ 297
Figure 10.34 Counter Clear Timing (Compare Match) .............................................................. 298
Figure 10.35 Counter Clear Timing (Input Capture) .................................................................. 298
Figure 10.36 Buffer Operation Timing (Compare Match).......................................................... 299
Figure 10.37 Buffer Operation Timing (Input Capture) ............................................................. 299
Figure 10.38 TGI Interrupt Timing (Compare Match) ............................................................... 300
Figure 10.39 TGI Interrupt Timing (Input Capture) ................................................................... 301
Figure 10.40 TCIV Interrupt Setting Timing.............................................................................. 301
Figure 10.41 TCIU Interrupt Setting Timing.............................................................................. 302
Figure 10.42 Timing for Status Flag Clearing by CPU .............................................................. 303
Figure 10.43 Timing for Status Flag Clearing by DTC Activation ............................................ 303
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 304
Figure 10.45 Conflict between TCNT Write and Clear Operations ........................................... 305
Rev. 2.00 Dec. 05, 2005 Page xxvii of xxxviii
Figure 10.46
Figure 10.47
Figure 10.48
Figure 10.49
Figure 10.50
Figure 10.51
Figure 10.52
Figure 10.53
Conflict between TCNT Write and Increment Operations.................................... 306
Conflict between TGR Write and Compare Match ............................................... 307
Conflict between Buffer Register Write and Compare Match .............................. 308
Conflict between TGR Read and Input Capture.................................................... 309
Conflict between TGR Write and Input Capture................................................... 310
Conflict between Buffer Register Write and Input Capture .................................. 311
Conflict between Overflow and Counter Clearing ................................................ 312
Conflict between TCNT Write and Overflow ....................................................... 313
Section 11 Programmable Pulse Generator (PPG)
Figure 11.1 Block Diagram of PPG............................................................................................ 316
Figure 11.2 PPG Output Operation ............................................................................................ 325
Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) ................................. 326
Figure 11.4 Setup Procedure for Normal Pulse Output (Example) ............................................ 327
Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output) ..................................... 328
Figure 11.6 Non-Overlapping Pulse Output ............................................................................... 329
Figure 11.7 Non-Overlapping Operation and NDR Write Timing ............................................. 330
Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)............................. 331
Figure 11.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)................ 332
Figure 11.10 Inverted Pulse Output (Example) .......................................................................... 334
Figure 11.11 Pulse Output Triggered by Input Capture (Example)............................................ 335
Section 12
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.3
Figure 12.4
Figure 12.5
Watchdog Timer (WDT)
Block Diagram of WDT_0 ...................................................................................... 338
Block Diagram of WDT_1 ...................................................................................... 338
(a) WDT_0 Operation in Watchdog Timer Mode ................................................... 345
(b) WDT_1 Operation in Watchdog Timer Mode................................................... 345
Writing to TCNT, TCSR, and RSTCSR (example for WDT0)............................... 347
Contention between TCNT Write and Increment.................................................... 348
Section 13 Serial Communication Interface (SCI)
Figure 13.1 Block Diagram of SCI............................................................................................. 352
Figure 13.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits).................................................. 373
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 375
Figure 13.4 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)............................................................................................. 376
Figure 13.5 Sample SCI Initialization Flowchart ....................................................................... 377
Figure 13.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 378
Figure 13.7 Sample Serial Transmission Flowchart ................................................................... 379
Rev. 2.00 Dec. 05, 2005 Page xxviii of xxxviii
Figure 13.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 380
Figure 13.9 Sample Serial Reception Data Flowchart (1) .......................................................... 382
Figure 13.9 Sample Serial Reception Data Flowchart (2) .......................................................... 383
Figure 13.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 385
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 387
Figure 13.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 388
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 389
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 390
Figure 13.14 Data Format in Synchronous Communication (For LSB-First) ............................ 391
Figure 13.15 Sample SCI Initialization Flowchart ..................................................................... 392
Figure 13.16 Sample SCI Transmission Operation in Clocked Synchronous Mode .................. 394
Figure 13.17 Sample Serial Transmission Flowchart ................................................................. 395
Figure 13.18 Example of SCI Operation in Reception ............................................................... 396
Figure 13.19 Sample Serial Reception Flowchart ...................................................................... 397
Figure 13.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ...... 399
Figure 13.21 Schematic Diagram of Smart Card Interface Pin Connections.............................. 400
Figure 13.22 Normal Smart Card Interface Data Format ........................................................... 401
Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 401
Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 402
Figure 13.25 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Transfer Rate) ..................................................... 404
Figure 13.26 Retransfer Operation in SCI Transmit Mode......................................................... 406
Figure 13.27 TEND Flag Generation Timing in Transmission Operation.................................. 406
Figure 13.28 Example of Transmission Processing Flow........................................................... 407
Figure 13.29 Retransfer Operation in SCI Receive Mode .......................................................... 408
Figure 13.30 Example of Reception Processing Flow................................................................ 409
Figure 13.31 Timing for Fixing Clock Output Level.................................................................. 410
Figure 13.32 Clock Halt and Restart Procedure ......................................................................... 411
Figure 13.33 Sample Transmission using DTC in Clocked Synchronous Mode........................ 415
Figure 13.34 Sample Flowchart for Mode Transition during Transmission............................... 416
Figure 13.35 Pin States during Transmission in Asynchronous Mode (Internal Clock)............. 417
Figure 13.36 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock) ..................................................................................................... 417
Figure 13.37 Sample Flowchart for Mode Transition during Reception .................................... 418
Figure 13.38 Operation when Switching from SCK Pin to Port Pin........................................... 419
Figure 13.39 Operation when Switching from SCK Pin to Port Pin
(Example of Preventing Low-Level Output)......................................................... 420
Rev. 2.00 Dec. 05, 2005 Page xxix of xxxviii
Section 14 Controller Area Network (HCAN)
Figure 14.1 HCAN Block Diagram ............................................................................................ 422
Figure 14.2 Message Control Register Configuration ................................................................ 447
Figure 14.3 Standard Format ...................................................................................................... 447
Figure 14.4 Extended Format ..................................................................................................... 447
Figure 14.5 Message Data Configuration ................................................................................... 449
Figure 14.6 Hardware Reset Flowchart ...................................................................................... 452
Figure 14.7 Software Reset Flowchart ....................................................................................... 453
Figure 14.8 Detailed Description of One-Bit Time .................................................................... 454
Figure 14.9 Transmission Flowchart .......................................................................................... 457
Figure 14.10 Transmit Message Cancellation Flowchart ........................................................... 460
Figure 14.11 Reception Flowchart ............................................................................................. 461
Figure 14.12 Unread Message Overwrite Flowchart.................................................................. 464
Figure 14.13 HCAN Sleep Mode Flowchart .............................................................................. 465
Figure 14.14 HCAN Halt Mode Flowchart ................................................................................ 467
Figure 14.15 DTC Transfer Flowchart ....................................................................................... 469
Figure 14.16 High-Speed Interface Using PCA82C250............................................................. 470
Section 15
Figure 15.1
Figure 15.2
Figure 15.3
Figure 15.4
Figure 15.5
Figure 15.6
Figure 15.7
Figure 15.8
A/D Converter
Block Diagram of A/D Converter ........................................................................... 476
A/D Conversion Timing.......................................................................................... 483
External Trigger Input Timing ................................................................................ 485
A/D Conversion Accuracy Definitions ................................................................... 487
A/D Conversion Accuracy Definitions ................................................................... 487
Example of Analog Input Circuit ............................................................................ 489
Example of Analog Input Protection Circuit........................................................... 490
Analog Input Pin Equivalent Circuit ....................................................................... 491
Section 16
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.4
Motor Control PWM Timer (PWM)
Block Diagram of PWM.......................................................................................... 494
Cycle Register Compare Match............................................................................... 500
Duty Register Compare Match (OPS = 0 in PWPR)............................................... 501
Differences in PWM Output According to Duty Register Set Value
(OPS = 0 in PWPR)................................................................................................. 502
16-Bit Register Access Operation (Bus Master ↔ PWCYR (16 Bits)) .................. 505
8-Bit Register Access Operation (Bus Master ↔ PWCR (Upper Eight Bits))........ 505
PWM Operation ...................................................................................................... 506
Disabling Buffer Transfer ....................................................................................... 507
Conflict between Buffer Register Write and Compare Match ................................ 508
Figure 16.5
Figure 16.6
Figure 16.7
Figure 16.8
Figure 16.9
Rev. 2.00 Dec. 05, 2005 Page xxx of xxxviii
Section 17
Figure 17.1
Figure 17.2
Figure 17.3
Figure 17.4
Figure 17.5
Figure 17.6
Figure 17.7
Figure 17.8
Figure 17.9
LCD Controller/Driver
Block Diagram of LCD Controller/Driver .............................................................. 510
Handling of LCD Drive Power Supply when Using 1/2 Duty ................................ 518
LCD RAM Map (1/4 Duty)..................................................................................... 520
LCD RAM Map (1/3 Duty)..................................................................................... 521
LCD RAM Map (1/2 Duty)..................................................................................... 521
LCD RAM Map (Static Mode)................................................................................ 522
Output Waveforms for Each Duty Cycle (A Waveform) ........................................ 523
Output Waveforms for Each Duty Cycle (B Waveform) ........................................ 524
Connection of External Split-Resistance ................................................................. 526
Section 19 ROM
Figure 19.1 Block Diagram of Flash Memory............................................................................ 530
Figure 19.2 Flash Memory State Transitions.............................................................................. 531
Figure 19.3 Boot Mode............................................................................................................... 532
Figure 19.4 User Program Mode (Example)............................................................................... 533
Figure 19.5 Flash Memory Block Configuration........................................................................ 535
Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode ........................ 545
Figure 19.7 Flowchart for Flash Memory Emulation in RAM ................................................... 546
Figure 19.8 Example of RAM Overlap Operation...................................................................... 548
Figure 19.9 Program/Program-Verify Flowchart........................................................................ 550
Figure 19.10 Erase/Erase-Verify Flowchart ............................................................................... 552
Section 20 Clock Pulse Generator
Figure 20.1 Block Diagram of Clock Pulse Generator ............................................................... 559
Figure 20.2 Connection of Crystal Resonator (Example)........................................................... 562
Figure 20.3 Crystal Resonator Equivalent Circuit ...................................................................... 562
Figure 20.4 External Clock Input (Examples) ............................................................................ 563
Figure 20.5 External Clock Input Timing................................................................................... 564
Figure 20.6 Connection Example of 32.768-kHz Crystal Resonator.......................................... 566
Figure 20.7 Equivalent Circuit for 32.768-kHz Crystal Resonator............................................. 566
Figure 20.8 Pin Handling when Subclock is not Used ............................................................... 567
Figure 20.9 Note on Board Design of Oscillator Circuit ............................................................ 568
Figure 20.10 External Circuitry Recommended for PLL Circuit................................................ 568
Section 21
Figure 21.1
Figure 21.2
Figure 21.3
Figure 21.4
Power-Down Modes
Mode Transition Diagram ....................................................................................... 571
Medium-Speed Mode Transition and Clearance Timing ........................................ 581
Software Standby Mode Application Example ....................................................... 583
Hardware Standby Mode Timing ............................................................................ 584
Rev. 2.00 Dec. 05, 2005 Page xxxi of xxxviii
Section 23 Electrical Characteristics [Preliminary]
Figure 23.1 Output Load Circuit ................................................................................................ 681
Figure 23.2 System Clock Timing.............................................................................................. 682
Figure 23.3 Oscillator Settling Timing ....................................................................................... 683
Figure 23.4 Reset Input Timing.................................................................................................. 684
Figure 23.5 Interrupt Input Timing............................................................................................. 684
Figure 23.6 Basic Bus Timing (Two-State Access).................................................................... 686
Figure 23.7 Basic Bus Timing (Three-State Access).................................................................. 687
Figure 23.8 Basic Bus Timing (Three-State Access with One Wait State) ................................ 688
Figure 23.9 Burst ROM Access Timing (Two-State Access)..................................................... 689
Figure 23.10 Burst ROM Access Timing (Two-State Access)................................................... 690
Figure 23.11 I/O Port Input/Output Timing................................................................................ 692
Figure 23.12 PPG Output Timing............................................................................................... 692
Figure 23.13 TPU Input/Output Timing ..................................................................................... 693
Figure 23.14 TPU Clock Input Timing....................................................................................... 693
Figure 23.15 Motor Control PWM Output Timing .................................................................... 693
Figure 23.16 SCK Clock Input Timing ...................................................................................... 694
Figure 23.17 SCI Input/Output Timing (Clock Synchronous Mode) ......................................... 694
Figure 23.18 A/D Converter External Trigger Input Timing...................................................... 694
Figure 23.19 HCAN Input/Output Timing ................................................................................. 695
Appendix
Figure C.1 FP-144G Package Dimensions ................................................................................. 707
Rev. 2.00 Dec. 05, 2005 Page xxxii of xxxviii
Tables
Section 1 Overview
Table 1.1
Pin Functions in Each Operating Mode .................................................................... 4
Table 1.2
Pin Functions .......................................................................................................... 10
Section 2 CPU
Table 2.1
Instruction Classification ........................................................................................ 31
Table 2.2
Operation Notation ................................................................................................. 32
Table 2.3
Data Transfer Instructions....................................................................................... 33
Table 2.4
Arithmetic Operations Instructions (1) ................................................................... 34
Table 2.4
Arithmetic Operations Instructions (2) ................................................................... 35
Table 2.5
Logic Operations Instructions................................................................................. 36
Table 2.6
Shift Instructions..................................................................................................... 36
Table 2.7
Bit Manipulation Instructions (1)............................................................................ 37
Table 2.7
Bit Manipulation Instructions (2)............................................................................ 38
Table 2.8
Branch Instructions ................................................................................................. 39
Table 2.9
System Control Instructions.................................................................................... 40
Table 2.10
Block Data Transfer Instructions ............................................................................ 41
Table 2.11
Addressing Modes .................................................................................................. 43
Table 2.12
Absolute Address Access Ranges ........................................................................... 45
Table 2.13
Effective Address Calculation (1)........................................................................... 47
Table 2.13
Effective Address Calculation (2)........................................................................... 48
Section 3 MCU Operating Modes
Table 3.1
MCU Operating Mode Selection ............................................................................ 53
Table 3.2
Pin Functions in Each Mode ................................................................................... 57
Section 4 Exception Handling
Table 4.1
Exception Types and Priority.................................................................................. 59
Table 4.2
Exception Handling Vector Table........................................................................... 60
Table 4.3
Statuses of CCR and EXR after Trace Exception Handling ................................... 65
Table 4.4
Statuses of CCR and EXR after Trap Instruction Exception Handling................... 66
Section 5 Interrupt Controller
Table 5.1
Pin Configuration.................................................................................................... 71
Table 5.2
Interrupt Sources, Vector Addresses, and Interrupt Priorities................................. 80
Table 5.3
Interrupt Control Modes ......................................................................................... 83
Table 5.4
Interrupt Response Times ....................................................................................... 89
Table 5.5
Number of States in Interrupt Handling Routine Execution Status ........................ 90
Rev. 2.00 Dec. 05, 2005 Page xxxiii of xxxviii
Section 7 Bus Controller (BSC)
Table 7.1
Pin Configuration.................................................................................................. 105
Table 7.2
Bus Specifications for Each Area (Basic Bus Interface) ...................................... 114
Table 7.3
Data Buses Used and Valid Strobes...................................................................... 117
Table 7.4
Pin States in Idle Cycle......................................................................................... 132
Section 8 Data Transfer Controller (DTC)
Table 8.1
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 147
Table 8.2
Register Information in Normal Mode.................................................................. 150
Table 8.3
Register Information in Repeat Mode................................................................... 151
Table 8.4
Register Information in Block Transfer Mode...................................................... 152
Table 8.5
DTC Execution Status .......................................................................................... 157
Table 8.6
Number of States Required for Each Execution Status ........................................ 157
Section 9 I/O Ports
Table 9.1
Port Functions....................................................................................................... 164
Table 9.2
MOS Input Pull-Up States (Port A) ...................................................................... 201
Table 9.3
MOS Input Pull-Up States (Port B) ...................................................................... 205
Table 9.4
MOS Input Pull-Up States (Port C) ...................................................................... 209
Table 9.5
MOS Input Pull-Up States (Port D) ...................................................................... 213
Table 9.6
MOS Input Pull-Up States (Port E) ...................................................................... 217
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.1
TPU Functions ...................................................................................................... 230
Table 10.2
TPU Pins............................................................................................................... 234
Table 10.3
CCLR0 to CCLR2 (Channels 0 and 3) ................................................................. 238
Table 10.4
CCLR0 to CCLR2 (Channels 1, 2, 4, and 5) ........................................................ 238
Table 10.5
TPSC0 to TPSC2 (Channel 0) .............................................................................. 239
Table 10.6
TPSC0 to TPSC2 (Channel 1) .............................................................................. 239
Table 10.7
TPSC0 to TPSC2 (Channel 2) .............................................................................. 240
Table 10.8
TPSC0 to TPSC2 (Channel 3) .............................................................................. 240
Table 10.9
TPSC0 to TPSC2 (Channel 4) .............................................................................. 241
Table 10.10
TPSC0 to TPSC2 (Channel 5) .......................................................................... 241
Table 10.11
MD0 to MD3 .................................................................................................... 243
Table 10.12
TIORH_0 (Channel 0) ...................................................................................... 245
Table 10.13
TIORL_0 (Channel 0)....................................................................................... 246
Table 10.14
TIOR_1 (Channel 1) ......................................................................................... 247
Table 10.15
TIOR_2 (Channel 2) ......................................................................................... 248
Table 10.16
TIORH_3 (Channel 3) ...................................................................................... 249
Table 10.17
TIORL_3 (Channel 3)....................................................................................... 250
Table 10.18
TIOR_4 (Channel 4) ......................................................................................... 251
Rev. 2.00 Dec. 05, 2005 Page xxxiv of xxxviii
Table 10.19
Table 10.20
Table 10.21
Table 10.22
Table 10.23
Table 10.24
Table 10.25
Table 10.26
Table 10.27
Table 10.28
Table 10.29
Table 10.30
Table 10.31
Table 10.32
Table 10.33
Table 10.34
Table 10.35
Table 10.36
TIOR_5 (Channel 5) ......................................................................................... 252
TIORH_0 (Channel 0) ...................................................................................... 253
TIORL_0 (Channel 0)....................................................................................... 254
TIOR_1 (Channel 1) ......................................................................................... 255
TIOR_2 (Channel 2) ......................................................................................... 256
TIORH_3 (Channel 3) ...................................................................................... 257
TIORL_3 (Channel 3)....................................................................................... 258
TIOR_4 (Channel 4) ......................................................................................... 259
TIOR_5 (Channel 5) ......................................................................................... 260
Register Combinations in Buffer Operation ..................................................... 276
Cascaded Combinations.................................................................................... 280
PWM Output Registers and Output Pins .......................................................... 283
Phase Counting Mode Clock Input Pins ........................................................... 287
Up/Down-Count Conditions in Phase Counting Mode 1.................................. 288
Up/Down-Count Conditions in Phase Counting Mode 2.................................. 289
Up/Down-Count Conditions in Phase Counting Mode 3.................................. 290
Up/Down-Count Conditions in Phase Counting Mode 4.................................. 291
TPU Interrupts .................................................................................................. 294
Section 11 Programmable Pulse Generator (PPG)
Table 11.1
Pin Configuration.................................................................................................. 317
Section 12 Watchdog Timer (WDT)
Table 12.1
WDT Interrupt Sources......................................................................................... 346
Section 13 Serial Communication Interface (SCI)
Table 13.1
Pin Configuration.................................................................................................. 353
Table 13.2
The Relationships between The N Setting in BRR and Bit Rate B ...................... 366
Table 13.3
BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ........................... 367
Table 13.3
BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ........................... 368
Table 13.3
BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ........................... 369
Table 13.4
Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 369
Table 13.5
Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 370
Table 13.6
BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 371
Table 13.7
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 371
Table 13.8
Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(When n = 0 and S = 372)..................................................................................... 372
Table 13.9
Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372)...................................................................................................... 372
Table 13.10
Serial Transfer Formats (Asynchronous Mode)................................................ 374
Table 13.11
SSR Status Flags and Receive Data Handling .................................................. 381
Table 13.12
SCI Interrupt Sources........................................................................................ 412
Rev. 2.00 Dec. 05, 2005 Page xxxv of xxxviii
Table 13.13
SCI Interrupt Sources........................................................................................ 413
Section 14 Controller Area Network (HCAN)
Table 14.1
HCAN Pins ........................................................................................................... 423
Table 14.2
Limits for the Settable Value ................................................................................ 454
Table 14.3
Setting Range for TSEG1 and TSEG2 in BCR..................................................... 455
Table 14.4
HCAN Interrupt Sources (HCAN_0, HCAN_1) .................................................. 468
Table 14.5
Interval Limitation between TXPR and TXPR or between TXPR and TXCR..... 474
Section 15 A/D Converter
Table 15.1
Pin Configuration.................................................................................................. 477
Table 15.2
Analog Input Channels and Corresponding ADDR Registers .............................. 478
Table 15.3
A/D Conversion Time (Single Mode)................................................................... 484
Table 15.4
A/D Conversion Time (Scan Mode) ..................................................................... 484
Table 15.5
A/D Converter Interrupt Source............................................................................ 485
Table 15.6
Analog Pin Specifications..................................................................................... 491
Section 16 Motor Control PWM Timer (PWM)
Table 16.1
Pin Configuration.................................................................................................. 495
Table 16.2
Output Selection by OTS Bit ................................................................................ 501
Section 17 LCD Controller/Driver
Table 17.1
Pin Configuration.................................................................................................. 511
Table 17.2
Duty Cycle and Common Function Selection....................................................... 513
Table 17.3
Segment Driver Selection ..................................................................................... 514
Table 17.4
Frame Frequency Selection .................................................................................. 516
Table 17.5
Output Levels (A Waveform) ............................................................................... 525
Table 17.6
Power-Down Modes and Display Operation ........................................................ 526
Section 19 ROM
Table 19.1
Differences between Boot Mode and User Program Mode .................................. 531
Table 19.2
Pin Configuration.................................................................................................. 536
Table 19.3
Setting On-Board Programming Modes ............................................................... 542
Table 19.4
Boot Mode Operation ........................................................................................... 544
Table 19.5
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate
is Possible ............................................................................................................. 544
Table 19.6
Flash Memory Operating States............................................................................ 555
Table 19.7
Registers Present in F-ZTAT Version but Absent in Mask ROM Version........... 558
Section 20 Clock Pulse Generator
Table 20.1
Damping Resistance Value................................................................................... 562
Table 20.2
Crystal Resonator Characteristics ......................................................................... 563
Table 20.3
External Clock Input Conditions .......................................................................... 564
Rev. 2.00 Dec. 05, 2005 Page xxxvi of xxxviii
Section 21 Power-Down Modes
Table 21.1
LSI Internal States in Each Mode ......................................................................... 570
Table 21.2
Power-Down Mode Transition Conditions ........................................................... 572
Table 21.3
Standby Time Settings .......................................................................................... 575
Table 21.4
φ Pin State in Each Processing State..................................................................... 588
Section 23 Electrical Characteristics [Preliminary]
Table 23.1
Absolute Maximum Ratings ................................................................................. 675
Table 23.2
DC Characteristics ................................................................................................ 676
Table 23.3
Permissible Output Currents ................................................................................. 680
Table 23.4
Clock Timing ........................................................................................................ 682
Table 23.5
Control Signal Timing .......................................................................................... 683
Table 23.6
Bus Timing ........................................................................................................... 685
Table 23.7
Timing of On-Chip Peripheral Modules ............................................................... 691
Table 23.8
A/D Conversion Characteristics............................................................................ 696
Table 23.9
LCD Characteristics.............................................................................................. 697
Table 23.10
Flash Memory Characteristics .......................................................................... 698
Rev. 2.00 Dec. 05, 2005 Page xxxvii of xxxviii
Rev. 2.00 Dec. 05, 2005 Page xxxviii of xxxviii
Section 1 Overview
Section 1 Overview
1.1
Features
• High-speed H8S/2600 central processing unit with 16-bit architecture
 Upward-compatible with H8/300 and H8/300H CPUs on an object level
 Sixteen 16-bit general registers
 Sixty-nine basic instructions
• Various peripheral functions
 PC break controller (PBC)
 Data transfer controller (DTC)
 16-bit timer pulse unit (TPU)
 Programmable pulse generator (PPG)
 Controller area network (HCAN)
 Watchdog timer (WDT)
 Asynchronous or clocked synchronous serial communication interface (SCI)
 Motor control PWM timer
 LCD controller/driver
 10-bit A/D converter
 Clock pulse generator
• On-chip memory
ROM
Product Code
ROM
RAM
Flash memory version
HD64F2649
256 kbytes
6 kbytes
Masked ROM version
HD6432649
256 kbytes
6 kbytes
Remarks
Under planning
• General I/O ports
 I/O pins: 97
 Input pins: 16
• Supports various power-down modes
• Compact package
Package
(Code)
Body Size
Pin Pitch
QFP-144
FP-144G
20.0 × 20.0 mm
0.5 mm
Rev. 2.00 Dec. 05, 2005 Page 1 of 724
REJ09B0200-0200
Section 1 Overview
1.2
Internal Block Diagram
Port 5
Port 3
A/D converter
PPG
Port H
PH0/PWM1A
PH1/PWM1B
PH2/PWM1C
PH3/PWM1D
PH4/PWM1E
PH5/ PWM1F
PH6/ PWM1G
PH7/PWM1H
Port J
Figure 1.1 Internal Block Diagram
Rev. 2.00 Dec. 05, 2005 Page 2 of 724
Port 4
PJ0/PWM2A
PJ1/PWM2B
PJ2/PWM2C
PJ3/PWM2D
PJ4/PWM2E
PJ5/ PWM2F
PJ6/ PWM2G
PJ7/PWM2H
Vref
AVcc
AVss
P47 / AN7
P46 / AN6
P45 / AN5
P44 / AN4
P43 / AN3
P42 / AN2
P41 / AN1
P40 / AN0
Port 1
P10 /PO8/TIOCA0
P11 /PO9/TIOCB0
P12 / PO10/ TIOCC0 / TCLKA
P13 / PO11/ TIOCD0 / TCLKB
P14 / PO12/ TIOCA1/IRQ0
P15 / PO13/ TIOCB1 / TCLKC
P16 / PO14/ TIOCA2/IRQ1
P17 / PO15/ TIOCB2 /TCLKD
Port 9
Port 2
Port K
Motor control PWM timer
× 2 channel
Note: * The FWE pin is available only for the flash memory version and is an NC pin for the Masked ROM version.
REJ09B0200-0200
PC7/A7/ SEG24
PC6/A6/ SEG23
PC5/A5/SEG22
PC4/A4/SEG21
PC3/A3/SEG20
PC2/A2/SEG19
PC1/A1/SEG18
PC0/A0/SEG17
HCAN × 2 channels
LCD controller/driver
PK7/HRxD1
PK6/HTxD1
PB7/A15/SEG32
PB6/A14/SEG31
PB5/A13/SEG30
PB4/A12/SEG29
PB3 / A11/SEG28
PB2/A10/SEG27
PB1/A9/SEG26
PB0/A8/SEG25
SCI × 4 channels
TPU
P20/TIOCA3
P21/TIOCB3
P22/TIOCC3
P23/TIOCD3
P24/TIOCA4
P25/TIOCB4
P26/TIOCA5
P27/TIOCB5
Port A
WDT × 2 channels
Port B
Peripheral data bus
ROM (flash memory) *
Masked ROM
Peripheral address bus
PC break controller
RAM
P52/SCK2
P51/RxD2
P50/TxD2
DTC
PA7/A23/SEG40
PA6/ A22/SEG39
PA5/A21/SEG38
PA4/A20/SEG37
PA3/A19/COM4
PA2/A18/COM3
PA1/A17/COM2
PA0/A16/COM1
Port C
Internal data bus
H8S/2600 CPU
Bus controller
PE7 / D7/SEG8
PE6 / D6/SEG7
PE5 / D5/SEG6
PE4 / D4/SEG5
PE3 / D3/SEG4
PE2 / D2/SEG3
PE1 / D1/SEG2
PE0 / D0/SEG1
Port E
Internal address bus
PD7 / D15/SEG16
PD6 / D14/SEG15
PD5 / D13/SEG14
PD4 / D12/SEG13
PD3 / D11/SEG12
PD2 / D10/SEG11
PD1 / D9/SEG10
PD0 / D8/SEG9
V1
V2
V3
Port D
Interrupt controller
Port F
PF7/φ
PF6/AS/SEG36
PF5/RD/SEG35
PF4/HWR/SEG34
PF3/LWR/ADTRG/IRQ3
PF2/WAIT/SEG33
PF0/IRQ2
PLL
MD2
MD1
MD0
OSC2
OSC1
EXTAL
XTAL
PLLCAP
PLLVss
STBY
RES
NMI
FWE/NC*
HTxD0
HRxD0
Clock pulse
generator
Vcc
PWMVcc
LPVcc
Vss
PWMVss
VCL
Figure 1.1 shows an internal block diagram.
P37/TxD4
P36/RxD4
P35/SCK1/SCK4/IRQ5
P34/RxD1
P33/TxD1
P32/SCK0/IRQ4
P31/RxD0
P30/TxD0
P97/AN15
P96/AN14
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
Section 1 Overview
1.3
Pin Assignments
1.3.1
Pin Assignments
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FP-144G
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
MD2
PWMVss
PJ7/PWM2H
PJ6/PWM2G
PJ5/PWM2F
PJ4/PWM2E
PWMVcc
PJ3/PWM2D
PJ2/PWM2C
PJ1/PWM2B
PJ0/PWM2A
PWMVss
PH7/PWM1H
PH6/PWM1G
PH5/PWM1F
PH4/PWM1E
PWMVcc
PH3/PWM1D
PH2/PWM1C
PH1/PWM1B
PH0/PWM1A
PWMVss
PA3/A19/COM4
PA2/A18/COM3
PA1/A17/COM2
PA0/A16/COM1
PA7/A23/SEG40
PA6/A22/SEG39
PA5/A21/SEG38
PA4/A20/SEG37
PF6/AS/SEG36
PF5/RD/SEG35
Vss
PF4/HWR/SEG34
PF2/WAIT/SEG33
PB7/A15/SEG32
V1
V2
V3
PE0/D0/SEG1
PE1/D1/SEG2
PE2/D2/SEG3
PE3/D3/SEG4
PE4/D4/SEG5
PE5/D5/SEG6
PE6/D6/SEG7
PE7/D7/SEG8
Vss
PD0/D8/SEG9
PD1/D9/SEG10
PD2/D10/SEG11
PD3/D11/SEG12
PD4/D12/SEG13
PD5/D13/SEG14
PD6/D14/SEG15
PD7/D15/SEG16
LPVcc
PC0/A0/SEG17
PC1/A1/SEG18
PC2/A2/SEG19
PC3/A3/SEG20
PC4/A4/SEG21
PC5/A5/SEG22
PC6/A6/SEG23
PC7/A7/SEG24
PB0/A8/SEG25
PB1/A9/SEG26
PB2/A10/SEG27
PB3/A11/SEG28
PB4/A12/SEG29
PB5/A13/SEG30
PB6/A14/SEG31
HTxD0
HRxD0
P50/TxD2
P51/RxD2
P52/SCK2
P20/TIOCA3
P21/TIOCB3
P22/TIOCC3
P23/TIOCD3
P25/TIOCB4
Vcc
P24/TIOCA4
PK6/HTxD1
P27/TIOCB5
Vss
P26/TIOCA5
PK7/HRxD1
AVcc
Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12
P95/AN13
P96/AN14
P97/AN15
AVss
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2/IRQ1
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1/IRQ0
P13/PO11/TIOCD0/TCLKB
P12/PO10/TIOCC0/TCLKA
P11/PO9/TIOCB0
P10/PO8/TIOCA0
PF7/φ
PF3/LWR/ADTRG/IRQ3
PF0/IRQ2
FWE/NC*
EXTAL
Vss
XTAL
VCL
Vcc
Vcc
OSC2
OSC1
Vss
PLLCAP
PLLVss
STBY
NMI
RES
P37/TxD4
P36/RxD4
P35/SCK1/SCK4/IRQ5
P34/RxD1
P33/TxD1
P32/SCK0/IRQ4
P31/RxD0
P30/TxD0
MD0
MD1
Figure 1.2 shows pin assignments.
Note: * The FWE pin is available only for the flash memory version and is an NC pin for the Masked ROM version.
Figure 1.2 Pin Assignments (FP-144G)
Rev. 2.00 Dec. 05, 2005 Page 3 of 724
REJ09B0200-0200
Section 1 Overview
1.3.2
Pin Functions in Each Operating Mode
Table 1.1 shows the pin functions in each of the operating modes.
Table 1.1
Pin Functions in Each Operating Mode
Pin Name
Pin No. Mode 4
Mode 5
Mode 6
Mode 7
1
V1
V1
V1
V1
2
V2
V2
V2
V2
3
V3
V3
V3
V3
4
PE0/D0/SEG1
PE0/D0/SEG1
PE0/D0/SEG1
PE0/SEG1
5
PE1/D1/SEG2
PE1/D1/SEG2
PE1/D1/SEG2
PE1/SEG2
6
PE2/D2/SEG3
PE2/D2/SEG3
PE2/D2/SEG3
PE2/SEG3
7
PE3/D3/SEG4
PE3/D3/SEG4
PE3/D3/SEG4
PE3/SEG4
8
PE4/D4/SEG5
PE4/D4/SEG5
PE4/D4/SEG5
PE4/SEG5
9
PE5/D5/SEG6
PE5/D5/SEG6
PE5/D5/SEG6
PE5/SEG6
10
PE6/D6/SEG7
PE6/D6/SEG7
PE6/D6/SEG7
PE6/SEG7
11
PE7/D7/SEG8
PE7/D7/SEG8
PE7/D7/SEG8
PE7/SEG8
12
Vss
Vss
Vss
Vss
13
D8
D8
D8/SEG9
PD0/SEG9
14
D9
D9
D9/SEG10
PD1/SEG10
15
D10
D10
D10/SEG11
PD2/SEG11
16
D11
D11
D11/SEG12
PD3/SEG12
17
D12
D12
D12/SEG13
PD4/SEG13
18
D13
D13
D13/SEG14
PD5/SEG14
19
D14
D14
D14/SEG15
PD6/SEG15
20
D15
D15
D15/SEG16
PD7/SEG16
21
LPVcc
LPVcc
LPVcc
LPVcc
22
A0
A0
PC0/A0/SEG17
PC0/SEG17
23
A1
A1
PC1/A1/SEG18
PC1/SEG18
24
A2
A2
PC2/A2/SEG19
PC2/SEG19
25
A3
A3
PC3/A3/SEG20
PC3/SEG20
26
A4
A4
PC4/A4/SEG21
PC4/SEG21
Rev. 2.00 Dec. 05, 2005 Page 4 of 724
REJ09B0200-0200
Section 1 Overview
Pin Name
Pin No. Mode 4
Mode 5
Mode 6
Mode 7
27
A5
A5
PC5/A5/SEG22
PC5/SEG22
28
A6
A6
PC6/A6/SEG23
PC6/SEG23
29
A7
A7
PC7/A7/SEG24
PC7/SEG24
30
PB0/A8/SEG25
PB0/A8/SEG25
PB0/A8/SEG25
PB0/SEG25
31
PB1/A9/SEG26
PB1/A9/SEG26
PB1/A9/SEG26
PB1/SEG26
32
PB2/A10/SEG27
PB2/A10/SEG27
PB2/A10/SEG27
PB2/SEG27
33
PB3/A11/SEG28
PB3/A11/SEG28
PB3/A11/SEG28
PB3/SEG28
34
PB4/A12/SEG29
PB4/A12/SEG29
PB4/A12/SEG29
PB4/SEG29
35
PB5/A13/SEG30
PB5/A13/SEG30
PB5/A13/SEG30
PB5/SEG30
36
PB6/A14/SEG31
PB6/A14/SEG31
PB6/A14/SEG31
PB6/SEG31
37
PB7/A15/SEG32
PB7/A15/SEG32
PB7/A15/SEG32
PB7/SEG32
38
WAIT/SEG33
WAIT/SEG33
WAIT/SEG33
PF2/SEG33
39
HWR/SEG34
HWR/SEG34
HWR/SEG34
PF4/SEG34
40
Vss
Vss
Vss
Vss
41
RD/SEG35
RD/SEG35
RD/SEG35
PF5/SEG35
42
AS/SEG36
AS/SEG36
AS/SEG36
PF6/SEG36
43
PA4/A20/SEG37
PA4/A20/SEG37
PA4/A20/SEG37
PA4/SEG37
44
PA5/A21/SEG38
PA5/A21/SEG38
PA5/A21/SEG38
PA5/SEG38
45
PA6/A22/SEG39
PA6/A22/SEG39
PA6/A22/SEG39
PA6/SEG39
46
PA7/A23/SEG40
PA7/A23/SEG40
PA7/A23/SEG40
PA7/SEG40
47
PA0/A16/COM1
PA0/A16/COM1
PA0/A16/COM1
PA0/COM1
48
PA1/A17/COM2
PA1/A17/COM2
PA1/A17/COM2
PA1/COM2
49
PA2/A18/COM3
PA2/A18/COM3
PA2/A18/COM3
PA2/COM3
50
PA3/A19/COM4
PA3/A19/COM4
PA3/A19/COM4
PA3/COM4
51
PWMVss
PWMVss
PWMVss
PWMVss
52
PH0/PWM1A
PH0/PWM1A
PH0/PWM1A
PH0/PWM1A
53
PH1/PWM1B
PH1/PWM1B
PH1/PWM1B
PH1/PWM1B
54
PH2/PWM1C
PH2/PWM1C
PH2/PWM1C
PH2/PWM1C
55
PH3/PWM1D
PH3/PWM1D
PH3/PWM1D
PH3/PWM1D
56
PWMVcc
PWMVcc
PWMVcc
PWMVcc
57
PH4/PWM1E
PH4/PWM1E
PH4/PWM1E
PH4/PWM1E
Rev. 2.00 Dec. 05, 2005 Page 5 of 724
REJ09B0200-0200
Section 1 Overview
Pin Name
Pin No. Mode 4
Mode 5
Mode 6
Mode 7
58
PH5/PWM1F
PH5/PWM1F
PH5/PWM1F
PH5/PWM1F
59
PH6/PWM1G
PH6/PWM1G
PH6/PWM1G
PH6/PWM1G
60
PH7/PWM1H
PH7/PWM1H
PH7/PWM1H
PH7/PWM1H
61
PWMVss
PWMVss
PWMVss
PWMVss
62
PJ0/PWM2A
PJ0/PWM2A
PJ0/PWM2A
PJ0/PWM2A
63
PJ1/PWM2B
PJ1/PWM2B
PJ1/PWM2B
PJ1/PWM2B
64
PJ2/PWM2C
PJ2/PWM2C
PJ2/PWM2C
PJ2/PWM2C
65
PJ3/PWM2D
PJ3/PWM2D
PJ3/PWM2D
PJ3/PWM2D
66
PWMVcc
PWMVcc
PWMVcc
PWMVcc
67
PJ4/PWM2E
PJ4/PWM2E
PJ4/PWM2E
PJ4/PWM2E
68
PJ5/PWM2F
PJ5/PWM2F
PJ5/PWM2F
PJ5/PWM2F
69
PJ6/PWM2G
PJ6/PWM2G
PJ6/PWM2G
PJ6/PWM2G
70
PJ7/PWM2H
PJ7/PWM2H
PJ7/PWM2H
PJ7/PWM2H
71
PWMVss
PWMVss
PWMVss
PWMVss
72
MD2
MD2
MD2
MD2
73
MD1
MD1
MD1
MD1
74
MD0
MD0
MD0
MD0
75
P30/TxD0
P30/TxD0
P30/TxD0
P30/TxD0
76
P31/RxD0
P31/RxD0
P31/RxD0
P31/RxD0
77
P32/SCK0/IRQ4
P32/SCK0/IRQ4
P32/SCK0/IRQ4
P32/SCK0/IRQ4
78
P33/TxD1
P33/TxD1
P33/TxD1
P33/TxD1
79
P34/RxD1
P34/RxD1
P34/RxD1
P34/RxD1
80
P35/SCK1/SCK4/
IRQ5
P35/SCK1/SCK4/
IRQ5
P35/SCK1/SCK4/
IRQ5
P35/SCK1/SCK4/
IRQ5
81
P36/RxD4
P36/RxD4
P36/RxD4
P36/RxD4
82
P37/TxD4
P37/TxD4
P37/TxD4
P37/TxD4
83
RES
RES
RES
RES
84
NMI
NMI
NMI
NMI
85
STBY
STBY
STBY
STBY
86
PLLVss
PLLVss
PLLVss
PLLVss
87
PLLCAP
PLLCAP
PLLCAP
PLLCAP
Rev. 2.00 Dec. 05, 2005 Page 6 of 724
REJ09B0200-0200
Section 1 Overview
Pin Name
Pin No. Mode 4
Mode 5
Mode 6
Mode 7
88
Vss
Vss
Vss
Vss
89
OSC1
OSC1
OSC1
OSC1
90
OSC2
OSC2
OSC2
OSC2
91
Vcc
Vcc
Vcc
Vcc
92
Vcc
Vcc
Vcc
Vcc
93
VCL
VCL
VCL
VCL
94
XTAL
XTAL
XTAL
XTAL
95
Vss
Vss
Vss
Vss
96
EXTAL
EXTAL
EXTAL
EXTAL
97
FWE
FWE
FWE
FWE
98
PF0/IRQ2
PF0/IRQ2
PF0/IRQ2
PF0/IRQ2
99
PF3/LWR/ADTRG/
IRQ3
PF3/LWR/ADTRG/
IRQ3
PF3/LWR/ADTRG/
IRQ3
PF3/ADTRG/IRQ3
100
PF7/φ
PF7/φ
PF7/φ
PF7/φ
101
P10/PO8/TIOCA0
P10/PO8/TIOCA0
P10/PO8/TIOCA0
P10/PO8/TIOCA0
102
P11/PO9/TIOCB0
P11/PO9/TIOCB0
P11/PO9/TIOCB0
P11/PO9/TIOCB0
103
P12/PO10/TIOCC0/
TCLKA
P12/PO10/TIOCC0/
TCLKA
P12/PO10/TIOCC0/
TCLKA
P12/PO10/TIOCC0/
TCLKA
104
P13/PO11/TIOCD0/
TCLKB
P13/PO11/TIOCD0/
TCLKB
P13/PO11/TIOCD0/
TCLKB
P13/PO11/TIOCD0/
TCLKB
105
P14/PO12/TIOCA1/
IRQ0
P14/PO12/TIOCA1/
IRQ0
P14/PO12/TIOCA1/
IRQ0
P14/PO12/TIOCA1/
IRQ0
106
P15/PO13/TIOCB1/
TCLKC
P15/PO13/TIOCB1/
TCLKC
P15/PO13/TIOCB1/
TCLKC
P15/PO13/TIOCB1/
TCLKC
107
P16/PO14/TIOCA2/
IRQ1
P16/PO14/TIOCA2/
IRQ1
P16/PO14/TIOCA2/
IRQ1
P16/PO14/TIOCA2/
IRQ1
108
P17/PO15/TIOCB2/
TCLKD
P17/PO15/TIOCB2/
TCLKD
P17/PO15/TIOCB2/
TCLKD
P17/PO15/TIOCB2/
TCLKD
109
HTxD0
HTxD0
HTxD0
HTxD0
110
HRxD0
HRxD0
HRxD0
HRxD0
111
P50/TxD2
P50/TxD2
P50/TxD2
P50/TxD2
112
P51/RxD2
P51/RxD2
P51/RxD2
P51/RxD2
Rev. 2.00 Dec. 05, 2005 Page 7 of 724
REJ09B0200-0200
Section 1 Overview
Pin Name
Pin No. Mode 4
Mode 5
Mode 6
Mode 7
113
P52/SCK2
P52/SCK2
P52/SCK2
P52/SCK2
114
P20/TIOCA3
P20/TIOCA3
P20/TIOCA3
P20/TIOCA3
115
P21/TIOCB3
P21/TIOCB3
P21/TIOCB3
P21/TIOCB3
116
P22/TIOCC3
P22/TIOCC3
P22/TIOCC3
P22/TIOCC3
117
P23/TIOCD3
P23/TIOCD3
P23/TIOCD3
P23/TIOCD3
118
P25/TIOCB4
P25/TIOCB4
P25/TIOCB4
P25/TIOCB4
119
Vcc
Vcc
Vcc
Vcc
120
P24/TIOCA4
P24/TIOCA4
P24/TIOCA4
P24/TIOCA4
121
PK6/HTxD1
PK6/HTxD1
PK6/HTxD1
PK6/HTxD1
122
P27/TIOCB5
P27/TIOCB5
P27/TIOCB5
P27/TIOCB5
123
Vss
Vss
Vss
Vss
124
P26/TIOCA5
P26/TIOCA5
P26/TIOCA5
P26/TIOCA5
125
PK7/HRxD1
PK7/HRxD1
PK7/HRxD1
PK7/HRxD1
126
AVcc
AVcc
AVcc
AVcc
127
Vref
Vref
Vref
Vref
128
P40/AN0
P40/AN0
P40/AN0
P40/AN0
129
P41/AN1
P41/AN1
P41/AN1
P41/AN1
130
P42/AN2
P42/AN2
P42/AN2
P42/AN2
131
P43/AN3
P43/AN3
P43/AN3
P43/AN3
132
P44/AN4
P44/AN4
P44/AN4
P44/AN4
133
P45/AN5
P45/AN5
P45/AN5
P45/AN5
134
P46/AN6
P46/AN6
P46/AN6
P46/AN6
135
P47/AN7
P47/AN7
P47/AN7
P47/AN7
136
P90/AN8
P90/AN8
P90/AN8
P90/AN8
137
P91/AN9
P91/AN9
P91/AN9
P91/AN9
138
P92/AN10
P92/AN10
P92/AN10
P92/AN10
139
P93/AN11
P93/AN11
P93/AN11
P93/AN11
140
P94/AN12
P94/AN12
P94/AN12
P94/AN12
141
P95/AN13
P95/AN13
P95/AN13
P95/AN13
142
P96/AN14
P96/AN14
P96/AN14
P96/AN14
Rev. 2.00 Dec. 05, 2005 Page 8 of 724
REJ09B0200-0200
Section 1 Overview
Pin Name
Pin No. Mode 4
Mode 5
Mode 6
Mode 7
143
P97/AN15
P97/AN15
P97/AN15
P97/AN15
144
AVss
AVss
AVss
AVss
Note: In mode 4 and mode 5, the following pins (D8 to D15, A0 to A7, RD, AS, and HWR) are
used to interface with external ROM. Therefore, these pins must not be set to the SEG
signal.
Rev. 2.00 Dec. 05, 2005 Page 9 of 724
REJ09B0200-0200
Section 1 Overview
1.3.3
Pin Functions
Table 1.2 shows pin functions.
Table 1.2
Pin Functions
Type
Symbol
Pin No.
I/O
Power supply
Vcc
91, 92, 119 Input
Name and Function
Power supply pins
These pins should be connected to the
system power supply.
PWMVcc
56, 66
Input
Power supply pin for port H, port J, and
the motor control PWM timer output
LPVcc
21
Input
Power supply pin for ports A, B, C, D, E,
and part of port F (PF2 and PF4 to PF6)
Input
Power supply pin for LCD controller/
driver
V1, V2, V3 1, 2, 3
There is an on-chip power supply
division resistor, so this pin is normally
left open. Power supply conditions:
LPVcc ≥ V1 ≥ V2 ≥ V3 ≥ Vss
Vss
12, 40, 88, Input
95, 123
Ground pins
PWMVss
51, 61, 71
Input
Power supply pin for port H, port J, and
the motor control PWM timer output
These pins should be connected to the
system power supply (0 V).
VCL
93
Input
Pin for connecting the on-chip stepdown power supply to a capacitor for
voltage stabilization. Connect to Vss via
a 0.1 µF capacitor (which should be
located near the pin). Do not connect
this pin to an external power supply.
Rev. 2.00 Dec. 05, 2005 Page 10 of 724
REJ09B0200-0200
These pins should be connected to the
system power supply (0 V).
Section 1 Overview
Type
Symbol
Pin No.
I/O
Name and Function
Clock
PLLVss
86
Input
Ground pin for on-chip PLL oscillator
PLLCAP
87
Input
External capacitance pin for on-chip PLL
oscillator
XTAL
94
Input
Connects to a crystal oscillator.
EXTAL
96
Input
See section 20, Clock Pulse Generator,
for typical connection diagrams for a
crystal oscillator.
The EXTAL pin can also input an
external clock.
Connects to a 32.768-MHz crystal
oscillator. See section 20, Clock Pulse
Generator, for typical connection
diagrams for a crystal oscillator.
OSC1
89
Input
OSC2
90
Input
φ
100
Output
Supplies the system clock to an external
device.
Operating mode
control
MD2 to
MD0
72 to 74
Input
These pins set the operating mode.
These pins should not be changed while
this LSI is operating.
System control
RES
83
Input
Reset pin
When this pin is driven low, the chip is
reset.
STBY
85
Input
When this pin is driven low, a transition
is made to hardware standby mode.
FWE
97
Input
Pin for flash memory
NMI
84
Input
Requests a nonmaskable interrupt.
When this pin is not used, it should be
fixed high.
IRQ5 to
IRQ0
80, 77, 99, Input
98, 107,
105
These pins request a maskable
interrupt.
Address bus
A23 to A0
46 to 43,
50 to 47,
37 to 22
Output
These pins output an address.
Data bus
D15 to D0
20 to 13,
11 to 4
I/O
These pins constitute a bidirectional
data bus.
Interrupts
Rev. 2.00 Dec. 05, 2005 Page 11 of 724
REJ09B0200-0200
Section 1 Overview
Type
Symbol
Pin No.
I/O
Name and Function
Bus control
AS
42
Output
When this pin is low, it indicates that
address output on the address bus is
enabled.
RD
41
Output
When this pin is low, it indicates that the
external address space can be read.
HWR
39
Output
A strobe signal that writes to external
space and indicates that the upper half
(D15 to D8) of the data bus is enabled.
LWR
99
Output
A strobe signal that writes to external
space and indicates that the lower half
(D7 to D0) of the data bus is enabled.
WAIT
38
Input
It is necessary to insert a wait state into
the bus cycle when accessing the
external three-state address space.
TCLKD to
TCLKA
103, 102,
106, 108
Input
These pins input an external clock.
TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0
101,
102,
123,
104
I/O
TGR0A to TGR0D input capture input,
output compare output, or output PWM.
TIOCA1,
TIOCB1
105,
106
I/O
TGR1A and TGR1B input capture input,
output compare output, or output PWM.
TIOCA2,
TIOCB2
107,
108
I/O
TGR2A and TGR2B input capture input,
output compare output, or output PWM.
TIOCA3,
TIOCB3,
TIOCC3,
TIOCD3
114,
115,
116,
117
I/O
TGR3A to TGR3D input capture input,
output compare output, or output PWM.
TIOCA4,
TIOCB4
120,
118
I/O
TGR4A and TGR4B input capture input,
output compare output, or output PWM.
TIOCA5,
TIOCB5
124,
122
I/O
TGR5A and TGR5B input capture input,
output compare output, or output PWM.
16-bit timer
pulse unit (TPU)
Programmable pulse PO15 to
generator (PPG)
PO8
108 to 101 Output
Rev. 2.00 Dec. 05, 2005 Page 12 of 724
REJ09B0200-0200
Pulse output pins
Section 1 Overview
Type
Pin No.
I/O
Name and Function
Serial communication TxD4,
interface (SCI)/
TxD2,
Smart Card interface TxD1,
TxD0
82
111
78
75
Output
Transmit data output pins
RxD4,
RxD2,
RxD1,
RxD0
81
112
79
76
Input
Receive data input pins
SCK4,
SCK2,
SCK1,
SCK0
80
113
80
77
I/O
Clock I/O pins
HTxD0
HTxD1
109,
121
Output
Pin for CAN bus transmission
HRxD0
HRxD1
110,
125
Input
Pin for CAN bus reception
AN15 to
AN0
143 to 128 Input
Analog input pins
ADTRG
99
Input
Pin for input of an external trigger to
start A/D conversion
AVcc
126
Input
A/D converter power supply pin
Controller area
network (HCAN)
A/D converter
Symbol
The SCK output type is NMOS pushpull.
If the A/D converter is not used, connect
this pin to the system power supply (+5
V).
AVss
144
Input
A/D converter ground pin
Connect this pin to the system power
supply (0 V).
Vref
127
Input
A/D converter reference voltage input
pin
If the A/D converter is not used, connect
this pin to the system power supply (+5
V).
Motor control PWM
timer
PWM1A to 52 to 55,
PWM1H
57 to 60
Output
PWM timer channel 1 output pins
PWM2A to 62 to 65,
PWM2H
67 to 70
Output
PWM timer channel 2 output pins
Rev. 2.00 Dec. 05, 2005 Page 13 of 724
REJ09B0200-0200
Section 1 Overview
Type
Symbol
LCD controller/driver SEG40 to
SEG1
COM4 to
COM1
I/O ports
Pin No.
I/O
Name and Function
46 to 41,
39 to 22,
20 to 13,
11 to 4
Output
LCD segment output pins
50 to 47
Output
LCD common output pins
P17 to P10 108 to 101 I/O
8-bit I/O pins
P27 to P20 122, 124, I/O
118, 120,
117 to 114
8-bit I/O pins
P37 to P30 82 to 75
8-bit I/O pins
P47 to P40 135 to 128 Input
8-bit input pins
P52 to P50 113 to 111 I/O
3-bit I/O pins
P97 to P90 143 to 136 Input
8-bit input pins
PA7 to
PA0
46 to 43,
50 to 47
I/O
8-bit I/O pins
PB7 to
PB0
37 to 30
I/O
8-bit I/O pins
PC7 to
PC0
29 to 22
I/O
8-bit I/O pins
PD7 to
PD0
20 to 13
I/O
8-bit I/O pins
PE7 to
PE0
11 to 4
I/O
8-bit I/O pins
PF7 to
PF2, PF0
100, 42,
I/O
41, 39, 99,
38, 98
7-bit I/O pins
PH7 to
PH0
60 to 57,
55 to 52
I/O
8-bit I/O pins
PK7, PK6
121, 125
I/O
2-bit I/O pins
Rev. 2.00 Dec. 05, 2005 Page 14 of 724
REJ09B0200-0200
I/O
Section 2 CPU
Section 2 CPU
The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1
Features
• Upward-compatible with H8/300 and H8/300H CPUs
 Can execute H8/300 and H8/300H CPUs object programs
• General-register architecture
 Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-nine basic instructions
 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
 Multiply-and-accumulate instruction
• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]
• 16-Mbyte address space
 Program: 16 Mbytes
 Data:
16 Mbytes
• High-speed operation
 All frequently-used instructions execute in one or two states
 8/16/32-bit register-register add/subtract: 1 state
 8 × 8-bit register-register multiply: 3 states
CPUS260A_000020020300
Rev. 2.00 Dec. 05, 2005 Page 15 of 724
REJ09B0200-0200
Section 2 CPU
 16 ÷ 8-bit register-register divide: 12 states
 16 × 16-bit register-register multiply: 4 states
 32 ÷ 16-bit register-register divide: 20 states
• Two CPU operating modes
 Normal mode*
 Advanced mode
• Power-down state
 Transition to power-down state by the SLEEP instruction
 CPU clock speed selection
Note: * Normal mode is not available in this LSI.
2.1.1
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported by the H8S/2600 CPU only.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600
CPU only.
• The number of execution states of the MULXU and MULXS instructions;
Execution States
Instruction
Mnemonic
H8S/2600
H8S/2000
MULXU
MULXU.B Rs, Rd
3
12
MULXU.W Rs, ERd
4
20
MULXS.B Rs, Rd
4
13
MULXS.W Rs, ERd
5
21
MULXS
In addition, there are differences in address space, CCR and EXR register functions, and powerdown modes, etc., depending on the model.
Rev. 2.00 Dec. 05, 2005 Page 16 of 724
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Section 2 CPU
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements:
• More general registers and control registers
 Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been
added.
• Expanded address space
 Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
 Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
 The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 Signed multiply and divide instructions have been added.
 A multiply-and-accumulate instruction has been added.
 Two-bit shift instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.
• Higher speed
 Basic instructions execute twice as fast.
2.1.3
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements:
• More control registers
 One 8-bit and two 32-bit control registers have been added.
• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 A multiply-and-accumulate instruction has been added.
 Two-bit shift instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.
Rev. 2.00 Dec. 05, 2005 Page 17 of 724
REJ09B0200-0200
Section 2 CPU
• Higher speed
 Basic instructions execute twice as fast.
2.2
CPU Operating Modes
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space. The mode is selected by the mode pins.
2.2.1
Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU.
• Address Space
Linear access to a 64-kbyte maximum address space is provided.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even
when the corresponding general register (Rn) is used as an address register. If the general
register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or
post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding
extended register (En) will be affected.
• Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
• Exception Vector Table and Memory Indirect Branch Addresses
In normal mode the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table structure in normal mode is
shown in figure 2.1. For details of the exception vector table, see section 4, Exception
Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode the operand is a 16-bit word operand,
providing a 16-bit branch address. Branch addresses can be stored in the area from H'0000 to
H'00FF. Note that the first part of this range is also used for the exception vector table.
Rev. 2.00 Dec. 05, 2005 Page 18 of 724
REJ09B0200-0200
Section 2 CPU
• Stack Structure
When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,
condition-code register (CCR), and extended control register (EXR) are pushed onto the stack
in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack
in interrupt control mode 0. For details, see section 4, Exception Handling.
Note: Normal mode is not available in this LSI.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Exception vector 1
Exception vector 2
Exception vector 3
Exception
vector table
Exception vector 4
Exception vector 5
Exception vector 6
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC
(16 bits)
EXR*1
SP
(SP *
2
Reserved*1,*3
)
CCR
CCR*3
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Figure 2.2 Stack Structure in Normal Mode
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Section 2 CPU
2.2.2
Advanced Mode
• Address Space
Linear access to a 16-Mbyte maximum address space is provided.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.
• Instruction Set
All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is
stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4,
Exception Handling.
H'00000000
Reserved
Exception vector 1
H'00000003
H'00000004
Reserved
Exception vector 2
H'00000007
H'00000008
Reserved
Exception vector table
Exception vector 3
H'0000000B
H'0000000C
Reserved
Exception vector 4
H'00000010
Reserved
Exception vector 5
Figure 2.3 Exception Vector Table (Advanced Mode)
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Section 2 CPU
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the first part of this range is also used for the exception vector table.
• Stack Structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When
EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4,
Exception Handling.
EXR*1
SP
SP
Reserved
PC
(24 bits)
(SP
*2
Reserved*1, *3
)
(a) Subroutine Branch
CCR
PC
(24 bits)
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
Figure 2.4 Stack Structure in Advanced Mode
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REJ09B0200-0200
Section 2 CPU
2.3
Address Space
Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, refer to section 3, MCU Operating
Modes.
H'0000
H'00000000
64-kbyte
16-Mbyte
H'FFFF
Program area
H'00FFFFFF
Data area
Cannot be
used in this LSI
H'FFFFFFFF
(a) Normal Mode
(b) Advanced Mode
Figure 2.5 Memory Map
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REJ09B0200-0200
Section 2 CPU
2.4
Registers
The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), an
8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit
multiply-accumulate register (MAC).
General Registers (Rn) and Extended Registers (En)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers (CR)
0
23
PC
7 6 5 4 3 2 1 0
- - - - I2 I1 I0
EXR T
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
63
41
MAC
32
MACH
Sign extension
MACL
31
0
[Legend]
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit
H:
U:
N:
Z:
V:
C:
MAC:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Multiply-accumulate register
Figure 2.6 CPU Registers
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Section 2 CPU
2.4.1
General Registers
The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers.
The usage of each register can be selected independently.
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.7 Usage of General Registers
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REJ09B0200-0200
Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.8 Stack
2.4.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0).
2.4.3
Extended Control Register (EXR)
EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
When these instructions, except for the STC instruction, are executed, all interrupts including NMI
will be masked for three states after execution is completed.
Bit
Bit Name
Initial
Value
R/W
Description
7
T
0
R/W
Trace Bit
When this bit is set to 1, a trace exception is generated
each time an instruction is executed. When this bit is
cleared to 0, instructions are executed in sequence.
6 to 3

All 1

Reserved
These bits are always read as 1.
2
I2
1
R/W
1
I1
1
R/W
0
I0
1
R/W
These bits designate the interrupt mask level (0 to 7).
For details, refer to section 5, Interrupt Controller.
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REJ09B0200-0200
Section 2 CPU
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit
Bit Name
Initial
Value
R/W
Description
7
I
1
R/W
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to
1 at the start of an exception-handling sequence. For
details, refer to section 5, Interrupt Controller.
6
UI
Undefined R/W
User Bit or Interrupt Mask Bit
Can be read or written by software using the LDC, STC,
ANDC, ORC, and XORC instructions. This bit cannot be
used as an interrupt mask bit in this LSI.
5
H
Undefined R/W
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined R/W
User Bit
Can be read or written by software using the LDC, STC,
ANDC, ORC, and XORC instructions.
3
N
Undefined R/W
Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2
Z
Undefined R/W
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
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REJ09B0200-0200
Section 2 CPU
Bit
Bit Name
Initial
Value
1
V
Undefined R/W
R/W
Description
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
0
C
Undefined R/W
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
2.4.5
Multiply-Accumulate Register (MAC)
This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are
a sign extension.
2.4.6
Initial Values of CPU Registers
Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.
Rev. 2.00 Dec. 05, 2005 Page 27 of 724
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Section 2 CPU
2.5
Data Formats
The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1
General Register Data Formats
Figure 2.9 shows the data formats in general registers.
Data Type
Register Number
Data Format
7
RnH
1-bit data
0
Don't care
7 6 5 4 3 2 1 0
0
7
1-bit data
RnL
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
Don't care
7
7 6 5 4 3 2 1 0
4 3
Upper
0
Lower
Don't care
7
Don't care
7
4 3
Upper
0
Don't care
MSB
LSB
7
Byte data
RnL
Figure 2.9 General Register Data Formats (1)
REJ09B0200-0200
0
Don't care
MSB
Rev. 2.00 Dec. 05, 2005 Page 28 of 724
0
Lower
LSB
Section 2 CPU
Data Type
Register Number
Word data
Rn
Data Format
15
0
MSB
Word data
15
0
MSB
Longword data
LSB
En
LSB
ERn
31
16 15
MSB
En
0
Rn
LSB
[Legend]
ERn:
General register ER
En:
General register E
Rn:
General register R
RnH:
General register RH
RnL:
General register RL
MSB:
Most significant bit
LSB:
Least significant bit
Figure 2.9 General Register Data Formats (2)
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2.5.2
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 is used as an address register to access the stack, the operand size should be word or
longword.
Data Type
Address
Data Format
7
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M+1
Longword data
1
MSB
Address 2N+1
Address 2N+2
Address 2N+3
Figure 2.10 Memory Data Formats
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LSB
Section 2 CPU
2.6
Instruction Set
The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Data transfer
Size
MOV
B/W/L 5
POP*1, PUSH*1
W/L
LDM, STM
3
MOVFPE* , MOVTPE*
Arithmetic
operation
Types
L
3
B
ADD, SUB, CMP, NEG
B/W/L 23
ADDX, SUBX, DAA, DAS
B
INC, DEC
B/W/L
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
W/L
TAS*4
B
MAC, LDMAC, STMAC, CLRMAC

Logic operations
AND, OR, XOR, NOT
B/W/L 4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8
Bit manipulation
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
B
14
Branch
Bcc*2, JMP, BSR, JSR, RTS

5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 
9

1
Block data transfer EEPMOV
Total: 69
Notes: B-byte; W-word; L-longword.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+,Rn and MOV.W Rn,@-SP.
POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+,ERn and
MOV.L ERn,@-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
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2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2
Operation Notation
Symbol
Description
Rd
General register (destination)*
Rs
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
MAC
Multiply-accumulate register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical XOR
→
Move
∼
NOT (logical complement)
:8/:16/:24/:32
8-, 16-, 24-, or 32-bit length
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Note:
*
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Table 2.3
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
Cannot be used in this LSI.
MOVTPE
B
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
LDM
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM
L
Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.4
Arithmetic Operations Instructions (1)
Instruction
Size*
Function
ADD
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the SUBX
or ADD instruction.)
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
INC
DEC
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS
SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA
DAS
B
Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.4
Arithmetic Operations Instructions (2)
Instruction
Size*1
Function
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.
NEG
B/W/L
0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
TAS*2
B
@ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
MAC

(EAs) × (EAd) + MAC → MAC
Performs signed multiplication on memory contents and adds the result
to the multiply-accumulate register. The following operations can be
performed:
16 bits × 16 bits + 32 bits → 32 bits, saturating
16 bits × 16 bits + 42 bits → 42 bits, non-saturating
CLRMAC

0 → MAC
Clears the multiply-accumulate register to zero.
LDMAC
STMAC
L
Rs → MAC, MAC → Rd
Transfers data between a general register and a multiply-accumulate
register.
Note:
1. Refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
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Section 2 CPU
Table 2.5
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
∼(Rd) → (Rd)
Takes the one’s complement (logical complement) of general register
contents.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shifts are possible.
SHLL
SHLR
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shifts are possible.
ROTL
ROTR
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotations are possible.
ROTXL
ROTXR
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotations are possible.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.7
Bit Manipulation Instructions (1)
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
∼(<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
∼(<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
BIAND
B
BOR
B
BIOR
B
Note:
*
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∧ [∼(<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∨ [∼(<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Refers to the operand size.
B: Byte
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Table 2.7
Bit Manipulation Instructions (2)
Instruction
Size*1
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIXOR
B
BLD
B
BILD
B
C ⊕ [∼(<bit-No.> of <EAd>)] → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
∼(<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
BIST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
∼C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note:
*
Refers to the operand size.
B: Byte
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Table 2.8
Branch Instructions
Instruction
Size
Function
Bcc

Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA(BT)
Always (true)
Always
BRN(BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC(BHS)
Carry clear
(high or same)
C=0
BCS(BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z∨(N ⊕ V) = 0
BLE
Less or equal
Z∨(N ⊕ V) = 1
JMP

Branches unconditionally to a specified address.
BSR

Branches to a subroutine at a specified address.
JSR

Branches to a subroutine at a specified address.
RTS

Returns from a subroutine
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Section 2 CPU
Table 2.9
System Control Instructions
Instruction
Size*
Function
TRAPA

Starts trap-instruction exception handling.
RTE

Returns from an exception-handling routine.
SLEEP

Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves general register or memory contents or immediate data to CCR
or EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are valid.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically XORs the CCR or EXR contents with immediate data.
NOP

PC + 2 → PC
Only increments the program counter.
Note:
*
Refers to the operand size.
B: Byte
W: Word
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Table 2.10 Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B

if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W

if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
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2.6.2
Basic Instruction Formats
The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).
Figure 2.11 shows examples of instruction formats.
• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition Field
Specifies the branching condition of Bcc instructions.
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm, etc.
EA(disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA(disp)
BRA d:16, etc.
Figure 2.11 Instruction Formats (Examples)
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2.7
Addressing Modes and Effective Address Calculation
The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR,
BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in
the operand.
Table 2.11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
2.7.1
Register DirectRn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2
Register Indirect@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand on memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
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2.7.3
Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4
Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn
Register indirect with post-increment@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for
longword transfer instruction. For the word or longword transfer instructions, the register value
should be even.
Register indirect with pre-decrement@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result is the
address of a memory operand. The result is also stored in the address register. The value
subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer
instruction. For the word or longword transfer instructions, the register value should be even.
2.7.5
Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
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Table 2.12 Absolute Address Access Ranges
Absolute Address
Data address
Normal Mode*
8 bits (@aa:8)
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits (@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
32 bits (@aa:32)
Program instruction
address
Advanced Mode
H'000000 to H'FFFFFF
24 bits (@aa:24)
Note: Normal mode is not available in this LSI.
2.7.6
Immediate#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
2.7.7
Program-Counter Relative@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.
Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0
(H′00). The PC value to which the displacement is added is the address of the first byte of the next
instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to
+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should
be an even number.
2.7.8
Memory Indirect@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode,
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode,
the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00).
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Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
Note: Normal mode is not available in this LSI.
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(a) Advanced Mode
Note: * Normal mode is not available in this LSI.
Figure 2.12 Branch Address Specification in Memory Indirect Mode
2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Note: Normal mode is not available in this LSI.
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Section 2 CPU
Table 2.13 Effective Address Calculation (1)
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct(Rn)
rm
Operand is general register contents.
rn
Register indirect(@ERn)
0
31
op
3
31
24 23
0
Don't care
General register contents
r
Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
0
31
General register contents
op
r
31
disp
Sign extension
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
op
disp
31
0
31
24 23
0
Don't care
General register contents
r
•Register indirect with pre-decrement @-ERn
0
0
31
4
24 23
Don't care
1, 2, or 4
31
0
General register contents
31
24 23
0
Don't care
op
r
1, 2, or 4
Operand Size
Byte
Word
Longword
Offset
1
2
4
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Section 2 CPU
Table 2.13 Effective Address Calculation (2)
No
5
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
31
op
@aa:16
31
op
0
H'FFFF
24 23
16 15
0
Don't care Sign extension
abs
@aa:24
31
op
8 7
24 23
Don't care
abs
24 23
0
Don't care
abs
@aa:32
op
31
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
0
24 23
Don't care
abs
Operand is immediate data.
IMM
0
23
Program-counter relative
PC contents
@(d:8,PC)/@(d:16,PC)
op
disp
23
0
Sign
extension
disp
31
24 23
0
Don't care
8
Memory indirect @@aa:8
• Normal mode*
8 7
31
op
abs
0
abs
H'000000
15
0
31
24 23
Don't care
Memory contents
16 15
0
H'00
• Advanced mode
8 7
31
op
abs
H'000000
31
0
Memory contents
Note: * Normal mode is not available in this LSI.
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REJ09B0200-0200
0
abs
31
24 23
Don't care
0
Section 2 CPU
2.8
Processing States
The H8S/2600 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state
transitions.
• Reset State
In this state, the CPU and all on-chip peripheral modules are initialized and not operating.
When the RES input goes low, all current processing stops and the CPU enters the reset state.
All interrupts are masked in the reset state. Reset exception handling starts when the RES
signal changes from low to high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.
• Program Execution State
In this state, the CPU executes program instructions in sequence.
• Bus-Released State
The bus has been released in response to a bus request from a bus master other than the CPU.
While the bus is released, the CPU halts operations.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further
details, refer to section 21, Power-Down Modes.
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Section 2 CPU
End of bus request
Bus request
Program execution
state
End of bus
request
SLEEP
instruction
with
SSBY = 1
Bus
request
SLEEP
instruction
with
SSBY = 0
Bus-released state
Request for
exception
handling
End of
exception
handling
Sleep mode
Interrupt
request
Exception-handling state
External interrupt
request
Software standby mode
RES = high
Reset state*1
STBY = high, RES = low
Hardware standby mode*2
Power-down state*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
3. For details, refer to section 21, Power-Down Modes.
Figure 2.13 State Transitions
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Section 2 CPU
2.9
Usage Note
2.9.1
Notes on Using the Bit Operation Instruction
Instructions BSET, BCLR, BNOT, BST, and BIST read data in byte units, and write data in byte
units after bit operation. Therefore, attention must be paid when these instructions are used for
ports or registers including write-only bits.
Instruction BCLR can be used to clear the flag in the internal I/O register to 0. If it is obvious that
the flag has been set to 1 by the interrupt processing routine, it is unnecessary to read the flag
beforehand.
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Section 2 CPU
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Operating Mode Selection
This LSI supports four operating modes (modes 4 to 7). These modes are determined by the mode
pin (MD2 to MD0) setting. Do not change the mode pin settings during operation.
Table 3.1
MCU Operating Mode Selection
MCU
Operating
Mode
MD2
MD1
MD0
CPU
Operating
Mode
4
1
0
0
Advanced mode
Expanded mode with on-chip
ROM disabled
Disabled
5
1
0
1
Advanced mode
Expanded mode with on-chip
ROM disabled
Disabled
6
1
1
0
Advanced mode
Expanded mode with on-chip
ROM enabled
Enabled
7
1
1
1
Advanced mode
Single-chip mode
Enabled
On-Chip
ROM
Description
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Section 3 MCU Operating Modes
3.2
Register Descriptions
The following registers are related to the operating mode.
• Mode control register (MDCR)
• System control register (SYSCR)
3.2.1
Mode Control Register (MDCR)
Bit
Bit Name
Initial
Value
R/W
Descriptions
7

1

Reserved
6 to 3

All 0

This bit is always read as 1 and cannot be modified.
Reserved
These bits are always read as 0 and cannot be
modified.
2
MDS2
*
R
Mode select 2 to 0
1
MDS1
*
R
0
MDS0
*
R
These bits indicate the input levels at pins MD2 to MD0
(the current operating mode). Bits MDS2 to MDS0
correspond to MD2 to MD0. MDS2 to MDS0 are readonly bits and they cannot be written to. The mode pin
(MD2 to MD0) input levels are latched into these bits
when MDCR is read. These latches are canceled by a
reset. These latches are canceled by a power-on reset.
Note:
*
Determined by pins MD2 to MD0.
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Section 3 MCU Operating Modes
3.2.2
System Control Register (SYSCR)
SYSCR selects saturating or non-saturating calculation for the MAC instruction, selects the
interrupt control mode and the detected edge for NMI, and enables or disables on-chip RAM.
Bit
Bit Name
Initial
Value
R/W
Descriptions
7
MACS
0
R/W
MAC Saturation
Selects either saturating or non-saturating calculation
for the MAC instruction.
0: Non-saturating calculation for the MAC instruction
1: Saturating calculation for the MAC instruction
6

0

Reserved
This bit is always read as 0 and cannot be modified.
5
INTM1
0
R/W
4
INTM0
0
R/W
These bits select the control mode of the interrupt
controller. For details of the interrupt control modes, see
section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Setting prohibited
10: Interrupt control mode 2
11: Setting prohibited
3
NMIEG
0
R/W
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
2, 1

All 0

Reserved
These bits are always read as 0 and cannot be
modified.
0
RAME
1
R/W
RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
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Section 3 MCU Operating Modes
3.3
Operating Mode Descriptions
3.3.1
Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A, B, and C function as an address bus, ports D and E function as a data bus, and part of port
F carries bus control signals.
The bus mode immediately after a reset is 16 bits, with 16-bit access to all areas. However, note
that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
3.3.2
Mode 5
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A, B, and C function as an address bus, port D functions as a data bus, and part of port F
carries bus control signals.
The bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, note that
if 16-bit access is designated by the bus controller for any area, the bus mode switches to 16 bits
and port E becomes a data bus.
3.3.3
Mode 6
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
Ports A, B, and C function as input port pins immediately after a reset. Address output can be
performed by setting the corresponding DDR (data direction register) bits to 1. Port D functions as
a data bus, and part of port F carries bus control signals.
The bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, note that
if 16-bit access is designated by the bus controller for any area, the bus mode switches to 16 bits
and port E becomes a data bus.
3.3.4
Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
but external addresses cannot be accessed. All I/O ports are available for use as input/output ports.
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Section 3 MCU Operating Modes
3.4
Pin Functions in Each Operating Mode
The pin functions of ports A to F vary depending on the operating mode. Table 3.2 shows their
functions in each operating mode.
Table 3.2
Pin Functions in Each Mode
Port
Mode 4
Mode 5
Mode 6
Mode 7
Port A
A
A
P*/A
P
Port B
A
A
P*/A
P
Port C
A
A
P*/A
P
Port D
D
D
D
P
Port E
P/D*
P*/D
P*/D
P
PF7
P/C*
P/C*
P/C*
P*/C
PF6 to PF4
C
C
C
P
PF3
P/C*
P*/C
P*/C
PF2, PF0
P*/C
P*/C
P*/C
P
P
P
Port F
Port K
P
[Legend]
P:
I/O port
A:
Address bus output
D:
Data bus I/O
C:
Control signals, clock I/O
*:
After reset
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Section 3 MCU Operating Modes
3.5
Address Map
Figure 3.1 shows the address map in each operating mode.
Modes 4 and 5
(advanced expanded modes
with on-chip ROM disabled)
H'000000
Mode 6
(advanced expanded mode
with on-chip ROM enabled)
H'000000
H'03FFFF
Reserved area
H'000000
On-chip ROM
External address
space
H'FFAFFF
H'FFB000
H'FFDFFF
H'FFE000
Mode 7
(advanced single-chip mode)
H'FFAFFF
H'FFB000
H'FFDFFF
H'FFE000
On-chip ROM
H'03FFFF
External address
space
Reserved area
H'FFE000
On-chip RAM *
On-chip RAM *
On-chip RAM
H'FFEFBF
H'FFEFC0
External address space
H'FFF800
H'FFEFC0
H'FFFF40
External area
Internal I/O registers
H'FFFFC0
H'FFFFFF
Note:
On-chip RAM *
H'FFF800
Internal I/O registers
Internal I/O registers
H'FFFF60
External address space
H'FFF800
H'FFFF40
H'FFFF60
H'FFFFC0
H'FFFFFF
Internal I/O registers
H'FFFF3F
External area
Internal I/O registers
On-chip RAM *
H'FFFF60
H'FFFFC0
H'FFFFFF
* External address can be accessed by clearing th RAME bit in SYSCR to 0.
Figure 3.1 Address Map
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Internal I/O registers
On-chip RAM
Section 4 Exception Handling
Section 4 Exception Handling
4.1
Exception Handling Types and Priority
As shown in table 4.1, exception handling may be caused by a reset, trace, interrupt, or trap
instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low.
Trace*1
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in EXR is set to 1.
Direct transition
Starts when a direction transition occurs as the result of
SLEEP instruction execution.
Interrupt
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.*2
Trap instruction *3
Started by execution of a trap instruction (TRAPA).
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in program
execution state.
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Section 4 Exception Handling
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.
Table 4.2
Exception Handling Vector Table
Vector Address*1
Exception Source
Vector Number
Normal Mode*2
Advanced Mode
Power-on reset
0
H'0000 to H'0001
H'0000 to H'0003
Reserved for system use
1
H'0002 to H'0003
H'0004 to H'0007
2
H'0004 to H'0005
H'0008 to H'000B
3
H'0006 to H'0007
H'000C to H'000F
4
H'0008 to H'0019
H'0010 to H'0013
5
H'000A to H'000B
H'0014 to H'0017
Interrupt (direct transitions)* 6
H'000C to H'000D
H'0018 to H'001B
Interrupt (NMI)
7
H'000E to H'000F
H'001C to H'001F
Trap instruction (#0)
8
H'0010 to H'0011
H'0020 to H'0023
(#1)
9
H'0012 to H'0013
H'0024 to H'0027
(#2)
10
H'0014 to H'0015
H'0028 to H'002B
(#3)
11
H'0016 to H'0017
H'002C to H'002F
12
H'0018 to H'0019
H'0030 to H'0033
13
H'001A to H'001B
H'0034 to H'0037
14
H'001C to H'001D
H'0038 to H'003B
15
H'001E to H'001F
H'003C to H'003F
IRQ0
16
H'0020 to H'0021
H'0040 to H'0043
IRQ1
17
H'0022 to H'0023
H'0044 to H'0047
IRQ2
18
H'0024 to H'0025
H'0048 to H'004B
IRQ3
19
H'0026 to H'0027
H'004C to H'004F
IRQ4
20
H'0028 to H'0029
H'0050 to H'0053
IRQ5
21
H'002A to H'002B
H'0054 to H'0057
Reserved for system use
22
H'002C to H'002D
H'0058 to H'005B
23
H'002E to H'002F
H'005C to H'005F
Trace
4
Reserved for system use
External interrupt
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Section 4 Exception Handling
Vector Address*1
Exception Source
3
Internal interrupt*
Vector Number
Normal Mode*2
Advanced Mode
24
H'0030 to H'0031
H'0060 to H'0063
127
H'00FE to H'00FF
H'01FC to H'01FF
Notes: 1. Lower 16 bits of the address.
2. Not available in this LSI.
3. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Vector Table.
4. For direct transitions, see section 21.10, Direct Transitions
4.3
Reset
A reset has the highest exception priority.
When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that
this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during
operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the
CPU and the registers of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. For details, see section 12,
Watchdog Timer (WDT).
The interrupt control mode is 0 immediately after reset.
4.3.1
Reset Exception Handling
When the RES pin goes high after being held low for the necessary period, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, the T bit in EXR is cleared to 0, and the I bit in EXR and CCR is set to 1.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.1 and 4.2 show examples of the reset sequence.
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Section 4 Exception Handling
Vector fetch
Fetch of first
Internal
processing program instruction
(1)
(3)
φ
RES
Internal
address bus
(5)
Internal read
signal
Internal write
signal
Internal data
bus
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)
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Section 4 Exception Handling
Internal
processing
Vector fetch
*
*
Fetch of first
program instruction
*
φ
RES
Address bus
(1)
(3)
(5)
RD
HWR, LWR
D15 to D0
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Note:* Three program wait states are inserted.
Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled)
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Section 4 Exception Handling
4.3.2
Interrupts after Reset
If an interrupt is accepted immediately after a reset and before the stack pointer (SP) is initialized,
the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all
interrupt requests, including NMI, are disabled immediately after a reset exception handling is
executed. Since the first instruction of a program is always executed immediately after the reset,
make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
State of On-Chip Peripheral Modules after Reset Release
After reset release, MSTPCRA to MSTPCRA are initialized to H'3F, H'FF, and H'FF, and
B'11xxxxxx respectively, and all modules except the DTC enter module stop mode. Consequently,
on-chip peripheral module registers cannot be read or written to. Register reading and writing is
enabled when the module stop mode is cancelled.
Note: The initial values of bits 5 to 0 in MSTPCRD are undefined.
4.4
Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt mask bit in CCR. Table 4.3
shows the states of CCR and EXR after execution of trace exception handling. Trace mode is
cancelled by clearing the T bit in EXR to 0 with the trace exception handling. The T bit saved on
the stack retains its value of 1, and when control is returned from the trace exception handling
routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out
after execution of the RTE instruction.
Interrupts are accepted even within the trace exception handling routine.
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Section 4 Exception Handling
Table 4.3
Statuses of CCR and EXR after Trace Exception Handling
CCR
Interrupt Control Mode
I
0
UI
EXR
I2 to I0
T
Trace exception handling cannot be used.
2
1
—
—
0
[Legend]
1:
Set to 1
0:
Cleared to 0
—:
Retains value prior to execution
4.5
Interrupts
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiplexed interrupt control. The source to start interrupt exception handling and the vector
address differ depending on the product. For details, refer to section 5, Interrupt Controller.
Interrupt exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended control
register (EXR) are saved to the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution begins from that address.
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Section 4 Exception Handling
4.6
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended control
register (EXR) are saved to the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the statuses of CCR and EXR after execution of trap instruction exception
handling.
Table 4.4
Statuses of CCR and EXR after Trap Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
I2 to I0
T
0
1



2
1


0
[Legend]
1:
Set to 1
0:
Cleared to 0
:
Retains value prior to execution
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Section 4 Exception Handling
4.7
Stack Status after Exception Handling
Figures 4.3 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
(a) Normal Modes*2
SP
EXR
Reserved*1
SP
CCR
CCR
CCR*1
CCR*1
PC (16 bits)
PC (16 bits)
Interrupt control mode 0
Interrupt control mode 2
(b) Advanced Modes
SP
EXR
Reserved*1
SP
CCR
PC (24 bits)
Interrupt control mode 0
CCR
PC (24 bits)
Interrupt control mode 2
Notes: 1. Ignored on return.
2. Normal modes are not available in this LSI.
Figure 4.3 Stack Status after Exception Handling
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Section 4 Exception Handling
4.8
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by word transfer instruction or longword transfer instruction, and
the value of the stack pointer (SP: ER7) should always be kept even. Use the following
instructions to save registers:
PUSH.W
Rn
(or MOV.W Rn, @-SP)
PUSH.L
ERn
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
(or MOV.W @SP+, Rn)
POP.L
ERn
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of what
happens when the SP value is odd.
Address
CCR
SP
R1L
SP
H'FFFEFA
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFE
SP
H'FFFEFF
SP set to H'FFFEFF
TRAP instruction executed
MOV.B R1L, @-ER7 instruction executed
Data saved above SP
Contents of CCR lost
[Legend]
CCR :
PC :
R1L :
SP :
Condition code register
Program counter
General register R1L
Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 4.4 Operation when SP Value Is Odd
Rev. 2.00 Dec. 05, 2005 Page 68 of 724
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Features
• Two interrupt control modes
 Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in
the system control register (SYSCR).
• Priorities settable with IPR
 An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI. NMI is assigned the
highest priority level of 8, and can be accepted at all times.
• Independent vector addresses
 All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Seven external interrupts
 NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level
sensing, can be selected for IRQ5 to IRQ0.
• DTC control
 The DTC can be activated by an interrupt request.
Rev. 2.00 Dec. 05, 2005 Page 69 of 724
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Section 5 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1.
CPU
INTM1, INTM0
SYSCR
NMIEG
NMI input
NMI input unit
IRQ input
IRQ input unit
ISR
ISCR
IER
Interrupt
request
Vector number
Priority
determination
I
Internal interrupt request
SWDTEND to SLE0
CCR
I2 to I0
IPR
Interrupt controller
[Legend]
ISCR:
IER:
ISR:
IPR:
SYSCR:
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt priority register
System control register
Figure 5.1 Block Diagram of Interrupt Controller
Rev. 2.00 Dec. 05, 2005 Page 70 of 724
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EXR
Section 5 Interrupt Controller
5.2
Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1
Pin Configuration
Name
I/O
Function
NMI
Input
Nonmaskable external interrupt
Rising or falling edge can be selected
IRQ5
Input
Maskable external interrupts
IRQ4
Input
IRQ3
Input
Rising, falling, or both edges, or level sensing, can be
selected
IRQ2
Input
IRQ1
Input
IRQ0
Input
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Section 5 Interrupt Controller
5.3
Register Descriptions
The interrupt controller has the following registers. For the system control register (SYSCR), refer
to section 3.2.2, System Control Register (SYSCR).
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
System control register (SYSCR)
IRQ sense control register H (ISCRH)
IRQ sense control register L (ISCRL)
IRQ enable register (IER)
IRQ status register (ISR)
Interrupt priority register A (IPRA)
Interrupt priority register B (IPRB)
Interrupt priority register C (IPRC)
Interrupt priority register D (IPRD)
Interrupt priority register E (IPRE)
Interrupt priority register F (IPRF)
Interrupt priority register G (IPRG)
Interrupt priority register H (IPRH)
Interrupt priority register J (IPRJ)
Interrupt priority register K (IPRK)
Interrupt priority register M (IPRM)
Interrupt priority register O (IPRO)
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Section 5 Interrupt Controller
5.3.1
Interrupt Priority Registers A to H, J, K, M, and O (IPRA to IPRH, IPRJ, IPRK,
IPRM, and IPRO)
The IPR registers set priorities (levels 7 to 0) for interrupts other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a
value in the range from H'0 to H'7 in the 3-bit groups of bits 0 to 2 and 4 to 6 sets the priority of
the corresponding interrupt.
Bit
Bit Name
Initial
Value
R/W
Description
7

0

Reserved
These bits are always read as 0.
6
IPR6
1
R/W
Sets the priority of the corresponding interrupt source.
5
IPR5
1
R/W
000: Priority level 0 (Lowest)
4
IPR4
1
R/W
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
3

0

Reserved
These bits are always read as 0.
2
IPR2
1
R/W
Sets the priority of the corresponding interrupt source.
1
IPR1
1
R/W
000: Priority level 0 (Lowest)
0
IPR0
1
R/W
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
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Section 5 Interrupt Controller
5.3.2
IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that controls the enabling and disabling of interrupt
requests IRQ0 to IRQ5.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0
R/W
Reserved
5
IRQ5E
0
R/W
IRQ5 Enable
The write value should always be 0.
The IRQ5 interrupt request is enabled when this bit is 1.
4
IRQ4E
0
R/W
IRQ4 Enable
The IRQ4 interrupt request is enabled when this bit is 1.
3
IRQ3E
0
R/W
IRQ3 Enable
The IRQ3 interrupt request is enabled when this bit is 1.
2
IRQ2E
0
R/W
IRQ2 Enable
The IRQ2 interrupt request is enabled when this bit is 1.
1
IRQ1E
0
R/W
IRQ1 Enable
The IRQ1 interrupt request is enabled when this bit is 1.
0
IRQ0E
0
R/W
IRQ0 Enable
The IRQ0 interrupt request is enabled when this bit is 1.
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Section 5 Interrupt Controller
5.3.3
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
The ISCR registers select the source that generates an interrupt request at pins IRQ0 to IRQ5.
•
ISCRH
Bit
Initial
Bit Name Value
R/W
Description
15 to 12

R/W
Reserved
All 0
The write value should always be 0.
11
IRQ5SCB 0
R/W
10
IRQ5SCA 0
R/W
IRQ5 Sense Control B
IRQ5 Sense Control A
00: Interrupt request generated at IRQ5 input level low
01: Interrupt request generated at falling edge of IRQ5
input
10: Interrupt request generated at rising edge of IRQ5
input
11: Interrupt request generated at both falling and rising
edges of IRQ5 input
9
IRQ4SCB 0
R/W
8
IRQ4SCA 0
R/W
IRQ4 Sense Control B
IRQ4 Sense Control A
00: Interrupt request generated at IRQ4 input level low
01: Interrupt request generated at falling edge of IRQ4
input
10: Interrupt request generated at rising edge of IRQ4
input
11: Interrupt request generated at both falling and rising
edges of IRQ4 input
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Section 5 Interrupt Controller
•
ISCRL
Bit
Initial
Bit Name Value
R/W
Description
7
IRQ3SCB 0
R/W
6
IRQ3SCA 0
R/W
IRQ3 Sense Control B
IRQ3 Sense Control A
00: Interrupt request generated at IRQ3 input level low
01: Interrupt request generated at falling edge of IRQ3
input
10: Interrupt request generated at rising edge of IRQ3
input
11: Interrupt request generated at both falling and rising
edges of IRQ3 input
5
IRQ2SCB 0
R/W
4
IRQ2SCA 0
R/W
IRQ2 Sense Control B
IRQ2 Sense Control A
00: Interrupt request generated at IRQ2 input level low
01: Interrupt request generated at falling edge of IRQ2
input
10: Interrupt request generated at rising edge of IRQ2
input
11: Interrupt request generated at both falling and rising
edges of IRQ2 input
3
IRQ1SCB 0
R/W
2
IRQ1SCA 0
R/W
IRQ1 Sense Control B
IRQ1 Sense Control A
00: Interrupt request generated at IRQ1 input level low
01: Interrupt request generated at falling edge of IRQ1
input
10: Interrupt request generated at rising edge of IRQ1
input
11: Interrupt request generated at both falling and rising
edges of IRQ1 input
1
IRQ0SCB 0
R/W
0
IRQ0SCA 0
R/W
IRQ0 Sense Control B
IRQ0 Sense Control A
00: Interrupt request generated at IRQ0 input level low
01: Interrupt request generated at falling edge of IRQ0
input
10: Interrupt request generated at rising edge of IRQ0
input
11: Interrupt request generated at both falling and rising
edges of IRQ0 input
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Section 5 Interrupt Controller
5.3.4
IRQ Status Register (ISR)
ISR indicates the status of IRQ0 to IRQ5 interrupt requests.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0
R/W*
Reserved
These bits are always read as 0.
5
IRQ5F
0
R/W*
[Setting conditions]
4
IRQ4F
0
R/W*
3
IRQ3F
0
R/W*
When the interrupt source selected by the ISCR
registers occurs
2
IRQ2F
0
R/W*
[Clearing conditions]
1
IRQ1F
0
R/W*
•
0
IRQ0F
0
R/W*
Cleared by reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
•
When interrupt exception handling is executed when
low-level detection is set and IRQn input is high
•
When IRQn interrupt exception handling is executed
when falling, rising, or both-edge detection is set
•
When the DTC is activated by an IRQn interrupt,
and the DISEL bit in MRB of the DTC is cleared to 0
Note:
*
Only 0 can be written to clear the flag.
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Section 5 Interrupt Controller
5.4
Interrupt Sources
5.4.1
External Interrupts
There are seven external interrupts: NMI and IRQ0 to IRQ5. These interrupts can be used to
restore this LSI from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ0 to IRQ5 Interrupts: Interrupts IRQ0 to IRQ5 are requested by an input signal at pins IRQ0
to IRQ5. Interrupts IRQ0 to IRQ5 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ0 to IRQ5.
• Enabling or disabling of interrupt requests IRQ0 to IRQ5 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ0 to IRQ5 is indicated in ISR. ISR flags can be cleared to 0
by software.
The detection of IRQ0 to IRQ5 interrupts does not depend on whether the relevant pin has been
set for input or output. However, when a pin is used as an external interrupt input pin, do not clear
the corresponding DDR to 0; and use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ0 to IRQ5 is shown in figure 5.2.
IRQnE
IRQnSCA, IRQnSCB
IRQnF
Edge/level
detection circuit
S
Q
IRQn interrupt
request
R
IRQn input
Clear signal
Note: n = 5 to 0
Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5
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Section 5 Interrupt Controller
5.4.2
Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1
for a particular interrupt source, an interrupt request is issued to the interrupt controller.
• The interrupt priority level can be set by means of IPR.
• The DTC can be activated by a TPU, SCI, or other interrupt request.
• When the DTC is activated by an interrupt request, it is not affected by the interrupt control
mode or CPU interrupt mask bit.
5.5
Interrupt Exception Handling Vector Table
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. Priorities among
modules can be set by means of IPR. Modules set at the same priority will conform to their default
priorities. Priorities within a module are fixed.
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Section 5 Interrupt Controller
Table 5.2
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector
Address*
Interrupt
Source
Origin of
Interrupt Source
Vector
Number
Advanced
Mode
IPR
Priority
High
7
H'001C

IRQ0
16
H'0040
IPRA6 to IPRA4
IRQ1
17
H'0044
IPRA2 to IPRA0
IPRB6 to IPRB4
External pin NMI
IRQ2
18
H'0048
IRQ3
19
H'004C
IRQ4
20
H'0050
IRQ5
21
H'0054
Reserved for
system use
22
H'0058

Reserved for
system use
23
H'005C

DTC
SWDTEND
24
H'0060
IPRC2 to IPRC0
WDT_0
WOVI0
25
H'0064
IPRD6 to IPRD4
PC break
control
PC break
27
H'006C
IPRE6 to IPRE4
A/D
ADI
28
H'0070
IPRE2 to IPRE0
WDT_1
WOVI1
29
H'0074
TPU_0
TGIA_0
32
H'0080
TGIB_0
33
H'0084
TGIC_0
34
H'0088
TGID_0
35
H'008C

TPU_1
TPU_2
TCIV_0
36
H'0090
TGIA_1
40
H'00A0
TGIB_1
41
H'00A4
TCIV_1
42
H'00A8
TCIU_1
43
H'00AC
TGIA_2
44
H'00B0
TGIB_2
45
H'00B4
TCIV_2
46
H'00B8
TCIU_2
47
H'00BC
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IPRB2 to IPRB0
IPRF6 to IPRF4
IPRF2 to IPRF0
IPRG6 to IPRG4
Low
Section 5 Interrupt Controller
Vector
Address*
Interrupt
Source
Origin of
Interrupt Source
TPU_3
TGIA_3
TGIB_3
TGIC_3
50
H'00C8
TGID_3
51
H'00CC
TCIV_3
52
H'00D0
TPU_4
TPU_5
SCI_0
SCI_1
SCI_2
Vector
Number
Advanced
Mode
IPR
Priority
48
H'00C0
IPRG2 to IPRG0
High
49
H'00C4
TGIA_4
56
H'00E0
TGIB_4
57
H'00E4
TCIV_4
58
H'00E8
TCIU_4
59
H'00EC
TGIA_5
60
H'00F0
TGIB_5
61
H'00F4
TCIV_5
62
H'00F8
TCIU_5
63
H'00FC
ERI_0
80
H'0140
RXI_0
81
H'0144
TXI_0
82
H'0148
TEI_0
83
H'014C
ERI_1
84
H'0150
RXI_1
85
H'0154
TXI_1
86
H'0158
TEI_1
87
H'015C
ERI_2
88
H'0160
RXI_2
89
H'0164
TXI_2
90
H'0168
TEI_2
91
H'016C
Motor
CMI_1
control
PWM timer
104
H'01A0
CMI_2
105
H'01A4
IPRH6 to IPRH4
IPRH2 to IPRH0
IPRJ2 to IPRJ0
IPRK6 to IPRK4
IPRK2 to IPRK0
IPRM6 to IPRM4
Low
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Section 5 Interrupt Controller
Vector
Address*
Interrupt
Source
Origin of
Interrupt Source
Vector
Number
Advanced
Mode
IPR
Priority
HCAN_1
ERS0, OVR0,
RM1, SLE0
106
H'01A8
IPRM6 to IPRM4
High
RM0
107
H'01AC
ERS0, OVR0,
RM1, SLE0
108
H'01B0
RM0
109
H'01B4
ERI_4
124
H'01F0
HCAN_0
SCI_4
Note:
*
RXI_4
125
H'01F4
TXI_4
126
H'01F8
TEI_4
127
H'01FC
Lower 16 bits of the start address.
Rev. 2.00 Dec. 05, 2005 Page 82 of 724
REJ09B0200-0200
IPRM2 to IPRM0
IPRO2 to IPRO0
Low
Section 5 Interrupt Controller
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 5.3
Interrupt Control Modes
Interrupt
Priority Setting
Control Mode Registers
Interrupt
Mask Bits Description
0
Default
I
The priorities of interrupt sources are fixed at
the default settings.
Interrupt sources, except for NMI, are masked
by the I bit.
2
IPR
I2 to I0
8 priority levels other than NMI can be set with
IPR.
8-level interrupt mask control is performed by
bits I2 to I0.
5.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests other than for NMI are masked by the I bit in CCR
in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. If the I bit in CCR is set to 1, only an NMI interrupt is accepted, and other interrupt requests
are held pending. If the I bit is cleared, an interrupt request is accepted.
3. When interrupt requests are sent to the interrupt controller, the interrupt with the highest
priority according to the interrupt priority levels is selected and other interrupt requests are
held pending.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
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Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program execution status
No
Interrupt generated?
Yes
Yes
NMI
No
I=0
No
Hold
pending
Yes
No
IRQ0
No
Yes
IRQ1
Yes
SLE0
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance
in Interrupt Control Mode 0
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Section 5 Interrupt Controller
5.6.2
Interrupt Control Mode 2
In interrupt control mode 2, mask control is applied to eight levels for interrupt requests other than
NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting.
Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt
request is sent to the interrupt controller.
2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.2 is selected.
3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set
in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of
the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H′7.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
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Section 5 Interrupt Controller
Program execution status
Interrupt generated?
No
Yes
Yes
NMI
No
Level 7 interrupt?
No
Yes
Mask level 6
or below?
Level 6 interrupt?
No
Yes
No
Yes
Level 1 interrupt?
Mask level 5
or below?
No
No
Yes
Yes
Mask level 0?
No
Yes
Save PC, CCR, and EXR
Hold
pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2
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Section 5 Interrupt Controller
5.6.3
Interrupt Exception Handling Sequence
Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
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REJ09B0200-0200
Rev. 2.00 Dec. 05, 2005 Page 88 of 724
Figure 5.5 Interrupt Exception Handling
(1)
(2)
(4)
(3)
Internal
operation
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address.)
(2) (4) Instruction code (Not executed.)
(3)
Instruction prefetch address (Not executed.)
(5)
SP-2
(7)
SP-4
(1)
Internal
data bus
Internal
write signal
Internal
read signal
Internal
address bus
Interrupt
request signal
φ
Interrupt level determination Instruction
Wait for end of instruction
prefetch
Interrupt
acceptance
(7)
(8)
(10)
(9)
(12)
(11)
Internal
operation
(14)
(13)
Interrupt service
routine instruction
prefetch
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (Vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
First instruction of interrupt handling routine
(6)
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
(5)
stack
Vector fetch
Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.6.4
Interrupt Response Times
Table 5.4 shows interrupt response times - the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.4 are explained in table 5.5.
This LSI is capable of fast word transfer to on-chip memory, has the program area in on-chip
ROM and the stack area in on-chip RAM, enabling high-speed processing.
Table 5.4
Interrupt Response Times
Normal Mode*5
No.
Execution Status
Interrupt
control
mode 0
1
Interrupt priority determination*1
3
2
Number of wait states until executing 1 to 19 +2·SI 1 to 19+2·SI
instruction ends*2
1 to 19+2·SI 1 to 19+2·SI
3
PC, CCR, EXR stack save
2·SK
3·SK
2·SK
3·SK
4
Vector fetch
SI
SI
2·SI
2·SI
2·SI
2·SI
2·SI
2·SI
2
2
2
2
11 to 31
12 to 32
12 to 32
13 to 33
5
6
3
Instruction fetch*
Internal processing*
4
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
5.
Interrupt
control
mode 2
3
Advanced Mode
Interrupt
control
mode 0
Interrupt
control
mode 2
3
3
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instructions.
Prefetch after interrupt acceptance and interrupt handling routine prefetch.
Internal processing after interrupt acceptance and internal processing after vector fetch.
Not available in this LSI.
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Section 5 Interrupt Controller
Table 5.5
Number of States in Interrupt Handling Routine Execution Status
Object of Access
External Device *
8-Bit Bus
Symbol
Instruction fetch
SI
Branch address read
SJ
Stack manipulation
SK
16-Bit Bus
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
1
4
6+2m
2
3+m
[Legend]
m:
Number of wait states in an external device access.
Note: * Not available in this LSI.
5.6.5
DTC Activation by Interrupt
The DTC can be activated by an interrupt. For details, see section 8, Data Transfer Controller
(DTC).
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Section 5 Interrupt Controller
5.7
Usage Notes
5.7.1
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.6 shows an example in which the TCIEV bit in TIER_0 of the TPU is cleared to 0.
The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the
interrupt is masked.
TIER_0 write cycle by CPU
TCIVexception handling
φ
Internal
address bus
TIER_0 address
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Figure 5.6 Conflict between Interrupt Generation and Disabling
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Section 5 Interrupt Controller
5.7.2
Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3
When Interrupts Are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
5.7.4
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1:
EEPMOV.W
MOV.W
R4,R4
BNE
L1
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Section 6 PC Break Controller (PBC)
Section 6 PC Break Controller (PBC)
The PC break controller (PBC) provides functions that simplify program debugging. Using these
functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with
the chip alone, without using an in-circuit emulator. A block diagram of the PC break controller is
shown in figure 6.1.
6.1
Features
• Two break channels (A and B)
• 24-bit break address
 Bit masking possible
• Four types of break compare conditions
 Instruction fetch
 data read
 data write
 data read/write
• Bus master
 Either CPU or CPU/DTC can be selected
• The timing of PC break exception handling after the occurrence of a break condition is as
follows:
 Immediately before execution of the instruction fetched at the set address (instruction
fetch)
 Immediately after execution of the instruction that accesses data at the set address (data
access)
• Module stop mode can be set
PBC0000A_000020020300
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Section 6 PC Break Controller (PBC)
BCRA
Mask control
Output control
BARA
Control
logic
Comparator
Internal address
PC break
interrupt
Access
status
Comparator
Match signal
Mask control
BARB
Output control
Control
logic
BCRB
Figure 6.1 Block Diagram of PC Break Controller
6.2
Register Descriptions
The PC break controller has the following registers.
•
•
•
•
Break address register A (BARA)
Break address register B (BARB)
Break control register A (BCRA)
Break control register B (BCRB)
6.2.1
Break Address Register A (BARA)
BARA is a 32-bit readable/writable register that specifies the channel A break address.
Bit
Bit Name
Initial
Value
31 to 24

Undefined 
R/W
Description
Reserved
These bits are read as an undefined value and
cannot be modified.
23 to 0
BAA23 to BAA0 H'000000
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R/W
These bits set the channel A PC break address.
Section 6 PC Break Controller (PBC)
6.2.2
Break Address Register B (BARB)
BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3
Break Control Register A (BCRA)
BCRA controls channel A PC breaks. BCRA also contains a condition match flag.
Bit
Bit Name
Initial
Value
R/W
Description
7
CMFA
0
R/W
Condition Match Flag A
[Setting condition]
When a condition set for channel A is satisfied
[Clearing condition]
When 0 is written to CMFA after reading CMFA = 1
6
CDA
0
R/W
CPU Cycle/DTC Cycle Select A
Selects the channel A break condition bus master.
0: CPU
1: CPU or DTC
5
BAMRA2
0
R/W
Break Address Mask Register A2 to A0
4
BAMRA1
0
R/W
3
BAMRA0
0
R/W
These bits specify which bits of the break address set in
BARA are to be masked.
000: BAA23 to BAA0 (All bits are unmasked)
001: BAA23 to BAA1 (Lowest bit is masked)
010: BAA23 to BAA2 (Lower 2 bits are masked)
011: BAA23 to BAA3 (Lower 3 bits are masked)
100: BAA23 to BAA4 (Lower 4 bits are masked)
101: BAA23 to BAA8 (Lower 8 bits are masked)
110: BAA23 to BAA12 (Lower 12 bits are masked)
111: BAA23 to BAA16 (Lower 16 bits are masked)
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Section 6 PC Break Controller (PBC)
Bit
Bit Name
Initial
Value
R/W
Description
2
CSELA1
0
R/W
Break Condition Select A
1
CSELA0
0
R/W
Selects break condition of channel A.
00: Instruction fetch is used as break condition
01: Data read cycle is used as break condition
10: Data write cycle is used as break condition
11: Data read/write cycle is used as break condition
0
BIEA
0
R/W
Break Interrupt Enable A
When this bit is 1, the PC break interrupt request of
channel A is enabled.
6.2.4
Break Control Register B (BCRB)
BCRB is the channel B break control register. The bit configuration is the same as for BCRA.
6.3
Operation
The operation flow from break condition setting to PC break interrupt exception handling is
shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt
Due to Data Access, taking the example of channel A.
6.3.1
PC Break Interrupt Due to Instruction Fetch
1. Set the break address in BARA.
For a PC break caused by an instruction fetch, set the address of the first instruction byte as the
break address.
2. Set the break conditions in BCR.
Set bit 6 (CDA) to 0 to select the CPU because the bus master must be the CPU for a PC break
caused by an instruction fetch. Set the address bits to be masked to bits 3 to 5 (BAMA0 to
BAMA2). Set bits 1 and 2 (CSELA0 and CSELA1) to 00 to specify an instruction fetch as the
break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.
3. When the instruction at the set address is fetched, a PC break request is generated immediately
before execution of the fetched instruction, and the condition match flag (CMFA) is set.
4. After priority determination by the interrupt controller, PC break interrupt exception handling
is started.
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Section 6 PC Break Controller (PBC)
6.3.2
PC Break Interrupt Due to Data Access
1. Set the break address in BARA.
For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address
space address as the break address. Stack operations and branch address reads are included in
data accesses.
2. Set the break conditions in BCRA.
Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 3 to 5 (BAMA
BAMA0 to BAMA2). Set bits 1 and 2 (CSELA0 and CSELA1) to 01, 10, or 11 to specify data
access as the break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.
3. After execution of the instruction that performs a data access on the set address, a PC break
request is generated and the condition match flag (CMFA) is set.
4. After priority determination by the interrupt controller, PC break interrupt exception handling
is started.
6.3.3
PC Break Operation at Consecutive Data Transfer
• When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction
PC break exception handling is executed after all data transfers have been completed and the
EEPMOV.B instruction has ended.
• When a PC break interrupt is generated at a DTC transfer address
PC break exception handling is executed after the DTC has completed the specified number of
data transfers, or after data for which the DISEL bit is set to 1 has been transferred.
6.3.4
Operation in Transitions to Power-Down Modes
The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP i.struction is shown below.
1. When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
sleep mode, or from subactive mode to subsleep mode:
After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep
mode, and PC break interrupt handling is executed. After execution of PC break interrupt
handling, the instruction at the address after the SLEEP instruction is executed (figure 6-2
(A)).
2. When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
subactive mode:
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Section 6 PC Break Controller (PBC)
After execution of the SLEEP instruction, a transition is made to subactive mode via direct
transition exception handling. After the transition, PC break interrupt handling is executed,
then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (B)).
3. When the SLEEP instruction causes a transition from subactive mode to high-speed (mediumspeed) mode:
After execution of the SLEEP instruction, and following the clock oscillation settling time, a
transition is made to high-speed (medium-speed) mode via direct transition exception
handling. After the transition, PC break interrupt handling is executed, then the instruction at
the address after the SLEEP instruction is executed (figure 6.2 (C)).
4. When the SLEEP instruction causes a transition to software standby mode or watch mode:
After execution of the SLEEP instruction, a transition is made to the respective mode, and PC
break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2
(D)).
SLEEP instruction
execution
SLEEP instruction
execution
SLEEP instruction
execution
SLEEP instruction
execution
PC break exception
handling
System clock
→ subclock
Subclock →
system clock,
oscillation settling time
Transition to
respective mode
(D)
Execution of instruction
after sleep instruction
Direct transition
exception handling
(A)
PC break exception
handling
Direct transition
exception handling
Subactive
mode
PC break exception
handling
Execution of instruction
after sleep instruction
Execution of instruction
after sleep instruction
(B)
(C)
High-speed
(medium-speed)
mode
Figure 6.2 Operation in Power-Down Mode Transitions
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Section 6 PC Break Controller (PBC)
6.3.5
When Instruction Execution Is Delayed by One State
While the break interrupt enable bit is set to 1, instruction execution is one state later than usual.
• For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip
ROM or RAM.
• When break interrupt by instruction fetch is set, the set address indicates on-chip ROM or
RAM space, and that address is used for data access, the instruction will be one state later than
in normal operation.
• When break interrupt by instruction fetch is set and a break interrupt is generated, if the
executing instruction immediately preceding the set instruction has one of the addressing
modes shown below, and that address indicates on-chip ROM or RAM, the instruction will be
one state later than in normal operation.
Addressing modes: @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24,
@aa:32, @(d:8,PC), @(d:16,PC), @@aa:8
• When break interrupt by instruction fetch is set and a break interrupt is generated, if the
executing instruction immediately preceding the set instruction is NOP or SLEEP, or has
#xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the
instruction will be one state later than in normal operation.
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Section 6 PC Break Controller (PBC)
6.4
Usage Notes
6.4.1
Module Stop Mode Setting
PBC operation can be disabled or enabled using the module stop control register. The initial
setting is for PBC operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 21, Power-Down Modes.
6.4.2
PC Break Interrupts
The PC break interrupt is shared by channels A and B. The channel from which the request was
issued must be determined by the interrupt handler.
6.4.3
CMFA and CMFB
The CMFA and CMFB flags are not automatically cleared to 0, so 0 must be written to CMFA or
CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt
will be requested after interrupt handling ends.
6.4.4
PC Break Interrupt when DTC Is Bus Master
A PC break interrupt generated when the DTC is the bus master is accepted after the bus
mastership has been transferred to the CPU by the bus controller.
6.4.5
PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA,
RTE, or RTS Instruction
Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS
instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the
instruction fetch at the next address.
6.4.6
I Bit Set by LDC, ANDC, ORC, or XORC Instruction
When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt
becomes valid two states after the end of the instruction execution. If a PC break interrupt is set
for the instruction following one of these instructions, since interrupts, including NMI, are
disabled for a 3-state period in the case of LDC, ANDC, ORC, and XOR, the next instruction is
always executed. For details, see section 5, Interrupt Controller.
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Section 6 PC Break Controller (PBC)
6.4.7
PC Break Set for Instruction Fetch at Address Following Bcc Instruction
A PC break interrupt is generated if the instruction at the next address is executed in accordance
with the branch condition, and is not generated if the instruction at the next address is not
executed.
6.4.8
PC Break Set for Instruction Fetch at Branch Destination Address of Bcc
Instruction
A PC break interrupt is generated if the instruction at the branch destination is executed in
accordance with the branch condition, and is not generated if the instruction at the branch
destination is not executed.
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Section 6 PC Break Controller (PBC)
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Section 7 Bus Controller (BSC)
Section 7 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas.
The bus controller also has a bus arbitration function, and controls the operation of the bus
masterships—the CPU and data transfer controller (DTC).
7.1
Features
• Manages external address space in area units
Manages the external address space divided into eight areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM interface can be set
• Basic bus interface
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
• Burst ROM interface
Burst ROM interface can be set for area 0
Choice of 1- or 2-state burst access
• Idle cycle insertion
An idle cycle can be inserted between external read cycles for different areas
An idle cycle can be inserted before an external write cycle immediately after an external read
cycle
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC
BSCS203A_010020020400
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Section 7 Bus Controller (BSC)
A block diagram of the bus controller is shown in figure 7.1.
Internal
address bus
Area decoder
ABWCR
External bus control signals
ASTCR
BCRH
Bus
controller
Wait
controller
WAIT
Internal data bus
BCRL
Internal control
signals
Bus mode signal
WCRH
WCRL
CPU bus request signal
DTC bus request signal
Bus arbiter
CPU bus acknowledge signal
DTC bus acknowledge signal
[Legend]
ABWCR:
ASTCR:
BCRH:
BCRL:
WCRH:
WCRL:
Bus width control register
Access state control register
Bus control register H
Bus control register L
Wait control register H
Wait control register L
Figure 7.1 Block Diagram of Bus Controller
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Section 7 Bus Controller (BSC)
7.2
Input/Output Pins
Table 7.1 summarizes the pin configuration of the bus controller.
Table 7.1
Pin Configuration
Name
Symbol
I/O
Function
Address strobe
AS
Output
Strobe signal indicating that an external address
space is accessed and address output on
address bus is enabled.
Read
RD
Output
Strobe signal indicating that an external address
space is being read.
High write
HWR
Output
Strobe signal indicating that an external address
space is written to, and upper half (D15 to D8) of
data bus is enabled.
Low write
LWR
Output
Strobe signal indicating that an external address
space is written to, and lower half (D7 to D0) of
data bus is enabled.
Wait
WAIT
Input
Wait request signal when accessing external
address space.
7.3
Register Descriptions
The bus controller has the following registers.
•
•
•
•
•
•
•
Bus width control register (ABWCR)
Access state control register (ASTCR)
Wait control register H (WTCRH)
Wait control register L (WTCRL)
Bus control register H (BCRH)
Bus control register L (BCRL)
Pin function control register (PFCR)
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Section 7 Bus Controller (BSC)
7.3.1
Bus Width Control Register (ABWCR)
ABWCR designates each area in the external address space as either 8-bit access space or 16-bit
access space.
Bit
Bit Name
Initial
Value
R/W
Description
7
ABW7
1/0
R/W
Area 7 to 0 Bus Width Control
6
ABW6
1/0
R/W
5
ABW5
1/0
R/W
4
ABW4
1/0
R/W
These bits select whether the corresponding area is to
be designated as 8-bit access space or 16-bit access
space.
3
ABW3
1/0
R/W
2
ABW2
1/0
R/W
1
ABW1
1/0
R/W
0
ABW0
1/0
R/W
7.3.2
0: Area n is designated as 16-bit access space
1: Area n is designated as 8-bit access space
(n = 7 to 0)
Access State Control Register (ASTCR)
ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space.
Bit
Bit Name
Initial
Value
R/W
Description
7
AST7
1
R/W
Area 7 to 0 Access State Control
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
These bits select whether the corresponding area is to
be designated as 2-state access space or 3-state
access space. Wait state insertion is enabled or
disabled at the same time.
3
AST3
1
R/W
2
AST2
1
R/W
1
AST1
1
R/W
0
AST0
1
R/W
0: Area n is designated as 2-state access space
Wait state insertion in area n access is disabled
1: Area n is designated as 3-state access space
Wait state insertion in area n access is enabled
(n = 7 to 0)
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Section 7 Bus Controller (BSC)
7.3.3
Wait Control Registers H and L (WCRH and WCRL)
WCRH and WCRL select the number of program wait states for each area in the external address
space.
• WCRH
Bit
Bit Name
Initial
Value
R/W
Description
7
W71
1
R/W
Area 7 Wait Control 1 and 0
6
W70
1
R/W
These bits select the number of program wait states
when accessing area 7 while AST7 bit in ASTCR = 1.
00: Program wait not inserted
01: 1 program wait state inserted
10: 2 program wait states inserted
11: 3 program wait states inserted
5
W61
1
R/W
Area 6 Wait Control 1 and 0
4
W60
1
R/W
These bits select the number of program wait states
when accessing area 6 while AST6 bit in ASTCR = 1.
00: Program wait not inserted
01: 1 program wait state inserted
10: 2 program wait states inserted
11: 3 program wait states inserted
3
W51
2
W50
1
1
R/W
Area 5 Wait Control 1 and 0
R/W
These bits select the number of program wait states
when accessing area 5 while AST5 bit in ASTCR = 1.
00: Program wait not inserted
01: 1 program wait state inserted
10: 2 program wait states inserted
11: 3 program wait states inserted
1
W41
1
R/W
Area 4 Wait Control 1 and 0
0
W40
1
R/W
These bits select the number of program wait states
when accessing area 4 while AST4 bit in ASTCR = 1.
00: Program wait not inserted
01: 1 program wait state inserted
10: 2 program wait states inserted
11: 3 program wait states inserted
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Section 7 Bus Controller (BSC)
• WCRL
Bit
Bit Name
Initial
Value
R/W
Description
7
W31
1
R/W
Area 3 Wait Control 1 and 0
6
W30
1
R/W
These bits select the number of program wait states
when accessing area 3 while AST3 bit in ASTCR = 1.
00: Program wait not inserted
01: 1 program wait state inserted
10: 2 program wait states inserted
11: 3 program wait states inserted
5
W21
1
R/W
Area 2 Wait Control 1 and 0
4
W20
1
R/W
These bits select the number of program wait states
when accessing area 2 while AST2 bit in ASTCR = 1.
00: Program wait not inserted
01: 1 program wait state inserted
10: 2 program wait states inserted
11: 3 program wait states inserted
3
W11
1
R/W
Area 1 Wait Control 1 and 0
2
W10
1
R/W
These bits select the number of program wait states
when accessing area 1 while AST1 bit in ASTCR = 1.
00: Program wait not inserted
01: 1 program wait state inserted
10: 2 program wait states inserted
11: 3 program wait states inserted
1
W01
1
R/W
Area 0 Wait Control 1 and 0
0
W00
1
R/W
These bits select the number of program wait states
when accessing area 0 while AST0 bit in ASTCR = 1.
00: Program wait not inserted
01: 1 program wait state inserted
10: 2 program wait states inserted
11: 3 program wait states inserted
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Section 7 Bus Controller (BSC)
7.3.4
Bus Control Register H (BCRH)
BCRH enables or disables idle cycle insertion and specifies the burst ROM interface.
Bit
Bit Name
Initial
Value
R/W
Description
7
ICIS1
1
R/W
Idle Cycle Insert 1
When consecutive external read cycles are performed
in different areas, an idle cycle can be inserted between
the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
6
ICIS0
1
R/W
Idle Cycle Insert 0
When an external read cycle and an external write cycle
are performed consecutively, an idle cycle can be
inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
5
4
3
BRSTRM
BRSTS1
BRSTS0
0
1
0
R/W
Burst ROM Enable
Selects whether the burst ROM interface is used for
area 0.
R/W
0: Basic bus interface for area 0
1: Burst ROM interface for area 0
Burst Cycle Select 1
Selects the number of burst cycles for the burst ROM
interface.
R/W
0: 1 state for a burst cycle
1: 2 states for a burst cycle
Burst Cycle Select 0
Selects the number of words that can be accessed in a
burst access with the burst ROM interface.
0: Maximum four words in burst access
1: Maximum eight words in burst access
2 to 0
—
All 0
R/W
Reserved
The write value should always be 0.
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Section 7 Bus Controller (BSC)
7.3.5
Bus Control Register L (BCRL)
BCRL selects the write data buffer function and enables or disables input to the WAIT pin.
Bit
Bit Name
Initial
Value
R/W
Description
7

0
R/W
Reserved
6

0
R/W
The write value should always be 0.
5

0

Reserved
This bit is always read as 0 and cannot be modified.
4

0
R/W
Reserved
The write value should always be 0.
3

1
R/W
Reserved
The write value should always be 1.
2

0
R/W
Reserved
The write value should always be 0.
1
WDBE
0
R/W
Write Data Buffer Enable
Selects the write data buffer function for an external
write cycle.
0: Write data buffer function not used
1: Write data buffer function used
0
WAITE
0
R/W
WAIT Pin Enable
Enables or disables wait signal input through the WAIT
pin.
0: Wait input through WAIT pin disabled
WAIT pin can be used as I/O port
1: Wait input through WAIT pin enabled
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Section 7 Bus Controller (BSC)
7.3.6
Pin Function Control Register (PFCR)
PFCR controls the address output in expanded mode with on-chip ROM enabled.
Bit
Initial
Bit Name Value
7 to 4 
All 0
R/W
Description

Reserved
The write value should always be 0.
3
AE3
0/1*
R/W
Address Output Enable 3 to 0
2
AE2
0/1*
R/W
1
AE1
0
R/W
0
AE0
0/1*
R/W
These bits enable or disable address outputs A8 to A23 in
expanded mode with on-chip ROM. When a pin is enabled
for address output, the address is output regardless of the
corresponding DDR setting. For a pin disabled for address
output, each becomes an output port when the
corresponding DDR bit is set to 1. For pins A7 to A0, each
becomes an address output when the corresponding DDR
bit is set to 1.
0000: A8 to A23 output disabled
0001: A8 output enabled; A9 to A23 output disabled
0010: A8 and A9 output enabled; A10 to A23 output disabled
0011: A8 to A10 output enabled; A11 to A23 output disabled
0100: A8 to A11 output enabled; A12 to A23 output disabled
0101: A8 to A12 output enabled; A13 to A23 output disabled
0110: A8 to A13 output enabled; A14 to A23 output disabled
0111: A8 to A14 output enabled; A15 to A23 output disabled
1000: A8 to A15 output enabled; A16 to A23 output disabled
1001: A8 to A16 output enabled; A17 to A23 output disabled
1010: A8 to A17 output enabled; A18 to A23 output disabled
1011: A8 to A18 output enabled; A19 to A23 output disabled
1100: A8 to A19 output enabled; A20 to A23 output disabled
1101: A8 to A20 output enabled; A21 to A23 output disabled
1110: A8 to A21 output enabled; A22 and A23 output
disabled
1111: A8 to A23 output enabled
Note:
*
In expanded mode with on-chip ROM enabled, bits 3 to 0 are initialized to B'0000. In
expanded mode with on-chip ROM disabled, bits 3 to 0 are initialized to B'1101.
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Section 7 Bus Controller (BSC)
7.4
Bus Control
7.4.1
Area Division
The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units,
and performs bus control for external address space in area units. Figure 7.2 shows an outline of
the memory map.
H'000000
Area 0
(2 Mbytes)
H'1FFFFF
H'200000
Area 1
(2 Mbytes)
H'3FFFFF
H'400000
Area 2
(2 Mbytes)
H'5FFFFF
H'600000
Area 3
(2 Mbytes)
H'7FFFFF
H'800000
Area 4
(2 Mbytes)
H'9FFFFF
H'A00000
Area 5
(2 Mbytes)
H'BFFFFF
H'C00000
Area 6
(2 Mbytes)
H'DFFFFF
H'E00000
Area 7
(2 Mbytes)
H'FFFFFF
Advanced mode
Figure 7.2 Area Divisions
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Section 7 Bus Controller (BSC)
7.4.2
Bus Specifications
The external address space bus specifications consist of three elements: bus width, number of
access states, and number of program wait states. The bus width and number of access states for
on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit
bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected
functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode
is set; if any area is designated as 16-bit access space, 16-bit bus mode is set.
Number of Access States: Two or three access states can be selected with ASTCR. An area for
which 2-state access is selected functions as a 2-state access space, and an area for which 3-state
access is selected functions as a 3-state access space.
When 2-state access space is designated, wait insertion is disabled. When 3-state access space is
designated, it is possible to insert program waits by means of the WCRH and WCRL, and external
waits by means of the WAIT pin.
Number of Program Wait States: When 3-state access space is designated by ASTCR, the
number of program wait states to be inserted automatically is selected with WCRH and WCRL.
From 0 to 3 program wait states can be selected.
Table 7.2 shows the bus specifications (bus width, number of access states, and program wait
states) for each basic bus interface area.
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Section 7 Bus Controller (BSC)
Table 7.2
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR
ASTCR
ABWn
ASTn
Wn1
Wn0
Bus Width
Access
States
Program Wait
States
0
0
—
—
16
2
0
1
0
0
3
0
WCRH, WCRL
1
1
1
1
0
2
1
3
0
—
—
1
0
0
1
Bus Specifications (Basic Bus Interface)
8
2
0
3
0
1
1
0
2
1
3
(n = 0 to 7)
7.4.3
Memory Interfaces
The memory interfaces in this LSI allow direct connection of ROM, SRAM, and so on.
The initial state of each area is 3-state access space with the basic bus interface. The initial bus
width is selected according to the operating mode.
Area 0: Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the
space excluding on-chip ROM is external address space. In expanded mode with on-chip ROM
disabled, all of area 0 is external address space.
Either basic bus interface or burst ROM interface can be selected for area 0.
Areas 1 to 6: In externally expanded mode, areas 1 to 6 are all external address space.
Only the basic bus interface can be used for areas 1 to 6.
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Section 7 Bus Controller (BSC)
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In externally expanded
mode, the space excluding the on-chip RAM and internal I/O registers is external address space.
The on-chip RAM is enabled when the RAME bit is set to 1 in the system control register
(SYSCR); when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding
addresses are in external address space.
Only the basic bus interface can be used for area 7.
7.5
Basic Bus Interface
The basic bus interface enables direct connection of ROM, SRAM, and so on.
7.5.1
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external address space, controls
whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space: Figure 7.3 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word access is performed as two byte accesses,
and a longword access, as four byte accesses.
Upper data bus
D15
Lower data bus
D8 D7
D0
Byte size
Word size
1st bus cycle
2nd bus cycle
1st bus cycle
Longword
size
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 7.3 Access Sizes and Data Alignment Control (8-Bit Access Space)
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Section 7 Bus Controller (BSC)
16-Bit Access Space: Figure 7.4 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Upper data bus
D15
Byte size
• Even address
Byte size
• Odd address
Lower data bus
D8 D7
D0
Word size
Longword
size
1st bus cycle
2nd bus cycle
Figure 7.4 Access Sizes and Data Alignment Control (16-bit Access Space)
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Section 7 Bus Controller (BSC)
7.5.2
Valid Strobes
Table 7.3 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write,
the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 7.3
Data Buses Used and Valid Strobes
Access
Size
Read/
Write
Address
Valid
Strobe
Upper Data Bus Lower Data
(D15 to D8)
Bus (D7 to D0)
8-bit access
space
Byte
Read
—
RD
Valid
Write
—
HWR
16-bit access
space
Byte
Read
Even
RD
Area
Odd
Hi-Z
Valid
Invalid
Invalid
Valid
Even
HWR
Valid
Hi-Z
Odd
LWR
Hi-Z
Valid
Read
—
RD
Valid
Valid
Write
—
HWR, LWR
Valid
Valid
Write
Word
Invalid
Note: Hi-Z: High-impedance state
Invalid: Input state; input value is ignored.
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Section 7 Bus Controller (BSC)
7.5.3
Basic Timing
8-Bit, 2-State Access Space: Figure 7.5 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states cannot be inserted.
Bus cycle
T2
T1
φ
Address bus
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Figure 7.5 Bus Timing for 8-Bit, 2-State Access Space
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Section 7 Bus Controller (BSC)
8-Bit, 3-State Access Space: Figure 7.6 shows the bus timing for an 8-bit, 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.
Bus cycle
T1
T3
T2
φ
Address bus
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Figure 7.6 Bus Timing for 8-Bit, 3-State Access Space
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Section 7 Bus Controller (BSC)
16-Bit, 2-State Access Space: Figures 7.7 to 7.9 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be
inserted.
Bus cycle
T1
T2
φ
Address bus
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Figure 7.7 Bus Timing for 16-Bit, 2-State Access Space
(Even Address Byte Access)
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Section 7 Bus Controller (BSC)
Bus cycle
T2
T1
φ
Address bus
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
High impedance
D15 to D8
D7 to D0
Valid
Figure 7.8 Bus Timing for 16-Bit, 2-State Access Space
(Odd Address Byte Access)
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Section 7 Bus Controller (BSC)
Bus cycle
T1
T2
φ
Address bus
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Figure 7.9 Bus Timing for 16-Bit, 2-State Access Space
(Word Access)
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Section 7 Bus Controller (BSC)
16-Bit, 3-State Access Space: Figures 7.10 to 7.12 show bus timings for a 16-bit, 3-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be
inserted.
Bus cycle
T1
T2
T3
φ
Address bus
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Figure 7.10 Bus Timing for 16-Bit, 3-State Access Space
(Even Address Byte Access)
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Section 7 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
D15 to D8
D7 to D0
High impedance
Valid
Figure 7.11 Bus Timing for 16-Bit, 3-State Access Space
(Odd Address Byte Access)
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Section 7 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Figure 7.12 Bus Timing for 16-Bit, 3-State Access Space
(Word Access)
7.5.4
Wait Control
When accessing external space, this LSI can extend the bus cycle by inserting one or more wait
states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait
insertion using the WAIT pin.
Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2
state and T3 state on an individual area basis in 3-state access space, according to the settings in
WCRH and WCRL.
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Section 7 Bus Controller (BSC)
Pin Wait Insertion: Setting the WAITE bit to 1 in BCRH enables wait input by means of the
WAIT pin. When an external address space is accessed in this state, a program wait is first
inserted in accordance with the settings in WCRH and WCRL. If the WAIT pin is low at the
falling edge of φ in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low,
Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or
when changing the number of Tw states to be inserted for different external devices. The WAITE
bit setting applies to all areas. Figure 7.13 shows an example of wait state insertion timing.
The settings after a power-on reset are: 3-state access, insertion of three program wait states, and
WAIT input disabled.
By program wait
T1
T2
Tw
By WAIT pin
Tw
Tw
T3
φ
WAIT
Address bus
AS
RD
Read
Data bus
Read data
HWR, LWR
Write
Data bus
Note:
Write data
Downward arrows indicate the timing of WAIT pin sampling.
Figure 7.13 Example of Wait State Insertion Timing
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Section 7 Bus Controller (BSC)
7.6
Burst ROM Interface
In this LSI, external space area 0 can be designated as burst ROM space, and burst ROM
interfacing performed. The burst ROM space interface enables ROM with burst access capability
to be accessed at high speed.
Area 0 can be designated as burst ROM space by means of bit BSTRM in BCRH. Continuous
burst accesses of four or eight words can be performed, according to the setting of the BRSTS0 bit
in BCRH. One or two states can be selected for burst access.
In burst ROM interface space, burst access covers only CPU read accesses.
7.6.1
Basic Timing
The number of access states in the initial cycle (full access) with the burst ROM interface is
determined by the AST0 setting in ASTCR. Wait states can be inserted when the AST0 bit is set to
1. One or two states can be selected for the burst cycle according to the BRSTS1 bit setting in
BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, area 0 is a
16-bit access space regardless of the ABW0 bit setting in ABWCR.
When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to four words is performed.
When the BRSTS0 bit is set to 1, burst access of up to eight words is performed.
The basic access timing for burst ROM space is shown in figures 7.14 and 7.15.
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Section 7 Bus Controller (BSC)
Burst access
Full access
T1
T2
T3
T1
T2
T1
T2
φ
Only the lower address changes
Address bus
AS
RD
Data bus
Read data
Read data
Read data
Note: n = 1 and 0
Figure 7.14 Example of Burst ROM Access Timing
(AST0 = 1 and BRSTS0 = 1)
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Section 7 Bus Controller (BSC)
Full access
T1
T2
Burst access
T1
T1
φ
Only the lower address changes
Address bus
AS
RD
Data bus
Read data
Read data
Read data
Note: n = 1 and 0
Figure 7.15 Example of Burst ROM Access Timing
(AST0 = 0 and BRSTS1 = 0)
7.6.2
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) on the burst ROM interface. See section 7.5.4,
Wait Control. Wait states cannot be inserted in a burst cycle.
7.6.3
Write Access
When a write access to burst ROM interface space is executed, burst access is interrupted at that
point and the write access is executed in line with the basic bus interface settings. Write accesses
are not performed in burst mode even though burst ROM space is designated.
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Section 7 Bus Controller (BSC)
7.7
Idle Cycle
7.7.1
Operation
When this LSI accesses external address space, it can insert a 1-state idle cycle (Ti) between bus
cycles in the following two cases: (1) when read accesses in different areas occur consecutively
and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle, it is
possible, for example, to avoid data collisions between memory with a long output floating time
(such as ROM) and high-speed memory, I/O interfaces, and so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit is set to 1 in BCRH, an idle cycle is inserted at the start of the second read cycle.
Figure 7.16 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS* (area A)
CS* (area A)
CS* (area B)
CS* (area B)
RD
RD
Data bus
Data bus
Long output floating time
T2
T3
Data collision
(a) No idle cycle insertion
(ICIS1 = 0)
T1
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
Figure 7.16 Example of Idle Cycle Operation
(Consecutive Reads in Different Areas)
REJ09B0200-0200
Ti
Idle cycle
Note: * The CS signal is generated outside the LSI.
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Bus cycle B
T2
Section 7 Bus Controller (BSC)
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCRH, an idle cycle is inserted at the start of the write cycle.
Figure 7.17 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in bus cycle B between the data read from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T1
T2
φ
φ
Address bus
Address bus
CS* (area A)
CS* (area A)
CS* (area B)
CS* (area B)
RD
RD
HWR
HWR
Data bus
Data bus
Long output floating time
Data collision
(a) No idle cycle insertion
(ICIS0 = 0)
T2
T3
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS0 = 1, initial value)
Note: * The CS signal is generated outside the LSI.
Figure 7.17 Example of Idle Cycle Operation (Write after Read)
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Section 7 Bus Controller (BSC)
Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system's load conditions, the RD signal may lag behind the CS signal (generated outside the LSI).
An example is shown in figure 7.18. In this case, with the setting for no idle cycle insertion (a),
there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS
signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD
and CS signals. In the initial state after reset release, idle cycle insertion (b) is set.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS* (area A)
CS* (area A)
CS* (area B)
CS* (area B)
RD
RD
Overlap period between CS (area B)
and RD may occur
(a) No idle cycle insertion
(ICIS1 = 0)
T2
T3
Bus cycle B
Ti
T1
Idle cycle
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
Note: * The CS signal is generated outside the LSI.
Figure 7.18 Relationship between Chip Select (CS) and Read (RD)
7.7.2
Pin States in Idle Cycle
Table 7.4 shows the pin states in an idle cycle.
Table 7.4
Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Contents of following bus cycle
D15 to D0
High impedance
AS
High
RD
High
HWR, LWR
High
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T2
Section 7 Bus Controller (BSC)
7.8
Write Data Buffer Function
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables external writes to be executed in parallel with internal accesses. The write data
buffer function is made available by setting the WDBE bit to 1 in BCRL.
Figure 7.19 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external address space write continues for two states or longer, and there is
an internal access next, an external write only is executed in the first state, but from the next state
onward an internal access (on-chip memory or internal I/O register read/write) is executed in
parallel with the external address space write rather than waiting until it ends.
On-chip memory read Internal I/O register read
External write cycle
T1
T2
TW
TW
T3
Internal address bus
Internal memory
Internal I/O register address
Internal read signal
A23 to A0
External space
write
External address
HWR, LWR
D15 to D0
Figure 7.19 Example of Timing when Write Data Buffer Function is Used
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Section 7 Bus Controller (BSC)
7.9
Bus Arbitration
This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration).
There are two bus masters—the CPU and DTC—that perform read/write operations when they
have the bus mastership. Each bus master requests the bus by means of a bus request signal. The
bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a
bus request acknowledge signal. The selected bus master then takes the bus mastership and begins
its operation.
7.9.1
Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a
bus request acknowledge signal to the bus master. If there are bus requests from more than one
bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a
bus master receives the bus request acknowledge signal, it takes the bus mastership until that
signal is canceled.
The order of priority of the bus masterships is as follows:
(High) DTC > CPU (Low)
7.9.2
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific timings at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,
the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of
the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the component operations.
• With bit manipulation instructions such as BSET and BCRL, the sequence of operations is:
data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is
not transferred during this read-modify-write cycle, which is executed as a series of bus cycles.
• If the CPU is in sleep mode, the bus is transferred immediately.
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Section 7 Bus Controller (BSC)
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
7.10
Bus Controller Operation in Reset
In a power-on reset, this LSI, including the bus controller, enters the reset state immediately, and
any executing bus cycle is aborted.
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Section 7 Bus Controller (BSC)
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Section 8 Data Transfer Controller (DTC)
Section 8 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 8.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM. When the DTC is used, the RAME
bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte),
enabling 32-bit/1-state reading and writing of the DTC register information.
8.1
Features
• Transfer is possible over any number of channels
• Three transfer modes
 Normal, repeat, and block transfer modes are available
• One activation source can trigger a number of data transfers (chain transfer)
• The direct specification of 16-Mbyte address space is possible
• Activation by software is possible
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
• Module stop mode can be set
DTCH80BA_020020040800
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Section 8 Data Transfer Controller (DTC)
Internal address bus
CPU interrupt
request
[Legend]
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERG,
DTCERI:
DTVECR:
Internal data bus
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC enable registers A to G, I
DTC vector register
Figure 8.1 Block Diagram of DTC
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Register information
MRA MRB
CRA
CRB
DAR
SAR
DTC service
request
DTVECR
DTCERA
to
DTCERG
DTCERI
Interrupt
request
On-chip
RAM
DTC
Control logic
Interrupt controller
Section 8 Data Transfer Controller (DTC)
8.2
Register Descriptions
The DTC has the following registers.
•
•
•
•
•
•
DTC mode register A (MRA)
DTC mode register B (MRB)
DTC source address register (SAR)
DTC destination address register (DAR)
DTC transfer count register A (CRA)
DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU.
When activated, the DTC reads a set of register information that is stored in on-chip RAM to the
corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated
register information back to the RAM.
• DTC enable registers A to G, and I (DTCERA to DTCERG, DTCERI)
• DTC vector register (DTVECR)
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Section 8 Data Transfer Controller (DTC)
8.2.1
DTC Mode Register A (MRA)
MRA is an 8-bit register that selects the DTC operating mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
SM1
Undefined

Source Address Mode 1 and 0
6
SM0
Undefined

These bits specify an SAR operation after a data
transfer.
0X: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
5
DM1
Undefined

Destination Address Mode 1 and 0
4
DM0
Undefined

These bits specify a DAR operation after a data
transfer.
0X: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
3
MD1
Undefined

DTC Mode
2
MD0
Undefined

These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
1
DTS
Undefined

DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area, in repeat
mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
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Section 8 Data Transfer Controller (DTC)
Bit
Bit Name
Initial
Value
R/W
Description
0
Sz
Undefined

DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
[Legend]
X:
Don't care
8.2.2
DTC Mode Register B (MRB)
MRB is an 8-bit register that selects the DTC operating mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
CHNE
Undefined

DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to 8.5.4, Chain Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers, clearing of
the interrupt source flag, and clearing of DTCER, are
not performed.
6
DISEL
Undefined

DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after the end of a data transfer.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
5 to 0

Undefined

Reserved
These bits have no effect on DTC operation. Only 0
should be written to these bits.
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Section 8 Data Transfer Controller (DTC)
8.2.3
DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
8.2.4
DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
8.2.5
DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts; the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00.
8.2.6
DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
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Section 8 Data Transfer Controller (DTC)
8.2.7
DTC Enable Registers A to G, and I (DTCERA to DTCERG, and DTCERI)
DTCER is comprised of seven registers; DTCERA to DTCERG, and DTCERI, and is a register
that specifies DTC activation interrupt sources. The correspondence between interrupt sources and
DTCE bits is shown in table 8.1. For DTCE bit setting, use bit manipulation instructions such as
BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources
can be set at one time (only at the initial setting) by writing data after executing a dummy read on
the relevant register.
Bit
Bit Name
Initial
Value
R/W
Description
7
DTCE7
0
R/W
DTC Activation Enable
6
DTCE6
0
R/W
5
DTCE5
0
R/W
Setting this bit to 1 specifies a relevant interrupt source
as a DTC activation source.
4
DTCE4
0
R/W
[Clearing conditions]
3
DTCE3
0
R/W
•
2
DTCE2
0
R/W
When the DISEL bit in MRB is 1 and the data
transfer has ended
1
DTCE1
0
R/W
•
When the specified number of transfers have ended
0
DTCE0
0
R/W
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not been
completed.
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Section 8 Data Transfer Controller (DTC)
8.2.8
DTC Vector Registers A to G (DTVECRA to DTVECRG)
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
Bit
Bit Name
Initial
Value
R/W
Description
7
SWDTE
0
R/W
DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be written
to this bit.
[Clearing conditions]
•
When the DISEL bit is 0 and the specified number
of transfers have not ended
•
When 0 is written to the DISEL bit after a softwareactivated data transfer end interrupt (SWDTEND)
request has been sent to the CPU.
When the DISEL bit is 1 and data transfer has ended or
when the specified number of transfers have ended,
this bit will not be cleared.
6
DTVEC6
0
R/W
DTC Software Activation Vectors 0 to 6
5
DTVEC5
0
R/W
4
DTVEC4
0
R/W
These bits specify a vector number for DTC software
activation.
3
DTVEC3
0
R/W
2
DTVEC2
0
R/W
1
DTVEC1
0
R/W
0
DTVEC0
0
R/W
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The vector address is expressed as H'0400 + (vector
number × 2). For example, when DTVEC6 to DTVEC0
= H'10, the vector address is H'0420. When the bit
SWDTE is 0, these bits can be written.
Section 8 Data Transfer Controller (DTC)
8.3
Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER
bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source or corresponding DTCER bit is cleared. The activation source flag, in the case
of RXI_0, for example, is the RDRF flag of SCI_0.
When an interrupt has been designated a DTC activation source, the existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
Figure 8.2 shows a block diagram of DTC activation source control. For details, see section 5,
Interrupt Controller.
Source flag cleared
Clear
controller
Clear
DTCER
On-chip
supporting
module
IRQ interrupt
DTVECR
Interrupt
request
Selection circuit
Select
Clear request
DTC
CPU
Interrupt controller
Interrupt mask
Figure 8.2 Block Diagram of DTC Activation Source Control
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Section 8 Data Transfer Controller (DTC)
8.4
Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF).
Register information should be located at an address that is a multiple of four within the range.
Locating the register information in address space is shown in figure 8.3. Locate the MRA, SAR,
MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register
information.
In the case of chain transfer, register information should be located in consecutive areas and the
register information start address should be located at the vector address corresponding to the
interrupt source as shown in figure 8.3. The DTC reads the start address of the register information
from the vector address set for each activation source, and then reads the register information from
that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420. The
configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit
being used in both cases. These two bytes specify the lower bits of the register information start
address.
Lower address
0
Register
information
start address
Chain
transfer
1
2
MRA
SAR
MRB
DAR
3
Register information
CRB
CRA
MRA
SAR
MRB
DAR
Register information
for 2nd transfer in
chain transfer
CRB
CRA
4 bytes
Figure 8.3 Location of DTC Register Information in Address Space
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Section 8 Data Transfer Controller (DTC)
Table 8.1
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Interrupt
Source
Origin of
Interrupt Source
DTC
Vector Number Vector Address
DTCE*
Priority
Software
Write to DTVECR
DTVECR
H'0400 + (vector
number × 2)

High
External pin
IRQ0
16
H'0420
DTCEA7
IRQ1
17
H'0422
DTCEA6
IRQ2
18
H'0424
DTCEA5
IRQ3
19
H'0426
DTCEA4
IRQ4
20
H'0428
DTCEA3
IRQ5
21
H'042A
DTCEA2
Reserved for
system use
22
H'042C
DTCEA1
23
H'042E
DTCEA0
A/D counter
ADI (A/D
conversion end)
28
H'0438
DTCEB6
TPU_0
TGIA_0
32
H'0440
DTCEB5
TGIB_0
33
H'0442
DTCEB4
TGIC_0
34
H'0444
DTCEB3
TGID_0
35
H'0446
DTCEB2
TGIA_1
40
H'0450
DTCEB1
TGIB_1
41
H'0452
DTCEB0
TGIA_2
44
H'0458
DTCEC7
TGIB_2
45
H'045A
DTCEC6
TGIA_3
48
H'0460
DTCEC5
TGIB_3
49
H'0462
DTCEC4
TGIC_3
50
H'0464
DTCEC3
TGID_3
51
H'0466
DTCEC2
TGIA_4
56
H'0470
DTCEC1
TGIB_4
57
H'0472
DTCEC0
TGIA_5
60
H'0478
DTCED5
TGIB_5
61
H'047A
DTCED4

TPU_1
TPU_2
TPU_3
TPU_4
TPU_5
Low
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Section 8 Data Transfer Controller (DTC)
Interrupt
Source
Origin of
Interrupt Source
DTC
Vector Number Vector Address
DTCE*
Priority

Reserved for
system use
64
H'0480
DTCED3
High
65
H'0482
DTCED2
68
H'0488
DTCED1
69
H'048A
DTCED0
72
H'0490
DTCEE7
73
H'0492
DTCEE6
74
H'0494
DTCEE5
75
H'0496
DTCEE4
RXI_0
81
H'04A2
DTCEE3
TXI_0
82
H'04A4
DTCEE2
RXI_1
85
H'04A8
DTCEE1
TXI_1
86
H'04AA
DTCEE0

Reserved for
system use
SCI_0
SCI_1
SCI_2
RXI_2
89
H'04B2
DTCEF7
TXI_2
90
H'04B4
DTCEF6
Reserved for
system use
92
H'04B8
DTCEF5
93
H'04BA
DTCEF4
96
H'04C0
DTCEF3
97
H'04C2
DTCEF2
Motor control CMI1
PWM
CMI2
104
H'04D0
DTCEG7
105
H'04D2
DTCEG6
Hcan_1
Reserved for
system use
106
H'04D4
DTCEG5
RM0
107
H'04D6
DTCEG4
Reserved for
system use
108
H'04D8
DTCEG3
RM0
109
H'04DA
DTCEG2
RXI_4
125
H'04FA
DTCEI5
TXI_4
126
H'04FC
DTCEI4


Reserved for
system use
HCAN_0
SCI_4
Note:
*
Low
DTCE bits with no corresponding interrupt are reserved, and the write value should
always be 0.
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Section 8 Data Transfer Controller (DTC)
8.5
Operation
Register information is stored in on-chip RAM. When activated, the DTC reads register
information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated
register information back to the on-chip RAM.
The pre-storage of register information in the on-chip RAM makes it possible to transfer data over
any required number of channels. The transfer mode can be specified as normal, repeat, and block
transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of
transfers with a single activation source (chain transfer).
The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed depending on its register information.
Start
Read DTC vector
Next transfer
Read register information
Data transfer
Write register information
CHNE=1
Yes
No
Transfer Counter=0
or DISEL=1
Yes
No
Clear an activation flag
Clear DTCER
End
Interrupt exception
handling
Figure 8.4 Flowchart of DTC Operation
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Section 8 Data Transfer Controller (DTC)
8.5.1
Normal Mode
In normal mode, one operation transfers one byte or one word of data.
Table 8.2 lists the register information in normal mode.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been
completed, a CPU interrupt can be requested.
Table 8.2
Register Information in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register A
CRA
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR
DAR
Transfer
Figure 8.5 Memory Mapping in Normal Mode
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Section 8 Data Transfer Controller (DTC)
8.5.2
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data. Table 8.3 lists the register
information in repeat mode.
From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the
initial state of the transfer counter and the address register specified as the repeat area is restored,
and transfer is repeated. In repeat mode the transfer counter value does not reach H′00, and
therefore CPU interrupts cannot be requested when DISEL = 0.
Table 8.3
Register Information in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR
or
DAR
DAR
or
SAR
Repeat area
Transfer
Figure 8.6 Memory Mapping in Repeat Mode
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Section 8 Data Transfer Controller (DTC)
8.5.3
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 8.4 lists the register information in block
transfer mode.
The block size can be between 1 and 256. When the transfer of one block ends, the initial state of
the block size counter and the address register specified as the block area is restored. The other
address register is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been
completed, a CPU interrupt is requested.
Table 8.4
Register Information in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Designates block size count
DTC transfer count register B
CRB
Transfer count
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Section 8 Data Transfer Controller (DTC)
First block
SAR
or
DAR
Block area
Transfer
DAR
or
SAR
Nth block
Figure 8.7 Memory Mapping in Block Transfer Mode
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Section 8 Data Transfer Controller (DTC)
8.5.4
Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB,
which define data transfers, can be set independently.
Figure 8.8 shows the outline of the chain transfer operation.
When activated, the DTC reads the register information start address stored at the vector address
corresponding to the activation source, and then reads the first register information at that start
address. After data transfer ends, the CHNE bit will be tested. When it has been set to 1, DTC
reads the next register information located in a consecutive area and performs the data transfer.
These sequences are repeated until the CHNE bit is cleared to 0.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Source
Destination
Register information
CHNE=1
DTC vector
address
Register information
start address
Register information
CHNE=0
Source
Destination
Figure 8.8 Chain Transfer Operation
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Section 8 Data Transfer Controller (DTC)
8.5.5
Interrupts
An interrupt request is issued to the CPU when the DTC has completed the specified number of
data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt
activation, the interrupt set as the activation source is generated. These interrupts to the CPU are
subject to CPU mask level and interrupt controller priority level control.
In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is
generated.
When the DISEL bit is 1 and one data transfer has been completed, or the specified number of
transfers have been completed, after data transfer ends the SWDTE bit is held at 1 and an
SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit
to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
8.5.6
Operation Timing
φ
DTC activation
request
DTC
request
Vector read
Data transfer
Address
Read Write
Transfer
information read
Transfer
information write
Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
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Section 8 Data Transfer Controller (DTC)
φ
DTC activation
request
DTC
request
Data transfer
Vector read
Read Write Read Write
Address
Transfer
information read
Transfer
information write
Figure 8.10 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
φ
DTC activation
request
DTC
request
Data transfer
Data transfer
Read Write
Read Write
Vector read
Address
Transfer
information read
Transfer
information
write
Transfer
information
read
Transfer
information write
Figure 8.11 DTC Operation Timing (Example of Chain Transfer)
8.5.7
Number of DTC Execution States
Table 8.5 lists execution status for a single DTC data transfer, and table 8.6 shows the number of
states required for each execution status.
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Section 8 Data Transfer Controller (DTC)
Table 8.5
DTC Execution Status
Mode
Vector Read
I
Register Information
Read/Write
Data Read
J
K
Data Write
L
Internal
Operations
M
Normal
1
6
1
1
3
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
[Legend]
N:
Block size (initial setting of CRAH and CRAL)
Table 8.6
Number of States Required for Each Execution Status
Object to be Accessed
OnChip
RAM
OnChip On-Chip I/O
ROM Registers
External Devices*
Bus width
32
16
8
16
8
Access states
1
1
2
2
2
Execution
status
Vector read SI

1


4
6+2m 2
3+m
Register information
read/write SJ
1







Byte data read SK
1
1
2
2
2
3+m
2
3+m
Word data read SK
1
1
4
2
4
6+2m 2
3+m
Byte data write SL
1
1
2
2
2
3+m
2
3+m
Word data write SL
1
1
4
2
4
6+2m 2
3+m
Internal operation SM
1
Note:
*
16
3
2
3
Not available in this LSI.
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · (1 + SI) + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in the on-chip ROM, normal mode is
set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for
the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev. 2.00 Dec. 05, 2005 Page 157 of 724
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Section 8 Data Transfer Controller (DTC)
8.6
Procedures for Using DTC
8.6.1
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
1.
2.
3.
4.
Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.
Set the start address of the register information in the DTC vector address.
Set the corresponding bit in DTCER to 1.
Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
5. After one data transfer has been completed, or after the specified number of data transfers have
been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to
continue transferring data, set the DTCE bit to 1.
8.6.2
Activation by Software
The procedure for using the DTC with software activation is as follows:
1.
2.
3.
4.
5.
6.
Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.
Set the start address of the register information in the DTC vector address.
Check that the SWDTE bit is 0.
Write 1 to SWDTE bit and the vector number to DTVECR.
Check the vector number written to DTVECR.
After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not
requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the
SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have
been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested.
Rev. 2.00 Dec. 05, 2005 Page 158 of 724
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Section 8 Data Transfer Controller (DTC)
8.7
Examples of Use of the DTC
8.7.1
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1
= 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI RDR address in SAR, the start address of the RAM area where data will be received in
DAR, and 128 (H′0080) in CRA. CRB can be set to any value.
2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the
reception complete (RXI) interrupt. Since the generation of a receive error during the SCI
reception operation will disable subsequent reception, the CPU should be enabled to accept
receive error interrupts.
5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in
SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is
transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented.
The RDRF flag is automatically cleared to 0.
6. When CRA becomes 0 after the 128 data transfers have been completed, the RDRF flag is held
at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The
interrupt handling routine will perform wrap-up processing.
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Section 8 Data Transfer Controller (DTC)
8.7.2
Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG.
Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle
updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain
transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing
of the activation source and interrupt generation at the end of the specified number of transfers are
restricted to the second half of the chain transfer (transfer when CHNE = 0).
1. Perform settings for transfer to the PPG's NDR. Set MRA to incrementing source address
(SM1 = 1, SM0 = 0), a fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,
MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to
chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH
address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.
2. Perform settings for transfer to the TPU's TGR. Set MRA to incrementing source address
(SM1 = 1, SM0 = 0), a fixed destination address (DM1 = DM0 = 0), normal mode (MD1 =
MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address
in DAR, and the data table size in CRA. CRB can be set to any value.
3. Locate the TPU transfer register information consecutively after the NDR transfer register
information.
4. Set the start address of the NDR transfer register information to the DTC vector address.
5. Set the bit corresponding to TGIA in DTCER to 1.
6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA
interrupt with TIER.
7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and
NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to
be used as the output trigger.
8. Set the CST bit in TSTR to 1, and start the TCNT count operation.
9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the
set value of the next output trigger period is transferred to TGRA. The activation source TGFA
flag is cleared.
10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the
TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the
CPU. Termination processing should be performed in the interrupt handling routine.
Rev. 2.00 Dec. 05, 2005 Page 160 of 724
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Section 8 Data Transfer Controller (DTC)
8.7.3
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the destination address is
H'2000. The vector number is H'60, so the vector address is H′04C0.
1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,
and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
2. Set the start address of the register information at the DTC vector address (H'04C0).
3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
Rev. 2.00 Dec. 05, 2005 Page 161 of 724
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Section 8 Data Transfer Controller (DTC)
8.8
Usage Notes
8.8.1
Module Stop Mode Setting
DTC operation can be disabled or enabled using the module stop control register. The initial
setting is for DTC operation to be enabled. Register access is disabled by setting module stop
mode. Note that module stop mode cannot be set during DTC being activated. For details, refer to
section 21, Power-Down Modes.
8.8.2
On-Chip RAM
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0.
8.8.3
DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are masked, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
Rev. 2.00 Dec. 05, 2005 Page 162 of 724
REJ09B0200-0200
Section 9 I/O Ports
Section 9 I/O Ports
This LSI has 13 I/O ports (ports 1 to 3, 5, A to F, H, J, and K), and two input-only port (ports 4
and 9).
Table 9.1 shows the port functions. The pins of each port also have other functions.
Each I/O port includes a data direction register (DDR) that controls input/output, a data register
(DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only
ports do not have a DR or DDR register.
Ports A to E have a built-in pull-up MOS function, and in addition to DR and DDR, have a MOS
input pull-up control register (PCR) to control the on/off state of MOS input pull-up.
Ports 3, and A to C include an open-drain control register (ODR) that controls the on/off state of
the output buffer PMOS.
When ports A to F are used as the output pins for expanded bus control signals, they can drive one
TTL load plus a 50pF capacitance load. Ports other than A to F can drive one TTL load and a
30pF capacitance load. All I/O ports can drive Darlington transistors when set to output. Ports 1
and A to C can drive a LED (10 mA sink current), and some of the pins in ports B, C, and E and
A, D, and F can be used as LCD driver pins.
Port 1 pins P16 and P14 are Schmitt-trigger inputs.
Rev. 2.00 Dec. 05, 2005 Page 163 of 724
REJ09B0200-0200
Section 9 I/O Ports
Table 9.1
Port Functions
Port
Description
Mode 4
Mode 5
Port 1
General I/O port
also functioning as
TPU I/O pins, PPG
output pins, and
interrupt input pins
P17/PO15/TIOCB2/TCLKD
Mode 6
Mode 7
Input/Output
Type
P16 /PO14/TIOCA2/IRQ1
P15 /PO13/TIOCB1/TCLKC
P14 /PO12/TIOCA1/IRQ0
P13 /PO11/TIOCD0/TCLKB
P12 /PO10/TIOCC0/TCLKA
P11/PO9/TIOCB0
P10/PO8/TIOCA0
Port 2
General I/O port
also functioning as
TPU I/O pins
P27/TIOCB5
P26/TIOCA5
P25/TIOCB4
P24/TIOCA4
P23/TIOCD3
P22/TIOCC3
P21/TIOCB3
P20/TIOCA3
Port 3
General I/O port
also functioning as
SCI I/O pins and
interrupt input pins
P37/TxD4
P36/RxD4
P35/SCK1/SCK4/IRQ5
P34/RxD1
P33/TxD1
P32/SCK0/IRQ4
P31/RxD0
P30/TxD0
Rev. 2.00 Dec. 05, 2005 Page 164 of 724
REJ09B0200-0200
Open-drain
output
Section 9 I/O Ports
Port
Description
Mode 4
Port 4
General input port
also functioning as
analog input pins
P47/AN7
Mode 5
Mode 6
Input/Output
Type
Mode 7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
Port 5
General I/O port
also functioning as
SCI I/O pins
P52/SCK2
P51/RxD2
P50/TxD2
Port 9
General input port
also functioning as
analog input pins
P97/AN15
P96/AN14
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
Port A
General I/O port
also functioning as
LCD segment
output pins,
common output
pins, and address
output pins
PA7/A23/SEG40
PA7/SEG40
PA6/A22/SEG39
PA6/SEG39
PA5/A21/SEG38
PA5/SEG38
PA4/A20/SEG37
PA4/SEG37
PA3/A19/COM4
PA3/COM4
PA2/A18/COM3
PA2/COM3
PA1/A17COM2
PA1/COM2
PA0/A16/COM1
PA0/COM1
Built-in
pull-up MOS
Open-drain
output
Rev. 2.00 Dec. 05, 2005 Page 165 of 724
REJ09B0200-0200
Section 9 I/O Ports
Port
Description
Mode 4
Port B
General I/O port
also functioning as
LCD segment
output pins, address
output pins
PB7/A15/SEG32
PB7/SEG32
PB6/A14/SEG31
PB6/SEG31
PB5/A13/SEG30
PB5/SEG30
PB4/A12/SEG29
PB4/SEG29
PB3/A11/SEG28
PB3/SEG28
PB2/A10/SEG27
PB2/SEG27
PB1/A9/SEG26
PB1/SEG26
PB0/A8/SEG25
PB0/SEG25
Port C
Port D
Port E
General I/O port
also functioning as
LCD segment
output pins and
address output pins
General I/O port
also functioning as
LCD segment
output pins and
data I/O pins
General I/O port
also functioning as
LCD segment
output pins and
data I/O pins
Mode 6
Mode 7
PC7/A7
PC7/A7/SEG24 PC7/SEG24
PC7/A6
PC6/A6/SEG23 PC6/SEG23
PC7/A5
PC5/A5/SEG22 PC5/SEG22
PC7/A4
PC4/A4/SEG21 PC4/SEG21
PC7/A3
PC3/A3/SEG20 PC3/SEG20
PC7/A2
PC2/A2/SEG19 PC2/SEG19
PC7/A1
PC1/A1/SEG18 PC1/SEG18
PC7/A0
PC0/A0/SEG17 PC0/SEG17
D15
D15/SEG16
PD7/SEG16
D14
D14/SEG15
PD6/SEG15
D13
D13/SEG14
PD5/SEG14
D12
D12/SEG13
PD4/SEG13
D11
D11/SEG12
PD3/SEG12
D10
D10/SEG11
PD2/SEG11
D9
D9/SEG10
PD1/SEG10
D8
D8/SEG9
PD0/SEG9
PE7/D7/SEG8
PE7/SEG8
PE6/D6/SEG7
PE6/SEG7
PE5/D5/SEG6
PE5/SEG6
PE4/D4/SEG5
PE4/SEG5
PE3/D3/SEG4
PE3/SEG4
PE2/D2/SEG3
PE2/SEG3
PE1/D1/SEG2
PE1/SEG2
PE0 /D0/SEG1
PE0/SEG1
Rev. 2.00 Dec. 05, 2005 Page 166 of 724
REJ09B0200-0200
Mode 5
Input/Output
Type
Built-in
pull-up MOS
Built-in
pull-up MOS
Section 9 I/O Ports
Description
Mode 4
Port F
General I/O port
also functioning as
φ output pin, bus
control I/O pins,
LCD segment
output pins, and
interrupt input pins
PF7/φ
PF7/φ
PF6/AS/SEG36
PF6/SEG36
PF5/RD/SEG35
PF5/SEG35
PF4/HWR/SEG34
PF4/SEG34
PF3/LWR/ADTRG/IRQ3
PF3/ADTRG/
IRQ3
PF2/WAIT/SEG33
PF2/SEG33
PF0/IRQ2
PF0/IRQ2
Port H
General I/O port
also functioning as
PWM output pins
Mode 5
Mode 6
Input/Output
Type
Port
Mode 7
PH7/PWM1H
PH6/PWM1G
PH5/PWM1F
PH4/PWM1E
PH3/PWM1D
PH2/PWM1C
PH1/PWM1B
PH0/PWM1A
Port J
General I/O port
also functioning as
PWM output pins
PJ7/PWM2H
PJ6/PWM2G
PJ5/PWM2F
PJ4/PWM2E
PJ3/PWM2D
PJ2/PWM2C
PJ1/PWM2B
PJ0/PWM2A
Port K
General I/O port
also functioning as
HCAN I/O pins
PK7/HRxD1
PK6/HTxD1
Rev. 2.00 Dec. 05, 2005 Page 167 of 724
REJ09B0200-0200
Section 9 I/O Ports
9.1
Port 1
Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins, TPU I/O pins, and external
interrupt pins.
• Port 1 data direction register (P1DDR)
• Port 1 data register (P1DR)
• Port 1 register (PORT1)
9.1.1
Port 1 Data Direction Register (P1DDR)
P1DDR is a write-only register, the individual bits of which specify input or output for the pins of
port 1. P1DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
Setting a P1DDR bit to 1 makes the corresponding port
1 pin an output pin, while clearing the bit to 0 makes the
pin an input pin.
4
P14DDR
0
W
3
P13DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
0
P10DDR
0
W
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REJ09B0200-0200
Section 9 I/O Ports
9.1.2
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
P17DR
0
R/W
6
P16DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
0
P10DR
0
R/W
9.1.3
Port 1 Register (PORT1)
PORT1 shows the pin states. It cannot be modified.
Bit
Bit Name
Initial
Value
R/W
Description
7
P17
*
R
6
P16
*
R
5
P15
*
R
If this register read is performed while P1DDR bits are
set to 1, the P1DR values are read. If this register read
is performed while P1DDR bits are cleared to 0, the pin
states are read.
4
P14
*
R
3
P13
*
R
2
P12
*
R
1
P11
*
R
0
P10
*
R
Note:
*
Determined by state of pins P17 to P10.
Rev. 2.00 Dec. 05, 2005 Page 169 of 724
REJ09B0200-0200
Section 9 I/O Ports
9.1.4
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
• P17/PO15/TIOCB2/TCLKD
The pin function is switched as shown below according to the combination of the TPU channel 2
setting (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and
CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in NDERH, and bit
P17DDR.
TPU channel 2
setting
Table below (1)
Table below (2)
P17DDR

0
1
1
NDER15


0
1
TIOCB2 output
P17 input
P17 output
PO15 output
Pin function
TIOCB2 input *1
TCLKD input *2
TPU channel 2
setting
(2)
MD3 to MD0
IOB3 to IOB0
(1)
B'0000, B'0010
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(2)
(2)
B'0010
(1)
(2)
B'0010

B'xx10
Other than B'xx10
B'1xxx
CCLR1, CCLR0




Other than
B'10
B'10
Output function

Output compare
output


PWM mode
2 output

[Legend]
x:
Don't care
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 = 1.
2. TCLKD input when the setting for either TCR_0 or TCR_5 is: TPSC2 to TPSC0 =
B'111.
TCLKD input when channels 2 and 4 are set to phase counting mode.
Rev. 2.00 Dec. 05, 2005 Page 170 of 724
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Section 9 I/O Ports
• P16/PO14/TIOCA2/IRQ1
The pin function is switched as shown below according to the combination of the TPU channel 2
setting (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and
CCLR0 in TCR_2), bit NDER14 in NDERH, and bit P16DDR.
TPU channel 2
setting
Table below (1)
Table below (2)
P16DDR

0
1
1
NDER14


0
1
TIOCA2 output
P16 input
P16 output
Pin function
PO14 output
1
TIOCB2 input *
IRQ1 input
TPU channel 2
setting
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000, B'01xx
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other than
B'xx00
Other than B'xx00
B'1xxx
CCLR1, CCLR0




Other than
B'01
B'01
Output function

Output compare
output

PWM mode
1 output *2
PWM
mode 2
output

[Legend]
x:
Don't care
Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 = 1.
2. TIOCB2 output is disabled.
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Section 9 I/O Ports
• P15/PO13/TIOCB1/TCLKC
The pin function is switched as shown below according to the combination of the TPU channel 1
setting (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and
CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13
in NDERH, and bit P15DDR.
TPU channel 1
setting
Table below (1)
Table below (2)
P15DDR

0
1
1
NDER13


0
1
TIOCB1 output
P15 input
P15 output
Pin function
TIOCB1 input *
PO13 output
1
TCLKC input *2
TPU channel 1
setting
(2)
MD3 to MD0
IOB3 to IOB0
(1)
B'0000, B'01xx
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(2)
(2)
B'0010
(1)
(2)
B'0011

B'xx00
Other than B'xx00
B'1xxx
CCLR1, CCLR0




Other than
B'10
B'10
Output function

Output compare
output


PWM
mode 2
output

[Legend]
x:
Don't care
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 to IOB0 = B'10xx.
2. TCLKC input when the setting for either TCR_0 or TCR_2 is: TPSC2 to TPSC0 =
B'110; or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101.
TCLKC input when channels 2 and 4 are set to phase counting mode.
Rev. 2.00 Dec. 05, 2005 Page 172 of 724
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Section 9 I/O Ports
• P14/PO12/TIOCA1/IRQ0
The pin function is switched as shown below according to the combination of the TPU channel 1
setting (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and
CCLR0 in TCR_1), bit NDER12 in NDERH, and bit P14DDR.
TPU channel 1
setting
Table below (1)
Table below (2)
P14DDR

0
1
1
NDER12


0
1
TIOCA1 output
P14 input
P14 output
Pin function
TIOCA1 input *
PO12 output
1
IRQ0 input
TPU channel 1
setting
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000, B'01xx
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other than
B'xx00
Other than B'xx00
B'1xxx
CCLR1, CCLR0




Other than
B'01
B'01
Output function

Output compare
output

PWM mode
1 output*2
PWM
mode 2
output

[Legend]
x:
Don't care
Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to IOA0 = B'10xx.
2. TIOCB1 output is disabled.
Rev. 2.00 Dec. 05, 2005 Page 173 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P13/PO11/TIOCD0/TCLKB
The pin function is switched as shown below according to the combination of the TPU channel 0
setting (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIORL_0, and bits CCLR2 to
CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH, and bit
P13DDR.
TPU channel 0
setting
Table below (1)
Table below (2)
P13DDR

0
1
1
NDER11


0
1
TIOCD0 output
P13 input
P13 output
Pin function
PO11 output
1
TIOCD0 input *
TCLKB input *2
TPU channel 0
setting
(2)
MD3 to MD0
IOD3 to IOD0
(1)
B'0000, B'01xx
B'0000
B'0001 to B'0011
B'0100
B'0101 toB'0111
(2)
(2)
B'0010
(1)
(2)
B'0011

B'xx00
Other than B'xx00
B'1xxx
CCLR2 to CCLR0




Other than
B'110
B'110
Output function

Output compare
output


PWM
mode 2
output

[Legend]
x:
Don't care
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx.
2. TCLKB input when the setting for TCR_0 to TCR_2 is: TPSC2 to TPSC0 = B'101.
TCLKB input when channels 1 and 5 are set to phase counting mode.
Rev. 2.00 Dec. 05, 2005 Page 174 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P12/PO10/TIOCC0/TCLKA
The pin function is switched as shown below according to the combination of the TPU channel 0
setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to
CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH, and bit
P12DDR.
TPU channel 0
setting
Table below (1)
Table below (2)
P12DDR

0
1
1
NDER10


0
1
TIOCC0 output
P12 input
P12 output
Pin function
PO10 output
1
TIOCC0 input *
TCLKA input *2
TPU channel0
setting
(2)
MD3 to MD0
IOC3 to IOC0
(1)
B'0000, B'01xx
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other than
B'xx00
Other than B'xx00
B'1xxx
CCLR2 to CCLR0




Other than
B'01
B'01
Output function

Output compare
output

PWM mode
1 output*3
PWM
mode 2
output

[Legend]
x:
Don't care
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx.
2. TCLKA input when the setting for TCR_0 to TCR_5 is: TPSC2 to TPSC0 = B'100.
TCLKA input when channels 1 and 5 are set to phase counting mode.
3. TIOCD0 output is disabled.
When BFA = 1 or BFB = 1 in TMDR_0, output is disabled and setting (2) applies.
Rev. 2.00 Dec. 05, 2005 Page 175 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P11/PO9/TIOCB0
The pin function is switched as shown below according to the combination of the operating mode,
and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR_0, and bits IOB3 to IOB0 in
TIORH_0), bit NDER9 in NDERH, and bit P11DDR.
TPU channel 0
setting
Table Below (1)
Table Below (2)
P11DDR

0
1
1
NDER9


0
1
TIOCB0 output
P11 input
P11 output
PO9 output
Pin function
TIOCB0 input *
TPU channel 0
setting
(2)
MD3 to MD0
IOB3 to IOB0
(1)
B'0000
(2)
(2)
B'0010
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(1)
(2)
B'0011

B'xx00
Other than B'xx00
B'1xxx
CCLR2 to CCLR0




Other than
B'010
B'010
Output function

Output compare
output


PWM
mode 2
output

[Legend]
x:
Don't care
Note: * TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx.
Rev. 2.00 Dec. 05, 2005 Page 176 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P10/PO8/TIOCA0
The pin function is switched as shown below according to the combination of the operating mode,
and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in
TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH, and bit P10DDR.
TPU channel 0
setting
Table Below (1)
Table Below (2)
P10DDR

0
1
1
NDER8


0
1
TIOCA0 output
P10 input
P10 output
Pin function
PO8 output
1
TIOCA0 input *
TPU channel 0
setting
(2)
(2)
(1)
B'0000
B'001x
B'0010
B'0000
B'0001 to B'0011
B'xx00
B'0100
B'0101 to B'0111
Other than
B'xx00
MD3 to MD0
IOA3 to IOA0
(1)
(1)
(2)
B'0011
B'1xxx
CCLR2 to CCLR0



—
Other than
B'001
B'001
Output function

Output compare
output

PWM mode
2
1 output*
PWM
mode 2
output
—
[Legend]
x:
Don't care
Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx.
2. TIOCB0 output is disabled.
Rev. 2.00 Dec. 05, 2005 Page 177 of 724
REJ09B0200-0200
Section 9 I/O Ports
9.2
Port 2
Port 2 is an 8-bit I/O port. Port 2 pins also function as TPU I/O pins. The pin functions of port 2
change with the operating mode.
• Port 2 data direction register (P2DDR)
• Port 2 data register (P2DR)
• Port 2 register (PORT2)
9.2.1
Port 2 Data Direction Register (P2DDR)
P2DDR is a write-only register, the individual bits of which specify input or output for the pins of
port 2. P2DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
P27DDR
0
W
6
P26DDR
0
W
5
P25DDR
0
W
Setting a P2DDR bit to 1 makes the corresponding port
2 pin an output pin, while clearing the bit to 0 makes the
pin an input pin.
4
P24DDR
0
W
3
P23DDR
0
W
2
P22DDR
0
W
1
P21DDR
0
W
0
P20DDR
0
W
Rev. 2.00 Dec. 05, 2005 Page 178 of 724
REJ09B0200-0200
Section 9 I/O Ports
9.2.2
Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
P27DR
0
R/W
6
P26DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
0
P20DR
0
R/W
9.2.3
Port 2 Register (PORT2)
PORT2 shows the pin states. It cannot be modified.
Bit
Bit Name
Initial
Value
R/W
Description
7
P27
*
R
6
P26
*
R
5
P25
*
R
If this register read is performed while P2DDR bits are
set to 1, the P2DR values are read. If this port read is
performed while P2DDR bits are cleared to 0, the pin
states are read.
4
P24
*
R
3
P23
*
R
2
P22
*
R
1
P21
*
R
0
P20
*
R
Note:
*
Determined by state of pins P27 to P20.
Rev. 2.00 Dec. 05, 2005 Page 179 of 724
REJ09B0200-0200
Section 9 I/O Ports
9.2.4
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
• P27/TIOCB5
The pin function is switched as shown below according to the combination of the TPU channel 5
setting (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and
CCLR0 in TCR_5), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, and bit P17DDR.
TPU channel 5
setting
Table below (1)

0
1
TIOCB5 output
P27 input
P27 output
P27DDR
Pin function
Table below (2)
TIOCB5 input*
TPU channel 5
setting
(2)
MD3 to MD0
IOB3 to IOB0
(1)
B'0000, B'01xx
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(2)
(2)
B'0010
(1)
(2)
B'0011

B'xx00
Other than B'xx00
B'1xxx
CCLR1, CCLR0




Other than
B'10
B'10
Output function

Output compare
output


PWM mode
2 output

[Legend]
x:
Don't care
Note: * TIOCB5 input if MD3 to MD0 = B'0000 or B'01xx, and IOB = 1.
Rev. 2.00 Dec. 05, 2005 Page 180 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P26/TIOCA5
The pin function is switched as shown below according to the combination of the TPU channel 5
setting (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and
CCLR0 in TCR_5), and bit P26DDR.
TPU channel 5
setting
Table below (1)

0
1
TIOCA5 output
P26 input
P26 output
P26DDR
Pin function
Table below (2)
TIOCA5 input
TPU channel 5
setting
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000, B'01xx
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other than
B'xx00
Other than B'xx00
B'1xxx
CCLR1, CCLR0




Other than
B'01
B'01
Output function

Output compare
output

PWM mode
1 output *
PWM
mode 2
output

[Legend]
x:
Don't care
Note: * TIOCB5 output prohibited.
Rev. 2.00 Dec. 05, 2005 Page 181 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P25/TIOCB4
The pin function is switched as shown below according to the combination of the TPU channel 4
setting (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and
CCLR0 in TCR_4) and bit P25DDR.
TPU channel 4
setting
Table below (1)

0
1
TIOCB4 output
P25 input
P25 output
P25DDR
Pin function
Table below (2)
TIOCB4 input
TPU channel 4
setting
(2)
MD3 to MD0
IOB3 to IOB0
(1)
B'0000, B'01xx
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(2)
(2)
B'0010
(1)
(2)
B'0011

B'xx00
Other than B'xx00
B'1xxx
CCLR1, CCLR0




Other than
B'10
B'10
Output function

Output compare
output


PWM
mode 2
output

[Legend]
x:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 182 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P24/TIOCA4
The pin function is switched as shown below according to the combination of the TPU channel 4
setting (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1 and
CCLR0 in TCR_4), and bit P24DDR.
TPU channel 4
setting
Table below (1)

0
1
TIOCA4 output
P24 input
P24 output
P24DDR
Pin function
Table below (2)
TIOCA4 input
TPU channel 4
setting
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000, B'01xx
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other than
B'xx00
Other than B'xx00
B'1xxx
CCLR1, CCLR0




Other than
B'01
B'01
Output function

Output compare
output

PWM mode
1 output*
PWM
mode 2
output

[Legend]
x:
Don't care
Note: * TIOCB4 output prohibited.
Rev. 2.00 Dec. 05, 2005 Page 183 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P23/TIOCD3
The pin function is switched as shown below according to the combination of the TPU channel 3
setting (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to
CCLR0 in TCR_3) and bit P23DDR.
TPU channel 3
setting
Table below (1)

0
1
TIOCD3 output
P23 input
P23 output
P23DDR
Pin function
Table below (2)
TIOCD3 input
TPU channel 3
setting
(2)
(2)
(2)
B'0000
B'001x
B'0010
B'0011
B'0000
B'0001 to B'0011
B'xx00
Other than B'xx00
B'0100
B'0101 to B'0111
Other than
B'xx00
MD3 to MD0
IOD3 to IOD0
(1)
(1)
(2)
B'1xxx
CCLR2 to CCLR0




Other than
B'101
B'101
Output function

Output compare
output


PWM
mode 2
output

[Legend]
x:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 184 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P22/TIOCC3
The pin function is switched as shown below according to the combination of the TPU channel 3
setting (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to
CCLR0 in TCR_3) and bit P22DDR.
TPU channel 3
setting
Table below (1)

0
1
TIOCC3 output
P22 input
P22 output
P22DDR
Pin function
Table below (2)
TIOCC3 input
TPU channel 3
setting
(2)
MD3 to MD0
IOC3 to IOC0
(1)
B'0000, B'01xx
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other than
B'xx00
Other than B'xx00
B'1xxx
CCLR2 to CCLR0




Other than
B'101
B'101
Output function

Output compare
output

PWM mode
1 output*
PWM
mode 2
output

[Legend]
x:
Don't care
Note: * TIOCD3 output prohibited.
Rev. 2.00 Dec. 05, 2005 Page 185 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P21/TIOCB3
The pin function is switched as shown below according to the combination of the TPU channel 3
setting (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORL_3, and bits CCLR2 to
CCLR0 in TCR_3) and bit P21DDR.
TPU channel 3
setting
Table Below (1)

0
1
TIOCB3 output
P21 input
P21 output
P21DDR
Pin function
Table Below (2)
TIOCB3 input
TPU channel 3
setting
(2)
MD3 to MD0
IOB3 to IOB0
(1)
B'0000
(2)
(2)
B'0010
B'0000
B'0001 to B'0011
B'0100
B'0101 to B'0111
(1)
(2)
B'0011

B'xx00
Other than B'xx00
B'1xxx
CCLR2 to CCLR0




Other than
B'010
B'010
Output function

Output compare
output


PWM
mode 2
output

[Legend]
x:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 186 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P20/TIOCA3
The pin function is switched as shown below according to the combination of the TPU channel 3
setting (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORL_3, and bits CCLR2 to
CCLR0 in TCR_3) and bit P20DDR.
TPU channel 3
setting
Table below (1)

0
1
TIOCA3 output
P20 input
P20 output
P20DDR
Pin function
Table below (2)
TIOCA3 input
TPU channel 3
setting
(2)
(2)
(1)
B'0000
B'001x
B'0010
B'0011
B'0000
B'0001 to B'0011
B'xx00
Other than B'xx00
B'0100
B'0101 to B'0111
Other than
B'xx00
MD3 to MD0
IOA3 to IOA0
(1)
(1)
(2)
B'1xxx
CCLR2 to CCLR0




Other than
B'001
B'001
Output function

Output compare
output

PWM mode
1 output*
PWM
mode 2
output

[Legend]
x:
Don't care
Note: * TIOCB3 output prohibited.
Rev. 2.00 Dec. 05, 2005 Page 187 of 724
REJ09B0200-0200
Section 9 I/O Ports
9.3
Port 3
Port 3 is an 8-bit I/O port. Port 3 pins also function as SCI I/O pins and external interrupt input
pins. All of the port 3 pin functions have the same operating mode.
•
•
•
•
Port 3 data direction register (P3DDR)
Port 3 data register (P3DR)
Port 3 register (PORT3)
Port 3 open-drain control register (PORT3)
9.3.1
Port 3 Data Direction Register (P3DDR)
P3DDR is a write-only register, the individual bits of which specify input or output for the pins of
port 3. P3DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
P37DDR
0
W
6
P36DDR
0
W
5
P35DDR
0
W
Setting a P3DDR bit to 1 makes the corresponding port
3 pin an output pin, while clearing the bit to 0 makes the
pin an input pin.
4
P34DDR
0
W
3
P33DDR
0
W
2
P32DDR
0
W
1
P31DDR
0
W
0
P30DDR
0
W
Rev. 2.00 Dec. 05, 2005 Page 188 of 724
REJ09B0200-0200
Section 9 I/O Ports
9.3.2
Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
P37DR
0
R/W
6
P36DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
5
P35DR
0
R/W
4
P34DR
0
R/W
3
P33DR
0
R/W
2
P32DR
0
R/W
1
P31DR
0
R/W
0
P30DR
0
R/W
9.3.3
Port 3 Register (PORT3)
PORT3 shows the pin states. It cannot be modified.
Bit
Bit Name
Initial
Value
R/W
Description
7
P37
*
R
6
P36
*
R
5
P35
*
R
If this register read is performed while P3DDR bits are
set to 1, the P3DR values are read. If this register read
is performed while P3DDR bits are cleared to 0, the pin
states are read.
4
P34
*
R
3
P33
*
R
2
P32
*
R
1
P31
*
R
0
P30
*
R
Note:
*
Determined by state of pins P37 to P30.
Rev. 2.00 Dec. 05, 2005 Page 189 of 724
REJ09B0200-0200
Section 9 I/O Ports
9.3.4
Port 3 Open-Drain Control Register (P3ODR)
P3ODR controls output of port 3.
Bit
Bit Name
Initial
Value
R/W
Description
7
P37ODR
0
R
6
P36ODR
0
R
5
P35ODR
0
R
By setting P3ODR to 1, the port 3 pins become an
NMOS open drain output, and when cleared to 0 they
become CMOS output.
4
P34ODR
0
R
3
P33ODR
0
R
2
P32ODR
0
R
1
P31ODR
0
R
0
P30ODR
0
R
9.3.5
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
• P37/TxD4
The pin function is switched as shown below according to the combination of the TE bit in SCR of
SCI_4 and P37DDR bit.
TE
0
P37DDR
Pin function
Note:
*
1
0
1

P37 input pin
P37 output pin*
TxD4 output pin
When P37ODR = 1, it becomes NMOS open drain output.
• P36/RxD4
The pin function is switched as shown below according to the combination of the RE bit in SCR
of SCI4 and P36DDR bit.
RE
0
P36DDR
Pin function
Note:
*
1
0
1

P36 input pin
P36 output pin*
RxD4 input pin
When P36ODR = 1, it becomes NMOS open drain output.
Rev. 2.00 Dec. 05, 2005 Page 190 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P35/SCK1/SCK4/IRQ5
The pin function is switched as shown below according to the combination of the C/A bit in SMR
of SCI_1 or SCI_4, the CKE0 and CKE1 bits in SCR, and the P35DDR bit. Do not set
simultaneously SCK1 and SCK4 to output.
CKE1
0
C/A
1
1

1


0
CKE0
0
P35DDR
Pin function
0
1



P35
input pin
P35
output pin
SCK1/SCK4
output pin*
SCK1/SCK4
output pin*
SCK1/SCK4
input pin
IRQ5 input
Note:
*
When P35ODR = 1, it becomes NMOS open drain output.
• P34/RxD1
The pin function is switched as shown below according to the combination of the RE bit in SCR
of SCI_1 and P34DDR bit.
RE
0
P34DDR
Pin function
Note:
*
1
0
1

P34 input pin
P34 output pin*
RxD1 input pin
When P34ODR = 1, it becomes NMOS open drain output.
• P33/TxD1
The pin function is switched as shown below according to the combination of the TE bit in SCR of
SCI_1 and P33DDR bit.
TE
0
P33DDR
Pin function
Note:
*
1
0
1

P33 input pin
P33 output pin*
TxD1 output pin
When P33ODR = 1, it becomes NMOS open drain output.
Rev. 2.00 Dec. 05, 2005 Page 191 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P32/SCK0/IRQ4
The pin function is switched as shown below according to the combination of the C/A bit in SMR
of SCI_0, the CKE0 and CKE1 bits in SCR, and the P32DDR bit.
CKE1
0
C/A
1
1

1


0
CKE0
0
P32DDR
Pin function
0
1



P32
input pin
P32
output pin
SCK0 output
pin*
SCK0 output
pin*
SCK0 input
pin
IRQ4 input
Note:
*
When P32ODR = 1, it becomes NMOS open drain output.
• P31/RxD0
The pin function is switched as shown below according to the combination of the RE bit in SCR
of SCI_0 and P31DDR bit.
RE
0
P31DDR
Pin function
Note:
*
1
0
1

P31 input pin
P31 output pin*
RxD0 input pin
When P31ODR = 1, it becomes NMOS open drain output.
• P30/TxD0
The pin function is switched as shown below according to the combination of the TE bit in SCR of
SCI_0 and P30DDR bit.
TE
0
P30DDR
Pin function
Note:
*
1
0
1

P30 input pin
P30 output pin*
TxD0 output pin
When P30ODR = 1, it becomes NMOS open drain output.
Rev. 2.00 Dec. 05, 2005 Page 192 of 724
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Section 9 I/O Ports
9.4
Port 4
Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins.
Port 4 pin functions are the same in all operating modes.
• Port 4 Register (PORT4)
9.4.1
Port 4 Register (PORT4)
PORT4 is a read-only register that shows the pin states.
Bit
Bit Name
Initial
Value
R/W
Description
7
P47
*
R
6
P46
*
R
The pin states are always read when PORT4 read is
performed.
5
P45
*
R
4
P44
*
R
3
P43
*
R
2
P42
*
R
1
P41
*
R
0
P40
*
R
Note:
9.4.2
*
Determined by state of pins P47 to P40.
Pin Functions
Port 4 pins also function as A/D converter analog input pins.
Rev. 2.00 Dec. 05, 2005 Page 193 of 724
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Section 9 I/O Ports
9.5
Port 5
Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI I/O pins. The pin functions of port 5 are
the same in all operating modes.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
• Port 5 register (PORT5)
9.5.1
Port 5 Data Direction Register (P5DDR)
P5DDR is a register, the individual bits of which specify input or output for the pins in port 5.
P5DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
7 to 3

Undefined 
Reserved
2
P52DDR
0
W
1
P51DDR
0
W
0
P50DDR
0
W
Setting a P5DDR bit to 1 makes the corresponding port
5 pin an output pin, while clearing the bit to 0 makes the
pin an input pin.
9.5.2
Port 5 Data Register (P5DR)
R/W
Description
P5DR stores output data for the port 5 pins.
Bit
Bit Name
Initial
Value
7 to 3

Undefined 
Reserved
2
P52DR
0
R/W
1
P51DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
0
P50DR
0
R/W
R/W
Rev. 2.00 Dec. 05, 2005 Page 194 of 724
REJ09B0200-0200
Description
Section 9 I/O Ports
9.5.3
Port 5 Register (PORT5)
PORT5 shows the pin states. It cannot be modified.
Initial
Value
Bit
Bit Name
7 to 3

Undefined 
Reserved
2
P52
*
R
1
P51
*
R
0
P50
*
R
If this register read is performed while P5DDR bits are
set to 1, the P5DR values are read. If this register read
is performed while P5DDR bits are cleared to 0, the pin
states are read.
Note:
*
9.5.4
R/W
Description
Determined by state of pins P52 to P50.
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
• P52/SCK2
The pin function is switched as shown below according to a combination of the C/A bit in SMR
and bits CKE0 and CKE1 in SCR of SCI_2, and the P52DDR bit.
CKE1
0
C/A
Pin function
1

1


0
CK0
P52DDR
1
0
0
1



P52 input pin
P52 output pin
SCK2 output
pin
SCK2 output
pin
SCK2 input pin
• P51/RxD2
The pin function is switched as shown below according to a combination of the RE bit in SCR of
SCI_2 and the P51DDR bit.
RE
P51DDR
Pin function
0
1
0
1

P51 input pin
P51 output pin
RxD2 input pin
Rev. 2.00 Dec. 05, 2005 Page 195 of 724
REJ09B0200-0200
Section 9 I/O Ports
• P50/TxD2
The pin function is switched as shown below according to a combination of the TE bit in SCR of
SCI_2 and the P50DDR bit.
TE
0
0
1

P50 input pin
P50 output pin
TxD2 output pin
P50DDR
Pin function
9.6
1
Port 9
Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins.
Port 9 pin functions are the same in all operating modes.
• Port 9 Register (PORT9)
9.6.1
Port 9 Register (PORT9)
PORT9 is a read-only register that shows the pin states.
Bit
Bit Name
Initial
Value
R/W
Description
7
P97
*
R
6
P96
*
R
The pin states are always read when PORT9 read is
performed.
5
P95
*
R
4
P94
*
R
3
P93
*
R
2
P92
*
R
1
P91
*
R
P90
*
R
0
Note:
9.6.2
*
Determined by state of pins P97 to P90.
Pin Functions
Port 9 pins also function as A/D converter analog input pins.
Rev. 2.00 Dec. 05, 2005 Page 196 of 724
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Section 9 I/O Ports
9.7
Port A
Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and LCD driver output
pins. The pin functions change according to the operating mode.
Port A has a built-in MOS input pull-up function that can be controlled by software.
•
•
•
•
•
Port A data direction register (PADDR)
Port A data register (PADR)
Port A register (PORTA)
Port A pull-up MOS control register (PAPCR)
Port A open-drain control register (PAODR)
9.7.1
Port A Data Direction Register (PADDR)
PADDR is a register, the individual bits of which specify input or output for the pins of port A.
PADDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PA7DDR
0
W
Mode 7:
6
PA6DDR
0
W
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
2
PA2DDR
0
W
These function as segment pins if the values of bits
SGS in LPCR are other than B'0000. If the values of
bits SGS are B'0000, setting a PADDR bit to 1 makes
the corresponding port A pin an output port, and
clearing a bit to 0 makes the corresponding pin an input
port.
1
PA1DDR
0
W
0
PA0DDR
0
W
Modes 4 to 6:
These function as segment pins if the values of bits
SGS in LPCR, the LCD driver, are other than B'0000. If
the values of bits SGS are B'0000, the port A pins
function as address outputs as specified by the setting
of bits AE3 to AE0 of PFCR, regardless of the values of
bits PA7DDR to PA0DDR. Also, when the pins are not
used as address outputs, setting a PADDR bit to 1
makes the corresponding port A pin an output port, and
clearing a bit to 0 makes the corresponding pin an input
port.
Rev. 2.00 Dec. 05, 2005 Page 197 of 724
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Section 9 I/O Ports
9.7.2
Port A Data Register (PADR)
PADR stores output data for the port A pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
PA7DR
0
R/W
6
PA6DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
5
PA5DR
0
R/W
4
PA4DR
0
R/W
3
PA3DR
0
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
9.7.3
Port A Register (PORTA)
PORTA shows the pin states. It cannot be modified.
Bit
Bit Name
Initial
Value
R/W
Description
7
PA7
*
R
6
PA6
*
R
5
PA5
*
R
If this register read is performed while PADDR bits are
set to 1, the PADR values are read. If this register read
is performed while PADDR bits are cleared to 0, the pin
states are read.
4
PA4
*
R
3
PA3
*
R
2
PA2
*
R
1
PA1
*
R
PA0
*
R
0
Note:
*
Determined by state of pins PA7 to PA0.
Rev. 2.00 Dec. 05, 2005 Page 198 of 724
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Section 9 I/O Ports
9.7.4
Port A Pull-Up MOS Control Register (PAPCR)
PAPCR controls the MOS input pull-up function incorporated into port A on an individual bit
basis.
Bit
Bit Name
Initial
Value
R/W
Description
7
PA7PCR
0
R/W
6
PA6PCR
0
R/W
5
PA5PCR
0
R/W
In modes 4 to 6, if a pin is in the input state in
accordance with the settings in PFCR, in LPCR, and in
DDR, setting the corresponding PAPCR bit to 1 turns
on the MOS input pull-up for that pin.
4
PA4PCR
0
R/W
3
PA3PCR
0
R/W
2
PA2PCR
0
R/W
1
PA1PCR
0
R/W
0
PA0PCR
0
R/W
9.7.5
Port A Open-Drain Control Register (PAODR)
In mode 7, if a pin is in the input state in accordance
with the settings in LPCR and DDR, setting the
corresponding PAPCR bit to 1 turns on the MOS input
pull-up for that pin.
PAODR controls output of port A.
Bit
Bit Name
Initial
Value
R/W
Description
7
PA7ODR
0
R/W
6
PA6ODR
0
R/W
5
PA5ODR
0
R/W
4
PA4ODR
0
R/W
When pins are not address and LCD outputs in
accordance with the setting of bits AE3 to AE0 in
PFCR, setting a PAODR bit makes the corresponding
port A pin an NMOS open-drain output, while clearing
the bit to 0 makes the pin a CMOS output.
3
PA3ODR
0
R/W
2
PA2ODR
0
R/W
1
PA1ODR
0
R/W
0
PA0ODR
0
R/W
Rev. 2.00 Dec. 05, 2005 Page 199 of 724
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Section 9 I/O Ports
9.7.6
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
• PA7/A23/SEG40 to PA4/A20/SEG37
The pin function is switched as shown below according to the combinations of bits SGS3 to SGS0
of LCD driver LPCR, bits AE3 to AE0 in PFGR, and bits PA7DDR to PA4DDR in PADDR.
Setting of
SGS3 to
SGS0
Port
Operating
mode
Modes 4 to 6
Setting of
AE3 to AE0
Address
output
enabled
Mode 7
—
—
—
Address output disabled

0
1
0
1
—
A23 to A20
output
PA7 to PA4
input
PA7 to PA4
output
PA7 to PA4
input
PA7 to PA4
output
SEG40 to
SEG37
output
PAnDDR
Pin function
SEG output
(n = 7 to 4)
• PA3/A19/COM4 to PA0/A16/COM1
The pin function is switched as shown below according to the combinations of bits SGS3 to SGS0
in LPCR of LCD driver, bits AE3 to AE0 in PFCR, and bits PA3DDR to PA0DDR of PADDR.
Setting of
SGS3 to
SGS0
B'0000
Operating
mode
Modes 4 to 6
Setting of
AE3 to AE0
Address
output
enabled
Mode 7



Address output disabled

0
1
0
1

A19 to A16
output
PA3 to PA0
input
PA3 to PA0
output
PA3 to PA0
input
PA3 to PA0
output
COM1 to
COM4
output
PAnDDR
Pin function
Other than
B'0000
(n = 3 to 0)
Rev. 2.00 Dec. 05, 2005 Page 200 of 724
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Section 9 I/O Ports
9.7.7
MOS Input Pull-Up Function
Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input
pull-up can be specified as on or off on an individual bit basis.
Table 9.2 shows the MOS input pull-up states.
Table 9.2
MOS Input Pull-Up States (Port A)
Pin States
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
Address output or
SCI output
OFF
OFF
OFF
OFF
ON/OFF
ON/OFF
Other than above
[Legend]
OFF:
ON/OFF:
MOS input pull-up is always off.
On when PADDR = 0 and PAODR = 1; otherwise off.
Rev. 2.00 Dec. 05, 2005 Page 201 of 724
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Section 9 I/O Ports
9.8
Port B
Port B is an 8-bit I/O port. Port B also functions as LCD driver output pins and as address bus
outputs. The pin functions are determined by the operating mode.
Port B has a built-in MOS input pull-up function that can be controlled by software.
•
•
•
•
•
Port B data direction register (PBDDR)
Port B data register (PBDR)
Port B register (PORTB)
Port B pull-up MOS control register (PBPCR)
Port B open-drain control register (PBODR)
9.8.1
Port B Data Direction Register (PBDDR)
PBDDR is a write-only register, the individual bits of which specify input or output for the pins of
port B. PBDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PB7DDR
0
W
6
PB6DDR
0
W
5
PB5DDR
0
W
Setting a PBDDR bit to 1 makes the corresponding
port B pin an output pin, while clearing the bit to 0
makes the pin an input pin.
4
PB4DDR
0
W
3
PB3DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
0
PB0DDR
0
W
Rev. 2.00 Dec. 05, 2005 Page 202 of 724
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Section 9 I/O Ports
9.8.2
Port B Data Register (PBDR)
PBDR stores output data for the port B pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
PB7DR
0
R/W
6
PB6DR
0
R/W
An output data for a pin is stored when the pin
function is specified to a general purpose output port.
5
PB5DR
0
R/W
4
PB4DR
0
R/W
3
PB3DR
0
R/W
2
PB2DR
0
R/W
1
PB1DR
0
R/W
0
PB0DR
0
R/W
9.8.3
Port B Register (PORTB)
PORTB shows the pin states. It cannot be modified.
Bit
Bit Name
Initial
Value
R/W
Description
7
PB7
*
R
6
PB6
*
R
5
PB5
*
R
If this register read is performed while PBDDR bits are
set to 1, the PBDR values are read. If this register read
is performed while PBDDR bits are cleared to 0, the pin
states are read.
4
PB4
*
R
3
PB3
*
R
2
PB2
*
R
1
PB1
*
R
0
PB0
*
R
Note:
*
Reading a pin being used as an LCD driver returns an
undefined value.
Determined by state of pins PB7 to PB0.
Rev. 2.00 Dec. 05, 2005 Page 203 of 724
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Section 9 I/O Ports
9.8.4
Port B Pull-Up MOS Control Register (PBPCR)
PBPCR controls the MOS input pull-up function incorporated into port B on an individual bit
basis.
Bit
Bit Name
Initial
Value
R/W
Description
7
PB7PCR
0
R/W
6
PB6PCR
0
R/W
5
PB5PCR
0
R/W
In modes 4 to 6, if a pin is in the input state in
accordance with the settings in the LCD driver’s LPCR
and in DDR, setting the corresponding PBPCR bit to 1
turns on the MOS input pull-up for that pin.
4
PB4PCR
0
R/W
3
PB3PCR
0
R/W
2
PB2PCR
0
R/W
1
PB1PCR
0
R/W
0
PB0PCR
0
R/W
9.8.5
Port B Open-Drain Control Register (PBODR)
In mode 7, if a pin is in the input state in accordance
with the settings in the LCD driver’s LPCR and in DDR,
setting the corresponding PBPCR bit to 1 turns on the
MOS input pull-up for that pin.
PBODR controls output of port B.
Bit
Bit Name
Initial
Value
R/W
Description
7
PB7ODR
0
R/W
6
PB6ODR
0
R/W
5
PB5ODR
0
R/W
4
PB4ODR
0
R/W
3
PB3ODR
0
R/W
When pins are not address and LCD outputs in
accordance with the setting of bits AE3 to AE0 in
PFCR, setting a PBODR bit makes the corresponding
port A pin an NMOS open-drain output, while clearing
the bit to 0 makes the pin a CMOS output. Do not set
this register to 1 when the pins are used as the LCD
driver pins.
2
PB2ODR
0
R/W
1
PB1ODR
0
R/W
0
PB0ODR
0
R/W
Rev. 2.00 Dec. 05, 2005 Page 204 of 724
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Section 9 I/O Ports
9.8.6
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
Setting of
SGS3 to
SGS0
Port
Operating
mode
Modes 4 to 6
Setting of
AE3 to AE0
Address
output
enabled
Pin function
Mode 7



Address output disabled

0
1
0
1

A15 to A8
output
PB7 to PB0
input
PB7 to PB0
output
PB7 to PB0
input
PB7 to PB0
output
SEG32 to
SEG25
output
PBDDR
9.8.7
SEG
output
MOS Input Pull-Up Function
Port B has a built-in MOS input pull-up function that can be controlled by software.
Table 9.3 shows the MOS input pull-up states.
Table 9.3
MOS Input Pull-Up States (Port B)
Pin States
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
Address output or
LCD output
OFF
OFF
OFF
OFF
ON/OFF
ON/OFF
Other than above
[Legend]
OFF:
ON/OFF:
MOS input pull-up is always off.
On when PBDDR = 0 and PBPCR = 1; otherwise off.
Rev. 2.00 Dec. 05, 2005 Page 205 of 724
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Section 9 I/O Ports
9.9
Port C
Port C is an 8-bit I/O port. Port C also functions as LCD driver output pins and as address bus
outputs. The pin functions are determined by the operating mode.
Port C has a built-in MOS input pull-up function that can be controlled by software.
•
•
•
•
•
Port C data direction register (PCDDR)
Port C data register (PCDR)
Port C register (PORTC)
Port C pull-up MOS control register (PCPCR)
Port C open-drain control register (PCODR)
9.9.1
Port C Data Direction Register (PCDDR)
PCDDR is a write-only register, the individual bits of which specify input or output for the pins of
port C. PCDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PC7DDR
0
W
6
PC6DDR
0
W
5
PC5DDR
0
W
Setting a PCDDR bit to 1 makes the corresponding port
C pin an output pin, while clearing the bit to 0 makes
the pin an input pin.
4
PC4DDR
0
W
3
PC3DDR
0
W
2
PC2DDR
0
W
1
PC1DDR
0
W
0
PC0DDR
0
W
Rev. 2.00 Dec. 05, 2005 Page 206 of 724
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Section 9 I/O Ports
9.9.2
Port C Data Register (PCDR)
PCDR stores output data for the port C pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
PC7DR
0
R/W
6
PC6DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
5
PC5DR
0
R/W
4
PC4DR
0
R/W
3
PC3DR
0
R/W
2
PC2DR
0
R/W
1
PC1DR
0
R/W
0
PC0DR
0
R/W
9.9.3
Port C Register (PORTC)
PORTC shows the pin states. It cannot be modified.
Bit
Bit Name
Initial
Value
R/W
Description
7
PC7
*
R
6
PC6
*
R
5
PC5
*
R
If this register read is performed while PCDDR bits are
set to 1, the PCDR values are read. If this register read
is performed while PCDDR bits are cleared to 0, the pin
states are read.
4
PC4
*
R
3
PC3
*
R
2
PC2
*
R
1
PC1
*
R
0
PC0
*
R
Note:
*
Reading a pin being used as an LCD driver returns an
undefined value.
Determined by state of pins PC7 to PC0.
Rev. 2.00 Dec. 05, 2005 Page 207 of 724
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Section 9 I/O Ports
9.9.4
Port C Pull-Up MOS Control Register (PCPCR)
PCPCR controls the MOS input pull-up function incorporated into port C on an individual bit
basis.
Bit
Bit Name
Initial
Value
R/W
Description
7
PC7PCR
0
R/W
6
PC6PCR
0
R/W
5
PC5PCR
0
R/W
In modes 6 and 7, if PCPCR is set to 1 when the port is
in the input state in accordance with the settings of the
LCD driver LPCR and PCDDR, the MOS input pull-up is
set to ON.
4
PC4PCR
0
R/W
3
PC3PCR
0
R/W
2
PC2PCR
0
R/W
1
PC1PCR
0
R/W
0
PC0PCR
0
R/W
9.9.5
Port C Open-Drain Control Register (PCODR)
PCODR controls output of port C.
Bit
Bit Name
Initial
Value
R/W
Description
7
PC7ODR
0
R/W
6
PC6ODR
0
R/W
5
PC5ODR
0
R/W
4
PC4ODR
0
R/W
If PCODR is set to 1 by setting AE3 to AE0 in PFCR in
mode other than address output mode, port C pins
function as NMOS open drain outputs and when the
setting is cleared to 0, the pins function as CMOS
outputs.
3
PC3ODR
0
R/W
2
PC2ODR
0
R/W
1
PC1ODR
0
R/W
0
PC0ODR
0
R/W
Rev. 2.00 Dec. 05, 2005 Page 208 of 724
REJ09B0200-0200
Do not set PCODR to 1 if the pins are being used for
LCD driver output.
Section 9 I/O Ports
9.9.6
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
Setting of
SGS3 to
SGS0
Port
Operating
mode
Modes
4 and 5
Mode 6

Mode 7


0
1
A7 to A0
output
A7 to A0
output
PC7 to
PC0 input
A7 to A0
output
PCDDR
Pin function
SEG
output
0
1

PC7 to
PC7 to SEG24 to
PC0 input PC0 output SEG17
output
Note: Modes 4 and 5 are extended modes in which the internal ROM is disabled. Address output
is disabled when port C is set to segment output, so it is not possible to interface with
external ROM. Therefore port C must not be set to segment output in mode 4 or mode 5.
9.9.7
MOS Input Pull-Up Function
Port C has a built-in MOS input pull-up function that can be controlled by software.
Table 9.4 shows the MOS input pull-up states.
Table 9.4
MOS Input Pull-Up States (Port C)
Pin States
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
Address output
OFF
OFF
OFF
OFF
ON/OFF
ON/OFF
Other than above
[Legend]
OFF:
ON/OFF:
MOS input pull-up is always off.
On when PCDDR = 0 and PCPCR = 1; otherwise off.
Rev. 2.00 Dec. 05, 2005 Page 209 of 724
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Section 9 I/O Ports
9.10
Port D
Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change
according to the operating mode.
Port D has a built-in MOS input pull-up function that can be controlled by software.
•
•
•
•
Port D data direction register (PDDDR)
Port D data register (PDDR)
Port D register (PORTD)
Port D pull-up MOS control register (PDPCR)
9.10.1
Port D Data Direction Register (PDDDR)
PDDDR is a write-only register, the individual bits of which specify input or output for the pins of
port D. PDDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PD7DDR
0
W
6
PD6DDR
0
W
5
PD5DDR
0
W
Setting a PDDDR bit to 1 makes the corresponding port
D pin an output pin, while clearing the bit to 0 makes
the pin an input pin.
4
PD4DDR
0
W
3
PD3DDR
0
W
2
PD2DDR
0
W
1
PD1DDR
0
W
0
PD0DDR
0
W
Rev. 2.00 Dec. 05, 2005 Page 210 of 724
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Section 9 I/O Ports
9.10.2
Port D Data Register (PDDR)
PDDR stores output data for the port D pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
PD7DR
0
R/W
6
PD6DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
5
PD5DR
0
R/W
4
PD4DR
0
R/W
3
PD3DR
0
R/W
2
PD2DR
0
R/W
1
PD1DR
0
R/W
0
PD0DR
0
R/W
9.10.3
Port D Register (PORTD)
PORTD shows the pin states. It cannot be modified.
Bit
Bit Name
Initial
Value
R/W
Description
7
PD7
*
R
6
PD6
*
R
5
PD5
*
R
If this register read is performed while PDDDR bits are
set to 1, the PDDR values are read. If this register read
is performed while PDDDR bits are cleared to 0, the pin
states are read.
4
PD4
*
R
3
PD3
*
R
2
PD2
*
R
1
PD1
*
R
0
PD0
*
R
Note:
*
Reading a pin being used as an LCD driver returns an
undefined value.
Determined by state of pins PD7 to PD0.
Rev. 2.00 Dec. 05, 2005 Page 211 of 724
REJ09B0200-0200
Section 9 I/O Ports
9.10.4
Port D Pull-Up MOS Control Register (PDPCR)
PDPCR controls the MOS input pull-up function incorporated into port D on an individual bit
basis.
Bit
Bit Name
Initial
Value
R/W
Description
7
PD7PCR
0
R/W
6
PD6PCR
0
R/W
5
PD5PCR
0
R/W
In mode 7, if a pin is in the input state in accordance
with the settings in PDDDR and LPCR, setting the
corresponding PDPCR bit to 1 turns on the MOS input
pull-up for that pin.
4
PD4PCR
0
R/W
3
PD3PCR
0
R/W
2
PD2PCR
0
R/W
1
PD1PCR
0
R/W
0
PD0PCR
0
R/W
9.10.5
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
Setting of SGS3 to
SGS0
Operating mode
PEDDR
Pin function
Port
Mode 4 to 6
SEG output

Mode 7

0
D15 to D12 I/O
PD7 to PD4 input
1

PD7 to PD4 output SEG16 to SEG9
output
Note: Modes 4 and 5 are expanded modes with on-chip ROM disabled.
If segment output is selected, data input/output and interfacing to external ROM are no
longer possible. Therefore segment output settings should not be made in these modes.
Rev. 2.00 Dec. 05, 2005 Page 212 of 724
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Section 9 I/O Ports
9.10.6
MOS Input Pull-Up Function
Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit
basis.
Table 9.5 shows the MOS input pull-up states.
Table 9.5
MOS Input Pull-Up States (Port D)
Pin States
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
4 to 6
OFF
OFF
OFF
OFF
ON/OFF
ON/OFF
7
[Legend]
OFF:
ON/OFF:
MOS input pull-up is always off.
On when PDDDR = 0, PDPCR = 1, and the pin is not used as a segment driver;
otherwise off.
Rev. 2.00 Dec. 05, 2005 Page 213 of 724
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Section 9 I/O Ports
9.11
Port E
Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change
according to the operating mode and whether 8-bit or 16-bit bus mode is selected.
Port E has a built-in MOS input pull-up function that can be controlled by software.
•
•
•
•
Port E data direction register (PEDDR)
Port E data register (PEDR)
Port E register (PORTE)
Port E pull-up MOS control register (PEPCR)
9.11.1
Port E Data Direction Register (PEDDR)
PEDDR is a write-only register, the individual bits of which specify input or output for the pins of
port E. PEDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PE7DDR
0
W
6
PE6DDR
0
W
5
PE5DDR
0
W
Setting a PEDDR bit to 1 makes the corresponding port
E pin an output pin, while clearing the bit to 0 makes the
pin an input pin.
4
PE4DDR
0
W
3
PE3DDR
0
W
2
PE2DDR
0
W
1
PE1DDR
0
W
0
PE0DDR
0
W
Rev. 2.00 Dec. 05, 2005 Page 214 of 724
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Section 9 I/O Ports
9.11.2
Port E Data Register (PEDR)
PEDR stores output data for the port E pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
PE7DR
0
R/W
6
PE6DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
5
PE5DR
0
R/W
4
PE4DR
0
R/W
3
PE3DR
0
R/W
2
PE2DR
0
R/W
1
PE1DR
0
R/W
0
PE0DR
0
R/W
9.11.3
Port E Register (PORTE)
PORTE shows the pin states. It cannot be modified.
Bit
Bit Name
Initial
Value
R/W
Description
7
PE7
*
R
6
PE6
*
R
5
PE5
*
R
If this register read is performed while PEDDR bits are
set to 1, the PEDR values are read. If this register read
is performed while PEDDR bits are cleared to 0, the pin
states are read.
4
PE4
*
R
3
PE3
*
R
2
PE2
*
R
1
PE1
*
R
0
PE0
*
R
Note:
*
Determined by state of pins PE7 to PE0.
Rev. 2.00 Dec. 05, 2005 Page 215 of 724
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Section 9 I/O Ports
9.11.4
Port E Pull-Up MOS Control Register (PEPCR)
PEPCR controls the MOS input pull-up function incorporated into port E on an individual bit
basis.
Bit
Bit Name
Initial
Value
R/W
Description
7
PE7PCR
0
R/W
6
PE6PCR
0
R/W
5
PE5PCR
0
R/W
4
PE4PCR
0
R/W
In modes 4 to 6 with 8-bit-bus mode selected, or in
mode 7, if a pin is in the input state in accordance with
the settings in PEDDR and PEDDR, setting the
corresponding PEPCR bit to 1 turns on the MOS input
pull-up for that pin.
3
PE3PCR
0
R/W
2
PE2PCR
0
R/W
1
PE1PCR
0
R/W
0
PE0PCR
0
R/W
9.11.5
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
Setting of
SEG3 to
SEG0
Port
Operating
mode
Bus width
setting
Modes 4 to 6
16-bit mode
PEDDR
Pin function
SEG
output
Mode 7
—
—
—
8-bit mode
—
0
1
0
1
—
D7 to D0 I/O
PE7 to PE0
input
PE7 to PE0
output
PE7 to PE0
input
PE7 to PE0
output
SEG8 to
SEG1
output
Rev. 2.00 Dec. 05, 2005 Page 216 of 724
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Section 9 I/O Ports
9.11.6
MOS Input Pull-Up Function
Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit
basis.
Table 9.6 shows the MOS input pull-up states.
Table 9.6
MOS Input Pull-Up States (Port E)
Pin States
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
7
OFF
OFF
ON/OFF
ON/OFF
OFF
OFF
4 to 6
8-bit bus
16-bit bus
[Legend]
OFF:
ON/OFF:
MOS input pull-up is always off.
On when PEDDR = 0, PEPCR = 1, and the pin is not used as a segment driver;
otherwise off.
Rev. 2.00 Dec. 05, 2005 Page 217 of 724
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Section 9 I/O Ports
9.12
Port F
Port F is a 7-bit I/O port. Port F also functions as LCD driver output pins, external interrupt input
pins, the A/D trigger input pin, bus control signal I/O pins, and as the system clock output pin.
• Port F data direction register (PFDDR)
• Port F data register (PFDR)
• Port F register (PORTF)
9.12.1
Port F Data Direction Register (PFDDR)
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PF7DDR
1*
W
Setting a PFDDR bit to 1 makes the PF7 pin a φ output
pin, while clearing the bit to 0 makes the pin an input
pin.
6
PF6DDR
0
W
5
PF5DDR
0
W
4
PF4DDR
0
W
Setting a PFDDR bit to 1 makes the corresponding port
F pin an output port, while clearing the bit to 0 makes
the pin an input port.
3
PF3DDR
0
W
2
PF2DDR
0
W
1

Undefined 
Reserved
0
PF0DDR
0
Setting a PFDDR bit to 1 makes the corresponding port
F pin an output port, while clearing the bit to 0 makes
the pin an input port.
Note:
*
W
The initial value is 0 in mode 7.
Rev. 2.00 Dec. 05, 2005 Page 218 of 724
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Section 9 I/O Ports
9.12.2
Port F Data Register (PFDR)
PFDR stores output data for the port F pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
PF7DR
0
R/W
6
PF6DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
2
PF2DR
0
R/W
1

Undefined 
Reserved
0
PF0DR
0
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
9.12.3
Port F Register (PORTF)
R/W
PORTF shows the pin states. It cannot be modified.
Bit
Bit Name
Initial
Value
R/W
Description
7
PF7
*
R
6
PF6
*
R
5
PF5
*
R
If this register read is performed while PFDDR bits are
set to 1, the PFDR values are read. If this register read
is performed while PFDDR bits are cleared to 0, the pin
states are read.
4
PF4
*
R
3
PF3
*
R
2
PF2
*
R
1

Undefined 
0
PF0
*
Note:
*
Reading a pin being used as an LCD driver returns an
undefined value.
Reserved
R
Determined by state of pins PF7 to PF2, and PF0.
Rev. 2.00 Dec. 05, 2005 Page 219 of 724
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Section 9 I/O Ports
9.12.4
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
• PF7/φ
The pin function is switched as shown below according to bit PF7DDR.
PF7DDR
Pin function
0
1
PF7 input pin
φ output pin
• PF6/AS/SEG36
The pin function is switched as shown below according to the operating mode and the setting of
SGS3 to SGS0 bits in LPCR and PF6DDR bit.
Operating
Mode
Setting of
SGS3 to SGS0
PF6DDR
Pin function
Modes 4 to 6
Mode 7
SEG output
Port
SEG output
Port



0
1
SEG36 output
AS output
SEG36 output
PF6 input
PF6 output
• PF5/RD/SEG35
The pin function is switched as shown below according to the operating mode and the setting of
SGS3 to SGS0 bits in LPCR and PF5DDR bit.
Operating
Mode
Setting of
SGS3 to SGS0
PF5DDR
Pin function
Modes 4 to 6
SEG output
Port
SEG output



0
1
SEG35 output
RD output
SEG35 output
PF5 input
PF5 output
Rev. 2.00 Dec. 05, 2005 Page 220 of 724
REJ09B0200-0200
Mode 7
Port
Section 9 I/O Ports
• PF4/HWR/SEG34
The pin function is switched as shown below according to the operating mode and the setting of
SGS3 to SGS0 bits in LPCR and PF4DDR bit.
Operating
Mode
Setting of
SGS3 to SGS0
PF4DDR
Pin function
Modes 4 to 6
Mode 7
SEG output
Port
SEG output
Port



0
1
SEG34 output
HWR output
SEG34 output
PF4 input
PF4 output
• PF3/LWR/ADTRG/IRQ3
The pin function is switched as shown below according to the operating mode and the setting of
bits TRGS1 and TRGS0 bits in ADCR and PF3DDR bit.
Operating
Mode
Modes 4 to 6
Mode 7
Bus Mode
16
PF3DDR

0
1
0
1
LWR output pin
PF3
input pin
PF3
output pin
PF3 input pin
PF3 output pin
Pin function
8
ADTRG input pin*1
IRQ3 input pin*2
Note:
1. ADTRG input when TRGS0=TRGS1=1.
2. Do not use this pin for other functions when this pin is used as an external interrupt pin.
Rev. 2.00 Dec. 05, 2005 Page 221 of 724
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Section 9 I/O Ports
• PF2/WAIT/SEG33
The pin function is switched as shown below according to the operating mode, and the setting of
SGS3 to SGS0 bits and WAITE bit in LPCR, and PF2DDR bit.
Operating
Mode
Setting of
SGS3 to
SGS0
Modes 4 to 6
SEG output
Port
WAITE

PF2DDR

0
SEG33
output
PF2 input
Pin function
Mode 7
0
1
SEG
output
Port
1



0
PF2 output WAIT input
SEG33
output

1
PF2 input PF2 output
• PF0/IRQ2
The pin function is switched as shown below according to the PF0DDR bit.
PF0DDR
Pin function
0
1
PF0 input
PF0 output
IRQ2 input
Rev. 2.00 Dec. 05, 2005 Page 222 of 724
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Section 9 I/O Ports
9.13
Port H
Port H is an 8-bit I/O port. Port H pins also function as motor control PWM timer output pins.
• Port H data direction register (PHDDR)
• Port H data register (PHDR)
• Port H register (PORTH)
9.13.1
Port H Data Direction Register (PHDDR)
PHDDR is a write-only register, the individual bits of which specify input or output for the pins of
port H. PHDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PH7DDR
0
W
6
PH6DDR
0
W
5
PH5DDR
0
W
Setting a PHDDR bit to 1 makes the corresponding port
H pin an output pin, while clearing the bit to 0 makes
the pin an input pin.
4
PH4DDR
0
W
3
PH3DDR
0
W
2
PH2DDR
0
W
1
PH1DDR
0
W
0
PH0DDR
0
W
Rev. 2.00 Dec. 05, 2005 Page 223 of 724
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Section 9 I/O Ports
9.13.2
Port H Data Register (PHDR)
PHDR stores output data for the port H pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
PH7DR
0
R/W
6
PH6DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
5
PH5DR
0
R/W
4
PH4DR
0
R/W
3
PH3DR
0
R/W
2
PH2DR
0
R/W
1
PH1DR
0
R/W
0
PH0DR
0
R/W
9.13.3
Port H Register (PORTH)
PORTH shows the pin states. It cannot be modified.
If a port H read is performed while PHDDR bits are set to 1, the PHDR values are read. If a port H
read is performed while PHDDR bits are cleared to 0, the pin states are read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PH7
*
R
6
PH6
*
R
5
PH5
*
R
If this register read is performed while PHDDR bits are
set to 1, the PHDR values are read. If this register read
is performed while PHDDR bits are cleared to 0, the pin
states are read.
4
PH4
*
R
3
PH3
*
R
2
PH2
*
R
1
PH1
*
R
0
PH0
*
R
Note:
*
Determined by state of pins PH7 to PH0.
Rev. 2.00 Dec. 05, 2005 Page 224 of 724
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Section 9 I/O Ports
9.13.4
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
OE1A to OE1H
1
PHDDR

0
1
Motor control PWM
timer output
PH7 to PH0 input
PH7 to PH0 output
Pin function
9.14
0
Port J
Port J is an 8-bit I/O port. Port J pins also function as motor control PWM timer output pins.
• Port J data direction register (PJDDR)
• Port J data register (PJDR)
• Port J register (PORTJ)
9.14.1
Port J Data Direction Register (PJDDR)
PJDDR is a write-only register, the individual bits of which specify input or output for the pins of
port J. PJDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PJ7DDR
0
W
6
PJ6DDR
0
W
5
PJ5DDR
0
W
Setting a PJDDR bit to 1 makes the corresponding port
J pin an output pin, while clearing the bit to 0 makes the
pin an input pin.
4
PJ4DDR
0
W
3
PJ3DDR
0
W
2
PJ2DDR
0
W
1
PJ1DDR
0
W
0
PJ0DDR
0
W
Rev. 2.00 Dec. 05, 2005 Page 225 of 724
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Section 9 I/O Ports
9.14.2
Port J Data Register (PJDR)
PJDR stores output data for the port J pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
PJ7DR
0
R/W
6
PJ6DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
5
PJ5DR
0
R/W
4
PJ4DR
0
R/W
3
PJ3DR
0
R/W
2
PJ2DR
0
R/W
1
PJ1DR
0
R/W
0
PJ0DR
0
R/W
9.14.3
Port J Register (PORTJ)
PORTJ shows the pin states. It cannot be modified.
Writing of output data for the port J pins must always be performed on PJDR.
Bit
Bit Name
Initial
Value
R/W
Description
7
PJ7
*
R
6
PJ6
*
R
5
PJ5
*
R
If this register read is performed while PJDDR bits are
set to 1, the PJDR values are read. If this register read
is performed while PJDDR bits are cleared to 0, the pin
states are read.
4
PJ4
*
R
3
PJ3
*
R
2
PJ2
*
R
1
PJ1
*
R
0
PJ0
*
R
Note:
*
Determined by state of pins PJ7 to PJ0.
Rev. 2.00 Dec. 05, 2005 Page 226 of 724
REJ09B0200-0200
Section 9 I/O Ports
9.14.4
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
OE2A to OE2H
1
PJDDR

0
1
Motor control PWM
timer output
PJ7 to PJ0 input
PJ7 to PH0 output
Pin function
9.15
0
Port K
Port K is a 2-bit I/O port. Port K pins also function as HCAN pins.
• Port K data direction register (PKDDR)
• Port K data register (PKDR)
• Port K register (PORTK)
9.15.1
Port K Data Direction Register (PKDDR)
PKDDR is a write-only register, the individual bits of which specify input or output for the pins of
port K. PKDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PK7DDR
0
W
6
PK6DDR
0
W
Setting a PKDDR bit to 1 makes the corresponding port
K pin an output pin, while clearing the bit to 0 makes the
pin an input pin.
5 to 0

Undefined 
Reserved
Rev. 2.00 Dec. 05, 2005 Page 227 of 724
REJ09B0200-0200
Section 9 I/O Ports
9.15.2
Port K Data Register (PKDR)
PKDR stores output data for the port K pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
PK7DR
0
R/W
6
PK6DR
0
R/W
An output data for a pin is stored when the pin function
is specified to a general purpose output port.
5 to 0

Undefined 
9.15.3
Port K Register (PORTK)
Reserved
PORTK shows the pin states. It cannot be modified.
Bit
Bit Name
Initial
Value
R/W
Description
7
PK7
*
R
6
PK6
*
R
If this register read is performed while PKDDR bits are
set to 1, the PKDR values are read. If this register read
is performed while PKDDR bits are cleared to 0, the pin
states are read.
5 to 0

Undefined 
Note:
*
9.15.4
Reserved
Determined by state of pins PK7 and PK6.
Pin Functions
The correspondence between the register specification and the pin functions is shown below.
PKFE*
1
0
PKDDR

0
1
HRxD1, HTxD1
PK7 and PK6 input
PK7 and PK6 output
Pin Function
Note:
*
The PKFE bit supports only HCAN_1.
Rev. 2.00 Dec. 05, 2005 Page 228 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Section 10 16-Bit Timer Pulse Unit (TPU)
This LSI has an on-chip 16-bit timer pulse unit (TPU) comprised of six 16-bit timer channels.
The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure
10.1, respectively.
10.1
Features
• Maximum 16-pulse input/output
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel:
 Waveform output at compare match
 Input capture function
 Counter clear operation
 Synchronous operation:
Multiple timer counters (TCNT) can be written to simultaneously
Simultaneous clearing by compare match and input capture is possible
Register simultaneous input/output is possible by synchronous counter operation
 A maximum 15-phase PWM output is possible in combination with synchronous operation
• Buffer operation settable for channels 0 and 3
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
• Cascaded operation
• Fast access via internal 16-bit bus
• 26 interrupt sources
• Automatic transfer of register data
• Programmable pulse generator (PPG) output trigger can be generated
• A/D converter conversion start trigger can be generated
• Module stop mode can be set
TIMTPU0A_000020020300
Rev. 2.00 Dec. 05, 2005 Page 229 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.1 TPU Functions
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
Count clock
φ/1
φ/4
φ/16
φ/64
TCLKA
TCLKB
TCLKC
TCLKD
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
TCLKA
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKC
TCLKD
General registers
(TGR)
TGRA_0
TGRB_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TGRA_5
TGRB_5
General registers/
buffer registers
TGRC_0
TGRD_0


TGRC_3
TGRD_3


I/O pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
Counter clear
function
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture


Compare 0 output
match
1 output
output
Toggle
output
Input capture
function
Synchronous
operation
PWM mode
Phase counting
mode
Buffer operation



Rev. 2.00 Dec. 05, 2005 Page 230 of 724
REJ09B0200-0200

Section 10 16-Bit Timer Pulse Unit (TPU)
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
DTC
TGR
activation compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
A/D
TGRA_0
converter compare
trigger
match or
input
capture
TGRA_1
compare
match or
input
capture
TGRA_2
compare
match or
input
capture
TGRA_3
compare
match or
input
capture
TGRA_4
compare
match or
input
capture
TGRA_5
compare
match or
input
capture
PPG
trigger
TGRA_1/
TGRB_1
compare
match or
input
capture
TGRA_2/
TGRB_2
compare
match or
input
capture
TGRA_3/
TGRB_3
compare
match or
input
capture


TGRA_0/
TGRB_0
compare
match or
input
capture
Rev. 2.00 Dec. 05, 2005 Page 231 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Interrupt
sources
5 sources
4 sources
4 sources
5 sources
4 sources
4 sources
•
Compare •
match or
input
capture
0A
Compare •
match or
input
capture
1A
Compare •
match or
input
capture
2A
Compare •
match or
input
capture
3A
Compare •
match or
input
capture
4A
Compare
match or
input
capture
5A
•
Compare •
match or
input
capture
0B
Compare •
match or
input
capture
1B
Compare •
match or
input
capture
2B
Compare •
match or
input
capture
3B
Compare •
match or
input
capture
4B
Compare
match or
input
capture
5B
•
Compare •
match or •
input
capture
0C
Overflow
•
Compare •
match or •
input
capture
3C
Overflow
•
Overflow
•
Underflow •
Overflow
Underflow
•
Compare
match or
input
capture
0D
•
Compare
match or
input
capture
3D
•
Overflow
•
Overflow
[Legend]
Possible
:
:
Not possible
Rev. 2.00 Dec. 05, 2005 Page 232 of 724
REJ09B0200-0200
Underflow •
Underflow
TGRD
TGRC
TGRB
TGRB
TGRB
TCNT
TGRA
TCNT
TGRA
TCNT
TGRA
Module data bus
Bus
interface
A/D converter conversion start signal
TGRB
TGRD
TGRB
TGRB
TGRC
TCNT
TGRA
TCNT
TCNT
PPG output trigger signal
TGRA
TSTR
TSR
TSR
TIER
TSR
TIER
Interrupt request signals
Channel 3: TGIA_3
TGIB_3
TGIC_3
TGID_3
TCIV_3
Channel 4: TGIA_4
TGIB_4
TCIV_4
TCIU_4
Channel 5: TGIA_5
TGIB_5
TCIV_5
TCIU_5
Internal data bus
TGRA
TSR
TIER
TSR
TSYR
TIER
TSR
TIER
TIOR
TIOR
TIOR
TIER
TMDR
TIORH TIORL
TCR
TMDR
Channel 4
TCR
TMDR
TCR
Channel 5
Common
Control logic
TMDR
Channel 2
TCR
TIOR
Channel 2:
TIORH TIORL
Channel 1:
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
Control logic for channel 0 to 2
Input/output pins
Channel 0:
TMDR
External clock:
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
TCLKA
TCLKB
TCLKC
TCLKD
Channel 1
Clock input
Internal clock:
TCR
Channel 5:
TMDR
Channel 4:
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
Channel 0
Channel 3:
Control logic for channels 3 to 5
Input/output pins
TCR
Channel 3
Section 10 16-Bit Timer Pulse Unit (TPU)
Interrupt request signals
Channel 3: TGIA_0
TGIB_0
TGIC_0
TGID_0
TCIV_0
Channel 4: TGIA_1
TGIB_1
TCIV_1
TCIU_1
Channel 5: TGIA_2
TGIB_2
TCIV_2
TCIU_2
[Legend]
TSTR:
TSYR:
TCR:
TMDR:
Timer start register
Timer synchro register
Timer control register
Timer mode register
TIOR (H, L):
TIER:
TSR:
TGR (A, B, C, D):
Timer I/O control registers (H, L)
Timer interrupt enable register
Timer status register
TImer general registers (A, B, C, D)
Figure 10.1 Block Diagram of TPU
Rev. 2.00 Dec. 05, 2005 Page 233 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
10.2
Input/Output Pins
Table 10.2 TPU Pins
Channel
Symbol
I/O
Function
All
TCLKA
Input
External clock A input pin
(Channel 1 and 5 phase counting mode A phase input)
TCLKB
Input
External clock B input pin
(Channel 1 and 5 phase counting mode B phase input)
TCLKC
Input
External clock C input pin
(Channel 2 and 4 phase counting mode A phase input)
TCLKD
Input
External clock D input pin
(Channel 2 and 4 phase counting mode B phase input)
TIOCA0
I/O
TGRA_0 input capture input/output compare output/PWM output pin
TIOCB0
I/O
TGRB_0 input capture input/output compare output/PWM output pin
TIOCC0
I/O
TGRC_0 input capture input/output compare output/PWM output pin
TIOCD0
I/O
TGRD_0 input capture input/output compare output/PWM output pin
TIOCA1
I/O
TGRA_1 input capture input/output compare output/PWM output pin
TIOCB1
I/O
TGRB_1 input capture input/output compare output/PWM output pin
0
1
2
3
4
5
TIOCA2
I/O
TGRA_2 input capture input/output compare output/PWM output pin
TIOCB2
I/O
TGRB_2 input capture input/output compare output/PWM output pin
TIOCA3
I/O
TGRA_3 input capture input/output compare output/PWM output pin
TIOCB3
I/O
TGRB_3 input capture input/output compare output/PWM output pin
TIOCC3
I/O
TGRC_3 input capture input/output compare output/PWM output pin
TIOCD3
I/O
TGRD_3 input capture input/output compare output/PWM output pin
TIOCA4
I/O
TGRA_4 input capture input/output compare output/PWM output pin
TIOCB4
I/O
TGRB_4 input capture input/output compare output/PWM output pin
TIOCA5
I/O
TGRA_5 input capture input/output compare output/PWM output pin
TIOCB5
I/O
TGRB_5 input capture input/output compare output/PWM output pin
Rev. 2.00 Dec. 05, 2005 Page 234 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3
Register Descriptions
The TPU has the following registers. To distinguish registers in each channel, an underscore and
the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as
TCR_0.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Timer control register_0 (TCR_0)
Timer mode register_0 (TMDR_0)
Timer I/O control register H_0 (TIORH_0)
Timer I/O control register L_0 (TIORL_0)
Timer interrupt enable register_0 (TIER_0)
Timer status register_0 (TSR_0)
Timer counter_0 (TCNT_0)
Timer general register A_0 (TGRA_0)
Timer general register B_0 (TGRB_0)
Timer general register C_0 (TGRC_0)
Timer general register D_0 (TGRD_0)
Timer control register_1 (TCR_1)
Timer mode register_1 (TMDR_1)
Timer I/O control register _1 (TIOR_1)
Timer interrupt enable register_1 (TIER_1)
Timer status register_1 (TSR_1)
Timer counter_1 (TCNT_1)
Timer general register A_1 (TGRA_1)
Timer general register B_1 (TGRB_1)
Timer control register_2 (TCR_2)
Timer mode register_2 (TMDR_2)
Timer I/O control register_2 (TIOR_2)
Timer interrupt enable register_2 (TIER_2)
Timer status register_2 (TSR_2)
Timer counter_2 (TCNT_2)
Timer general register A_2 (TGRA_2)
Timer general register B_2 (TGRB_2)
Timer control register_3 (TCR_3)
Timer mode register_3 (TMDR_3)
Rev. 2.00 Dec. 05, 2005 Page 235 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Timer I/O control register H_3 (TIORH_3)
Timer I/O control register L_3 (TIORL_3)
Timer interrupt enable register_3 (TIER_3)
Timer status register_3 (TSR_3)
Timer counter_3 (TCNT_3)
Timer general register A_3 (TGRA_3)
Timer general register B_3 (TGRB_3)
Timer general register C_3 (TGRC_3)
Timer general register D_3 (TGRD_3)
Timer control register_4 (TCR_4)
Timer mode register_4 (TMDR_4)
Timer I/O control register _4 (TIOR_4)
Timer interrupt enable register_4 (TIER_4)
Timer status register_4 (TSR_4)
Timer counter_4 (TCNT_4)
Timer general register A_4 (TGRA_4)
Timer general register B_4 (TGRB_4)
Timer control register_5 (TCR_5)
Timer mode register_5 (TMDR_5)
Timer I/O control register_5 (TIOR_5)
Timer interrupt enable register_5 (TIER_5)
Timer status register_5 (TSR_5)
Timer counter_5 (TCNT_5)
Timer general register A_5 (TGRA_5)
Timer general register B_5 (TGRB_5)
Common Registers
• Timer start register (TSTR)
• Timer synchro register (TSYR)
Rev. 2.00 Dec. 05, 2005 Page 236 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.1
Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The TPU has a total of six TCR registers, one for each channel (channel 0 to 5). TCR
register settings should be conducted only when TCNT operation is stopped.
Bit
Bit Name
Initial
value
R/W
Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 0 to 2
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 0 and 1
These bits select the TCNT counter clearing source.
See tables 10.3 and 10.4 for details.
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock
period is halved (e.g. φ/4 both edges = φ/2 rising edge).
If phase counting mode is used on channels 1, 2, 4, and
5, this setting is ignored and the phase counting mode
setting has priority. Internal clock edge selection is valid
when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1, or when
overflow/underflow of another channel is selected.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
[Legend]
X: Don't care
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables10.5 to 10.10 for details.
Rev. 2.00 Dec. 05, 2005 Page 237 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.3 CCLR0 to CCLR2 (Channels 0 and 3)
Bit 7
Channel CCLR2
Bit 6
CCLR1
Bit 5
CCLR0
Description
0, 3
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input
2
capture*
0
TCNT cleared by TGRD compare match/input
capture*2
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
0
1
1
0
1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 10.4 CCLR0 to CCLR2 (Channels 1, 2, 4, and 5)
Bit 7
Bit 6
Channel Reserved*2 CCLR1
Bit 5
CCLR0
Description
1, 2, 4, 5 0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
0
1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
Rev. 2.00 Dec. 05, 2005 Page 238 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.5 TPSC0 to TPSC2 (Channel 0)
Bit 2
Channel TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
1
1
0
1
0
External clock: counts on TCLKC pin input
1
External clock: counts on TCLKD pin input
Table 10.6 TPSC0 to TPSC2 (Channel 1)
Bit 2
Channel TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
1
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
Internal clock: counts on φ/256
1
Counts on TCNT2 overflow/underflow
0
1
1
0
1
Note: This setting is ignored when channel 1 is in phase counting mode.
Rev. 2.00 Dec. 05, 2005 Page 239 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.7 TPSC0 to TPSC2 (Channel 2)
Bit 2
Channel TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
2
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
1
1
0
1
0
External clock: counts on TCLKC pin input
1
Internal clock: counts on φ/1024
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 10.8 TPSC0 to TPSC2 (Channel 3)
Bit 2
Channel TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
3
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
Internal clock: counts on φ/1024
0
Internal clock: counts on φ/256
1
Internal clock: counts on φ/4096
0
1
1
0
1
Rev. 2.00 Dec. 05, 2005 Page 240 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.9 TPSC0 to TPSC2 (Channel 4)
Bit 2
Channel TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
4
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKC pin input
0
1
1
0
1
0
Internal clock: counts on φ/1024
1
Counts on TCNT5 overflow/underflow
Note: This setting is ignored when channel 4 is in phase counting mode.
Table 10.10 TPSC0 to TPSC2 (Channel 5)
Bit 2
Channel TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
5
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKC pin input
0
Internal clock: counts on φ/256
1
External clock: counts on TCLKD pin input
0
1
1
0
1
Note: This setting is ignored when channel 5 is in phase counting mode.
Rev. 2.00 Dec. 05, 2005 Page 241 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.2
Timer Mode Register (TMDR)
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings
should be changed only when TCNT operation is stopped.
Bit
Bit Name
Initial
value
R/W
Description
7, 6

All 1

Reserved
These bits are always read as 1 and cannot be
modified.
5
BFB
0
R/W
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
4
BFA
0
R/W
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
3
2
1
0
MD3
MD2
MD1
MD0
0
0
0
0
R/W
R/W
R/W
R/W
Rev. 2.00 Dec. 05, 2005 Page 242 of 724
REJ09B0200-0200
Modes 0 to 3
These bits are used to set the timer operating mode.
MD3 is a reserved bit. In a write, it should always be
written with 0. See table 10.11 for details.
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.11 MD0 to MD3
Bit 3
1
MD3*
Bit 2
MD2*2
Bit 1
MD1
Bit 0
MD0
Description
0
0
0
0
Normal operation
1
Reserved
0
PWM mode 1
1
PWM mode 2
0
Phase counting mode 1
1
Phase counting mode 2
1
1
0
1
1
X
X
0
Phase counting mode 3
1
Phase counting mode 4
X

[Legend]
X:
Don't care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
Rev. 2.00 Dec. 05, 2005 Page 243 of 724
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.3
Timer I/O Control Register (TIOR)
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The TPU
has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5.
Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is
valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM
mode 2, the output at the point at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
Bit
Bit Name
Initial
value
R/W
Description
7
6
5
4
IOB3
IOB2
IOB1
IOB0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control B0 to B3
3
2
1
0
IOA3
IOA2
IOA1
IOA0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control A0 to A3
Specify the function of TGRB.
Specify the function of TGRA.
• TIORL_0, TIORL_3
Bit
Bit Name
Initial
value
R/W
Description
7
6
5
4
IOD3
IOD2
IOD1
IOD0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control D0 to D3
3
2
1
0
IOC3
IOC2
IOC1
IOC0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control C0 to C3
Rev. 2.00 Dec. 05, 2005 Page 244 of 724
REJ09B0200-0200
Specify the function of TGRD.
Specify the function of TGRC.
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.12 TIORH_0 (Channel 0)
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_0
Function
0
0
0
0
Output
compare
register
1
TIOCB0 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCB0 pin
register
Input capture at rising edge
1
Capture input source is the TIOCB0 pin
Input capture at falling edge
1
X
Capture input source is the TIOCB0 pin
Input capture at both edges.
1
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down*
[Legend]
X:
Don't care
Note: * When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
Rev. 2.00 Dec. 05, 2005 Page 245 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.13 TIORL_0 (Channel 0)
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_0
Function
0
0
0
0
Output
compare
register*2
1
TIOCD0 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCD0 pin
register*2
Input capture at rising edge
1
Capture input source is the TIOCD0 pin
Input capture at falling edge
1
X
Capture input source is the TIOCD0 pin
Input capture at both edges
1
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down*
1
[Legend]
X:
Don't care
Notes: 1. When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 2.00 Dec. 05, 2005 Page 246 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.14 TIOR_1 (Channel 1)
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_1
Function
0
0
0
0
Output
compare
register
1
TIOCB1 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCB1 pin
register
Input capture at rising edge
1
Capture input source is the TIOCB1 pin
Input capture at falling edge
1
X
Capture input source is the TIOCB1 pin
Input capture at both edges
1
X
X
TGRC_0 compare match/ input capture
Input capture at generation of TGRC_0 compare
match/input capture
[Legend]
X:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 247 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.15 TIOR_2 (Channel 2)
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_2
Function
0
0
0
0
Output
compare
register
1
TIOCB2 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
Initial output is 1
1
Toggle output at compare match
1
X
0
0
Input capture Capture input source is the TIOCB2 pin
register
Input capture at rising edge
1
Capture input source is the TIOCB2 pin
Input capture at falling edge
1
X
Capture input source is the TIOCB2 pin
Input capture at both edges
[Legend]
X:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 248 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.16 TIORH_3 (Channel 3)
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_3
Function
0
0
0
0
Output
compare
register
1
TIOCB3 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCB3 pin
register
Input capture at rising edge
1
Capture input source is the TIOCB3 pin
Input capture at falling edge
1
X
Capture input source is the TIOCB3 pin
Input capture at both edges
1
X
X
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down*
[Legend]
X:
Don't care
Note: * When bits TPSC0 to TPSC2 in TCR_4 are set to B′000 and φ/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
Rev. 2.00 Dec. 05, 2005 Page 249 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.17 TIORL_3 (Channel 3)
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_3
Function
0
0
0
0
Output
compare
register*2
1
TIOCD3 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCD3 pin
register*2
Input capture at rising edge
1
Capture input source is the TIOCD3 pin
Input capture at falling edge
1
X
Capture input source is the TIOCD3 pin
Input capture at both edges
1
X
X
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down*
1
[Legend]
X:
Don't care
Notes: 1. When bits TPSC0 to TPSC2 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 2.00 Dec. 05, 2005 Page 250 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.18 TIOR_4 (Channel 4)
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_4
Function
0
0
0
0
Output
compare
register
1
TIOCB4 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCB4 pin
register
Input capture at rising edge
1
Capture input source is the TIOCB4 pin
Input capture at falling edge
1
X
Capture input source is the TIOCB4 pin
Input capture at both edges
1
X
X
Capture input source is TGRC_3 compare
match/input capture
Input capture at generation of TGRC_3 compare
match/input capture
[Legend]
X:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 251 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.19 TIOR_5 (Channel 5)
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_5
Function
0
0
0
0
Output
compare
register
1
TIOCB5 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
Initial output is 1
1
Toggle output at compare match
1
X
0
0
Input capture Capture input source is the TIOCB5 pin
register
Input capture at rising edge
1
Capture input source is the TIOCB5 pin
Input capture at falling edge
1
X
Capture input source is the TIOCB5 pin
Input capture at both edges
[Legend]
X:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 252 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.20 TIORH_0 (Channel 0)
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_0
Function
0
0
0
0
Output
compare
register
1
TIOCA0 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCA0 pin
register
Input capture at rising edge
1
Capture input source is the TIOCA0 pin
Input capture at falling edge
1
X
Capture input source is the TIOCA0 pin
Input capture at both edges
1
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
X:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 253 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.21 TIORL_0 (Channel 0)
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_0
Function
0
0
0
0
Output
compare
register*
1
TIOCC0 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
Initial output is 1
1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCC0 pin
register*
Input capture at rising edge
1
Capture input source is the TIOCC0 pin
Input capture at falling edge
1
X
Capture input source is the TIOCC0 pin
Input capture at both edges
1
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
X:
Don't care
Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 2.00 Dec. 05, 2005 Page 254 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.22 TIOR_1 (Channel 1)
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_1
Function
0
0
0
0
Output
compare
register
1
TIOCA1 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCA1 pin
register
Input capture at rising edge
1
Capture input source is the TIOCA1 pin
Input capture at falling edge
1
X
Capture input source is the TIOCA1 pin
Input capture at both edges
1
X
X
Capture input source is TGRA_0 compare
match/input capture
Input capture at generation of channel 0/TGRA_0
compare match/input capture
[Legend]
X:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 255 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.23 TIOR_2 (Channel 2)
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_2
Function
0
0
0
0
Output
compare
register
1
TIOCA2 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
Initial output is 1
1
Toggle output at compare match
1
X
0
0
Input capture Capture input source is the TIOCA2 pin
register
Input capture at rising edge
1
Capture input source is the TIOCA2 pin
Input capture at falling edge
1
X
Capture input source is the TIOCA2 pin
Input capture at both edges
[Legend]
X:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 256 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.24 TIORH_3 (Channel 3)
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_3
Function
0
0
0
0
Output
compare
register
1
TIOCA3 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCA3 pin
register
Input capture at rising edge
1
Capture input source is the TIOCA3 pin
Input capture at falling edge
1
X
Capture input source is the TIOCA3 pin
Input capture at both edges
1
X
X
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down
[Legend]
X:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 257 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.25 TIORL_3 (Channel 3)
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_3
Function
0
0
0
0
Output
compare
register*
1
TIOCC3 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
Initial output is 1
1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCC3 pin
register*
Input capture at rising edge
1
Capture input source is the TIOCC3 pin
Input capture at falling edge
1
X
Capture input source is the TIOCC3 pin
Input capture at both edges
1
X
X
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down
[Legend]
X:
Don't care
Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 2.00 Dec. 05, 2005 Page 258 of 724
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.26 TIOR_4 (Channel 4)
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_4
Function
0
0
0
0
Output
compare
register
1
TIOCA4 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input capture Capture input source is the TIOCA4 pin
register
Input capture at rising edge
1
Capture input source is the TIOCA4 pin
Input capture at falling edge
1
X
Capture input source is the TIOCA4 pin
Input capture at both edges
1
X
X
Capture input source is TGRA_3 compare
match/input capture
Input capture at generation of TGRA_3 compare
match/input capture
[Legend]
X:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 259 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.27 TIOR_5 (Channel 5)
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_5
Function
0
0
0
0
Output
compare
register
1
TIOCA5 Pin Function
Output disabled
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
Initial output is 1
1
Toggle output at compare match
1
X
0
0
Input capture Capture input source is the TIOCA5 pin
register
Input capture at rising edge
1
Capture input source is the TIOCA5 pin
Input capture at falling edge
1
X
Capture input source is the TIOCA5 pin
Input capture at both edges
[Legend]
X:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 260 of 724
REJ09B0200-0200
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.4
Timer Interrupt Enable Register (TIER)
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of
interrupt requests for each channel. The TPU has six TIER registers, one for each channel.
Bit
Bit Name
Initial
value
R/W
Description
7
TTGE
0
R/W
A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
6

1

Reserved
This bit is always read as 1 and cannot be modified.
5
TCIEU
0
R/W
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1, 2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always read
as 0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
4
TCIEV
0
R/W
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
3
TGIED
0
R/W
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial
value
R/W
Description
2
TGIEC
0
R/W
TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in
channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.5
Timer Status Register (TSR)
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The
TPU has six TSR registers, one for each channel.
Bit
Bit Name
Initial
value
R/W
Description
7
TCFD
1
R
Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 7 is reserved. It is always read
as 1 and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6

1

Reserved
This bit is always read as 1 and cannot be modified.
5
TCFU
0
R/(W)
Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1, 2, 4, and 5 are set to phase
counting mode. Only 0 can be written, for flag clearing.
In channels 0 and 3, bit 5 is reserved. It is always read
as 0 and cannot be modified.
[Setting condition]
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
4
TCFV
0
R/(W)
Overflow Flag
Status flag that indicates that TCNT overflow has
occurred. Only 0 can be written, for flag clearing.
[Setting condition]
When the TCNT value overflows (changes from H'FFFF
to H'0000)
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial
value
R/W
Description
3
TGFD
0
R/(W)
Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input
capture or compare match in channels 0 and 3. Only 0
can be written, for flag clearing. In channels 1, 2, 4, and
5, bit 3 is reserved. It is always read as 0 and cannot be
modified.
[Setting conditions]
•
When TCNT = TGRD and TGRD is functioning as
output compare register
•
When TCNT value is transferred to TGRD by input
capture signal and TGRD is functioning as input
capture register
[Clearing conditions]
2
TGFC
0
R/(W)
•
When DTC is activated by TGID interrupt and the
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFD after reading TGFD = 1
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0 and 3. Only 0
can be written, for flag clearing. In channels 1, 2, 4, and
5, bit 2 is reserved. It is always read as 0 and cannot be
modified.
[Setting conditions]
•
When TCNT = TGRC and TGRC is functioning as
output compare register
•
When TCNT value is transferred to TGRC by input
capture signal and TGRC is functioning as input
capture register
[Clearing conditions]
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•
When DTC is activated by TGIC interrupt and the
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFC after reading TGFC = 1
Section 10 16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial
value
R/W
Description
1
TGFB
0
R/(W)
Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB input
capture or compare match. Only 0 can be written, for
flag clearing.
[Setting conditions]
•
When TCNT = TGRB and TGRB is functioning as
output compare register
•
When TCNT value is transferred to TGRB by input
capture signal and TGRB is functioning as input
capture register
[Clearing conditions]
0
TGFA
0
R/(W)
•
When DTC is activated by TGIB interrupt and the
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFB after reading TGFB = 1
Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match. Only 0 can be written, for
flag clearing.
[Setting conditions]
•
When TCNT = TGRA and TGRA is functioning as
output compare register
•
When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
[Clearing conditions]
•
When DTC is activated by TGIA interrupt and the
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFA after reading TGFA = 1
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.6
Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
10.3.7
Timer General Register (TGR)
The TGR registers are dual function 16-bit readable/writable registers, functioning as either output
compare or input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3
and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be
designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units;
they must always be accessed as a 16-bit unit. TGR buffer register combinations are
TGRATGRC and TGRBTGRD.
10.3.8
Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5.
When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT
counter.
Bit
Bit Name
Initial
value
R/W
Description
7, 6

All 0

Reserved
The write value should always be 0.
5
4
3
2
1
0
CST5
CST4
CST3
CST2
CST1
CST0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Counter Start 0 to 5 (CST0 to CST5)
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained. If
TIOR is written to when the CST bit is cleared to 0, the
pin output level will be changed to the set initial output
value.
0: TCNT_0 to TCNT_5 count operation is stopped
1: TCNT_0 to TCNT_5 performs count operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.9
Timer Synchro Register (TSYR)
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 5 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
Bit
Bit Name
Initial
value
R/W
Description
7, 6

All 0
R/W
Reserved
The write value should always be 0.
5
4
3
2
1
0
SYNC5
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Timer Synchro 0 to 5
These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit , the
TCNT clearing source must also be set by means of
bits CCLR0 to CCLR2 in TCR.
0: TCNT_0 to TCNT_5 operates independently (TCNT
presetting /clearing is unrelated to other channels)
1: TCNT_0 to TCNT_5 performs synchronous operation
TCNT synchronous presetting/synchronous clearing is
possible
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4
Operation
10.4.1
Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, periodic counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for
the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic
counter, for example.
1. Example of count operation setting procedure
Figure 10.2 shows an example of the count operation setting procedure.
Operation selection
Select counter clock
[1]
Periodic counter
Select counter clearing source
Free-running counter
[2]
[3]
Select output compare register
Set period
[4]
Start count operation
[5]
<Periodic counter>
Start count operation
<Free-running counter>
[1] Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. At the same
time, select the
input clock edge
with bits CKEG1
and CKEG0 in TCR.
[2] For periodic counter
operation, select the
TGR to be used as
the TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
[3] Designate the TGR
selected in [2] as an
output compare
register by means of
TIOR.
[4] Set the periodic
counter cycle in the
TGR selected in [2].
[5] Set the CST bit in
TSTR to 1 to start
the counter
operation.
Figure 10.2 Example of Counter Operation Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
2. Free-running count operation and periodic count operation
Immediately after a reset, the TPU's TCNT counters are all designated as free-running
counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000),
the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at
this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from
H'0000.
Figure 10.3 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
Time
CST bit
TCFV
Figure 10.3 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the
relevant channel performs periodic count operation. The TGR register for setting the period is
designated as an output compare register, and counter clearing by compare match is selected
by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts
up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When
the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared
to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an
interrupt. After a compare match, TCNT starts counting up again from H'0000.
Figure 10.4 illustrates periodic counter operation.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Counter cleared by TGR
compare match
TCNT value
TGR
H'0000
Time
CST bit
Flag cleared by software or
DTC activation
TGF
Figure 10.4 Periodic Counter Operation
Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the
corresponding output pin using compare match.
1. Example of setting procedure for waveform output by compare match
Figure 10.5 shows an example of the setting procedure for waveform output by compare match
Output selection
Select waveform output mode
[1]
Set output timing
[2]
Start count operation
[3]
[1] Select initial value 0 output or 1 output, and
compare match output value 0 output, 1 output,
or toggle output, by means of TIOR. The set
initial value is output at the TIOC pin unit the
first compare match occurs.
[2] Set the timing for compare match generation in
TGR.
[3] Set the CST bit in TSTR to 1 to start the count
operation.
<Waveform output>
Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match
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Section 10 16-Bit Timer Pulse Unit (TPU)
2. Examples of waveform output operation
Figure 10.6 shows an example of 0 output/1 output.
In this example TCNT has been designated as a free-running counter, and settings have been
made such that 1 is output by compare match A, and 0 is output by compare match B. When
the set level and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF
TGRA
TGRB
Time
H'0000
No change
No change
1 output
TIOCA
TIOCB
No change
No change
0 output
Figure 10.6 Example of 0 Output/1 Output Operation
Figure 10.7 shows an example of toggle output.
In this example, TCNT has been designated as a periodic counter (with counter clearing on
compare match B), and settings have been made such that the output is toggled by both
compare match A and compare match B.
TCNT value
Counter cleared by TGRB compare match
H'FFFF
TGRB
TGRA
Time
H'0000
Toggle output
TIOCB
Toggle output
TIOCA
Figure 10.7 Example of Toggle Output Operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC
pin input edge.
Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3,
and 4, it is also possible to specify another channel's counter input clock or compare match signal
as the input capture source.
Note: When another channel's counter input clock is used as the input capture input for channels
0 and 3, φ/1 should not be selected as the counter input clock used for input capture input.
Input capture will not be generated if φ/1 is selected.
1. Example of input capture operation setting procedure
Figure 10.8 shows an example of the input capture operation setting procedure.
Input selection
Select input capture input
Start count
[1] Designate TGR as an input capture register by
means of TIOR, and select rising edge, falling
edge, or both edges as the input capture source
and input signal edge.
[2] Set the CST bit in TSTR to 1 to start the count
operation.
[1]
[2]
<Input capture operation>
Figure 10.8 Example of Input Capture Operation Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
2. Example of input capture operation
Figure 10.9 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TIOCA pin input
capture input edge, the falling edge has been selected as the TIOCB pin input capture input
edge, and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB
input (falling edge)
TCNT value
H'0180
H'0160
H'0010
H'0005
Time
H'0000
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB
TGRB
H'0180
Figure 10.9 Example of Input Capture Operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.2
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten
simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared
simultaneously by making the appropriate setting in TCR (synchronous clearing).
Synchronous operation enables TGR to be incremented with respect to a single time base.
Channels 0 to 5 can all be designated for synchronous operation.
Example of Synchronous Operation Setting Procedure: Figure 10.10 shows an example of the
synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation
[1]
Synchronous presetting
Set TCNT
Synchronous clearing
[2]
Clearing
source generation
channel?
No
Yes
<Synchronous presetting>
Select counter
clearing source
[3]
Set synchronous
counter clearing
[4]
Start count
[4]
Start count
[5]
<Counter clearing>
<Synchronous clearing>
[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
operation.
[2] When the TCNT counter of any of the channels designated for synchronous operation is
written to, the same value is simultaneously written to the other TCNT counters.
[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare,
etc.
[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing
source.
[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 10.10 Example of Synchronous Operation Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation: Figure 10.11 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are
performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM
cycle.
For details of PWM modes, see section 10.4.5, PWM Modes.
Synchronous clearing by TGRB_0 compare match
TCNT0 to TCNT2 values
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
Time
H'0000
TIOCA_0
TIOCA_1
TIOCA_2
Figure 10.11 Example of Synchronous Operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.3
Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 10.28 shows the register combinations used in buffer operation.
Table 10.28 Register Combinations in Buffer Operation
Channel
Timer General Register
Buffer Register
0
TGRA_0
TGRC_0
TGRB_0
TGRD_0
TGRA_3
TGRC_3
TGRB_3
TGRD_3
3
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 10.12.
Compare match signal
Timer general
register
Buffer register
Comparator
TCNT
Figure 10.12 Compare Match Buffer Operation
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 10.13.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Input capture
signal
Timer general
register
Buffer register
TCNT
Figure 10.13 Input Capture Buffer Operation
Example of Buffer Operation Setting Procedure: Figure 10.14 shows an example of the buffer
operation setting procedure.
Buffer operation
Select TGR function
[1]
Set buffer operation
[2]
Start count
[3]
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
[3] Set the CST bit in TSTR to 1 start the count
operation.
<Buffer operation>
Figure 10.14 Example of Buffer Operation Setting Procedure
Examples of Buffer Operation:
1. When TGR is an output compare register
Figure 10.15 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time that compare match A occurs.
For details of PWM modes, see section 10.4.5, PWM Modes.
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Section 10 16-Bit Timer Pulse Unit (TPU)
TCNT value
TGRB_0
H'0520
H'0450
H'0200
TGRA_0
Time
H'0000
TGRC_0 H'0200
H'0450
H'0520
Transfer
TGRA_0
H'0200
H'0450
TIOCA
Figure 10.15 Example of Buffer Operation (1)
2. When TGR is an input capture register
Figure 10.16 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon the
occurrence of input capture A, the value previously stored in TGRA is simultaneously
transferred to TGRC.
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Section 10 16-Bit Timer Pulse Unit (TPU)
TCNT value
H'0F07
H'09FB
H'0532
H'0000
Time
TIOCA
TGRA
TGRC
H'0532
H'0F07
H'09FB
H'0532
H'0F07
Figure 10.16 Example of Buffer Operation (2)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.4
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow
of TCNT_2 (TCNT_5) as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 10.29 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counters operates independently in phase counting mode.
Table 10.29 Cascaded Combinations
Combination
Upper 16 Bits
Lower 16 Bits
Channels 1 and 2
TCNT_1
TCNT_2
Channels 4 and 5
TCNT_4
TCNT_5
Example of Cascaded Operation Setting Procedure: Figure 10.17 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
Start count
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
[2] Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
<Cascaded operation>
Figure 10.17 Cascaded Operation Setting Procedure
Examples of Cascaded Operation: Figure 10.18 illustrates the operation when TCNT_2
overflow/underflow counting has been set for TCNT_1, when TGRA_1 and TGRA_2 have been
designated as input capture registers, and when TIOC pin rising edge has been selected.
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Section 10 16-Bit Timer Pulse Unit (TPU)
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
TCNT_1
clock
TCNT_1
H'03A1
H'03A2
TCNT_2
clock
TCNT_2
H'FFFF
H'0001
H'0000
TIOCA1,
TIOCA2
TGRA_1
H'03A2
TGRA_2
H'0000
Figure 10.18 Example of Cascaded Operation (1)
Figure 10.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for
TCNT_1 and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKA
TCLKB
TCNT_2
TCNT_1
FFFD
FFFE
0000
FFFF
0000
0001
0002
0001
0000
0001
FFFF
0000
Figure 10.19 Example of Cascaded Operation (2)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected
as 0, 1, or toggle output in response to a compare match of each TGR.
TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty
cycle.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is
output from the TIOCA and TIOCC pins at compare matches A and C, and the output
specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B
and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired
TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty cycle
registers. The output specified in TIOR is performed by means of compare matches. Upon
counter clearing by a synchronization register compare match, the output value of each pin is
the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical,
the output value does not change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is possible in combination use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 10.30.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.30 PWM Output Registers and Output Pins
Output Pins
Channel
0
Registers
PWM Mode 1
PWM Mode 2
TGRA_0
TIOCA0
TIOCA0
TGRB_0
TGRC_0
TIOCB0
TIOCC0
TGRD_0
1
TGRA_1
TIOCD0
TIOCA1
TGRB_1
2
TGRA_2
TGRA_3
TIOCA2
TIOCA3
TGR4A_4
TIOCC3
TGRA_5
TGRB_5
Note:
*
TIOCC3
TIOCD3
TIOCA4
TGR4B_4
5
TIOCA3
TIOCB3
TGRD_3
4
TIOCA2
TIOCB2
TGRB_3
TGRC_3
TIOCA1
TIOCB1
TGRB_2
3
TIOCC0
TIOCA4
TIOCB4
TIOCA5
TIOCA5
TIOCB5
In PWM mode 2, PWM output is not possible for the TGR register in which the period is
set.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Example of PWM Mode Setting Procedure: Figure 10.20 shows an example of the PWM mode
setting procedure.
PWM mode
Select counter clock
[1]
Select counter clearing source
[2]
Select waveform output level
[3]
Set TGR
[4]
Set PWM mode
[5]
Start count
[6]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0
in TCR.
[2] Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
[3] Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
[4] Set the cycle in the TGR selected in [2], and set
the duty in the other the TGR.
[5] Select the PWM mode with bits MD3 to MD0 in
TMDR.
[6] Set the CST bit in TSTR to 1 start the count
operation.
<PWM mode>
Figure 10.20 Example of PWM Mode Setting Procedure
Examples of PWM Mode Operation: Figure 10.21 shows an example of PWM mode 1
operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers
are used as the duty cycle levels.
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Section 10 16-Bit Timer Pulse Unit (TPU)
TCNT value
Counter cleared by
TGRA compare match
TGRA
TGRB
H'0000
Time
TIOCA
Figure 10.21 Example of PWM Mode Operation (1)
Figure 10.22 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase
PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are
used as the duty cycle levels.
TCNT value
Counter cleared by
TGRB_1 compare match
TGRB_1
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
H'0000
Time
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 10.22 Example of PWM Mode Operation (2)
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Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle
in PWM mode.
TCNT value
TGRB rewritten
TGRA
TGRB
TGRB rewritten
TGRB
rewritten
H'0000
Time
0% duty
TIOCA
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB rewritten
TGRB
H'0000
Time
100% duty
TIOCA
Output does not change when cycle register and duty
register compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB
TGRB rewritten
Time
H'0000
100% duty
TIOCA
0% duty
Figure 10.23 Example of PWM Mode Operation (3)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits
CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of
TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two-phase encoder pulse input.
If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs
when TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is
counting up or down.
Table 10.31 shows the correspondence between external clock pins and channels.
Table 10.31 Phase Counting Mode Clock Input Pins
External Clock Pins
Channels
A-Phase
B-Phase
When channel 1 or 5 is set to phase counting mode
TCLKA
TCLKB
When channel 2 or 4 is set to phase counting mode
TCLKC
TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 10.24 shows an example of the
phase counting mode setting procedure.
[1] Select phase counting mode with bits MD3 to
MD0 in TMDR.
[2] Set the CST bit in TSTR to 1 to start the count
operation.
Phase counting mode
Select phase counting mode
[1]
Start count
[2]
<Phase counting mode>
Figure 10.24 Example of Phase Counting Mode Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or
down according to the phase difference between two external clocks. There are four modes,
according to the count conditions.
1. Phase counting mode 1
Figure 10.25 shows an example of phase counting mode 1 operation, and table 10.32
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 10.25 Example of Phase Counting Mode 1 Operation
Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
Operation
Up-count
High level
Low level
Low level
High level
High level
Down-count
Low level
High level
Low level
[Legend]
:
Rising edge
:
Falling edge
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Section 10 16-Bit Timer Pulse Unit (TPU)
2. Phase counting mode 2
Figure 10.26 shows an example of phase counting mode 2 operation, and table 10.33
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 10.26 Example of Phase Counting Mode 2 Operation
Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Don't care
Low level
Don't care
Low level
Don't care
High level
Up-count
High level
Don't care
Low level
Don't care
High level
Don't care
Low level
Down-count
[Legend]
:
Rising edge
:
Falling edge
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Section 10 16-Bit Timer Pulse Unit (TPU)
3. Phase counting mode 3
Figure 10.27 shows an example of phase counting mode 3 operation, and table 10.34
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 10.27 Example of Phase Counting Mode 3 Operation
Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
Operation
High level
Don't care
Low level
Don't care
Low level
Don't care
High level
Up-count
High level
Down-count
Low level
Don't care
[Legend]
:
Rising edge
:
Falling edge
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High level
Don't care
Low level
Don't care
Section 10 16-Bit Timer Pulse Unit (TPU)
4. Phase counting mode 4
Figure 10.28 shows an example of phase counting mode 4 operation, and table 10.35
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 10.28 Example of Phase Counting Mode 4 Operation
Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Up-count
Low level
Low level
Don't care
High level
High level
Down-count
Low level
High level
Don't care
Low level
[Legend]
:
Rising edge
:
Falling edge
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Section 10 16-Bit Timer Pulse Unit (TPU)
Phase Counting Mode Application Example: Figure 10.29 shows an example in which channel
1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase
encoder pulses in order to detect position or speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input
to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and
TGRC_0 are used for the compare match function and are set with the speed control period and
position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating
in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture
source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected.
TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and
TGRC_0 compare matches are selected as the input capture source and store the up/down-counter
values for the control periods.
This procedure enables the accurate detection of position and speed.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Channel 1
TCLKA
TCLKB
Edge
detection
circuit
TCNT_1
TGRA_1
(speed period capture)
TGRB_1
(speed period capture)
TCNT_0
TGRA_0
(speed control period)
+
-
TGRC_0
(position control period)
+
-
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation)
Channel 0
Figure 10.29 Phase Counting Mode Application Example
10.5
Interrupt Sources
There are three kinds of TPU interrupt source; TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, however the priority order
within a channel is fixed. For details, see section 5, Interrupt Controller.
Table 10.36 lists the TPU interrupt sources.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.36 TPU Interrupts
Channel
Name
Interrupt Source
DTC
Interrupt Flag Activation
0
TGIA_0
TGRA_0 input capture/compare match
TGFA_0
Possible
TGIB_0
TGRB_0 input capture/compare match
TGFB_0
Possible
TGIC_0
TGRC_0 input capture/compare match
TGFC_0
Possible
TGID_0
TGRD_0 input capture/compare match
TGFD_0
Possible
TCIV_0
TCNT_0 overflow
TCFV_0
Not possible
TGIA_1
TGRA_1 input capture/compare match
TGFA_1
Possible
TGIB_1
TGRB_1 input capture/compare match
TGFB_1
Possible
TCIV_1
TCNT_1 overflow
TCFV_1
Not possible
TCIU_1
TCNT_1 underflow
TCFU_1
Not possible
TGIA_2
TGRA_2 input capture/compare match
TGFA_2
Possible
TGIB_2
TGRB_2 input capture/compare match
TGFB_2
Possible
TCIV_2
TCNT_2 overflow
TCFV_2
Not possible
TCIU_2
TCNT_2 underflow
TCFU_2
Not possible
TGIA_3
TGRA_3 input capture/compare match
TGFA_3
Possible
TGIB_3
TGRB_3 input capture/compare match
TGFB_3
Possible
TGIC_3
TGRC_3 input capture/compare match
TGFC_3
Possible
TGID_3
TGRD_3 input capture/compare match
TGFD_3
Possible
TCIV_3
TCNT_3 overflow
TCFV_3
Not possible
TGIA_4
TGRA_4 input capture/compare match
TGFA_4
Possible
TGIB_4
TGRB_4 input capture/compare match
TGFB_4
Possible
TCIV_4
TCNT_4 overflow
TCFV_4
Not possible
TCIU_4
TCNT_4 underflow
TCFU_4
Not possible
1
2
3
4
5
Note:
*
TGIA_5
TGRA_5 input capture/compare match
TGFA_5
Possible
TGIB_5
TGRB_5 input capture/compare match
TGFB_5
Possible
TCIV_5
TCNT_5 overflow
TCFV_5
Not possible
TCIU_5
TCNT_5 underflow
TCFU_5
Not possible
This table shows the initial state immediately after a reset. The relative channel
priorities can be changed by the interrupt controller.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each
for channels 1, 2, 4, and 5.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one
each for channels 1, 2, 4, and 5.
10.6
DTC Activation
The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For
details, see section 8, Data Transfer Controller (DTC).
A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources,
four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
10.7
A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to begin A/D conversion is
sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D
converter side at this time, A/D conversion is begun.
In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.8
Operation Timing
10.8.1
Input/Output Timing
TCNT Count Timing: Figure 10.30 shows TCNT count timing in internal clock operation, and
figure 10.31 shows TCNT count timing in external clock operation.
φ
Internal clock
Falling edge
Rising edge
TCNT
input clock
TCNT
N-1
N
N+1
N+2
Figure 10.30 Count Timing in Internal Clock Operation
φ
External clock
Falling edge
Rising edge
Falling edge
TCNT
input clock
TCNT
N-1
N
N+1
Figure 10.31 Count Timing in External Clock Operation
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N+2
Section 10 16-Bit Timer Pulse Unit (TPU)
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin. After a match between TCNT and TGR, the compare match signal is not
generated until the TCNT input clock is generated.
Figure 10.32 shows output compare output timing.
φ
TCNT
input clock
N+1
N
TCNT
N
TGR
Compare
match signal
TIOC pin
Figure 10.32 Output Compare Output Timing
Input Capture Signal Timing: Figure 10.33 shows input capture signal timing.
φ
Input capture
input
Input capture
signal
TCNT
TGR
N
N+1
N+2
N
N+2
Figure 10.33 Input Capture Input Signal Timing
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Section 10 16-Bit Timer Pulse Unit (TPU)
Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.34 shows the
timing when counter clearing on compare match is specified, and figure 10.35 shows the timing
when counter clearing on input capture is specified.
φ
Compare
match signal
Counter
clear signal
TCNT
N
TGR
N
H'0000
Figure 10.34 Counter Clear Timing (Compare Match)
φ
Input capture
signal
Counter clear
signal
TCNT
N
H'0000
N
TGR
Figure 10.35 Counter Clear Timing (Input Capture)
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Section 10 16-Bit Timer Pulse Unit (TPU)
Buffer Operation Timing: Figures 10.36 and 10.37 show the timing in buffer operation.
φ
TCNT
n
n+1
Compare
match signal
TGRA,
TGRB
n
TGRC,
TGRD
N
N
Figure 10.36 Buffer Operation Timing (Compare Match)
φ
Input capture
signal
TCNT
N
TGRA,
TGRB
n
TGRC,
TGRD
N+1
N
N+1
n
N
Figure 10.37 Buffer Operation Timing (Input Capture)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.8.2
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 10.38 shows the timing for
setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing.
φ
TCNT input
clock
TCNT
N
TGR
N
N+1
Compare
match signal
TGF flag
TGI interrupt
Figure 10.38 TGI Interrupt Timing (Compare Match)
TGF Flag Setting Timing in Case of Input Capture: Figure 10.39 shows the timing for setting
of the TGF flag in TSR on input capture, and TGI interrupt request signal timing.
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Section 10 16-Bit Timer Pulse Unit (TPU)
φ
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 10.39 TGI Interrupt Timing (Input Capture)
TCFV Flag/TCFU Flag Setting Timing: Figure 10.40 shows the timing for setting of the TCFV
flag in TSR on overflow, and TCIV interrupt request signal timing.
Figure 10.41 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU
interrupt request signal timing.
φ
TCNT input
clock
TCNT
(overflow)
H'FFFF
H'0000
Overflow
signal
TCFV flag
TCIV interrupt
Figure 10.40 TCIV Interrupt Setting Timing
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Section 10 16-Bit Timer Pulse Unit (TPU)
φ
TCNT
input clock
TCNT
(underflow)
H'0000
H'FFFF
Underflow
signal
TCFU flag
TCIU interrupt
Figure 10.41 TCIU Interrupt Setting Timing
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Section 10 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.42 shows the
timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag
clearing by the DTC.
TSR write cycle
T1
T2
φ
Address
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 10.42 Timing for Status Flag Clearing by CPU
DTC
read cycle
T1
T2
DTC
write cycle
T1
T2
φ
Address
Source address
Destination
address
Status flag
Interrupt
request
signal
Figure 10.43 Timing for Status Flag Clearing by DTC Activation
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9
Usage Notes
10.9.1
Module Stop Mode Setting
TPU operation can be disabled or enabled using the module stop control register. The initial
setting is for TPU operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 21, Power-Down Modes.
10.9.2
Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.44 shows the input clock
conditions in phase counting mode.
Overlap
Phase
Phase
differdifference Overlap ence
Pulse width
Pulse width
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.3
Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
φ
f=
(N + 1)
Where
10.9.4
f: Counter frequency
φ: Operating frequency
N: TGR set value
Conflict between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed.
Figure 10.45 shows the timing in this case.
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 10.45 Conflict between TCNT Write and Clear Operations
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.5
Conflict between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 10.46 shows the timing in this case.
TCNT write cycle
T1
T2
φ
TCNT address
Address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 10.46 Conflict between TCNT Write and Increment Operations
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.6
Conflict between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is inhibited. A compare match does not occur even if the previous
value is written.
Figure 10.47 shows the timing in this case.
TGR write cycle
T1
T2
φ
TGR address
Address
Write signal
Compare
match signal
Inhibited
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 10.47 Conflict between TGR Write and Compare Match
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.7
Conflict between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation will be that in the buffer prior to the write.
Figure 10.48 shows the timing in this case.
TGR write cycle
T2
T1
φ
Buffer register
address
Address
Write signal
Compare
match signal
Buffer register write data
Buffer
register
TGR
N
M
N
Figure 10.48 Conflict between Buffer Register Write and Compare Match
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.8
Conflict between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 10.49 shows the timing in this case.
TGR read cycle
T2
T1
φ
TGR address
Address
Read signal
Input capture
signal
TGR
X
Internal
data bus
M
M
Figure 10.49 Conflict between TGR Read and Input Capture
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.9
Conflict between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 10.50 shows the timing in this case.
TGR write cycle
T2
T1
φ
TGR address
Address
Write signal
Input capture
signal
TCNT
M
M
TGR
Figure 10.50 Conflict between TGR Write and Input Capture
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.10 Conflict between Buffer Register Write and Input Capture
If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 10.51 shows the timing in this case.
Buffer register write cycle
T2
T1
φ
Buffer register
address
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
N
M
N
M
Figure 10.51 Conflict between Buffer Register Write and Input Capture
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.11 Conflict between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 10.52 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
H'FFFF
H'0000
Counter
clear signal
TGF
Disabled
TCFV
Figure 10.52 Conflict between Overflow and Counter Clearing
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.12 Conflict between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 10.53 shows the operation timing when there is conflict between TCNT write and
overflow.
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
TCNT
TCNT write data
H'FFFF
M
TCFV flag
Figure 10.53 Conflict between TCNT Write and Overflow
10.9.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
10.9.14 Interrupts in Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be
disabled before entering module stop mode.
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Section 10 16-Bit Timer Pulse Unit (TPU)
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Section 11 Programmable Pulse Generator (PPG)
Section 11 Programmable Pulse Generator (PPG)
The programmable pulse generator provides pulse outputs using the 16-bit timer pulse unit (TPU)
as a time base. The PPG pulse outputs are divided into 4-bit groups (group 2 and group 3) that can
operate both simultaneously and independently. The block diagram of the PPG is shown in figure
11.1.
11.1
•
•
•
•
•
•
•
Features
8-bit output data
Two output groups
Selectable output trigger signals
Non-overlap mode
Can operate in tandem with the data transfer controller (DTC)
Settable inverted output
Module stop mode can be set
PPG0000A_000020020300
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Section 11 Programmable Pulse Generator (PPG)
Compare match signals
Control logic
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
NDERH
NDERL
PMR
PCR
Pulse output
pins, group 3
PODRH
NDRH
PODRL
NDRL
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
[Legend]
PMR:
PCR:
NDERH:
NDERL:
NDRH:
NDRL:
PODRH:
PODRL:
PPG output mode register
PPG output control register
Next data enable register H
Next data enable register L
Next data register H
Next data register L
Output data register H
Output data register L
Figure 11.1 Block Diagram of PPG
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Internal
data bus
Section 11 Programmable Pulse Generator (PPG)
11.2
Input/Output Pins
Table 11.1 summarizes the pin configuration of the PPG.
Table 11.1 Pin Configuration
Pin Name
I/O
Function
PO15
Output
Group 3 pulse output
PO14
Output
PO13
Output
PO12
Output
PO11
Output
PO10
Output
PO9
Output
PO8
Output
11.3
Group 2 pulse output
Register Descriptions
The PPG has the following registers.
•
•
•
•
•
•
•
•
PPG output control register (PCR)
PPG output mode register (PMR)
Next data enable register H (NDERH)
Next data enable register L (NDERL)
Output data register H (PODRH)
Output data register L (PODRL)
Next data register H (NDRH)
Next data register L (NDRL)
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Section 11 Programmable Pulse Generator (PPG)
11.3.1
Next Data Enable Registers H, L (NDERH, NDERL)
NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a
bit-by-bit basis. The corresponding DDR also needs to be set to 1 in order to enable pulse output
by the PPG.
• NDERH
Bit
Bit Name
Initial
Value
R/W
Description
7
NDER15
0
R/W
Next Data Enable 8 to 15
6
NDER14
0
R/W
5
NDER13
0
R/W
4
NDER12
0
R/W
3
NDER11
0
R/W
When a bit is set to 1 for pulse output by NDRH, the
value in the corresponding NDRH bit is transferred to
the PODRH bit by the selected output trigger. Values
are not transferred from NDRH to PODRH for cleared
bits.
2
NDER10
0
R/W
1
NDER9
0
R/W
0
NDER8
0
R/W
• NDERL
Bit
Bit Name
Initial
Value
R/W
Description
7
NDER7
0
R/W
Next Data Enable 0 to 7
6
NDER6
0
R/W
5
NDER5
0
R/W
4
NDER4
0
R/W
3
NDER3
0
R/W
When a bit is set to 1 for pulse output by NDRL, the
value in the corresponding NDRL bit is transferred to
the PODRL bit by the selected output trigger. Values
are not transferred from NDRL to PODRL for cleared
bits.
2
NDER2
0
R/W
1
NDER1
0
R/W
0
NDER0
0
R/W
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Section 11 Programmable Pulse Generator (PPG)
11.3.2
Output Data Registers H, L (PODRH, PODRL)
PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse
output. A bit that has been set for pulse output by NDER is read-only and cannot be modified.
• PODRH
Bit
Bit Name
Initial
Value
R/W
Description
7
POD15
0
R/W
Output Data Register 8 to 15
6
POD14
0
R/W
5
POD13
0
R/W
4
POD12
0
R/W
3
POD11
0
R/W
For bits that have been set to pulse output by NDERH,
the output trigger transfers NDRH values to this register
during PPG operation. While NDERH is set to 1, the
CPU cannot write to this register. While NDERH is
cleared, the initial output value of the pulse can be set.
2
POD10
0
R/W
1
POD9
0
R/W
0
POD8
0
R/W
• PODRL
Bit
Bit Name
Initial
Value
R/W
Description
7
POD7
0
R/W
Output Data Register 0 to 7
6
POD6
0
R/W
5
POD5
0
R/W
4
POD4
0
R/W
3
POD3
0
R/W
For bits which have been set to pulse output by
NDERL, the output trigger transfers NDRL values to this
register during PPG operation. While NDERL is set to 1,
the CPU cannot write to this register. While NDERL is
cleared, the initial output value of the pulse can be set.
2
POD2
0
R/W
1
POD1
0
R/W
0
POD0
0
R/W
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Section 11 Programmable Pulse Generator (PPG)
11.3.3
Next Data Registers H, L (NDRH, NDRL)
NDRH and NDRL are 8-bit readable/writable registers that store the data for the next pulse output.
The NDR addresses differ depending on whether pulse output groups have the same output trigger
or different output triggers.
• NDRH
If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
Bit Name
Initial
Value
R/W
Description
7
NDR15
0
R/W
Next Data Register 8 to 15
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
If pulse output groups 2 and output pulse groups 3 have different output triggers, the upper 4 bits
and the lower 4 bits are mapped to different addresses, as shown below.
Bit
Bit Name
Initial
Value
R/W
Description
7
NDR15
0
R/W
Next Data Register 12 to 15
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
All 1

3 to 0 
Reserved
These bits are always read as 1 and cannot be
modified.
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Section 11 Programmable Pulse Generator (PPG)
Bit
Bit Name
7 to 4 
Initial
Value
R/W
Description
All 1

Reserved
These bits are always read as 1 and cannot be
modified.
3
NDR11
0
R/W
Next Data Register 8 to11
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
• NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
Bit Name
Initial
Value
R/W
Description
7
NDR7
0
R/W
Next Data Register 0 to 7
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
If pulse output groups 0 and output pulse groups 1 have different output triggers, upper 4 bits and
lower 4 bits are mapped to the different addresses as shown below.
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Section 11 Programmable Pulse Generator (PPG)
Bit
Bit Name
Initial
Value
R/W
Description
7
NDR7
0
R/W
Next Data Register 4 to 7
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
All 1

3 to 0 
Reserved
These bits are always read as 1 and cannot be
modified.
Bit
Bit Name
7 to 4 
Initial
Value
R/W
Description
All 1

Reserved
These bits are always read as 1 and cannot be
modified.
3
NDR3
0
R/W
Next Data Register 3 to 0
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
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Section 11 Programmable Pulse Generator (PPG)
11.3.4
PPG Output Control Register (PCR)
PCR is an 8-bit readable/writable register that selects output trigger signals on a group-by-group
basis. For details on output trigger selection, see section 11.3.5, PPG Output Mode Register
(PMR).
Bit
Bit Name
Initial
Value
R/W
Description
7
G3CMS1
1
R/W
Group 3 Compare Match Select 0 and 1
6
G3CMS0
1
R/W
Select output trigger of pulse output group 3.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
5
G2CMS1
1
R/W
Group 2 Compare Match Select 0 and 1
4
G2CMS0
1
R/W
Select output trigger of pulse output group 2.
00: Compare match in TPC channel 0
01: Compare match in TPC channel 1
10: Compare match in TPC channel 2
11: Compare match in TPC channel 3
3
G1CMS1
1
R/W
2
G1CMS0
1
R/W
1
G0CMS1
1
R/W
0
G0CMS0
1
R/W
Reserved
Reserved
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Section 11 Programmable Pulse Generator (PPG)
11.3.5
PPG Output Mode Register (PMR)
The PMR is an 8-bit readable/writable register that selects the pulse output mode of the PPG for
each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a
high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG
updates its output values on compare match A or B of the TPU that becomes the output trigger.
For details, see section 11.4.5, Non-Overlapping Pulse Output.
Bit
Bit Name
Initial
Value
R/W
Description
7
G3INV
1
R/W
Group 3 Inversion
Selects direct output or inverted output for pulse output
group 3.
0: Inverted output
1: Direct output
6
G2INV
1
R/W
Group 2 Inversion
Selects direct output or inverted output for pulse output
group 2.
0: Inverted output
1: Direct output
5, 4

All 1
R/W
Reserved
3
G3NOV
0
R/W
Group 3 Non-Overlap
Selects normal or non-overlapping operation for pulse
output group 3.
0: Normal operation (output values updated at compare
match A in the selected TPU channel)
1: Non-overlapping operation (output values at compare
match A or B in the selected TPU channel)
2
G2NOV
0
R/W
Group 2 Non-Overlap
Selects normal or non-overlapping operation for pulse
output group 2.
0: Normal operation (output values updated at compare
match A in the selected TPU channel)
1: Non-overlapping operation (output values at compare
match A or B in the selected TPU channel)
1, 0

All 0
R/W
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Reserved
Section 11 Programmable Pulse Generator (PPG)
11.4
Operation
11.4.1
Overview
Figure 11.2 shows a block diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR and NDER are set to 1. An initial output value is determined by its
corresponding PODR initial setting. When the compare match event specified by PCR occurs, the
corresponding NDR bit contents are transferred to PODR to update the output values.
The sequential output of up to 8 bits of data is possible by writing new output data to NDR before
the next compare match.
DDR
NDER
Q
Output trigger signal
C
Q PODR D
Q NDR D
Internal data bus
Pulse output pin
Normal output/inverted output
Figure 11.2 PPG Output Operation
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Section 11 Programmable Pulse Generator (PPG)
11.4.2
Output Timing
If pulse output is enabled, the contents of NDR contents are transferred to PODR and output when
the specified compare match event occurs. Figure 11.3 shows the timing of these operations for
the case of normal output in groups 2 and 3, triggered by compare match A.
φ
N
TCNT
TGRA
N+1
N
Compare match
A signal
n
NDRH
PODRH
PO8 to PO15
m
n
m
n
Figure 11.3 Timing of Transfer and Output of NDR Contents (Example)
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Section 11 Programmable Pulse Generator (PPG)
11.4.3
Sample Setup Procedure for Normal Pulse Output
Figure 11.4 shows a sample procedure for setting up normal pulse output.
Normal PPG output
[1] Set TIOR to make TGRA an output
compare register (with output
disabled)
Select TGR functions
[1]
Set TGRA value
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
[4] Enable the TGIA interrupt in TIER.
The DTC can also be set up to
transfer data to NDR.
Enable pulse output
[6]
[5] Set the initial output values in
PODR.
Select output trigger
[7]
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to 1.
Set next pulse
output data
[8]
[7] Select the TPU compare match
event to be used as the output
trigger in PCR.
Start counter
[9]
[8] Set the next pulse output values in
NDR.
[2] Set the PPG output trigger period
TPU setup
Port and
PPG setup
TPU setup
Compare match?
No
Yes
Set next pulse
output data
[10]
[3] Select the counter clock source with
bits TPSC2 to TPSC0 in TCR.
Select the counter clear source with
bits CCLR1 and CCLR0.
[9] Set the CST bit in TSTR to 1 to start
the TCNT counter.
[10] At each TGIA interrupt, set the next
output values in NDR.
Figure 11.4 Setup Procedure for Normal Pulse Output (Example)
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Section 11 Programmable Pulse Generator (PPG)
11.4.4
Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
Figure 11.5 shows an example in which pulse output is used for cyclic five-phase pulse output.
TCNT value
Compare match
TCNT
TGRA
H'0000
Time
80
NDRH
PODRH
00
C0
80
40
C0
60
40
20
60
30
20
10
30
18
10
08
18
88
08
80
88
C0
80
40
C0
PO15
PO14
PO13
PO12
PO11
Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output)
1. Set up TGRA of the TPU that is used as the output trigger to be an output compare register.
Set a frequency in TGRA so the counter will be cleared on compare match A. Set the TGIEA
bit of TIER to 1 to enable the compare match/input capture A (TGIA) interrupt.
2. Write H'F8 in P1DDR and NDERH, and set the G3CMS0, G3CMS1, G2CMS0, and G2CMS1
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Write output data H'80 in NDRH.
3. When compare match A occurs, the NDRH contents are transferred to PODRH and output.
The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH.
4. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained
subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA
interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained
without imposing a load on the CPU.
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Section 11 Programmable Pulse Generator (PPG)
11.4.5
Non-Overlapping Pulse Output
During non-overlapping operation, transfer from NDR to PODR is performed as follows:
• NDR bits are always transferred on PODR bits on compare match A.
• On compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 11.6 illustrates the non-overlapping pulse output operation.
DDR
NDER
Q
Compare match A
Compare match B
Pulse
output
pin
C
Q PODR D
Q NDR D
Internal data bus
Normal output/inverted output
Figure 11.6 Non-Overlapping Pulse Output
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. The NDR contents should not be altered during the interval between compare
match B and compare match A (the non-overlap margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC. Note, however, that the next data must
be written before the next compare match B occurs.
Figure 11.7 shows the timing of this operation.
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Section 11 Programmable Pulse Generator (PPG)
Compare match A
Compare match B
Write to NDR
Write to NDR
NDR
PODR
0 output
0/1 output
Write to NDR
Do not write here
to NDR here
0 output 0/1 output
Do not write
to NDR here
Write to NDR
here
Figure 11.7 Non-Overlapping Operation and NDR Write Timing
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Section 11 Programmable Pulse Generator (PPG)
11.4.6
Sample Setup Procedure for Non-Overlapping Pulse Output
Figure 11.8 shows a sample procedure for setting up non-overlapping pulse output.
Non-overlapping
PPG output
[1] Set TIOR to make TGRA and
TGRB an output compare registers
(with output disabled)
Select TGR functions
[1]
Set TGR values
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
Enable pulse output
[6]
Select output trigger
[7]
Set non-overlapping groups
[8]
Set next pulse
output data
[9]
[7] Select the TPU compare match
event to be used as the pulse
output trigger in PCR.
Start counter
[10]
[8] In PMR, select the groups that will
operate in non-overlap mode.
TPU setup
PPG setup
TPU setup
Compare match A?
No
Yes
Set next pulse
output data
[2] Set the pulse output trigger period
in TGRB and the non-overlap
margin in TGRA.
[3] Select the counter clock source
with bits TPSC2 to TPSC0 in TCR.
Select the counter clear source
with bits CCLR1 and CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC can also be set up to
transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to
1.
[9] Set the next pulse output values in
NDR.
[10] Set the CST bit in TSTR to 1 to
start the TCNT counter.
[11]
[11] At each TGIA interrupt, set the next
output values in NDR.
Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)
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Section 11 Programmable Pulse Generator (PPG)
11.4.7
Example of Non-Overlapping Pulse Output
(Example of Four-Phase Complementary Non-Overlapping Output)
Figure 11.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRH
Time
65
95
00
95
59
05
65
56
41
59
95
50
56
65
14
95
05
65
Non-overlap margin
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 11.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
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Section 11 Programmable Pulse Generator (PPG)
1. Set up the TPU channel to be used as the output trigger channel such that TGRA and TGRB
are output compare registers. Set the trigger period in TGRB and the non-overlap margin in
TGRA, and set the counter to be cleared on compare match B. Set the TGIEA bit in TIER to 1
to enable the TGIA interrupt.
2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.
Write output data H'95 in NDRH.
3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs,
outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0
to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt
handling routine writes the next output data (H'65) in NDRH.
4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by
writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC is set for activation by
this interrupt, pulse output can be obtained without imposing a load on the CPU.
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Section 11 Programmable Pulse Generator (PPG)
11.4.8
Inverted Pulse Output
If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the
inverse of the PODR contents can be output.
Figure 11.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the
settings of figure 11.9.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRL
Time
65
95
00
95
59
05
65
56
41
59
95
50
56
65
14
95
05
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 11.10 Inverted Pulse Output (Example)
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65
Section 11 Programmable Pulse Generator (PPG)
11.4.9
Pulse Output Triggered by Input Capture
Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA
functions as an input capture register in the TPU channel selected by PCR, pulse output will be
triggered by the input capture signal.
Figure 11.11 shows the timing of this output.
φ
TIOC pin
Input capture
signal
NDR
N
PODR
M
PO
M
N
N
Figure 11.11 Pulse Output Triggered by Input Capture (Example)
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Section 11 Programmable Pulse Generator (PPG)
11.5
Usage Notes
11.5.1
Module Stop Mode Setting
PPG operation can be disabled or enabled using the module stop control register. The initial
setting is for PPG operation to be halted. Register access is enabled by clearing module stop mode.
For details, see section 21, Power-Down Modes.
11.5.2
Operation of Pulse Output Pins
Pins PO8 to PO15 are also used for other peripheral functions such as the TPU. When output by
another peripheral function is enabled, the corresponding pins cannot be used for pulse output.
Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage
of the pins.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
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Section 12 Watchdog Timer (WDT)
Section 12 Watchdog Timer (WDT)
This LSI has a two-channel watchdog timer (WDT_0, WDT_1). WDT is an 8-bit timer that can
generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to
the timer counter, thus allowing it to overflow.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
The block diagrams of the WDT_0 and WDT_1 are shown in figures 12.1 and 12.2, respectively.
12.1
Features
• Selectable from eight counter input clocks (WDT_0) or sixteen counter input clocks (WDT_1)
• Switchable between watchdog timer mode and interval timer mode
In watchdog timer mode:
• If the counter overflows, it is possible to select whether this LSI is internally reset or not or
whether an internal NMI interrupt is generated or not.
In interval timer mode:
• If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
WDT0100A_010020040800
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Section 12 Watchdog Timer (WDT)
Overflow
Internal reset signal*
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
sources
Interrupt
control
Clock
select
Clock
Reset
control
RSTCSR
TCNT_0
Internal bus
WOVI
(interrupt request
signal)
TCSR_0
Bus
interface
Module bus
WDT_0
[Legend]
TCSR_0: Timer control/status register_0
TCNT_0: Timer counter_0
RSTCSR: Reset control/status register
Note: * An internal reset signal can be generated by setting the register.
Figure 12.1 Block Diagram of WDT_0
Interrupt
control
Overflow
Internal NMI
interrupt request signal
Clock
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
select
Reset
control
Internal reset signal*
Internal clock
TCNT_1
TCSR_1
Module bus
Bus
interface
WDT_1
[Legend]
TCSR_1: Timer control/status register_1
TCNT_1: Timer counter_1
Note: * An internal reset signal can be generated by setting the register.
Figure 12.2 Block Diagram of WDT_1
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φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
Internal bus
WOVI
(interrupt request
signal)
Section 12 Watchdog Timer (WDT)
12.2
Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR, TCNT, and
RSTCSR have to be written to by a different method to normal registers. For details, see section
12.5.1, Notes on Register Access.
•
•
•
•
•
Timer counter_0 (TCNT_0)
Timer control/status register_0 (TCSR_0)
Timer counter_1 (TCNT_1)
Timer control/status register_1 (TCSR_1)
Reset control/status register (RSTCSR)
12.2.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the
TME bit in TCSR is cleared to 0.
12.2.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT and the timer mode.
• TCSR_0
Bit
Bit Name
Initial
Value
R/W
7
OVF
0
R/(W)* Overflow Flag
Description
Indicates that TCNT has overflowed. Only a write of 0 is
permitted, to clear the flag.
[Setting conditions]
•
When TCNT overflows (changes from H'FF to H'00)
•
When internal reset request generation is selected
in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing condition]
•
Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
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Section 12 Watchdog Timer (WDT)
Bit
Bit Name
Initial
Value
R/W
Description
6
WT/IT
0
R/W
Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer.
0: Interval timer mode
1: Watchdog timer mode
5
TME
0
R/W
Timer Enable
When this bit is set to 1, TCNT starts counting. When
this bit is cleared, TCNT stops counting and is initialized
to H'00.
4, 3
—
All 1
—
Reserved
These bits are always read as 1 and cannot be
modified.
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
These bits select the clock source to be input to TCNT.
The overflow frequency for φ = 20 MHz is enclosed in
parentheses.
000: Clock φ/2 (frequency: 25.6 µs)
001: Clock φ/64 (frequency: 819.2 µs)
010: Clock φ/128 (frequency: 1.6 ms)
011: Clock φ/512 (frequency: 6.6 ms)
100: Clock φ/2048 (frequency: 26.2 ms)
101: Clock φ/8192 (frequency: 104.9 ms)
110: Clock φ/32768 (frequency: 419.4 ms)
111: Clock φ/131072 (frequency: 1.68 s)
Note:
*
Only 0 can be written, for flag clearing.
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Section 12 Watchdog Timer (WDT)
• TCSR_1
Bit
Bit Name
Initial
Value
R/W
7
OVF
0
R/(W)* Overflow Flag
Description
Indicates that TCNT has overflowed from H'FF to H'00.
Only a write of 0 is permitted, to clear the flag.
[Setting conditions]
•
When TCNT overflows (changes from H'FF to H'00)
•
When internal reset request generation is selected
in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing condition]
•
6
WT/IT
0
R/W
Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer.
0: Interval timer mode
1: Watchdog timer mode
5
TME
0
R/W
Timer Enable
When this bit is set to 1, TCNT starts counting. When
this bit is cleared, TCNT stops counting and is initialized
to H'00.
4
PSS
0
R/W
Prescaler Select
Selects the clock source to be input to TCNT.
0: Counts the divided clock of φ–based prescaler (PSM)
1: Counts the divided clock of φSUB–based prescaler
(PSS)
3
RST/NMI
0
R/W
Reset or NMI
Selects whether an internal reset request or an NMI
interrupt request when the TCNT overflows during the
watchdog timer mode.
0: NMI interrupt request
1: Internal reset request
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Section 12 Watchdog Timer (WDT)
Bit
Bit Name
Initial
Value
R/W
Description
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
Selects the clock source to be input to TCNT. The
overflow cycle is the period from which TCNT starts
incrementing at H'00 and until it overflows.
When PSS = 0 (values in parentheses are for φ = 20
MHz):
000: φ/2 (cycle: 25.6 µs)
001: φ/64 (cycle: 819.2 ms)
010: φ/128 (cycle: 1.6 ms)
011: φ/512 (cycle: 6.6 ms)
100: φ/2048 (cycle: 26.2 ms)
101: φ/8192 (cycle: 104.9 ms)
110: φ/32768 (cycle: 419.4 ms)
111: φ/131072 (cycle: 1.68 s)
When PSS = 1 (values in parentheses are for φSUB =
32.768 kHz):
000: φSUB/2 (cycle: 15.6 ms)
001: φSUB/4 (cycle: 31.3 ms)
010: φSUB/8 (cycle: 62.5 ms)
011: φSUB/16 (cycle: 125 ms)
100: φSUB/32 (cycle: 250 ms)
101: φSUB/64 (cycle: 500 ms)
110: φSUB/128 (cycle: 1 s)
111: φSUB/256 (cycle: 2 s)
Note:
*
Only 0 can be written, for flag clearing.
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Section 12 Watchdog Timer (WDT)
12.2.3
Reset Control/Status Register (RSTCSR)
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
and not by the WDT internal reset signal caused by overflows.
Bit
Bit Name
Initial
Value
R/W
7
WOVF
0
R/(W)* Watchdog Overflow Flag
Description
This bit is set when TCNT overflows in watchdog timer
mode. This bit cannot be set in interval timer mode, and
only 0 can be written.
[Setting condition]
•
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
•
6
RSTE
0
R/W
Cleared by reading RSTCSR when WOVF = 1, and
then writing 0 to WOVF
Reset Enable
Specifies whether or not a reset signal is generated in
the chip if TCNT overflows during watchdog timer
operation.
0: Reset signal is not generated even if TCNT overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
1: Reset signal is generated if TCNT overflows
5
RSTS
0
R/W
Reset Select
Selects the type of internal reset generated if TCNT
overflows during watchdog timer operation.
0: Power-on reset
1: Setting prohibited
4 to 0
—
All 1
—
Reserved
These bits are always read as 1 and cannot be
modified.
Note:
*
Only 0 can be written, for flag clearing.
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Section 12 Watchdog Timer (WDT)
12.3
Operation
12.3.1
Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. TCNT
does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
When the WDT is used as a watchdog timer, and if TCNT overflows without being rewritten
because of a system malfunction or other error, a WDTOVF signal is output when using the
WDT_0.
In watchdog timer mode, the WDT can internally reset this LSI with a WDTOVF signal.
When the RSTE bit of the RSTCSR is set to 1, and if the TCNT overflows, an internal reset signal
for this LSI is issued at the same time as a WDTOVF signal. In this case, select power-on reset by
setting the RSTS bit in RSTCSR to 0.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
The WDTOVF signal is output for 132 states when the RSTE bit = 1 in RSTCSR, and for 130
states when the RSTE bit = 0.
The internal reset signal is output for 518 states. This is illustrated in figure 12.3 (a).
When the TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If the
RSTE bit in RSTCSR has been set to 1, an internal reset signal for the entire LSI is generated at
TCNT overflow.
In the case of the WDT_1, the chip is reset, or an NMI interrupt request is generated, for 516
system clock periods (516 φ) (515 or 516 states when the clock source is φSUB (PSS = 1)). This is
illustrated in figure 12.3 (b).
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are
both treated as having the same vector. So, avoid handling an NMI interrupt request from the
watchdog timer and an interrupt request from the NMI pin at the same time.
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Section 12 Watchdog Timer (WDT)
TCNT value
Overflow
H'FF
Time
H'00
WT/IT = 1
TME = 1
Write H'00
to TCNT
*1
WOVF = 1
WT/IT = 1 Write H'00
TME = 1
to TCNT
Internal reset is
generated
Internal reset signal* 2
518 states
[Legend]
Timer mode select bit
WT/IT:
Timer enable bit
TME:
Notes: 1. After the WOVF bit becomes 1, it is cleared to 0 by an internal reset.
2. The internal reset signal is generated only if the RSTE bit is set to 1.
Figure 12.3 (a) WDT_0 Operation in Watchdog Timer Mode
TCNT value
Overflow
H'FF
Time
H'00
WT/IT = 1
TME = 1
Write H'00
to TCNT
WOVF = 1*1
WT/IT = 1
TME = 1
Write H'00
to TCNT
Internal reset
is generated
2
Internal reset signal*
515/516 states
[Legend]
WT/IT:
Timer mode select bit
TME:
Timer enable bit
Notes: 1. After the WOVF bit becomes 1, it is cleared to 0 by an internal reset.
2. The internal reset signal is generated only if the RSTE bit is set to 1.
Figure 12.3 (b) WDT_1 Operation in Watchdog Timer Mode
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Section 12 Watchdog Timer (WDT)
12.3.2
Interval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows. Therefore, an interrupt can be generated at intervals.
When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested
at the time the OVF bit of the TCSR is set to 1.
12.4
Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
If an NMI interrupt request has been selected in watchdog timer mode, an NMI interrupt request is
generated when the TCNT overflows.
Table 12.1 WDT Interrupt Sources
Name
Interrupt Source
Interrupt Flag
WOVI
TCNT overflow (interval timer mode)
OVF
NMI
TCNT overflow (watchdog timer mode)
OVF
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Section 12 Watchdog Timer (WDT)
12.5
Usage Notes
12.5.1
Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT, TCSR, and RSTCSR
These registers must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
TCNT and TCSR both have the same write address. Therefore, the relative condition shown in
figure 12.4 needs to be satisfied in order to write to TCNT or TCSR. The transfer instruction
writes the lower byte data to TCNT or TCSR according to the satisfied condition.
To write to RSTCSR, execute a word transfer instruction for address H'FF76. A byte transfer
instruction cannot write to RSTCSR.
The method of writing 0 to the WOVF bit differs from that of writing to the RSTE and RSTS bits.
To write 0 to the WOVF bit, satisfy the condition shown in figure 12.4. If satisfied, the transfer
instruction clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to
the RSTE and RSTS bits, satisfy the condition shown in figure 12.4. If satisfied, the transfer
instruction writes the values in bits 5 and 6 of the lower byte into the RSTE and RSTS bits,
respectively, but has no effect on the WOVF bit.
TCNT write
Writing to RSTE and RSTS bits
Address: H'FF74
H'FF76
15
8
H'5A
7
0
Write data
TCSR write
Writing 0 to WOVF bit
Address: H'FF74
H'FF76
15
8
H'A5
7
0
Write data or H'00
Figure 12.4 Writing to TCNT, TCSR, and RSTCSR (example for WDT0)
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Section 12 Watchdog Timer (WDT)
Reading TCNT, TCSR, and RSTCSR (WDT0)
These registers are read in the same way as other registers. The read addresses are H'FF74 for
TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR.
12.5.2
Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 12.5 shows this operation.
TCNT write cycle
T1
T2
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.5 Contention between TCNT Write and Increment
12.5.3
Changing Value of CKS2 to CKS0
If bits CKS0 to CKS2 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to
0) before changing the value of bits CKS0 to CKS2.
12.5.4
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer while the WDT is operating, errors
could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing
the TME bit to 0) before switching the mode.
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Section 12 Watchdog Timer (WDT)
12.5.5
Internal Reset in Watchdog Timer Mode
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer operation, however TCNT and TCSR of the WDT are reset.
TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this
period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states
after overflow to write 0 to the WOVF flag for clearing.
12.5.6
OVF Flag Clearing in Interval Timer Mode
When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0
to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there
is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is
polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before
writing 0 to the OVF bit to clear the flag.
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Section 12 Watchdog Timer (WDT)
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Section 13 Serial Communication Interface (SCI)
Section 13 Serial Communication Interface (SCI)
This LSI has four independent serial communication interface (SCI) channels. The SCI can handle
both asynchronous and clocked synchronous serial communication. Serial data communication
can be carried out using standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface
Adapter (ACIA). A function is also provided for serial communication between processors
(multiprocessor communication function). The SCI also supports an IC card (smart card) interface
conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension
function.
Figure 13.1 shows a block diagram of the SCI.
13.1
Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
External clock can be selected as a transfer clock source (except for in Smart card interface
mode).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, and receive error  that can issue
requests.
The transmit-data-empty interrupt and receive data full interrupts can be used to activate the
data transfer controller (DTC).
• Module stop mode can be set
Asynchronous mode
•
•
•
•
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
SCI0027B_0000020040900
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Section 13 Serial Communication Interface (SCI)
• Break detection: Break can be detected by reading the RxD pin level directly in the case of a
framing error
Clocked Synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Smart Card Interface
Bus interface
• Automatic transmission of error signal (parity error) in receive mode
• Error signal detection and automatic data retransmission in transmit mode
• Direct convention and inverse convention both supported
Module data bus
RDR
TDR
BRR
SCMR
SSR
RxD
TxD
SCR
RSR
TSR
SMR
Baud rate
generator
Transmission/
reception control
Parity generation
φ
φ/4
φ/16
φ/64
Clock
Parity check
External clock
SCK
[Legend]
RSR:
Receive shift register
RDR:
Receive data register
TSR:
Transmit shift register
TDR:
Transmit data register
SMR: Serial mode register
SCR:
Serial control register
SSR:
Serial status register
SCMR: Smart card mode register
BRR:
Bit rate register
Figure 13.1 Block Diagram of SCI
Rev. 2.00 Dec. 05, 2005 Page 352 of 724
REJ09B0200-0200
TEI
TXI
RXI
ERI
Internal
data bus
Section 13 Serial Communication Interface (SCI)
13.2
Input/Output Pins
Table 13.1 shows the serial pins for each SCI channel.
Table 13.1 Pin Configuration
Channel
Pin Name*
I/O
Function
0
SCK0
I/O
SCI0 clock input/output
RxD0
Input
SCI0 receive data input
TxD0
Output
SCI0 transmit data output
SCK1
I/O
SCI1 clock input/output
1
2
4
Note:
*
RxD1
Input
SCI1 receive data input
TxD1
Output
SCI1 transmit data output
SCK2
I/O
SCI2 clock input/output
RxD2
Input
SCI2 receive data input
TxD2
Output
SCI2 transmit data output
SCK4
I/O
SCI4 clock input/output
RxD4
Input
SCI4 receive data input
TxD4
Output
SCI4 transmit data output
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
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Section 13 Serial Communication Interface (SCI)
13.3
Register Descriptions
The SCI has the following registers for each channel. The serial mode register (SMR), serial status
register (SSR), and serial control register (SCR) are described separately for normal serial
communication interface mode and smart card interface mode because their bit functions differ in
part.
•
•
•
•
•
•
•
•
•
Receive shift register (RSR)
Receive data register (RDR)
Transmit data register (TDR)
Transmit shift register (TSR)
Serial mode register (SMR)
Serial control register (SCR)
Serial status register (SSR)
Smart card mode register (SCMR)
Bit rate register (BRR)
13.3.1
Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
13.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI has received one byte of serial
data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is
receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive
operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only
once. RDR cannot be written to by the CPU.
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Section 13 Serial Communication Interface (SCI)
13.3.3
Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI detects that TSR is empty,
it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structure of TDR and TSR enables continuous serial transmission. If the next transmit data has
already been written to TDR during serial transmission, the SCI transfers the written data to TSR
to continue transmission. Although TDR can be read or written to by the CPU at all times, to
achieve reliable serial transmission, write transmit data to TDR only once after confirming that the
TDRE bit in SSR is set to 1.
13.3.4
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be
directly accessed by the CPU.
13.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source.
Some bit functions of SMR differ between normal serial communication interface mode and smart
card interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
Bit Name
Initial
Value
R/W
Description
7
C/A
0
R/W
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6
CHR
0
R/W
Character Length (enabled only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is fixed
and the MSB of TDR is not transmitted in
transmission.
In clocked synchronous mode, a fixed data length of 8
bits is used.
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Section 13 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
Value
R/W
Description
5
PE
0
R/W
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. For a multiprocessor format,
parity bit addition and checking are not performed
regardless of the PE bit setting.
4
O/E
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the
next transmit character.
2
MP
0
R/W
Multiprocessor Mode (enabled only in asynchronous
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and O/E
bit settings are invalid in multiprocessor mode.
1
CKS1
0
R/W
Clock Select 0 and 1:
0
CKS0
0
R/W
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register setting
and the baud rate, see section 13.3.9, Bit Rate Register
(BRR). n is the decimal representation of the value of n
in BRR (see section 13.3.9, Bit Rate Register (BRR)).
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Section 13 Serial Communication Interface (SCI)
• Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
Bit Name
Initial
Value
R/W
Description
7
GM
0
R/W
GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND setting is
advanced by 11.0 etu (Elementary Time Unit: the time
for transfer of one bit), and clock output control mode
addition is performed. For details, see section 13.7.8,
Clock Output Control.
6
BLK
0
R/W
When this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode, see
section 13.7.3, Block Transfer Mode.
5
PE
0
R/W
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data in transmission, and the parity bit is
checked in reception. In smart card interface mode, this
bit must be set to 1.
4
O/E
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
For details on setting this bit in smart card interface
mode, see section 13.7.2, Data Format (Except for
Block Transfer Mode).
3
BCP1
0
R/W
Basic Clock Pulse 1 and 2
2
BCP0
0
R/W
These bits specify the number of basic clock periods in
a 1-bit transfer interval on the smart card interface.
00: 32 clock (S = 32)
01: 64 clock (S = 64)
10: 372 clock (S = 372)
11: 256 clock (S = 256)
For details, see section 13.7.4, Receive Data Sampling
Timing and Reception Margin in smart card Interface
Mode. S stands for the value of S in BRR (see section
13.3.9, Bit Rate Register (BRR)).
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Section 13 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
Value
R/W
Description
1
CKS1
0
R/W
Clock Select 0 and 1
0
CKS0
0
R/W
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register setting
and the baud rate, see section 13.3.9, Bit Rate Register
(BRR). n is the decimal representation of the value of n
in BRR (see section 13.3.9, Bit Rate Register (BRR)).
13.3.6
Serial Control Register (SCR)
SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also
used to selection of the transfer clock source. For details on interrupt requests, see section 13.8,
Interrupt Sources. Some bit functions of SCR differ between normal serial communication
interface mode and smart card interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
Bit Name
Initial
Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5
TE
0
R/W
Transmit Enable
4
RE
0
R/W
Receive Enable
When this bit s set to 1, transmission is enabled.
When this bit is set to 1, reception is enabled.
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Section 13 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
Value
R/W
Description
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, see
section 13.5, Multiprocessor Communication Function.
2
TEIE
0
R/W
Transmit End Interrupt Enable
This bit is set to 1, TEI interrupt request is enabled.
1
CKE1
0
R/W
Clock Enable 0 and 1
0
CKE0
0
R/W
Selects the clock source and SCK pin function.
Asynchronous mode
00: Internal baud rate generator
SCK pin functions as I/O port
01: Internal baud rate generator
Outputs a clock of the same frequency as the bit
rate from the SCK pin.
1X: External clock
Inputs a clock with a frequency 16 times the bit rate
from the SCK pin.
Clocked synchronous mode
0X: Internal clock (SCK pin functions as clock output)
1X: External clock (SCK pin functions as clock input)
[Legend]
X:
Don't care
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Section 13 Serial Communication Interface (SCI)
• Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
Bit Name
Initial
Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5
TE
0
R/W
Transmit Enable
When this bit is set to 1, transmission is enabled.
4
RE
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled.
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in smart card interface mode.
2
TEIE
0
R/W
Transmit End Interrupt Enable
Write 0 to this bit in smart card interface mode.
1
CKE1
0
R/W
Clock Enable 0 and 1
0
CKE0
0
R/W
Enables or disables clock output from the SCK pin. The
clock output can be dynamically switched in GSM
mode. For details, see section 13.7.8, Clock Output
Control.
When the GM bit in SMR is 0:
00: Output disabled (SCK pin can be used as an I/O
port pin)
01: Clock output
1X: Reserved
When the GM bit in SMR is 1:
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
[Legend]
X:
Don't care
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Section 13 Serial Communication Interface (SCI)
13.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ between normal serial communication interface mode and smart card
interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
Bit Name
Initial
Value
R/W
Description
7
TDRE
1
R/W
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR and data
can be written to TDR
[Clearing conditions]
6
RDRF
0
R/W
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DTC is activated by a TXI interrupt
request and writes data to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF = 1
•
When the DTC is activated by an RXI interrupt and
transferred data from RDR
The RDRF flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
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Section 13 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
Value
R/W
Description
5
ORER
0
R/W
Overrun Error
[Setting condition]
•
When the next serial reception is completed while
RDRF = 1
[Clearing condition]
•
4
FER
0
R/W
When 0 is written to ORER after reading ORER = 1
Framing Error
[Setting condition]
•
When the stop bit is 0
[Clearing condition]
•
When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
3
PER
0
R/W
Parity Error
[Setting condition]
•
When a parity error is detected during reception
[Clearing condition]
•
2
TEND
1
R
When 0 is written to PER after reading PER = 1
Transmit End
[Setting conditions]
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
[Clearing conditions]
1
MPB
0
R
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DTC is activated by a TXI interrupt and
writes data to TDR
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0 its previous
state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit data.
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Section 13 Serial Communication Interface (SCI)
• Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
Bit Name
Initial
Value
R/W
Description
7
TDRE
1
R/W
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR and data
can be written to TDR
[Clearing conditions]
6
RDRF
0
R/W
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DTC is activated by a TXI interrupt
request and writes data to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF = 1
•
When the DTC is activated by an RXI interrupt and
transferred data from RDR
The RDRF flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
5
ORER
0
R/W
Overrun Error
[Setting condition]
•
When the next serial reception is completed while
RDRF = 1
[Clearing condition]
•
4
ERS
0
R/W
When 0 is written to ORER after reading ORER = 1
Error Signal Status
[Setting condition]
•
When the low level of the error signal is sampled
[Clearing conditions]
•
When 0 is written to ERS after reading ERS = 1
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Section 13 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
Value
R/W
Description
3
PER
0
R/W
Parity Error
[Setting condition]
•
When a parity error is detected during reception
[Clearing condition]
•
2
TEND
1
R
When 0 is written to PER after reading PER = 1
Transmit End
This bit is set to 1 when no error signal has been sent
back from the receiving end and the next transmit data
is ready to be transferred to TDR.
[Setting conditions]
•
When the TE bit in SCR is 0 and the ERS bit is also
0
•
When the ERS bit is 0 and the TDRE bit is 1 after
the specified interval following transmission of 1byte data.
The timing of bit setting differs according to the
register setting as follows:
When GM = 0 and BLK = 0, 2.5 etu after
transmission starts
When GM = 0 and BLK = 1, 1.5 etu after
transmission starts
When GM = 1 and BLK = 0, 1.0 etu after
transmission starts
When GM = 1 and BLK = 1, 1.0 etu after
transmission starts
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DTC is activated by a TXI interrupt and
writes data to TDR
1
MPB
0
R
Multiprocessor Bit
0
MPBT
0
R/W
Multiprocessor Bit Transfer
This bit is not used in smart card interface mode.
Write 0 to this bit in smart card interface mode.
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Section 13 Serial Communication Interface (SCI)
13.3.8
Smart Card Mode Register (SCMR)
SCMR is a register that selects smart card interface mode and its format.
Bit
Bit Name
7 to 4 
Initial
Value
R/W
Description
All 1

Reserved
These bits are always read as 1.
3
SDIR
0
R/W
Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer data
format is 8 bits. For 7-bit data, LSB-first is fixed.
2
SINV
0
R/W
Smart Card Data Invert
Specifies inversion of the data logic level. The SINV bit
does not affect the logic level of the parity bit. To invert
the parity bit, invert the O/E bit in SMR.
0: TDR contents are transmitted as they are. Receive
data is stored as it is in RDR
1: TDR contents are inverted before being transmitted.
Receive data is stored in inverted form in RDR
1

1

Reserved
This bit is always read as 1.
0
SMIF
0
R/W
Smart Card Interface Mode Select
This bit is set to 1 to make the SCI operate in smart
card interface mode.
0: Normal asynchronous mode or clocked synchronous
mode
1: Smart card interface mode
Rev. 2.00 Dec. 05, 2005 Page 365 of 724
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Section 13 Serial Communication Interface (SCI)
13.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 13.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 13.2 The Relationships between The N Setting in BRR and Bit Rate B
Mode
BRR Setting N
Asynchronous
Mode
N=
Clocked
Synchronous
Mode
N=
Smart Card
Interface Mode
N=
[Legend]
B:
N:
φ:
n and S:
φ × 106
64 × 2 2n−1 × B
φ × 106
8 × 2 2n−1 × B
φ × 106
S × 2 2n+1 × B
Error
−1
Error (%) = {
φ × 106
B × 64 × 2 2n−1 × (N + 1)
− 1 } × 100
−1
− 1 Error (%) = {
φ × 106
B × S × 2 2n+1 × (N + 1)
− 1 } × 100
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Determined by the SMR settings shown in the following tables.
SMR Setting
SMR Setting
CKS1
CKS0
n
BCP1
BCP0
S
0
0
0
0
0
32
0
1
1
0
1
64
1
0
2
1
0
372
1
1
3
1
1
256
Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 13.6 shows sample N
settings in BRR in clocked synchronous mode. Table 13.8 shows sample N settings in BRR in
smart card interface mode. In smart card interface mode, S (the number of basic clock periods in a
1-bit transfer interval) can be selected. For details, see section 13.7.4, Receive Data Sampling
Timing and Reception Margin in smart card Interface Mode. Tables 13.5 and 13.7 show the
maximum bit rates with external clock input.
Rev. 2.00 Dec. 05, 2005 Page 366 of 724
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Section 13 Serial Communication Interface (SCI)
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency φ (MHz)
4
4.9152
5
Bit Rate
(bit/s)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
110
2
70
0.03
2
86
0.31
2
88
–0.25
150
1
207
0.16
1
255
0.00
2
64
0.16
300
1
103
0.16
1
127
0.00
1
129
0.16
600
0
207
0.16
0
255
0.00
1
64
0.16
1200
0
103
0.16
0
127
0.00
0
129
0.16
2400
0
51
0.16
0
63
0.00
0
64
0.16
4800
0
25
0.16
0
31
0.00
0
32
–1.36
9600
0
12
0.16
0
15
0.00
0
15
1.73
19200



0
7
0.00
0
7
1.73
31250
0
3
0.00
0
4
–1.70
0
4
0.00
38400



0
3
0.00
0
3
1.73
Operating Frequency φ (MHz)
6
6.144
7.3728
8
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
106
–0.44
2
108
0.08
2
130
–0.07
2
141
0.03
150
2
77
0.16
2
79
0.00
2
95
0.00
2
103
0.16
300
1
155
0.16
1
159
0.00
1
191
0.00
1
207
0.16
600
1
77
0.16
1
79
0.00
1
95
0.00
1
103
0.16
1200
0
155
0.16
0
159
0.00
0
191
0.00
0
207
0.16
2400
0
77
0.16
0
79
0.00
0
95
0.00
0
103
0.16
4800
0
38
0.16
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
–2.34
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
–2.34
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.40



0
7
0.00
38400
0
4
–2.34
0
4
0.00
0
5
0.00



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Section 13 Serial Communication Interface (SCI)
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency φ (MHz)
9.8304
10
12
12.288
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
174
–0.26
2
177
–0.25
2
212
0.03
2
217
0.08
150
2
127
0.00
2
129
0.16
2
155
0.16
2
159
0.00
300
1
255
0.00
2
64
0.16
2
77
0.16
2
79
0.00
600
1
127
0.00
1
129
0.16
1
155
0.16
1
159
0.00
1200
0
255
0.00
1
64
0.16
1
77
0.16
1
79
0.00
2400
0
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
4800
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
–1.36
0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
0
19
–2.34
0
19
0.00
31250
0
9
–1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
0
7
0.00
0
7
1.73
0
9
–2.34
0
9
0.00
Operating Frequency φ (MHz)
14
14.7456
Bit Rate
(bit/s)
n
N
Error
(%)
110
2
248
–0.17
3
64
0.70
150
2
181
0.13
2
191
0.00
300
2
90
0.13
2
95
0.00
600
1
181
0.13
1
191
1200
1
90
0.13
1
2400
0
181
0.13
4800
0
90
9600
0
19200
31250
38400
17.2032
N
Error
(%)
n
N
Error
(%)
3
70
0.03
3
75
0.48
2
207
0.13
2
223
0.00
2
103
0.13
2
111
0.00
0.00
1
207
0.13
1
223
0.00
95
0.00
1
103
0.13
1
111
0.00
0
191
0.00
0
207
0.13
0
223
0.00
0.13
0
95
0.00
0
103
0.13
0
111
0.00
45
–0.93
0
47
0.00
0
51
0.13
0
55
0.00
0
22
–0.93
0
23
0.00
0
25
0.13
0
27
0.00
0
13
0.00
0
14
–1.70
0
15
0.00
0
13
1.20



0
11
0.00
0
12
0.13
0
13
0.00
n
Rev. 2.00 Dec. 05, 2005 Page 368 of 724
REJ09B0200-0200
N
Error
(%)
16
n
Section 13 Serial Communication Interface (SCI)
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
Operating Frequency φ (MHz)
18
19.6608
20
24
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
79
–0.12
3
86
0.31
3
88
–0.25
3
106
–0.44
150
2
233
0.16
2
255
0.00
3
64
0.16
3
77
0.16
300
2
116
0.16
2
127
0.00
2
129
0.16
2
155
0.16
600
1
233
0.16
1
255
0.00
2
64
0.16
2
77
0.16
1200
1
116
0.16
1
127
0.00
1
129
0.16
1
155
0.16
2400
0
233
0.16
0
255
0.00
1
64
0.16
1
77
0.16
4800
0
116
0.16
0
127
0.00
0
129
0.16
0
155
0.16
9600
0
58
–0.69
0
63
0.00
0
64
0.16
0
77
0.16
19200
0
28
1.02
0
31
0.00
0
32
–1.36
0
38
0.16
31250
0
17
0.00
0
19
–1.70
0
19
0.00
0
23
0
38400
0
14
–2.34
0
15
0.00
0
15
1.73
0
19
–2.34
Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
4
125000
0
0
12
375000
0
0
4.9152
153600
0
0
12.288
384000
0
0
5
156250
0
0
14
437500
0
0
6
187500
0
0
14.7456
460800
0
0
6.144
192000
0
0
16
500000
0
0
7.3728
230400
0
0
17.2032
537600
0
0
8
250000
0
0
18
562500
0
0
9.8304
307200
0
0
19.6608
614400
0
0
10
312500
0
0
20
625000
0
0
24
750000
0
0
Rev. 2.00 Dec. 05, 2005 Page 369 of 724
REJ09B0200-0200
Section 13 Serial Communication Interface (SCI)
Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
4
1.0000
62500
12
3.0000
187500
4.9152
1.2288
76800
12.288
3.0720
192000
5
1.2500
78125
14
3.5000
218750
6
1.5000
93750
14.7456
3.6864
230400
6.144
1.5360
96000
16
4.0000
250000
7.3728
1.8432
115200
17.2032
4.3008
268800
8
2.0000
125000
18
4.5000
281250
9.8304
2.4576
153600
19.6608
4.9152
307200
10
2.5000
156250
20
5.0000
312500
24
6.0000
375000
Rev. 2.00 Dec. 05, 2005 Page 370 of 724
REJ09B0200-0200
Section 13 Serial Communication Interface (SCI)
Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency φ (MHz)
Bit Rate
(bit/s)
4
n
N
8
10
16
n
N
n
N
n
N
20
24
n
N
n
N
110


250
2
249
3
124


3
249
500
2
124
2
249


3
124




1k
1
249
2
124


2
249




2.5k
1
99
1
199
1
249
2
99
2
124
2
149
5k
0
199
1
99
1
124
1
199
1
249
2
74
10k
0
99
0
199
0
249
1
99
1
124
1
149
25k
0
39
0
79
0
99
0
159
0
199
1
59
50k
0
19
0
39
0
49
0
79
0
99
1
29
100k
0
9
0
19
0
24
0
39
0
49
0
59
250k
0
3
0
7
0
9
0
15
0
19
0
23
500k
0
1
0
3
0
4
0
7
0
9
0
11
1M
0
0*
0
1
0
3
0
4
0
5
0
1


0
0*


2.5M
0
0*
5M
[Legend]
Blank: Setting prohibited.
:
Can be set, but there will be a degree of error.
*:
Continuous transfer is not possible.
Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
4
0.6667
666666.7
14
2.3333
2333333.3
6
1.0000
1.000000.0
16
2.6667
2666666.7
8
1.3333
1333333.3
18
3.0000
3000000.0
10
1.6667
1666666.7
20
3.3333
3333333.3
12
2.0000
2000000.0
24
4
4000000.0
Rev. 2.00 Dec. 05, 2005 Page 371 of 724
REJ09B0200-0200
Section 13 Serial Communication Interface (SCI)
Table 13.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(When n = 0 and S = 372)
Operating Frequency φ (MHz)
7.1424
10.00
10.7136
13.00
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
9600
0
0
0.00
0
1
30
0
1
25
0
1
8.99
Operating Frequency φ (MHz)
14.2848
16.00
18.00
20.00
24.00
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
N
N
Error
(%)
n
n
Error
(%)
9600
0
1
0.00
0
1
12.01
0
2
15.99
0
2
6.60
0
2
12.01
Table 13.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372)
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
7.1424
9600
0
0
14.2848
19200
0
0
10.00
13441
0
0
16.00
21505
0
0
10.7136
14400
0
0
18.00
24194
0
0
13.00
17473
0
0
20.00
26882
0
0
24.00
32258
0
0
Rev. 2.00 Dec. 05, 2005 Page 372 of 724
REJ09B0200-0200
Section 13 Serial Communication Interface (SCI)
13.4
Operation in Asynchronous Mode
Figure 13.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). In asynchronous serial communication, the transmission line is
usually held in the mark state (high level). The SCI monitors the transmission line. When the
transmission line goes to the space state (low level), the SCI recognizes a start bit and starts serial
communication. In asynchronous serial communication, the communication line is usually held in
the mark state (high level). The SCI monitors the communication line, and when it goes to the
space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the
transmitter and receiver are independent units, enabling full-duplex. Both the transmitter and the
receiver also have a double-buffered structure, so data can be read or written during transmission
or reception, enabling continuous data transfer.
1
Serial
data
LSB
D0
0
Idle state
(mark state)
1
MSB
D1
D2
D3
D4
D5
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
D6
D7
0/1
Parity
bit
1 bit,
or none
1
1
Stop bit
1 or
2 bits
One unit of transfer data (character or frame)
Figure 13.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
13.4.1
Data Transfer Format
Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, see section 13.5, Multiprocessor Communication Function.
Rev. 2.00 Dec. 05, 2005 Page 373 of 724
REJ09B0200-0200
Section 13 Serial Communication Interface (SCI)
Table 13.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings
Serial Transfer Format and Frame Length
CHR
PE
MP
STOP
1
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
[Legend]
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
Rev. 2.00 Dec. 05, 2005 Page 374 of 724
REJ09B0200-0200
2
3
4
5
6
7
8
9
10
11
12
Section 13 Serial Communication Interface (SCI)
13.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer
rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and
performs internal synchronization. Receive data is latched internally at the rising edge of the 8th
pulse of the basic clock as shown in figure 13.3. Thus, the reception margin in asynchronous mode
is given by formula (1) below.
M = { (0.5 –
1
D – 0.5
)–
2N
N
– (L – 0.5) F} × 100 [%]
... Formula (1)
Where N: Ratio of bit rate to clock (N = 16)
D: Clock duty cycle (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty cycle) = 0.5
in formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal basic
clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode
Rev. 2.00 Dec. 05, 2005 Page 375 of 724
REJ09B0200-0200
Section 13 Serial Communication Interface (SCI)
13.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in
SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 13.4.
SCK
0
TxD
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 13.4 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)
Rev. 2.00 Dec. 05, 2005 Page 376 of 724
REJ09B0200-0200
Section 13 Serial Communication Interface (SCI)
13.4.4
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize
the SCI as described below. When the operating mode, or transfer format, is changed for example,
the TE and RE bits must be cleared to 0 before making the change using the following procedure.
When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does
not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
When the external clock is used in asynchronous mode, the clock must be supplied even during
initialization.
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are cleared to 0.)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if
an external clock is used.
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
[4]
<Initialization completion>
Figure 13.5 Sample SCI Initialization Flowchart
Rev. 2.00 Dec. 05, 2005 Page 377 of 724
REJ09B0200-0200
Section 13 Serial Communication Interface (SCI)
13.4.5
Data Transmission (Asynchronous Mode)
Figure 13.6 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI)
is generated. Continuous transmission is possible because the TXI interrupt routine writes next
transmit data to TDR before transmission of the current transmit data has been completed.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark
state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 13.7 shows a sample flowchart for transmission in asynchronous mode.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
Data written to TDR and
TXI interrupt
request generated TDRE flag cleared to 0 in
request generated
TXI interrupt service routine
TEI interrupt
request generated
1 frame
Figure 13.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 2.00 Dec. 05, 2005 Page 378 of 724
REJ09B0200-0200
Section 13 Serial Communication Interface (SCI)
[1]
Initialization
Start transmission
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
No
TDRE = 1
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes
[3]
Read TEND flag in SSR
No
TEND = 1
Yes
No
Break output?
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[4]
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DTC is
activated by a transmit data empty
interrupt (TXI) request, and data is
written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 13.7 Sample Serial Transmission Flowchart
Rev. 2.00 Dec. 05, 2005 Page 379 of 724
REJ09B0200-0200
Section 13 Serial Communication Interface (SCI)
13.4.6
Serial Data Reception (Asynchronous Mode)
Figure 13.8 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
RDRF
FER
RXI interrupt
request
generated
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt service routine
1 frame
Figure 13.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
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ERI interrupt request
generated by framing
error
Section 13 Serial Communication Interface (SCI)
Table 13.11 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error is detected, the RDRF flag retains its state before receiving
data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the
ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.9 shows a sample
flow chart for serial data reception.
Table 13.11 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF*
ORER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR
Framing error
0
0
0
1
Transferred to RDR
Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
1
Lost
Overrun error + framing error +
parity error
Note:
*
The RDRF flag retains the state it had before data reception.
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Section 13 Serial Communication Interface (SCI)
Initialization
[1]
Start reception
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing and break
detection:
[2]
If a receive error occurs, read the
ORER, PER, and FER flags in SSR to
identify the error. After performing the
Yes
appropriate error processing, ensure
PER∨FER∨ORER = 1
that the ORER, PER, and FER flags are
[3]
all cleared to 0. Reception cannot be
No
Error processing
resumed if any of these flags are set to
1. In the case of a framing error, a
(Continued on next page)
break can be detected by reading the
value of the input port corresponding to
[4]
Read RDRF flag in SSR
the RxD pin.
Read ORER, PER, and
FER flags in SSR
[4] SCI status check and receive data read:
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
No
RDRF = 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[5] Serial reception continuation procedure:
To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag, read
RDR, and clear the RDRF flag to 0.
The RDRF flag is cleared automatically
when DTC is activated by an RXI
interrupt and the RDR value is read.
<End>
Figure 13.9 Sample Serial Reception Data Flowchart (1)
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Section 13 Serial Communication Interface (SCI)
[3]
Error processing
No
ORER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCR to 0
No
PER = 1
Yes
Parity error processing
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 13.9 Sample Serial Reception Data Flowchart (2)
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Section 13 Serial Communication Interface (SCI)
13.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of
processors sharing communication lines by asynchronous serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data. When
multiprocessor communication is performed, each receiving station is addressed by a unique ID
code. The serial communication cycle consists of two component cycles; an ID transmission cycle
that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to
differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 13.10 shows an example of inter-processor
communication using the multiprocessor format. The transmitting station first sends the ID code
of the receiving station with which it wants to perform serial communication as data with a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and ORER to 1, are inhibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the
MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to
1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
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Section 13 Serial Communication Interface (SCI)
Transmitting
station
Serial transmission line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB = 1)
(MPB = 0)
ID transmission cycle = Data transmission cycle =
receiving station
Data transmission to
specification
receiving station specified by ID
[Legend]
MPB: Multiprocessor bit
Figure 13.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
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Section 13 Serial Communication Interface (SCI)
13.5.1
Multiprocessor Serial Data Transmission
Figure 13.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
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Section 13 Serial Communication Interface (SCI)
[1]
Initialization
Start transmission
Read TDRE flag in SSR
[2]
No
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
TDRE = 1
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
[3]
Yes
Read TEND flag in SSR
No
TEND = 1
Yes
No
Break output?
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
[4]
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DTC is activated by a transmit
data empty interrupt (TXI)
request, and data is written to
TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart
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Section 13 Serial Communication Interface (SCI)
13.5.2
Multiprocessor Serial Data Reception
Figure 13.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
13.12 shows an example of SCI operation for multiprocessor format reception.
1
Start
bit
0
Data (ID1)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data1)
D0
D1
Stop
MPB bit
D7
0
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
If not this station’s ID,
MPIE bit is set to 1
again
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
service routine
RXI interrupt request is
not generated, and RDR
retains its state
(a) Data does not match station’s ID
1
Start
bit
0
Data (ID2)
D0
D1
Stop
MPB bit
D7
1
1
Start
bit
0
Data (Data2)
D0
D1
D7
Stop
MPB bit
0
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
Data2
ID2
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt service routine
MPIE bit set to 1
again
(b) Data matches station’s ID
Figure 13.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 13 Serial Communication Interface (SCI)
Initialization
[1] SCI initialization:
The RxD pin is automatically designated
as the receive data input pin.
[1]
Start reception
Read MPIE bit in SCR
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
[2]
[3] SCI status check, ID reception and
comparison:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and compare it with this
station’s ID.
If the data is not this station’s ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
If the data is this station’s ID, clear the
RDRF flag to 0.
Read ORER and FER flags in SSR
Yes
FER∨ORER = 1
No
Read RDRF flag in SSR
[3]
No
RDRF = 1
[4] SCI status check and data reception:
Read SSR and check that the RDRF
flag is set to 1, then read the data in
RDR.
Yes
Read receive data in RDR
No
This station’s ID?
Yes
Read ORER and FER flags in SSR
Yes
FER∨ORER = 1
No
Read RDRF flag in SSR
[5] Receive error processing and break
detection:
If a receive error occurs, read the ORER
and FER flags in SSR to identify the
error. After performing the appropriate
error processing, ensure that the ORER
and FER flags are all cleared to 0.
Reception cannot be resumed if either
of these flags is set to 1.
In the case of a framing error, a break
can be detected by reading the RxD pin
[4]
value.
No
RDRF = 1
Yes
Read receive data in RDR
No
All data received?
[5]
Error processing
Yes
Clear RE bit in SCR to 0
(Continued on
next page)
<End>
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 13 Serial Communication Interface (SCI)
[5]
Error processing
No
ORER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCR to 0
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 13 Serial Communication Interface (SCI)
13.6
Operation in Clocked Synchronous Mode
Figure 13.14 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received synchronous with clock pulses. In clocked
synchronous serial communication, data on the transmission line is output from one falling edge of
the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronous
with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the
MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI,
the transmitter and receiver are independent units, enabling full-duplex communication through
the use of a common clock. Both the transmitter and the receiver also have a double-buffered
structure, so data can be read or written during transmission or reception, enabling continuous data
transfer.
One unit of transfer data (character or frame)
*
*
Synchronization
clock
MSB
LSB
Bit 0
Serial data
Bit 1
Don’t care
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Note:* High except in continuous transfer
Figure 13.14 Data Format in Synchronous Communication (For LSB-First)
13.6.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of CKE0 and
CKE1 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from
the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no
transfer is performed the clock is fixed high.
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Section 13 Serial Communication Interface (SCI)
13.6.2
SCI Initialization (Clocked Synchronous Mode)
Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, then the
SCI should be initialized as described in a sample flowchart in figure 13.15. When the operating
mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before
making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag
is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER,
FER, and ORER flags, or the contents of RDR.
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
Start initialization
Clear TE and RE bits in SCR to 0
[2] Set the data transfer format in SMR and
SCMR.
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
Wait
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
No
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
[4]
<Transfer start>
Note:* In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
to 0 or set to 1 simultaneously.
Figure 13.15 Sample SCI Initialization Flowchart
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Section 13 Serial Communication Interface (SCI)
13.6.3
Serial Data Transmission (Clocked Synchronous Mode)
Figure 13.16 shows an example of SCI operation for transmission in clocked synchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has
been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI)
is generated. Continuous transmission is possible because the TXI interrupt routine writes the
next transmit data to TDR before transmission of the current transmit data has been completed.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified.
4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request
is generated. The SCK pin is fixed high.
Figure 13.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission. Note that
clearing the RE bit to 0 does not clear the receive error flags.
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Section 13 Serial Communication Interface (SCI)
Transfer direction
Synchronization
clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request generated
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
service routine
TXI interrupt
request generated
TEI interrupt request
generated
1 frame
Figure 13.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
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Section 13 Serial Communication Interface (SCI)
Initialization
[1]
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
All data transmitted?
[3]
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit data empty
interrupt (TXI) request and data is
written to TDR.
Read TEND flag in SSR
No
TEND = 1
Yes
Clear TE bit in SCR to 0
<End>
Figure 13.17 Sample Serial Transmission Flowchart
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Section 13 Serial Communication Interface (SCI)
13.6.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 13.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization synchronous with a synchronous clock input or output,
starts receiving data, and stores the received data in RSR.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
3. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has finished.
Synchronization
clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt
request
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
RXI interrupt
request generated
ERI interrupt request
generated by overrun
error
1 frame
Figure 13.18 Example of SCI Operation in Reception
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.19 shows a sample flow
chart for serial data reception.
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Section 13 Serial Communication Interface (SCI)
Initialization
[1]
Start reception
[2]
Read ORER flag in SSR
Yes
ORER = 1
[3]
No
Error processing
(Continued below)
Read RDRF flag in SSR
[4]
No
RDRF = 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
[4] SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI
interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception, before
the MSB (bit 7) of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished. The
RDRF flag is cleared automatically
when the DTC is activated by a
receive data full interrupt (RXI) request
and the RDR value is read.
<End>
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
<End>
Figure 13.19 Sample Serial Reception Flowchart
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Section 13 Serial Communication Interface (SCI)
13.6.5
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous
Mode)
Figure 13.20 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations after initializing the SCI. To switch from transmit mode to simultaneous transmit and
receive mode, after checking that the SCI has finished transmission and the TDRE and TEND
flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction.
To switch from receive mode to simultaneous transmit and receive mode, after checking that the
SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error
flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single
instruction.
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Section 13 Serial Communication Interface (SCI)
Initialization
[1]
[1]
SCI initialization:
The TxD pin is designated as the
transmit data output pin, and the RxD
pin is designated as the receive data
input pin, enabling simultaneous
transmit and receive operations.
[2]
SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR and clear the TDRE flag
to 0.
Transition of the TDRE flag from 0 to
1 can also be identified by a TXI
interrupt.
Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
Start transmission/reception
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
[3]
Read ORER flag in SSR
ORER = 1
No
Read RDRF flag in SSR
Yes
[3]
Error processing
[4]
SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0. Transition of the RDRF flag from
0 to 1 can also be identified by an RXI
interrupt.
[5]
Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR,
and clearing the RDRF flag to 0.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR and clear the TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit data empty
interrupt (TXI) request and data is
written to TDR. Also, the RDRF flag
is cleared automatically when the
DTC is activated by a receive data full
interrupt (RXI) request and the RDR
value is read.
[4]
No
RDRF = 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
Clear TE and RE bits in SCR to 0
<End>
Note:* When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE bit and RE bit to 0,
then set both these bits to 1 simultaneously.
Figure 13.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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Section 13 Serial Communication Interface (SCI)
13.7
Operation in Smart Card Interface
The SCI supports an IC card (smart card) interface that conforms to ISO/IEC 7816-3
(Identification Card) as a serial communication interface extension function. Switching between
the normal serial communication interface and the smart card interface mode is carried out by
means of a register setting.
13.7.1
Pin Connection Example
Figure 13.21 shows an example of connection with the smart card. In communication with an IC
card, as both transmission and reception are carried out on a single data transmission line, the TxD
pin and RxD pin should be connected to the LSI pin. The data transmission line should be pulled
up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and RE bits
are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried
out. When the clock generated on the smart card interface is used by an IC card, the SCK pin
output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal.
VCC
TxD
RxD
SCK
Rx (port)
This LSI
Data line
Clock line
Reset line
I/O
CLK
RST
IC card
Connected equipment
Figure 13.21 Schematic Diagram of Smart Card Interface Pin Connections
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Section 13 Serial Communication Interface (SCI)
13.7.2
Data Format (Except for Block Transfer Mode)
Figure 13.22 shows the transfer data format in smart card interface mode.
• One frame consists of 8-bit data plus a parity bit in asynchronous mode.
• In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of
one bit) is left between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for one etu
period, 10.5 etu after the start bit.
• If an error signal is sampled during transmission, the same data is retransmitted automatically
after a delay of 2 etu or longer.
When there is no parity error
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D6
D7
Dp
Transmitting station output
When a parity error occurs
Ds
D0
D1
D2
D3
D4
D5
DE
Transmitting station output
[Legend]
DS:
D0 to D7:
Dp:
DE:
Receiving station
output
Start bit
Data bits
Parity bit
Error signal
Figure 13.22 Normal Smart Card Interface Data Format
Data transfer with other types of IC cards (direct convention and inverse convention) are
performed as described in the following.
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Z
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
(Z)
State
Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0)
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Section 13 Serial Communication Interface (SCI)
With the direction convention type IC and the above sample start character, the logic 1 level
corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.
The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV
bits in SCMR to 0. According to smart card regulations, clear the O/E bit in SMR to 0 to select
even parity mode.
(Z)
A
Z
Z
A
A
A
A
A
A
Z
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
(Z)
State
Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1)
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The start character data for the above is
H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to
smart card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to
state Z. In this LSI, the SINV bit inverts only data bits D0 to D7. Therefore, set the O/E bit in
SMR to 1 to invert the parity bit for both transmission and reception.
13.7.3
Block Transfer Mode
Operation in block transfer mode is the same as that in SCI asynchronous mode, except for the
following points.
• In reception, though the parity check is performed, no error signal is output even if an error is
detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the
parity bit of the next frame.
• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the
start of the next frame.
• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu
after transmission start.
• As with the normal smart card interface, the ERS flag indicates the error signal status, but
since error signal transfer is not performed, this flag is always cleared to 0.
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Section 13 Serial Communication Interface (SCI)
13.7.4
Receive Data Sampling Timing and Reception Margin in Smart Card Interface
Mode
In smart card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or
256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by bits
BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic
clock, and performs internal synchronization. As shown in figure 13.25, by sampling receive data
at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at
the middle of the bit. The reception margin is given by the following formula.
M = | (0.5 –
1
| D – 0.5 |
) – (L – 0.5) F –
(1 + F) | × 100%
2N
N
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
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Section 13 Serial Communication Interface (SCI)
372 clocks
186 clocks
0
185
185
371 0
371 0
Internal
basic clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 13.25 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Transfer Rate)
13.7.5
Initialization
Before transmitting and receiving data, initialize the SCI as described below. Initialization is also
necessary when switching from transmit mode to receive mode, or vice versa.
1.
2.
3.
4.
Clear the TE and RE bits in SCR to 0.
Clear the error flags ERS, PER, and ORER in SSR to 0.
Set the GM, BLK, O/E, BCP0, BCP1, CKS0, and CKS1 bits in SMR. Set the PE bit to 1.
Set the SMIF, SDIR, and SINV bits in SCMR.
When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins,
and are placed in the high-impedance state.
5. Set the value corresponding to the bit rate in BRR.
6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0.
If the CKE0 bit is set to 1, the clock is output from the SCK pin.
7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
To switch from receive mode to transmit mode, after checking that the SCI has finished reception,
initialize the SCI, and set RE to 0 and TE to 1. Whether SCI has finished reception or not can be
checked with the RDRF, PER, or ORER flags. To switch from transmit mode to receive mode,
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Section 13 Serial Communication Interface (SCI)
after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to
1. Whether SCI has finished transmission or not can be checked with the TEND flag.
13.7.6
Data Transmission (Except for Block Transfer Mode)
As data transmission in smart card interface mode involves error signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 13.26 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sent back from the receiving end after transmission of one frame is
complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next
parity bit is sampled.
2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality
is received. Data is retransferred from TDR to TSR, and retransmitted automatically.
3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
Transmission of one frame, including a retransfer, is judged to have been completed, and the
TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt
request is generated. Writing transmit data to TDR transfers the next transmit data.
Figure 13.28 shows a flowchart for transmission. The sequence of transmit operations can be
performed automatically by specifying the DTC to be activated with a TXI interrupt source. In a
transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set, and
a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is
designated beforehand as a DTC activation source, the DTC will be activated by the TXI request,
and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically
cleared to 0 when data is transferred by the DTC. In the event of an error, the SCI retransmits the
same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC is
not activated. Therefore, the SCI and DTC will automatically transmit the specified number of
bytes in the event of an error, including retransmission. However, the ERS flag is not cleared
automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an
ERI request will be generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DTC, it is essential to set and enable the DTC before carrying
out SCI setting. For details of the DTC setting procedures, see section 8, Data Transfer Controller
(DTC).
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Section 13 Serial Communication Interface (SCI)
Transfer
frame n+1
Retransferred frame
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
TDRE
Transfer to TSR from TDR
Transfer to TSR
from TDR
Transfer to TSR from TDR
TEND
[7]
[9]
FER/ERS
[6]
[8]
Figure 13.26 Retransfer Operation in SCI Transmit Mode
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
set timing is shown in figure 13.27.
I/O data
Ds
D0
D1
TXI
(TEND interrupt)
D2
D3
D4
D5
D6
D7
Dp
DE
Guard
time
12.5etu
When GM = 0
11.0etu
When GM = 1
[Legend]
Ds:
D0 to D7:
Dp:
DE:
Start bit
Data bits
Parity bit
Error signal
Figure 13.27 TEND Flag Generation Timing in Transmission Operation
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Section 13 Serial Communication Interface (SCI)
Start
Initialization
Start transmission
ERS = 0?
No
Yes
Error processing
No
TEND = 1?
Yes
Write data to TDR,
and clear TDRE flag
in SSR to 0
No
All data transmitted ?
Yes
No
ERS = 0?
Yes
Error processing
No
TEND = 1?
Yes
Clear TE bit to 0
End
Figure 13.28 Example of Transmission Processing Flow
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Section 13 Serial Communication Interface (SCI)
13.7.7
Serial Data Reception (Except for Block Transfer Mode)
Data reception in smart card interface mode uses the same operation procedure as for normal serial
communication interface mode. Figure 13.29 illustrates the retransfer operation when the SCI is in
receive mode.
1. If an error is found when the received parity bit is checked, the PER bit in SSR is
automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
2. The RDRF bit in SSR is not set for a frame in which an error has occurred.
3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1,
the receive operation is judged to have been completed normally, and the RDRF flag in SSR is
automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is
generated.
Figure 13.30 shows a flowchart for reception. A sequence of receive operations can be performed
automatically by specifying the DTC to be activated using an RXI interrupt source. In a receive
operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI
request is designated beforehand as a DTC activation source, the DTC will be activated by the
RXI request, and the receive data will be transferred. The RDRF flag is cleared to 0 automatically
when data is transferred by the DTC. If an error occurs in receive mode and the ORER or PER
flag is set to 1, a transfer error interrupt (ERI) request will be generated. Hence, so the error flag
must be cleared to 0. In the event of an error, the DTC is not activated and receive data is skipped.
Therefore, receive data is transferred for only the specified number of bytes in the event of an
error. Even when a parity error occurs in receive mode and the PER flag is set to 1, the data that
has been received is transferred to RDR and can be read from there.
Note: For details on receive operations in block transfer mode, see section 13.4, Operation in
Asynchronous Mode.
Transfer
frame n+1
Retransferred frame
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
RDRF
[2]
[4]
[1]
[3]
PER
Figure 13.29 Retransfer Operation in SCI Receive Mode
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Section 13 Serial Communication Interface (SCI)
Start
Initialization
Start reception
ORER = 0 and
PER = 0
No
Yes
Error processing
No
RDRF = 1?
Yes
Read RDR and clear
RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit to 0
Figure 13.30 Example of Reception Processing Flow
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Section 13 Serial Communication Interface (SCI)
13.7.8
Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and
CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Figure 13.31 shows the timing for fixing the clock output level. In this example, GM is set to 1,
CKE1 is cleared to 0, and the CKE0 bit is controlled.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 13.31 Timing for Fixing Clock Output Level
When turning on the power or switching between smart card interface mode and software standby
mode, the following procedures should be followed in order to maintain the clock duty cycle.
Powering On: To secure clock duty cycle from power-on, the following switching procedure
should be followed.
1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down
resistor to fix the potential.
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
When changing from smart card interface mode to software standby mode:
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin
to the value for the fixed output state in software standby mode.
2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive
operation. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
3. Write 0 to the CKE0 bit in SCR to halt the clock.
4. Wait for one serial clock period.
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Section 13 Serial Communication Interface (SCI)
During this interval, clock output is fixed at the specified level, with the duty cycle
preserved.
5. Make the transition to the software standby state.
When returning to smart card interface mode from software standby mode:
1. Exit the software standby state.
2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
normal duty cycle.
Software
standby
Normal operation
[1] [2] [3]
[4] [5]
Normal operation
[6] [7]
Figure 13.32 Clock Halt and Restart Procedure
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Section 13 Serial Communication Interface (SCI)
13.8
Interrupt Sources
13.8.1
Interrupts in Normal Serial Communication Interface Mode
Table 13.12 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to
perform data transfer. The TDRE flag is cleared to 0 automatically when data is transferred by the
DTC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt
request can activate the DTC to transfer data. The RDRF flag is cleared to 0 automatically when
data is transferred by the DTC.
A TEI interrupt is requested when the TEND flag is set to 1 and the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for
acceptance. However, if the TDRE and TEND flags are cleared simultaneously by the TXI
interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 13.12 SCI Interrupt Sources
Channel
Name
Interrupt Source
Interrupt Flag
DTC Activation
0
ERI_0
Receive Error
ORER, FER, PER
Not possible
RXI_0
Receive Data Full
RDRF
Possible
TXI_0
Transmit Data Empty
TDRE
Possible
TEI_0
Transmission End
TEND
Not possible
ERI_2
Receive Error
ORER, FER, PER
Not possible
RXI_2
Receive Data Full
RDRF
Possible
TXI_2
Transmit Data Empty
TDRE
Possible
TEI_2
Transmission End
TEND
Not possible
2
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Section 13 Serial Communication Interface (SCI)
13.8.2
Interrupts in Smart Card Interface Mode
Table 13.13 shows the interrupt sources in smart card interface mode. The transmit end interrupt
(TEI) request cannot be used in this mode.
Table 13.13 SCI Interrupt Sources
Channel
Name
Interrupt Source
Interrupt Flag
DTC Activation
0
ERI_0
Receive Error, error
signal detection
ORER, PER, ERS
Not possible
RXI_0
Receive Data Full
RDRF
Possible
TXI_0
Transmit Data Empty
TEND
Possible
ERI_2
Receive Error, error
signal detection
ORER, PER, ERS
Not possible
RXI_2
Receive Data Full
RDRF
Possible
TXI_2
Transmit Data Empty
TEND
Possible
2
In smart card interface mode, as in normal serial communication interface mode, transfer can be
carried out using the DTC. In transmit operations, the TDRE flag is also set to 1 at the same time
as the TEND flag in SSR is set, and a TXI interrupt is generated. If the TXI request is designated
beforehand as a DTC activation source, the DTC will be activated by the TXI request, and
transmit data will be transferred. The TDRE and TEND flags are automatically cleared to 0 when
data is transferred by the DTC. In the event of an error, the SCI retransmits the same data
automatically. During this period, the TEND flag remains cleared to 0 and the DTC is not
activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes
in the event of an error, including retransmission. However, the ERS flag is not cleared
automatically when an error occurs. Hence, the RIE bit should be set to 1 beforehand so that an
ERI request will be generated in the event of an error, and the ERS flag will be cleared.
When transferring using the DTC, it is essential to set and enable the DTC before carrying out SCI
setting. For details of the DTC setting procedures, see section 8, Data Transfer Controller (DTC).
In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to
1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be
activated by the RXI request, and the receive data will be transferred. The RDRF flag is cleared to
0 automatically when data is transferred by the DTC. If an error occurs, an error flag is set but the
RDRF flag is not. Consequently, the DTC is not activated, instead, an ERI interrupt request is sent
to the CPU. Therefore, the error flag should be cleared.
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Section 13 Serial Communication Interface (SCI)
13.9
Usage Notes
13.9.1
Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, see section 21, Power-Down Modes.
13.9.2
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly
the PER flag. Note that as the SCI continues the receive operation after receiving a break, even if
the FER flag is cleared to 0, it will be set to 1 again.
13.9.3
Mark State and Break Detection
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are
determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send
a break during serial data transmission. To maintain the communication line at mark state until TE
is set to 1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an
I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set
DDR to 1 and DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is
initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is
output from the TxD pin.
13.9.4
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
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Section 13 Serial Communication Interface (SCI)
13.9.5
Restrictions on Using DTC
When the external clock source is used as a synchronization clock, update TDR by the DTC and
wait for at least five φ clock cycles before allowing the transmit clock to be input. If the transmit
clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure
13.33).
When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC
activation source.
SCK
t
TDRE
LSB
Serial data
D0
D1
D2
D3
D4
D5
D6
D7
Note: When external clock is supplied, t must be more than four clock cycles.
Figure 13.33 Sample Transmission using DTC in Clocked Synchronous Mode
13.9.6
SCI Operations during Mode Transitions
Transmission: Before making the transition to module stop, software standby, watch, sub-active,
or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are
reset. The states of the output pins during each mode depend on the port settings, and the pins
output a high-level signal after mode is cancelled and then the TE is set to 1 again. If the transition
is made during data transmission, the data being transmitted will be undefined.
To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR,
write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different
transmission mode, initialize the SCI first.
Figure 13.34 shows a sample flowchart for mode transition during transmission. Figures 13.35 and
13.36 show the pin states during transmission.
Before making the transition from the transmission mode using DTC transfer to module stop,
software standby, watch, sub-active, or sub-sleep mode, stop all transmit operations (TE = TIE =
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Section 13 Serial Communication Interface (SCI)
TEIE = 0). Setting TE and TIE to 1 after mode cancellation generates a TXI interrupt request to
start transmission using the DTC.
Transmission
No
All data transmitted?
[1]
Yes
Read TEND flag in SSR
No
TEND = 1
Yes
TE = 0
[2]
[2] Also clear TIE and TEIE to 0
when they are 1.
[3]
Make transition to software standby mode etc.
Cancel software standby mode etc.
Change operating mode?
[1] Data being transmitted is lost
halfway. Data can be normally
transmitted from the CPU by
setting TE to 1, reading SSR,
writing to TDR, and clearing
TDRE to 0 after mode
cancellation; however, if the DTC
has been initiated, the data
remaining in DTC RAM will be
transmitted when TE and TIE are
set to 1.
[3] Module stop, watch, sub-active,
and sub-sleep modes are
included.
No
Yes
Initialization
TE = 1
Start transmission
Figure 13.34 Sample Flowchart for Mode Transition during Transmission
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Section 13 Serial Communication Interface (SCI)
Transmission start
Transition to
Software standby
Transmission end software standby mode cancelled
mode
TE bit
SCK
output pin
TxD
output pin
Port
input/output
Port
input/output
High output
Start
Stop
Port input/output
SCI TxD output
Port
High output
SCI
TxD output
Port
Figure 13.35 Pin States during Transmission in Asynchronous Mode (Internal Clock)
Transmission start
Transmission end
Transition to
Software standby
software standby mode cancelled
mode
TE bit
SCK
output pin
TxD
output pin
Port
input/output
Port
input/output
Marking output
Port
Last TxD bit retained
Port input/output
SCI TxD output
Port
High output*
SCI
TxD output
Note: Initialized in software standby mode
Figure 13.36 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock)
Reception: Before making the transition to module stop, software standby, watch, sub-active, or
sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made
during data reception, the data being received will be invalid.
To receive data in the same reception mode after mode cancellation, set RE to 1, and then start
reception. To receive data in a different reception mode, initialize the SCI first.
Figure 13.37 shows a sample flowchart for mode transition during reception.
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Section 13 Serial Communication Interface (SCI)
Reception
Read RDRF flag in SSR
RDRF = 1
No
[1]
[1] Data being received will be invalid.
Yes
Read receive data in RDR
[2] Module stop, watch, sub-active, and subsleep modes are included.
RE = 0
[2]
Make transition to software standby mode etc.
Cancel software standby mode etc.
Change operating mode?
No
Yes
Initialization
RE = 1
Start reception
Figure 13.37 Sample Flowchart for Mode Transition during Reception
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Section 13 Serial Communication Interface (SCI)
13.9.7
Notes when Switching from SCK Pin to Port Pin
• Problem in Operation: When DDR and DR are set to 1, SCI clock output is used in clocked
synchronous mode, and the SCK pin is changed to the port pin while transmission is ended,
port output is enabled after low-level output occurs for one half-cycle.
When switching the SCK pin to the port pin by making the following settings while DDR = 1,
DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, low-level output occurs for one halfcycle.
1. End of serial data transmission
2. TE bit = 0
3. C/A bit = 0 ... switchover to port output
4. Occurrence of low-level output (see figure 13.38)
Half-cycle low-level output
SCK/port
1. End of transmission
Data
TE
C/A
Bit 6
4. Low-level output
Bit 7
2. TE = 0
3. C/A = 0
CKE1
CKE0
Figure 13.38 Operation when Switching from SCK Pin to Port Pin
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Section 13 Serial Communication Interface (SCI)
• Usage Note: To prevent low-level output occurred when switching the SCK pin to port pin,
follow the procedure described below.
As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin
should be pulled up beforehand with an external circuit.
With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following
settings in the order shown.
1. End of serial data transmission
2. TE bit = 0
3. CKE1 bit = 1
4. C/A bit = 0 ... switchover to port output
5. CKE1 bit = 0
High-level output
SCK/port
1. End of transmission
Bit 6
Data
Bit 7
2. TE = 0
TE
4. C/A = 0
C/A
3. CKE1 = 1
5. CKE1 = 0
CKE1
CKE0
Figure 13.39 Operation when Switching from SCK Pin to Port Pin
(Example of Preventing Low-Level Output)
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Section 14 Controller Area Network (HCAN)
Section 14 Controller Area Network (HCAN)
The HCAN is a module for controlling a controller area network (CAN) for realtime
communication in vehicular and industrial equipment systems, etc. For details on CAN
specification, see Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH.
The block diagram of the HCAN is shown in figure 14.1.
14.1
Features
• CAN version: Bosch 2.0B active compatible
 Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function)
 Broadcast communication system
 Transmission path: Bidirectional 2-wire serial communication
 Communication speed: Max. 1 Mbps
 Data length: 0 to 8 bytes
• Number of channels: 2
• Data buffers: 16 for each channel (one receive-only buffer and 15 buffers settable for
transmission/reception)
• Data transmission: Two methods
 Mailbox (buffer) number order (low-to-high)
 Message priority (identifier) reverse-order (high-to-low)
• Data reception: Two methods
 Message identifier match (transmit/receive-setting buffers)
 Reception with message identifier masked (receive-only)
• CPU interrupts: 12 for each channel
 Error interrupt
 Reset processing interrupt
 Message reception interrupt
 Message transmission interrupt
• HCAN operating modes
IFCAN10C_000020040800
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Section 14 Controller Area Network (HCAN)
• Support for various modes
 Hardware reset
 Software reset
 Normal status (error-active, error-passive)
 Bus off status
 HCAN configuration mode
 HCAN sleep mode
 HCAN halt mode
• Other features
 DTC can be activated by message reception mailbox (HCAN mailbox 0 only)
• Module stop mode can be set
HCAN_0
MBI
Message buffer
Message control
MC0 to MC15
Message data
MD0 to MD15
(CDLC)
CAN
LAFM
Data Link Controller
Bosch CAN 2.0B active
HTxD0
Tx buffer
Peripheral data bus
Peripheral address bus
MPI
Microprocessor interface
Rx buffer
HRxD0
CPU interface
Control register
Status register
HCAN_1
MBI
Message buffer
Message control
MC0 to MC15
Message data
MD0 to MD15
(CDLC)
CAN
LAFM
Data Link Controller
Bosch CAN 2.0B active
HTxD1
Tx buffer
MPI
Microprocessor interface
Rx buffer
CPU interface
Control register
Status register
Figure 14.1 HCAN Block Diagram
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HRxD1
Section 14 Controller Area Network (HCAN)
• Message Buffer Interface (MBI)
The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN
transmit/receive messages (identifiers, data, etc.) Transmit messages are written by the CPU.
For receive messages, the data received by the CDLC is stored automatically.
• Microprocessor Interface (MPI)
The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN
internal data, status, and so forth.
• CAN Data Link Controller (CDLC)
The CDLC, conforming to the Bosch CAN Ver. 2.0B active standard, performs transmission
and reception of messages (data frames, remote frames, error frames, overload frames, interframe spacing), as well as CRC checking, bus arbitration, and other functions.
14.2
Input/Output Pins
Table 14.1 shows the HCAN pins.
When using HCAN pins, settings must be made in the HCAN configuration mode (during
initialization: MCR0 = 1 and GSR3 = 1).
Table 14.1 HCAN Pins
Channel
Name
Abbreviation
Input/Output
Function
0
HCAN transmit data
pin 0
HTxD0
Output
CAN bus transmission pin
for channel 0
HCAN receive data
pin 0
HRxD0
Input
CAN bus reception pin for
channel 0
HCAN transmit data
pin 1
HTxD1
Output
CAN bus transmission pin
for channel 1
HCAN receive data
pin 1
HRxD1
Input
CAN bus reception pin for
channel 1
1
A bus driver is necessary for the interface between the pins and the CAN bus. A Philips
PCA82C250 compatible model is recommended.
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Section 14 Controller Area Network (HCAN)
14.3
Register Descriptions
The HCAN has the following registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Master control register (MCR)
General status register (GSR)
Bit configuration register (BCR)
Mailbox configuration register (MBCR)
Transmit wait register (TXPR)
Transmit wait cancel register (TXCR)
Transmit acknowledge register (TXACK)
Abort acknowledge register (ABACK)
Receive complete register (RXPR)
Remote request register (RFPR)
Interrupt register (IRR)
Mailbox interrupt mask register (MBIMR)
Interrupt mask register (IMR)
Receive error counter (REC)
Transmit error counter (TEC)
Unread message status register (UMSR)
Local acceptance filter mask H (LAFMH)
Local acceptance filter mask L (LAFML)
Message control (8-bit × 8 registers × 16 sets) (MC0 to MC15)
Message data (8-bit × 8 registers × 16 sets) (MD0 to MD15)
HCAN Monitor Register (HCANMON)
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Section 14 Controller Area Network (HCAN)
14.3.1
Master Control Register (MCR)
MCR is an 8-bit register that controls the HCAN.
Bit
Bit Name
Initial
Value
R/W
Description
7
MCR7
0
R/W
HCAN Sleep Mode Release
When this bit is set to 1, the HCAN automatically exits
HCAN sleep mode on detection of CAN bus operation.
6

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
5
MCR5
0
R/W
HCAN Sleep Mode
When this bit is set to 1, the HCAN requests HCAN
sleep mode transition. When this bit is cleared to 0,
HCAN sleep mode is released.
4, 3

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
MCR2
0
R/W
Message Transmission Method
0: Transmission order determined by message identifier
priority
1: Transmission order determined by mailbox (buffer)
number priority (TXPR1 > TXPR15)
1
MCR1
0
R/W
Halt Request
When this bit is set to 1, the HCAN requests HCAN
HALT mode transition. When this bit is cleared to 0,
HCAN HALT mode is released.
0
MCR0
1
R/W
Reset Request
When this bit is set to 1, the HCAN requests reset mode
transition. For details, see section 14.4.1, Hardware and
Software Resets.
[Setting conditions]
•
Writing 1 to this bit (software reset)
[Clearing condition]
•
When 0 is written to this bit while the GSR3 bit in
GSR is 1
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Section 14 Controller Area Network (HCAN)
14.3.2
General Status Register (GSR)
GSR is an 8-bit register that indicates the status of the CAN bus.
Bit
Bit Name
7 to 4 
Initial
Value
R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
3
GSR3
1
R
Reset Status Bit
Indicates whether the HCAN module is in the normal
operation state or the reset state. This bit cannot be
modified.
[Setting condition]
•
When entering configuration mode after the HCAN
internal reset has finished
•
Sleep mode
[Clearing condition]
•
2
GSR2
1
R
When entering the normal operation state after the
MCR0 bit in MCR is cleared to 0 (Note that there is
a delay between clearing of the MCR0 bit and the
GSR3 bit.)
Message Transmission Status Flag
Flag that indicates whether the module is currently in
the message transmission period. This bit cannot be
modified.
[Setting condition]
•
Third bit of intermission after EOF (End of Frame)
[Clearing condition]
•
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Start of message transmission (SOF)
Section 14 Controller Area Network (HCAN)
Bit
Bit Name
Initial
Value
R/W
Description
1
GSR1
0
R
Transmit/Receive Warning Flag
This bit cannot be modified.
[Clearing condition]
•
When TEC < 96 and REC < 96
•
TEC ≥ 256 (bus-off state)
[Setting condition]
•
0
GSR0
0
R
When TEC ≥ 96 or REC ≥ 96
Bus Off Flag
This bit cannot be modified.
[Setting condition]
•
When TEC ≥ 256 (bus off state)
[Clearing condition]
•
14.3.3
Recovery from bus off state
Bit Configuration Register (BCR)
BCR is a 16-bit register that is used to set HCAN bit timing parameters and the baud rate
prescaler. For details on parameters, see section 14.4.2, Initialization after Hardware Reset.
Bit
Bit Name
Initial
Value
R/W
Description
15
BCR7
0
R/W
Re-Synchronization Jump Width (SJW)
14
BCR6
0
R/W
Set the maximum bit synchronization width.
00: 1 time quantum
01: 2 time quanta
10: 3 time quanta
11: 4 time quanta
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Section 14 Controller Area Network (HCAN)
Bit
Bit Name
Initial
Value
R/W
Description
13
BCR5
0
R/W
Baud Rate Prescaler (BRP)
12
BCR4
0
R/W
Set the length of time quanta.
11
BCR3
0
R/W
000000: 2 × system clock
10
BCR2
0
R/W
000001: 4 × system clock
9
BCR1
0
R/W
000010: 6 × system clock
8
BCR0
0
R/W
7
BCR15
0
R/W
:
111111: 128 × system clock
Bit Sample Point (BSP)
Sets the point at which data is sampled.
0: Bit sampling at one point (end of time segment 1
(TSEG1))
1: Bit sampling at three points (end of TSEG1 and
preceding and following time quanta)
6
BCR14
0
R/W
Time Segment 2 (TSEG2)
5
BCR13
0
R/W
4
BCR12
0
R/W
Set the TSEG2 width within a range of 2 to 8 time
quanta.
000: Setting prohibited
001: 2 time quanta
010: 3 time quanta
011: 4 time quanta
100: 5 time quanta
101: 6 time quanta
110: 7 time quanta
111: 8 time quanta
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Section 14 Controller Area Network (HCAN)
Bit
Bit Name
Initial
Value
R/W
Description
3
BCR11
0
R/W
Time Segment 1 (TSEG1)
2
BCR10
0
R/W
1
BCR9
0
R/W
Set the TSEG1 (PRSEG + PHSEG1) width to between
4 and 16 time quanta.
0
BCR8
0
R/W
0000: Setting prohibited
0001: Setting prohibited
0010: Setting prohibited
0011: 4 time quanta
0100: 5 time quanta
0101: 6 time quanta
0110: 7 time quanta
0111: 8 time quanta
1000: 9 time quanta
1001: 10 time quanta
1010: 11 time quanta
1011: 12 time quanta
1100: 13 time quanta
1101: 14 time quanta
1110: 15 time quanta
1111: 16 time quanta
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Section 14 Controller Area Network (HCAN)
14.3.4
Mailbox Configuration Register (MBCR)
MBCR is a 16-bit register that is used to set the transfer direction for each mailbox.
Bit
Bit Name
Initial
Value
R/W
Description
15
MBCR7
0
R/W
14
MBCR6
0
R/W
13
MBCR5
0
R/W
These bits set the transfer direction for the
corresponding mailboxes 1 to 15. MBCRn determines
the transfer direction for mailbox n (n =1 to 15).
12
MBCR4
0
R/W
11
MBCR3
0
R/W
10
MBCR2
0
R/W
9
MBCR1
0
R/W
8

1
R
7
MBCR15
0
R/W
6
MBCR14
0
R/W
5
MBCR13
0
R/W
4
MBCR12
0
R/W
3
MBCR11
0
R/W
2
MBCR10
0
R/W
1
MBCR9
0
R/W
0
MBCR8
0
R/W
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0: Corresponding mailbox is set for transmission
1: Corresponding mailbox is set for reception
Bit 8 is reserved. This bit is always read as 1. The write
value should always be 1.
Section 14 Controller Area Network (HCAN)
14.3.5
Transmit Wait Register (TXPR)
TXPR is a 16-bit register that is used to set a transmit wait after a transmit message is stored in a
mailbox (buffer) (CAN bus arbitration wait).
Bit
Bit Name
Initial
Value
R/W
Description
15
TXPR7
0
R/W
14
TXPR6
0
R/W
13
TXPR5
0
R/W
These bits set a transmit wait (CAN bus arbitration wait)
for the corresponding mailboxes 1 to 15. When TXPRn
(n = 1 to 15) is set to 1, the message in mailbox n
becomes the transmit wait state.
12
TXPR4
0
R/W
[Clearing condition]
11
TXPR3
0
R/W
•
Completion of message transmission
10
TXPR2
0
R/W
•
Completion of transmission cancellation
9
TXPR1
0
R/W
8

0
R
Bit 8 is reserved. This bit is always read as 1. The write
value should always be 1.
7
TXPR15
0
R/W
6
TXPR14
0
R/W
5
TXPR13
0
R/W
4
TXPR12
0
R/W
3
TXPR11
0
R/W
2
TXPR10
0
R/W
1
TXPR9
0
R/W
0
TXPR8
0
R/W
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Section 14 Controller Area Network (HCAN)
14.3.6
Transmit Wait Cancel Register (TXCR)
TXCR is a 16-bit register that controls the cancellation of transmit wait messages in mailboxes
(buffers).
Bit
Bit Name
Initial
Value
R/W
Description
15
TXCR7
0
R/W
14
TXCR6
0
R/W
13
TXCR5
0
R/W
These bits cancel the transmit wait message in the
corresponding mailboxes 1 to 15. When TXCRn (n = 1
to 15) is set to 1, the transmit wait message in mailbox
n is canceled.
12
TXCR4
0
R/W
[Clearing condition]
11
TXCR3
0
R/W
•
10
TXCR2
0
R/W
9
TXCR1
0
R/W
8

0
R
7
TXCR15
0
R/W
6
TXCR14
0
R/W
5
TXCR13
0
R/W
4
TXCR12
0
R/W
3
TXCR11
0
R/W
2
TXCR10
0
R/W
1
TXCR9
0
R/W
0
TXCR8
0
R/W
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Completion of TXPR clearing when transmit
message is canceled normally
Bit 8 is reserved. This bit is always read as 0. The write
value should always be 0.
Section 14 Controller Area Network (HCAN)
14.3.7
Transmit Acknowledge Register (TXACK)
TXACK is a 16-bit register containing status flags that indicate the normal transmission of
mailbox (buffer) transmit messages.
Bit
Bit Name
Initial
Value
15
TXACK7
0
14
TXACK6
0
13
TXACK5
0
12
TXACK4
0
R/(W)* These bits are status flags that indicate error-free
R/(W)* transmission of the transmit message in the
corresponding mailboxes 1 to 15. When the message in
R/(W)* mailbox n (n = 1 to 15) has been transmitted error-free,
R/(W)* TXACKn is set to 1.
11
TXACK3
0
R/(W)* [Setting condition]
10
TXACK2
0
R/(W)* •
9
TXACK1
0
R/(W)*
8

0
R
7
TXACK15
0
6
TXACK14
0
5
TXACK13
0
R/(W)* • Writing 1
R/(W)* Bit 8 is reserved. This bit is always read as 0. The write
value should always be 0.
R/(W)*
4
TXACK12
0
R/(W)*
3
TXACK11
0
R/(W)*
2
TXACK10
0
R/(W)*
1
TXACK9
0
R/(W)*
0
TXACK8
0
R/(W)*
Note:
*
R/W
Description
Completion of message transmission for
corresponding mailbox
[Clearing condition]
Only 1 can be written to clear the flag.
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Section 14 Controller Area Network (HCAN)
14.3.8
Abort Acknowledge Register (ABACK)
ABACK is a 16-bit register containing status flags that indicate the normal cancellation (aborting)
of mailbox (buffer) transmit messages.
Bit
Bit Name
Initial
Value
15
ABACK7
0
14
ABACK6
0
13
ABACK5
0
12
ABACK4
0
R/(W)* These bits are status flags that indicate error-free
R/(W)* cancellation (abortion) of the transmit message in the
corresponding mailboxes 1 to 15. When the message in
R/(W)* mailbox n (n = 1 to 15) has been canceled error-free,
R/(W)* ABACKn is set to 1.
11
ABACK3
0
R/(W)* [Setting condition]
10
ABACK2
0
R/(W)* •
9
ABACK1
0
R/(W)*
8

0
R
7
ABACK15
0
6
ABACK14
0
5
ABACK13
0
R/(W)* • Writing 1
R/(W)* Bit 8 is reserved. This bit is always read as 0. The write
value should always be 0.
R/(W)*
4
ABACK12
0
R/(W)*
3
ABACK11
0
R/(W)*
2
ABACK10
0
R/(W)*
1
ABACK9
0
R/(W)*
0
ABACK8
0
R/(W)*
Note:
*
R/W
Description
Completion of transmit message cancellation for
corresponding mailbox
[Clearing condition]
Only 1 can be written to clear the flag.
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Section 14 Controller Area Network (HCAN)
14.3.9
Receive Complete Register (RXPR)
RXPR is a 16-bit register containing status flags that indicate the normal reception of messages in
mailboxes (buffers). For reception of a remote frame, when a bit in this register is set to 1, the
corresponding remote request register (RFPR) bit is also set to 1 simultaneously.
Bit
Bit Name
Initial
Value
15
RXPR7
0
14
RXPR6
0
13
RXPR5
0
12
RXPR4
0
11
RXPR3
0
10
RXPR2
0
9
RXPR1
0
R/(W)* [Setting condition]
R/(W)* • Completion of message (data frame or remote
frame) reception in corresponding mailbox
R/(W)*
[Clearing condition]
R/(W)*
• Writing 1
R/(W)*
8
RXPR0
0
R/(W)*
7
RXPR15
0
R/(W)*
6
RXPR14
0
R/(W)*
5
RXPR13
0
R/(W)*
4
RXPR12
0
R/(W)*
3
RXPR11
0
R/(W)*
2
RXPR10
0
R/(W)*
1
RXPR9
0
R/(W)*
0
RXPR8
0
R/(W)*
Note:
*
R/W
Description
R/(W)* When the message in mailbox n (n = 1 to 15) has been
R/(W)* received error-free, RXPRn is set to 1.
Only 1 can be written to clear the flag.
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Section 14 Controller Area Network (HCAN)
14.3.10 Remote Request Register (RFPR)
RFPR is a 16-bit register containing status flags that indicate normal reception of remote frames in
mailboxes (buffers). When a bit in this register is set to 1, the corresponding receive complete
register (RXPR) bit is also set to 1 simultaneously.
Bit
Bit Name
Initial
Value
15
RFPR7
0
14
RFPR6
0
13
RFPR5
0
12
RFPR4
0
11
RFPR3
0
10
RFPR2
0
9
RFPR1
0
R/(W)* [Setting condition]
R/(W)* • Completion of remote frame reception in
corresponding mailbox
R/(W)*
[Clearing condition]
R/(W)*
• Writing 1
R/(W)*
8
RFPR0
0
R/(W)*
7
RFPR15
0
R/(W)*
6
RFPR14
0
R/(W)*
5
RFPR13
0
R/(W)*
4
RFPR12
0
R/(W)*
3
RFPR11
0
R/(W)*
2
RFPR10
0
R/(W)*
1
RFPR9
0
R/(W)*
0
RFPR8
0
R/(W)*
Note:
*
R/W
Description
R/(W)* When mailbox n (n = 0 to 15) has received the remote
R/(W)* frame error-free, RFPRn (n = 1 to 15) is set to 1.
Only 1 can be written to clear the flag.
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Section 14 Controller Area Network (HCAN)
14.3.11 Interrupt Register (IRR)
IRR is a 16-bit interrupt status flag register.
Bit
Bit Name
Initial
Value
R/W
15
IRR7
0
R/(W)* Overload Frame
Description
[Setting condition]
•
When an overload frame is transmitted in error
active/passive state
[Clearing condition]
•
14
IRR6
0
Writing 1
R/(W)* Bus Off Interrupt Flag
Status flag indicating the bus off state caused by the
transmit error counter.
[Setting condition]
•
When TEC ≥ 256
[Clearing condition]
•
13
IRR5
0
Writing 1
R/(W)* Error Passive Interrupt Flag
Status flag indicating the error passive state caused by
the transmit/receive error counter.
[Setting condition]
When TEC ≥ 128 or REC ≥ 128
[Clearing condition]
•
12
IRR4
0
Writing 1
R/(W)* Receive Overload Warning Interrupt Flag
Status flag indicating the error warning state caused by
the receive error counter.
[Setting condition]
When REC ≥ 96
[Clearing condition]
•
Writing 1
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Section 14 Controller Area Network (HCAN)
Bit
Bit Name
Initial
Value
R/W
11
IRR3
0
R/(W)* Transmit Overload Warning Interrupt Flag
Description
Status flag indicating the error warning state caused by
the transmit error counter.
[Setting condition]
•
When TEC ≥ 96
[Clearing condition]
•
10
IRR2
0
R
Writing 1
Remote Frame Request Interrupt Flag
Status flag indicating that a remote frame has been
received in a mailbox (buffer) when the corresponding
bit in MBIMR is 0.
[Setting condition]
•
When remote frame reception is completed, when
corresponding MBIMR = 0
[Clearing condition]
•
9
IRR1
0
R
Clearing of all bits in RFPR (remote request
register)
Receive Message Interrupt Flag
Status flag indicating that a mailbox (buffer) has
received a message normally when the corresponding
bit in MBIMR is 0.
[Setting condition]
•
When data frame or remote frame reception is
completed, when corresponding MBIMR = 0
[Clearing condition]
•
Rev. 2.00 Dec. 05, 2005 Page 438 of 724
REJ09B0200-0200
Clearing of all bits in RXPR (receive complete
register)
Section 14 Controller Area Network (HCAN)
Bit
Bit Name
Initial
Value
R/W
8
IRR0
1
R/(W)* Reset Interrupt Flag
Description
Status flag indicating that the HCAN module has been
reset. This bit cannot be masked by the interrupt mask
register (IMR). If this bit is not cleared to 0 after entering
power-on reset or returning from software standby
mode, interrupt processing will start immediately when
the interrupt controller enables interrupts.
[Setting condition]
•
When the reset operation has finished after entering
power-on reset or software standby mode
[Clearing condition]
•
7 to 5 
All 0

Writing 1
Reserved
These bits are always read as 0. The write value should
always be 0.
4
IRR12
0
R/(W)* Bus Operation Interrupt Flag
Status flag indicating detection of a dominant bit due to
bus operation when the HCAN module is in HCAN
sleep mode.
[Setting condition]
•
Bus operation (dominant bit) detection in HCAN
sleep mode
[Clearing condition]
•
3, 2

All 0

Writing 1
Reserved
These bits are always read as 0. The write value should
always be 0.
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Section 14 Controller Area Network (HCAN)
Bit
Bit Name
Initial
Value
R/W
Description
1
IRR9
0
R
Unread Interrupt Flag
Status flag indicating that a receive message has been
overwritten before being read.
[Setting condition]
•
When UMSR (unread message status register) is
set
[Clearing condition]
•
0
IRR8
0
Clearing of all bits in UMSR (unread message
status register)
R/(W)* Mailbox Empty Interrupt Flag
Status flag indicating that the next transmit message
can be stored in the mailbox.
[Setting condition]
•
When TXPR (transmit wait register) is cleared by
completion of transmission or completion of
transmission abort
[Clearing condition]
•
Note:
*
Writing 1
Only 1 can be written to clear the flag.
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Section 14 Controller Area Network (HCAN)
14.3.12 Mailbox Interrupt Mask Register (MBIMR)
MBIMR is a 16-bit register that controls the enabling or disabling of individual mailbox (buffer)
interrupt requests.
Bit
Bit Name
Initial
Value
R/W
Description
15
MBIMR7
1
R/W
Mailbox Interrupt Mask (MBIMRx)
14
MBIMR6
1
R/W
13
MBIMR5
1
R/W
12
MBIMR4
1
R/W
When MBIMRn (n = 1 to 15) is cleared to 0, the
interrupt request in mailbox n is enabled. When set to 1,
the interrupt request is masked.
11
MBIMR3
1
R/W
10
MBIMR2
1
R/W
9
MBIMR1
1
R/W
8
MBIMR0
1
R/W
7
MBIMR15
1
R/W
6
MBIMR14
1
R/W
5
MBIMR13
1
R/W
4
MBIMR12
1
R/W
3
MBIMR11
1
R/W
2
MBIMR10
1
R/W
1
MBIMR9
1
R/W
0
MBIMR8
1
R/W
The interrupt source in a transmit mailbox is TXPR
clearing caused by transmission end or transmission
cancellation. The interrupt source in a receive mailbox
is RXPR setting on reception end.
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Section 14 Controller Area Network (HCAN)
14.3.13 Interrupt Mask Register (IMR)
IMR is a 16-bit register containing flags that enable or disable requests by individual interrupt
sources. The reset interrupt flag cannot be masked.
Bit
Bit Name
Initial
Value
R/W
Description
15
IMR7
1
R/W
Overload Frame Interrupt Mask
When this bit is cleared to 0, an interrupt request by
IRR7 (OVR0) is enabled. When set to 1, it is masked.
14
IMR6
1
R/W
Bus Off Interrupt Mask
When this bit is cleared to 0, an interrupt request by
IRR6 (ERS0) is enabled. When set to 1, it is masked.
13
IMR5
1
R/W
Error Passive Interrupt Mask
When this bit is cleared to 0, an interrupt request by
IRR5 (ERS0) is enabled. When set to 1, it is masked.
12
IMR4
1
R/W
Receive Overload Warning Interrupt Mask
When this bit is cleared to 0, an interrupt request by
IRR4 (OVR0) is enabled. When set to 1, it is masked.
11
IMR3
1
R/W
Transmit Overload Warning Interrupt Mask
When this bit is cleared to 0, an interrupt request by
IRR3 (OVR0) is enabled. When set to 1, it is masked.
10
IMR2
1
R/W
Remote Frame Request Interrupt Mask
When this bit is cleared to 0, an interrupt request by
IRR2 (OVR0) is enabled. When set to 1, it is masked.
9
IMR1
1
R/W
Receive Message Interrupt Mask
When this bit is cleared to 0, an interrupt request by
IRR1 (RM1) is enabled. When set to 1, it is masked.
8

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
7 to 5 
All 1
R
Reserved
These bits are always read as 1. The write value should
always be 1.
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Section 14 Controller Area Network (HCAN)
Bit
Bit Name
Initial
Value
R/W
Description
4
IMR12
1
R/W
Bus Operation Interrupt Mask
When this bit is cleared to 0, an interrupt request by
IRR12 (OVR0) is enabled. When set to 1, it is masked.
3, 2

All 1
R
Reserved
These bits are always read as 1. The write value should
always be 1.
1
IMR9
1
R/W
Unread Interrupt Mask
When this bit is cleared to 0, an interrupt request by
IRR9 (OVR0) is enabled. When set to 1, it is masked.
0
IMR8
1
R/W
Mailbox Empty Interrupt Mask
When this bit is cleared to 0, an interrupt request by
IRR8 (SLE0) is enabled. When set to 1, it is masked.
14.3.14 Receive Error Counter (REC)
The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating
the number of receive message errors on the CAN bus. The count value is stipulated in the CAN
protocol.
14.3.15 Transmit Error Counter (TEC)
The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter
indicating the number of transmit message errors on the CAN bus. The count value is stipulated in
the CAN protocol.
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Section 14 Controller Area Network (HCAN)
14.3.16 Unread Message Status Register (UMSR)
UMSR is a 16-bit register containing status flags that indicate, for individual mailboxes (buffers),
that a received message has been overwritten by a new receive message before being read. When
overwritten by a new message, data in the unread receive message is lost.
Bit
Bit Name
Initial
Value
15
UMSR7
0
14
UMSR6
0
13
UMSR5
0
12
UMSR4
0
11
UMSR3
0
10
UMSR2
0
9
UMSR1
0
R/(W)* [Setting condition]
R/(W)* • When a new message is received before RXPR is
cleared
R/(W)*
[Clearing condition]
R/(W)*
• Writing 1
R/(W)*
8
UMSR0
0
R/(W)*
7
UMSR15
0
R/(W)*
6
UMSR14
0
R/(W)*
5
UMSR13
0
R/(W)*
4
UMSR12
0
R/(W)*
3
UMSR11
0
R/(W)*
2
UMSR10
0
R/(W)*
1
UMSR9
0
R/(W)*
0
UMSR8
0
R/(W)*
Note:
*
R/W
Description
R/(W)* Each bit indicates that the received message has been
R/(W)* overwritten by a new message before being read.
Only 1 can be written to clear the flag.
14.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)
LAFML and LAFMH are 16-bit registers that individually set the identifier bits of the message to
be stored in mailbox 0 as Don't Care. For details, see section 14.4.4, Message Reception. The
relationship between the identifier bits and mask bits are shown in the following.
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Section 14 Controller Area Network (HCAN)
• LAFML
Bit
Bit Name
Initial
Value
R/W
Description
15
LAFML7
0
R/W
When this bit is set to 1, ID-7 of the receive message
identifier is not compared.
14
LAFML6
0
R/W
When this bit is set to 1, ID-6 of the receive message
identifier is not compared.
13
LAFML5
0
R/W
When this bit is set to 1, ID-5 of the receive message
identifier is not compared.
12
LAFML4
0
R/W
When this bit is set to 1, ID-4 of the receive message
identifier is not compared.
11
LAFML3
0
R/W
When this bit is set to 1, ID-3 of the receive message
identifier is not compared.
10
LAFML2
0
R/W
When this bit is set to 1, ID-2 of the receive message
identifier is not compared.
9
LAFML1
0
R/W
When this bit is set to 1, ID-1 of the receive message
identifier is not compared.
8
LAFML0
0
R/W
When this bit is set to 1, ID-0 of the receive message
identifier is not compared.
7
LAFML15
0
R/W
When this bit is set to 1, ID-15 of the receive message
identifier is not compared.
6
LAFML14
0
R/W
When this bit is set to 1, ID-14 of the receive message
identifier is not compared.
5
LAFML13
0
R/W
When this bit is set to 1, ID-13 of the receive message
identifier is not compared.
4
LAFML12
0
R/W
When this bit is set to 1, ID-12 of the receive message
identifier is not compared.
3
LAFML11
0
R/W
When this bit is set to 1, ID-11 of the receive message
identifier is not compared.
2
LAFML10
0
R/W
When this bit is set to 1, ID-10 of the receive message
identifier is not compared.
1
LAFML9
0
R/W
When this bit is set to 1, ID-9 of the receive message
identifier is not compared.
0
LAFML8
0
R/W
When this bit is set to 1, ID-8 of the receive message
identifier is not compared.
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Section 14 Controller Area Network (HCAN)
• LAFMH
Bit
Bit Name
Initial
Value
R/W
Description
15
LAFMH7
0
R/W
When this bit is set to 1, ID-20 of the receive message
identifier is not compared.
14
LAFMH6
0
R/W
When this bit is set to 1, ID-19 of the receive message
identifier is not compared.
13
LAFMH5
0
R/W
When this bit is set to 1, ID-18 of the receive message
identifier is not compared.
12 to 
10
All 0
R
Reserved
9
LAFMH1
0
R/W
When this bit is set to 1, ID-17 of the receive message
identifier is not compared.
8
LAFMH0
0
R/W
When this bit is set to 1, ID-16 of the receive message
identifier is not compared.
7
LAFMH15
0
R/W
When this bit is set to 1, ID-28 of the receive message
identifier is not compared.
6
LAFMH14
0
R/W
When this bit is set to 1, ID-27 of the receive message
identifier is not compared.
5
LAFMH13
0
R/W
When this bit is set to 1, ID-26 of the receive message
identifier is not compared.
4
LAFMH12
0
R/W
When this bit is set to 1, ID-25 of the receive message
identifier is not compared.
3
LAFMH11
0
R/W
When this bit is set to 1, ID-24 of the receive message
identifier is not compared.
2
LAFMH10
0
R/W
When this bit is set to 1, ID-23 of the receive message
identifier is not compared.
1
LAFMH9
0
R/W
When this bit is set to 1, ID-22 of the receive message
identifier is not compared.
0
LAFMH8
0
R/W
When this bit is set to 1, ID-21 of the receive message
identifier is not compared.
These bits are always read as 0. The write value should
always be 0.
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Section 14 Controller Area Network (HCAN)
14.3.18 Message Control (MC0 to MC15)
The message control register sets consist of eight 8-bit registers for one mailbox. The HCAN has
16 sets of these registers. Because message control registers are in RAM, their initial values after
power-on are undefined. Be sure to initialize them by writing 0 or 1. Figure 14.2 shows the
register names for each mailbox.
Mail box 0
MC0[1]
MC0[2]
MC0[3]
MC0[4]
MC0[5]
MC0[6]
MC0[7]
MC0[8]
Mail box 1
MC1[1]
MC1[2]
MC1[3]
MC1[4]
MC1[5]
MC1[6]
MC1[7]
MC1[8]
Mail box 2
MC2[1]
MC2[2]
MC2[3]
MC2[4]
MC2[5]
MC2[6]
MC2[7]
MC2[8]
Mail box 3
MC3[1]
MC3[2]
MC3[3]
MC3[4]
MC3[5]
MC3[6]
MC3[7]
MC3[8]
Mail box 15
MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8]
Figure 14.2 Message Control Register Configuration
The setting of message control registers are shown in the following. Figures 14.3 and 14.4 show
the correspondence between the identifiers and register bit names.
SOF
ID-28 ID-27
ID-18
RTR
IDE
R0
identifier
Figure 14.3 Standard Format
SOF
ID-28 ID-27
ID-18
Standard identifier
SRR
IDE
ID-17 ID-16
ID-0
RTR
R1
Extended identifier
Figure 14.4 Extended Format
Rev. 2.00 Dec. 05, 2005 Page 447 of 724
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Section 14 Controller Area Network (HCAN)
Register
Name
Bit
Bit Name
R/W
Description
MCx[1]
7 to 4

R/W
The initial value of these bits is undefined. They
must be initialized by writing 0 or 1.
3 to 0
DLC3 to DLC0
R/W
Data Length Code
Set the data length of a data frame or the data
length requested in a remote frame within the
range of 0 to 8 bits.
0000: 0 byte
0001: 1 byte
0010: 2 bytes
0011: 3 bytes
0100: 4 bytes
0101: 5 bytes
0110: 6 bytes
0111: 7 bytes
1xxx: 8 bytes
MCx[2]
7 to 0

R/W
MCx[3]
7 to 0

R/W
MCx[4]
7 to 0

R/W
MCx[5]
7 to 5
ID-20 to ID-18
R/W
Sets ID-20 to ID-18 in the identifier.
4
RTR
R/W
Remote Transmission Request
The initial value of these bits is undefined; they
must be initialized by writing 0 or 1.
Used to distinguish between data frames and
remote frames.
0: Data frame
1: Remote frame
3
IDE
R/W
Identifier Extension
Used to distinguish between the standard format
and extended format of data frames and remote
frames.
0: Standard format
1: Extended format
2

R/W
The initial value of this bit is undefined. It must be
initialized by writing 0 or 1.
1 to 0
ID-17 to ID-16
R/W
Sets ID-17 and ID-16 in the identifier.
MCx[6]
7 to 0
ID-28 to ID-21
R/W
Sets ID-28 to ID-21 in the identifier.
MCx[7]
7 to 0
ID-7 to ID-0
R/W
Sets ID-7 to ID-0 in the identifier.
MCx[8]
7 to 0
ID-15 to ID-8
R/W
Sets ID-15 to ID-8 in the identifier.
Note: x: Mailbox number
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Section 14 Controller Area Network (HCAN)
14.3.19 Message Data (MD0 to MD15)
The message data register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16
sets of these registers. Because message data registers are in RAM, their initial values after poweron are undefined. Be sure to initialize them by writing 0 or 1. Figure 14.5 shows the register
names for each mailbox.
Mail box 0
MD0[1]
MD0[2]
MD0[3]
MD0[4]
MD0[5]
MD0[6]
MD0[7]
MD0[8]
Mail box 1
MD1[1]
MD1[2]
MD1[3]
MD1[4]
MD1[5]
MD1[6]
MD1[7]
MD1[8]
Mail box 2
MD2[1]
MD2[2]
MD2[3]
MD2[4]
MD2[5]
MD2[6]
MD2[7]
MD2[8]
Mail box 3
MD3[1]
MD3[2]
MD3[3]
MD3[4]
MD3[5]
MD3[6]
MD3[7]
MD3[8]
Mail box 15
MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8]
Figure 14.5 Message Data Configuration
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Section 14 Controller Area Network (HCAN)
14.3.20 HCAN Monitor Register (HCANMON)
HCANMON is an 8-bit register that enables/disables an HCAN receive interrupt, controls
transmission stop of the HTxD pin, and reflects the states of the HCAN pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
RxDIE
0
R/W
HRxD Interrupt Enable
Selects whether an IRQ2 interrupt is caused by PF0 or
HRxD pin.
0: An IRQ2 interrupt is caused by pin PF0
1: An IRQ2 interrupt is caused by the HRxD pin
6
TxSTP
0
R/W
HTxD Transmission Stop
Controls transmission stop of the HTxD pin.
0: Enables transmission from the HTxD pin
1: Fixes an output level of the HTxD pin at 1 and
transmission is stopped
5
PKFE*
0
R/W
HCAN Enable
Selects PK7/HRxD1 and PK6/HTxD1 pin function
0: puts PK7 and PK6 pins in port function
1: puts PK7 pin in HRxD1 function and puts PK6 pin in
HTxD1 function
4 to 2 
Undefined 
Reserved
These bits are always read as undefined values and
cannot be modified.
1
TxD
Undefined R
Transmission pin
The state of the HTxD pin is read.
This bit cannot be modified.
0
RxD
Undefined R
Reception pin
The state of the HRxD pin is read.
This bit cannot be modified.
Note:
*
The PKFE bit supports only HCAN_1
Rev. 2.00 Dec. 05, 2005 Page 450 of 724
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Section 14 Controller Area Network (HCAN)
14.4
Operation
14.4.1
Hardware and Software Resets
The HCAN can be reset by a hardware reset or software reset.
• Hardware Reset
At power-on reset, or in hardware or software standby mode, the HCAN is initialized by
automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3)
in GSR. At the same time, all internal registers, except for message control and message data
registers, are initialized by a hardware reset.
• Software Reset
The HCAN can be reset by setting the MCR reset request bit (MCR0) in MCR via software. In
a software reset, the error counters (TEC and REC) are initialized, however other registers are
not. If the MCR0 bit is set while the CAN controller is performing a communication operation
(transmission or reception), the initialization state is not entered until message transfer has
been completed. The reset status bit (GSR3) in GSR is set on completion of initialization.
14.4.2
Initialization after Hardware Reset
After a hardware reset, the following initialization processing should be carried out:
1.
2.
3.
4.
5.
Clearing of IRR0 bit in the interrupt register (IRR)
Bit rate setting
Mailbox transmit/receive settings
Mailbox (RAM) initialization
Message transmission method setting
These initial settings must be made while the HCAN is in bit configuration mode. Configuration
mode is a state in which the GSR3 bit in GSR is set to 1 by a reset. Configuration mode is exited
by clearing the MCR0 bit in MCR to 0; when the MCR0 bit is cleared to 0, the HCAN
automatically clears the GSR3 bit in GSR. There is a delay between clearing the MCR0 bit and
clearing the GSR3 bit because the HCAN needs time to be internally reset. After the HCAN exits
configuration mode, the power-up sequence begins, and communication with the CAN bus is
possible as soon as 11 consecutive recessive bits have been detected.
Rev. 2.00 Dec. 05, 2005 Page 451 of 724
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Section 14 Controller Area Network (HCAN)
IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery
from software standby mode. Since an HCAN interrupt is initiated immediately when interrupts
are enabled, IRR0 should be cleared.
Hardware reset
: Settings by user
: Processing by hardware
MCR0 = 1 (automatic)
IRR0 = 1 (automatic)
GSR3 = 1 (automatic)
Initialization of HCAN module
Bit configuration mode
Period in which BCR, MBCR, etc.,
are initialized
Clear IRR0
BCR setting
MBCR setting
Mailbox initialization
Message transmission method initialization
MCR0 = 0
GSR3 = 0?
No
Yes
IMR setting (interrupt mask setting)
MBIMR setting (interrupt mask setting)
MC[x] setting (receive identifier setting)
LAFM setting (receive identifier mask setting)
GSR3 = 0 & 11
recessive bits received?
No
Yes
Can bus communication enabled
Figure 14.6 Hardware Reset Flowchart
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REJ09B0200-0200
Section 14 Controller Area Network (HCAN)
MCR0 = 1
: Settings by user
Bus idle?
No
: Processing by hardware
Yes
GSR3 = 1 (automatic)
Initialization of REC and TEC only
Correction
BCR setting
MBCR setting
Mailbox (RAM) initialization
Message transmission method
initialization
OK?
GSR3 = 1?
No
No
Yes
MCR0 = 0
GSR3 = 0?
No
Yes
Correction
IMR setting
MBIMR setting
MC[x] setting
LAFM setting
OK?
No
Yes
GSR3 = 0 & 11
recessive bits received?
No
Yes
CAN bus communication enabled
Figure 14.7 Software Reset Flowchart
Rev. 2.00 Dec. 05, 2005 Page 453 of 724
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Section 14 Controller Area Network (HCAN)
Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit
configuration register (BCR). Settings should be made such that all CAN controllers connected to
the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the
settable time quanta (tq).
1-bit time (8–25 time quanta)
SYNC_SEG
PRSEG
1 time quantum
PHSEG1
PHSEG2
Time segment 1 (TSEG1)
Time segment 2
(TSEG2)
4–16 time quanta
2–8 time quanta
Figure 14.8 Detailed Description of One-Bit Time
SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal
bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, BSP, and
SJW) are shown in table 14.2.
Table 14.2 Limits for the Settable Value
Name
Time segment 1
Abbreviation
TSEG1
Min. Value
B'0011*
2
3
Max. Value
B'1111
Time segment 2
TSEG2
B'001*
B'111
Baud rate prescaler
BRP
B'000000
B'111111
Bit sample point
BSP
B'0
B'1
B'00
B'11
Re-synchronization jump width
SJW*
1
Notes: 1. SJW is stipulated in the CAN specifications:
3 ≥ SJW ≥ 0
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
TSEG2 ≥ SJW
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
TSEG1 > TSEG2
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Section 14 Controller Area Network (HCAN)
Time quanta (tq) is an integer multiple of the number of system clocks, and is determined by the
baud rate prescaler (BRP) as follows. fCLK is the system clock frequency.
tq = 2 × (BPR setting + 1)/fCLK
The following formula is used to calculate the 1-bit time and bit rate.
1-bit time = tq × (3 + TSEG1 + TSEG2)
Bit rate = 1/Bit time
= fCLK/{2 × (BPR setting + 1) × (3 + TSEG1 + TSEG2)}
Note:
fCLK = φ (system clock)
A BCR value is used for BRP, TSEG1, and TSEG2.
Example: With a system clock of 24 MHz, a BRP setting of B'000000, a TSEG1 setting of
B'0101, and a TSEG2 setting of B'100:
Bit rate = 24/{2 × (0 + 1) × (3 + 5 + 4)} = 1 Mbps
Table 14.3 Setting Range for TSEG1 and TSEG2 in BCR
TSEG2 (BCR14−BCR12)
001
010
011
100
101
110
111
TSEG1
0011
No
Yes
No
No
No
No
No
(BCR11−BCR8)
0100
Yes*
Yes
Yes
No
No
No
No
0101
Yes*
Yes
Yes
Yes
No
No
No
0110
Yes*
Yes
Yes
Yes
Yes
No
No
0111
Yes*
Yes
Yes
Yes
Yes
Yes
No
1000
Yes*
Yes
Yes
Yes
Yes
Yes
Yes
1001
Yes*
Yes
Yes
Yes
Yes
Yes
Yes
1010
Yes*
Yes
Yes
Yes
Yes
Yes
Yes
1011
Yes*
Yes
Yes
Yes
Yes
Yes
Yes
1100
Yes*
Yes
Yes
Yes
Yes
Yes
Yes
1101
Yes*
Yes
Yes
Yes
Yes
Yes
Yes
1110
Yes*
Yes
Yes
Yes
Yes
Yes
Yes
1111
Yes*
Yes
Yes
Yes
Yes
Yes
Yes
Note: The time quantum values for TSEG1 and TSEG2 are determined by TSEG value + 1.
* Settable unless BRP = B'000000.
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Section 14 Controller Area Network (HCAN)
Mailbox Transmit/Receive Settings: The HCAN has 16 mailboxes. Mailbox 0 is receive-only,
while mailboxes 1 to 15 can be set for transmission or reception. The initial status of mailboxes 1
to 15 is for transmission. Mailbox transmit/receive settings are not initialized by a software reset.
Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding
mailbox for transmission use, whereas a setting of 1 in MBCR designates the corresponding
mailbox for reception use. When setting mailboxes for reception, in order to improve message
reception efficiency, high-priority messages should be set in low-to-high mailbox order.
Mailbox (Message Control/Data) Initial Settings: Message control/data are held in RAM, and
so their initial values are undefined after power is supplied. Initial values must therefore be set in
all the mailboxes (by writing 0s or 1s).
Setting the Message Transmission Method: The following two kinds of message transmission
methods are available.
• Transmission order determined by message identifier priority
• Transmission order determined by mailbox number priority
Either of the message transmission methods can be selected with the message transmission method
bit (MCR2) in the master control register (MCR): When messages are set to be transmitted
according to the message identifier priority, if several messages are designated as waiting for
transmission (TXPR = 1), the message with the highest priority in the message identifier is stored
in the transmit buffer. CAN bus arbitration is then carried out for the message stored in the
transmit buffer, and the message is transmitted when the transmission right is acquired. When the
TXPR bit is set, the highest-priority message is found and stored in the transmit buffer.
When messages are set to be transmitted according to the mailbox number priority, if several
messages are designated as waiting for transmission (TXPR = 1), messages are stored in the
transmit buffer in low-to-high mailbox order. CAN bus arbitration is then carried out for the
message stored in the transmit buffer, and the message is transmitted when the transmission right
is acquired.
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Section 14 Controller Area Network (HCAN)
14.4.3
Message Transmission
Messages are transmitted using mailboxes 1 to 15. The transmission procedure after initial settings
is described below, and a transmission flowchart is shown in figure 14.9.
Initialization (after hardware reset only)
Clear IRR0
BCR setting
MBCR setting
Mailbox initialization
Message transmission method setting
: Settings by user
: Processing by hardware
Interrupt settings
Transmit data setting
Arbitration field setting
Control field setting
Data field setting
Message transmission wait
TXPR setting
Bus idle?
No
Yes
Message transmission
GSR2 = 0 (during transmission only)
Transmission completed?
No
Yes
TXACK = 1
IRR8 = 1
IMR8 = 1?
Yes
No
Interrupt to CPU
Clear TXACK
Clear IRR8
End of transmission
Figure 14.9 Transmission Flowchart
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Section 14 Controller Area Network (HCAN)
CPU interrupt source settings: The CPU interrupt source is set by the interrupt mask register
(IMR) and mailbox interrupt mask register (MBIMR). Transmission acknowledge and
transmission abort acknowledge interrupts can be generated for individual mailboxes in the
mailbox interrupt mask register (MBIMR).
Arbitration field setting: The arbitration field is set by the message control registers MCx[5] to
MCx[8] in a transmit mailbox. For a standard format, an 11-bit identifier (ID-28 to ID-18) and the
RTR bit are set, and the IDE bit is cleared to 0. For an extended format, a 29-bit identifier (ID-28
to ID-0) and the RTR bit are set, and the IDE bit is set to 1.
Control field setting: In the control field, the byte length of the data to be transmitted is set within
the range of zero to eight bytes. The register to be set is the message control register MCx[1] in a
transmit mailbox.
Data field setting: In the data field, the data to be transmitted is set within the range zero to eight.
The registers to be set are the message data registers MDx[1] to MDx[8]. The byte length of the
data to be transmitted is determined by the data length code in the control field. Even if data
exceeding the value set in the control field is set in the data field, up to the byte length set in the
control field will actually be transmitted.
Message transmission: If the corresponding mailbox transmit wait bit (TXPR1 to TXPR15) in
the transmit wait register (TXPR) is set to 1 after message control and message data registers have
been set, the message enters transmit wait state. If the message is transmitted error-free, the
corresponding acknowledge bit (TXACK1 to TXACK15) in the transmit acknowledge register
(TXACK) is set to 1, and the corresponding transmit wait bit (TXPR1 to TXPR15) in the transmit
wait register (TXPR) is automatically cleared to 0. Also, if the corresponding bit (MBIMR1 to
MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit
(IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts,
interrupts may be sent to the CPU.
If transmission of a transmit message is aborted in the following cases, the message is
retransmitted automatically:
• CAN bus arbitration failure (failure to acquire the bus)
• Error during transmission (bit error, stuff error, CRC error, frame error, or ACK error)
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Section 14 Controller Area Network (HCAN)
Message transmission cancellation: Transmission cancellation can be specified for a message
stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the
bit for the corresponding mailbox (TXCR1 to TXCR15) to 1 in the transmit cancel register
(TXCR). Clearing the transmit wait register (TXPR) does not cancel transmission. When
cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the
corresponding bit is set to 1 in the abort acknowledge register (ABACK), and then an interrupt to
the CPU can be requested. Also, if the corresponding bit (MBIMR1-MBIMR15) in the mailbox
interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask
register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU.
However, a transmit wait message cannot be canceled at the following times:
• During internal arbitration or CAN bus arbitration
• During data frame or remote frame transmission
Figure 14.10 shows a flowchart for transmit message cancellation.
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Section 14 Controller Area Network (HCAN)
Message transmit wait TXPR setting
: Settings by user
: Processing by hardware
Set TXCR bit corresponding to
message to be canceled
No
Cancellation possible?
Yes
Message not sent
Clear TXCR, TXPR
ABACK = 1
IRR8 = 1
IMR8 = 1?
Completion of message transmission
TXACK = 1
Clear TXCR, TXPR
IRR8 = 1
Yes
No
Interrupt to CPU
Clear TXACK
Clear ABACK
Clear IRR8
End of transmission/transmission
cancellation
Figure 14.10 Transmit Message Cancellation Flowchart
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Section 14 Controller Area Network (HCAN)
14.4.4
Message Reception
The reception procedure after initial settings is described below. A reception flowchart is shown in
Figure 14.11.
Initialization
: Settings by user
Clear IRR0
BCR setting
MBCR setting
Mailbox (RAM) initialization
: Processing by hardware
Interrupt settings
Receive data setting
Arbitration field setting
Local acceptance filter settings
Message reception
(Match of identifier
in mailbox?)
No
Yes
Yes
Same RXPR = 1?
Unread message
No
Data frame?
No
Yes
RXPR, RFPR = 1
IRR2 = 1, IRR1 = 1
RXPR
IRR1 = 1
Yes
IMR1 = 1?
IMR2 = 1?
No
No
Interrupt to CPU
Interrupt to CPU
Message control read
Message data read
Message control read
Message data read
Clear IRR1
Clear IRR2, IRR1
Yes
Transmission of data frame corresponding
to remote frame
End of reception
Figure 14.11 Reception Flowchart
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Section 14 Controller Area Network (HCAN)
CPU interrupt source settings: CPU interrupt source settings are made in the interrupt mask
register (IMR) and mailbox interrupt register (MBIMR). The message to be received is also
specified. Data frame and remote frame receive wait interrupt requests can be generated for
individual mailboxes in the MBIMR.
Arbitration field setting: To receive a message, the message identifier must be set in advance in
the message control registers (MCx[1] to MCx[8]) for the receiving mailbox. When a message is
received, all the bits in the receive message identifier are compared with those in each message
control register identifier, and if a complete match is found, the message is stored in the matching
mailbox. Mailbox 0 has a local acceptance filter mask (LAFM) that allows Don't Care settings.
The LAFM setting can be made only for mailbox 0. By setting the Don't Care for all the bits in the
receive message identifier, messages of multiple identifiers can be received.
Examples:
• When the identifier of mailbox 1 is 010_1010_1010 (standard format), only one kind of
message identifier can be received by mailbox 1:
Identifier 1:
010_1010_1010
• When the identifier of mailbox 0 is 010_1010_1010 (standard format) and the LAFM setting is
000_0000_0011 (0: Care, 1: Don't Care), a total of four kinds of message identifiers can be
received by mailbox 0:
Identifier 1:
010_1010_1000
Identifier 2:
010_1010_1001
Identifier 3:
010_1010_1010
Identifier 4:
010_1010_1011
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Section 14 Controller Area Network (HCAN)
Message reception: When a message is received, a CRC check is performed automatically. If the
result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether
the message can be received or not.
• Data frame reception
If the received message is confirmed to be error-free by the CRC check, the identifier in the
mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive
message are compared. If a complete match is found, the message is stored in the matching
mailbox. The message identifier comparison is carried out on each mailbox in turn, starting
with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison
ends at that point, the message is stored in the matching mailbox, and the corresponding
receive complete bit (RXPR0 to RXPR15) in the receive complete register (RXPR) is set.
However, if the identifier matches that of mailbox 0 LAFM, the mailbox comparison sequence
does not end at that point, but continues from mailbox 1. Therefore, the message for mailbox 0
can also be received by another mailbox. Note that the same message cannot be stored in two
or more mailbox of the mailboxes 1 to 15. On receiving a message, a CPU interrupt request
may be generated according to the settings of the mailbox interrupt mask register (MBIMR)
and interrupt mask register (IMR).
• Remote frame reception
A mailbox can store two kinds of messages: data frames and remote frames. A remote frame
differs from a data frame in the value of the remote transmission request bit (RTR) in the
message control register and its 0-byte data field. The data length to be returned in a data frame
must be stored in the data length code (DLC) in the message control.
When a remote frame (RTR = recessive) is received, the corresponding bit in the remote
request wait register (RFPR) is set. Interrupts can be sent to the CPU according to the settings
of the corresponding bit (MBIMR0 to MBIMR15) in the mailbox interrupt mask register
(MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register
(IMR).
Unread message overwrite: If the receive message identifier matches the mailbox identifier, the
receive message is stored in the mailbox regardless of whether the mailbox contains an unread
message or not. If a message overwrite occurs, the corresponding bit (UMSR0 to UMSR15) in the
unread message register (UMSR) is set. In overwriting an unread message, the unread message
register (UMSR) is set when a new message is received before the corresponding bit in the receive
complete register (RXPR) has been cleared. If the unread interrupt flag (IRR9) in the interrupt
mask register (IMR) is set to enable interrupts at this time, an interrupt can be sent to the CPU.
Figure 14.12 shows a flowchart for unread message overwriting.
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Section 14 Controller Area Network (HCAN)
: Settings by user
Unread message overwrite
: Processing by hardware
UMSR = 1
IRR9 = 1
IMR9 = 1?
Yes
No
Interrupt to CPU
Clear IRR9
Message control/message data read
End
Figure 14.12 Unread Message Overwrite Flowchart
14.4.5
HCAN Sleep Mode
The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep
state in order to reduce current consumption. Figure 14.13 shows a flowchart of the HCAN sleep
mode.
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Section 14 Controller Area Network (HCAN)
MCR5 = 1
: Settings by user
: Processing by hardware
No
Bus idle?
Initialize TEC and REC
No
Bus operation?
Yes
IRR12 = 1
Do not access MB
during these steps
No
IMR12 = 1?
CPU interrupt
Yes
Sleep mode clearing method
MCR7 = 0?
No (automatic)
Yes (manual)
Clear sleep mode?
No
GSR3 = 1?
No
Yes
MCR5 = 0
GSR3 = 1?
No
Yes
Yes
MCR5 = 0
11 recessive bits
received?
No
Yes
CAN bus communication possible
Figure 14.13 HCAN Sleep Mode Flowchart
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Section 14 Controller Area Network (HCAN)
HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master
control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is
delayed until the bus becomes idle.
Either of the following methods of clearing HCAN sleep mode can be selected:
• Clearing by software
• Clearing by CAN bus operation
In order to re-enter CAN bus communication enabled state, eleven recessive bits must be received
after HCAN sleep mode was cleared.
Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.
Clearing by CAN bus operation: The cancellation method is selected by the MCR7 bit setting in
MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs an
operation and this change is detected. In this case, the first message is not stored in a mailbox;
messages will be received normally from the second message onward. When a change is detected
on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the
interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is
set to enable interrupts at this time, an interrupt can be sent to the CPU.
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Section 14 Controller Area Network (HCAN)
14.4.6
HCAN Halt Mode
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an
HCAN hardware or software reset. Figure 14.14 shows a flowchart of the HCAN halt mode.
MCR1 = 1
Bus idle?
No
Yes
Set MBCR
MCR1 = 0
: Settings by user
CAN bus communication possible
: Processing by hardware
Figure 14.14 HCAN Halt Mode Flowchart
HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until
the bus becomes idle.
HCAN halt mode is cleared by clearing MCR1 to 0.
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Section 14 Controller Area Network (HCAN)
14.5
Interrupt Sources
Table 14.4 lists the HCAN interrupt sources. These sources can be masked except the reset
processing interrupt by power-on reset (IRR0). Masking is implemented using the mailbox
interrupt mask register (MBIMR), interrupt mask register (IMR), and IRQ enable register (IER).
For details on the interrupt vector of each interrupt source, see section 5, Interrupt Controller.
Table 14.4 HCAN Interrupt Sources (HCAN_0, HCAN_1)
Name
ERS0/OVR0
Description
Interrupt
Flag
DTC
Activation
Not possible
Error passive interrupt (TEC ≥ 128 or REC ≥ 128)
IRR5
Bus off interrupt (TEC ≥ 256)
IRR6
Reset processing interrupt by power-on reset
IRR0
Remote frame reception
IRR2
Error warning interrupt (TEC ≥ 96)
IRR3
Error warning interrupt (REC ≥ 96)
IRR4
Overload frame transmission interrupt
IRR7
Unread message overwrite
IRR9
Detection of CAN bus operation in HCAN sleep mode
IRR12
RM0
Mailbox 0 message reception
IRR1
Possible
RM1
Mailbox 1-15 message reception
IRR1
Not possible
SLE0
Message transmission/cancellation
IRR8
Not possible
IRQ2
Setting the RxDIE bit in HCANMON to 1 generates an
IRQ2 interrupt caused by an HRxD input signal. (While
HRxD1 is selected in PK7)
IRQ2F
Possible
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Section 14 Controller Area Network (HCAN)
14.6
DTC Interface
The DTC can be activated by the reception of a message in HCAN mailbox 0. When the DTC
activation is set and DTC transfer ends, the RXPR0 and RFPR0 flags are automatically cleared.
An interrupt request is not sent to the CPU by a reception interrupt from the HCAN. Figure 14.15
shows a DTC transfer flowchart.
: Settings by user
DTC initialization
DTC enable register setting
DTC register information setting
: Processing by hardware
Message reception in HCAN’s
mailbox 0
DTC activation
End of DTC transfer?
No
Yes
RXPR and RFPR clearing
Transfer counter = 0
or DISEL = 1?
No
Yes
Interrupt to CPU
End
Figure 14.15 DTC Transfer Flowchart
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Section 14 Controller Area Network (HCAN)
14.7
CAN Bus Interface
A bus transceiver IC is necessary to connect this LSI to a CAN bus. A Philips PCA82C250
transceiver IC is recommended. If any other product is used, confirm that it is compatible with the
PCA82C250. Figure 14.16 shows a sample connection diagram.
124 Ω
This LSI
Vcc
PCA82C250
RS
Vcc
HRxD
RxD CANH
HTxD
TxD CANL
Vref
CAN bus
GND
NC
124 Ω
Note: NC: No Connection
Figure 14.16 High-Speed Interface Using PCA82C250
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Section 14 Controller Area Network (HCAN)
14.8
Usage Notes
14.8.1
Module Stop Mode Setting
HCAN operation can be disabled or enabled using the module stop control register. The HCAN
operation is set to be halted initially. Register access is enabled by clearing module stop mode. For
details, see section 21, Power-Down Modes.
14.8.2
Reset
The HCAN is reset by a power-on reset, in hardware standby mode, in software standby mode,
and in module stop mode. All the registers are initialized by a reset, however mailboxes (message
control (MCx[x])/message data (MDx[x])) are not initialized. Mailboxes (message control
(MCx[x])/message data (MDx[x])) are initialized after power-on and at this time, their initial
values are undefined. Therefore, always initialize mailboxes after a power-on reset, a transition to
hardware standby mode, software standby mode, module stop mode, or watch mode. After a
power-on reset, recovery from software standby mode, or cancellation of module stop mode, the
reset interrupt flag (IRR0) is automatically set. Since this bit cannot be masked in the interrupt
mask register (IMR), an HCAN interrupt will be initiated immediately after an HCAN interrupt is
enabled by the interrupt controller without clearing the flag. IRR0 should therefore be cleared at
initialization.
14.8.3
HCAN Sleep Mode
The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus
operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep
mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set even
in sleep mode.
14.8.4
Interrupts
When the mailbox interrupt mask register (MBIMR) is set, the interrupt registers (IRR8, 2, 1) are
not set by reception completion, transmission completion, or transmission cancellation of the set
mailboxes.
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Section 14 Controller Area Network (HCAN)
14.8.5
Error Counters
In the case of error active and error passive, REC and TEC perform count up and down normally.
In the bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. When REC
reaches 96 during the count, IRR4 and GSR1 are set.
14.8.6
Register Access
Byte or word access can be performed for all HCAN registers. Longword access should be
avoided.
14.8.7
HCAN Medium-Speed Mode
In medium-speed mode, the HCAN registers cannot be read/written.
14.8.8
Register Hold in Standby Modes
All HCAN registers are initialized in hardware standby mode and software standby mode.
14.8.9
Use on Bit Manipulation Instructions
Since the HCAN status flag is cleared by writing 1, do not use the bit manipulation instructions to
clear the flag. To clear the flag, use the MOV instructions and write 1 only to the bit to be cleared.
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Section 14 Controller Area Network (HCAN)
14.8.10 HCAN TXCR Operation
1.
When the transmit wait cancel register (TXCR) is used to cancel transmission of the message
in a mailbox waiting for transmission, the corresponding bit in TXCR and the transmit wait
register (TXPR) may not be cleared even after the transmission is canceled. This occurs when
the following conditions are all satisfied.
[Conditions]
 The HRxD pin is tied to "1" because of a CAN bus error, etc.
 There is one or more mailboxes waiting for transmission or transmitting.
 Ongoing message transmission from a mailbox is canceled by TXCR.
If this occurs, the transmission is canceled but TXPR and TXCR continue to indicate a wrong
status telling that a message is being cancelled. As a result, transmission cannot be restarted
even after the HRxD pin is released from the tied state and the CAN bus has recovered. If there
are two or more messages for transmission, a message which is not being transmitted is
canceled and a message being transmitted retains its state.
To avoid this, take either of the following countermeasures.
[Countermeasures]
 Do not cancel transmission by TXCR. Transmission will be completed after the CAN bus
has recovered, then TXPR is cleared and the HCAN operates normally.
 To cancel transmission, write 1 to the corresponding bit in TXCR repeatedly until the bit
becomes 0. TXPR and TXCR are cleared, and the HCAN operates normally.
2. When the bus-off state is entered while any mailbox is waiting for transmission with TXPR
set, transmission cannot be canceled even if TXCR is set because the internal state machine
does not operate during the bus-off state. Because of this, on recovery from the bus-off state,
one message will be transmitted or the message will be canceled with a transmission error. For
message clearing on recovery from the bus-off state, take the following countermeasure.
[Countermeasure]
 Reset the HCAN during the bus-off period to clear the messages in the mailboxes waiting
for transmission. To reset the HCAN, set the module stop bit (MSTPC3 in MSTPCRC) to 1
and then clear it. In this case, the HCAN is entirely reset. Therefore the initial settings must
be made again.
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Section 14 Controller Area Network (HCAN)
14.8.11 HCAN Transmit Procedure
When transmission is set while the bus is in the idle state, if the next transmission is set or the set
transmission is canceled under the following conditions within 50 µs, the transmit message ID of
being set may be damaged.
•
•
When the second transmission has the message whose priority is higher than the first one
When the massage of the highest priority is canceled in the first transmission
Make whichever setting shown below to avoid the message IDs from being damaged.
• Set transmission in one TXPR. After transmission of all transmit messages is completed, set
transmission again (mass transmission setting). The interval between transmission settings
should be 50 µs or longer.
• Make the transmission setting according to the priority of transmit messages.
• Set the interval to be 50 µs or longer between TXPR and another TXPR or between TXPR and
TXCR.
Table 14.5 Interval Limitation between TXPR and TXPR or between TXPR and TXCR
Baud Rate (bps)
Set Interval (µs)
1M
50
500 k
50
250 k
50
14.8.12 Note on Releasing the HCAN Reset or HCAN Sleep
Before releasing the HCAN reset or HCAN sleep (MCR0 = 0 or MCR5 = 0), confirm that the
GSR3 bit (the reset status bit) is set to 1.
14.8.13 Note on Accessing Mailbox during the HCAN Sleep
Do not access the mailbox during the HCAN sleep. If accessed, the CPU might halt. Accessing
registers during the HCAN sleep does not cause the CPU halt, nor does accessing the mailbox in
other than the HCAN sleep mode.
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Section 15 A/D Converter
Section 15 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to sixteen
analog input channels to be selected. The block diagram of the A/D converter is shown in figure
15.1.
15.1
•
•
•
•
•
•
•
•
•
Features
10-bit resolution
Sixteen input channels
Conversion time: 13.3 µs per channel (at 20 MHz operation)
Two operating modes
 Single mode: Single-channel A/D conversion
 Scan mode: Continuous A/D conversion on 1 to 4 channels
Four data registers
 Conversion results are held in a 16-bit data register for each channel
Sample and hold function
Three conversion start methods
 Software
 16-bit timer pulse unit (TPU) conversion start trigger
 External trigger signal
Interrupt request
 An A/D conversion end interrupt request (ADI) can be generated
Module stop mode can be set
ADCMS38A_000020020300
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Section 15 A/D Converter
Module data bus
Vref
10-bit D/A
AVSS
Bus interface
A
D
D
R
A
A
D
D
R
B
A
D
D
R
C
A
D
D
R
D
A
D
C
S
R
A
D
C
R
φ/2
+
φ/4
Comparator
Multiplexer
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
Successive approximations
register
AVCC
Internal data bus
Control circuit
φ/8
Sample-andhold circuit
φ/16
ADI
interrupt
Conversion start
trigger from TPU
ADTRG
[Legend]
ADCR:
A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
Figure 15.1 Block Diagram of A/D Converter
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Section 15 A/D Converter
15.2
Input/Output Pins
Table 15.1 summarizes the input pins used by the A/D converter. 16 analog input pins are divided
into four groups, each of which includes four channels; analog input pins 0 to 3 (AN0 to AN3)
comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1, analog input pins
8 to 11 (AN8 to AN11) comprising group 2, and analog input pins 12 to 15 (AN12 to AN15)
comprising group 3. The AVcc and AVss pins are the power supply pins for the A/D converter
analog section. The Vref pin is the A/D conversion reference voltage pin.
Table 15.1 Pin Configuration
Pin Name
Symbol
I/O
Function
Analog power supply pin
AVCC
Input
Analog section power supply and reference
voltage
Analog ground pin
AVSS
Input
Analog section ground and reference voltage
Reference voltage pin
Vref
Input
Reference voltage of A/D conversion
Analog input pin 0
AN0
Input
Group 0 analog input pins
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
Analog input pin 8
AN8
Input
Analog input pin 9
AN9
Input
Analog input pin 10
AN10
Input
Analog input pin 11
AN11
Input
Analog input pin 12
AN12
Input
Analog input pin 13
AN13
Input
Analog input pin 14
AN14
Input
Analog input pin 15
AN15
Input
A/D external trigger input pin ADTRG
Input
Group 1 analog input pins
Group 2 analog input pins
Group 3 analog input pins
External trigger input pin for starting A/D
conversion
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Section 15 A/D Converter
15.3
Register Description
The A/D converter has the following registers. Module stop mode for the A/D converter is
specified with the MSTPA1 bit in the module stop control register (MSTPCRA). For details on the
module stop control register A (MSTPCRA), refer to section 21.1.3, Module Stop Control
Register A to D (MSTPCRA to MSTPCRD).
•
•
•
•
•
•
A/D data register A (ADDRA)
A/D data register B (ADDRB)
A/D data register C (ADDRC)
A/D data register D (ADDRD)
A/D control/status register (ADCSR)
A/D control register (ADCR)
15.3.1
A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers to store conversion results for each channel are shown in
table 15.2.
The converted 10-bit data is stored in bits 6 to 15 in ADDR. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading the ADDR, always read the upper byte first, and then read the lower byte, or read in
word unit. Otherwise, the read contents are not guaranteed.
Table 15.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
CH3 = 0
CH3 = 1
Group 0
(CH2 = 0)
Group 1
(CH2 = 1)
Group 2
(CH2 = 0)
Group 3
(CH2 = 1)
A/D Data Register to
Store the A/D
Conversion Results
AN0
AN4
AN8
AN12
ADDRA
AN1
AN5
AN9
AN13
ADDRB
AN2
AN6
AN10
AN14
ADDRC
AN3
AN7
AN11
AN15
ADDRD
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Section 15 A/D Converter
15.3.2
A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit
Bit Name
Initial
Value
R/W
Description
7
ADF
0
R/(W)
A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
•
When A/D conversion ends
•
When A/D conversion ends on all specified
channels
[Clearing conditions]
6
ADIE
0
R/W
•
When 0 is written after reading ADF = 1
•
When the DTC is activated by an ADI interrupt and
ADDR is read
A/D Interrupt Enable
A/D conversion end interrupt (ADI) is enabled when this
bit is set to 1.
5
ADST
0
R/W
A/D Start
Clearing this bit to 0 stops A/D conversion, and the A/D
converter enters the wait state.
Setting this bit to 1 starts A/D conversion. In single
mode, this bit is automatically cleared to 0 when
conversion on the specified channel is complete. In
scan mode, conversion continues sequentially on the
specified channels until this bit is cleared to 0 by
software, a reset, or a transition to software standby
mode, hardware standby mode or module stop mode.
4
SCAN
0
R/W
Scan Mode
Selects the A/D conversion operating mode.
0: Single mode
1: Scan mode
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Section 15 A/D Converter
Bit
Bit Name
Initial
Value
R/W
Description
3
CH3
0
R/W
Channel Select 0 to 3
2
CH2
0
R/W
Select analog input channels.
1
CH1
0
R/W
When SCAN = 0
When SCAN = 1
0
CH0
0
R/W
0000: AN0
0000: AN0
0001: AN1
0001: AN0, AN1
0010: AN2
0010: AN0 to AN2
0011: AN3
0011: AN0 to AN3
0100: AN4
0100: AN4
0101: AN5
0101: AN4, AN5
0110: AN6
0110: AN4 to AN6
0111: AN7
0111: AN4 to AN7
1000: AN8
1000: AN8
1001: AN9
1001: AN8, AN9
1010: AN10
1010: AN8 to AN10
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1011: AN11
1011: AN8 to AN11
1100: AN12
1100: AN12
1101: AN13
1101: AN12, AN13
1110: AN14
1110: AN12 to AN14
1111: AN15
1111: AN12 to AN15
Section 15 A/D Converter
15.3.3
A/D Control Register (ADCR)
The ADCR enables A/D conversion started by an external trigger signal.
Bit
Bit Name
Initial
Value
R/W
Description
7
TRGS1
0
R/W
Timer Trigger Select 0 and 1
6
TRGS0
0
R/W
Enable the start of A/D conversion by a trigger signal.
Bits TRGS0 and TRGS1 should be set while A/D
conversion is stopped (ADST = 0).
00: A/D conversion is started by software
01: A/D conversion is started by TPU conversion start
trigger
10: Setting prohibited
11: A/D conversion is started by the ADTRG pin
5, 4

All 1

Reserved
These bits are always read as 1.
3
CKS1
0
R/W
Clock Select 0 and 1
2
CKS0
0
R/W
Specify the A/D conversion time. The conversion time
should be changed only when ADST = 0. Specify a
value within the range shown in table 23.7 in section 23,
Electrical Characteristics.
00: Conversion time = 530 states (max.)
01: Conversion time = 266 states (max.)
10: Conversion time = 134 states (max.)
11: Conversion time = 68 states (max.)
1, 0

All 1

Reserved
These bits are always read as 1.
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Section 15 A/D Converter
15.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. When changing the operating mode or analog input
channel, clear the ADST bit in ADCSR to 0 first in order to prevent incorrect operation. The
ADST bit can be set at the same time as the operating mode or analog input channel is changed.
15.4.1
Single Mode
In single mode, A/D conversion is performed only once on the specified single channel as follows:
1. A/D conversion is started when the ADST bit is set to 1 by software or external trigger input.
2. When A/D conversion is completed, the result is transferred to the A/D data register
corresponding to the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit retains 1 during A/D conversion. When A/D conversion ends, the ADST bit is
automatically cleared to 0 and the A/D converter enters the wait state. If the ADST bit is
cleared to 0 during A/D conversion, the conversion is stopped and the A/D converter enters the
wait state.
15.4.2
Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the specified channels up to four
channels as follows.
1. When the ADST bit is set to 1 by software, TPU or external trigger input, A/D conversion
starts on the first channel in the group (for example, AN0 when CH3 and CH2 = 00, AN4
when CH3 and CH2 = 01, AN8 when CH3 and CH2 = 10, or AN12 when CH3 and CH2 = 11).
2. When the A/D conversion is completed on one channel, the result is sequentially transferred to
the A/D data register corresponding to the channel.
3. When the conversion is completed on all the selected channels, the ADF bit in ADCSR is set
to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion
ends. Then, the A/D converter restarts the conversion from the first channel in the group.
4. Steps 2 to 3 are repeated as long as the ADST bit is set to 1. When the ADST bit is cleared to
0, the A/D conversion stops and the A/D converter enters the wait state.
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Section 15 A/D Converter
15.4.3
Input Sampling and A/D Conversion Time
The A/D converter includes the sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, and
then conversion is started. Figure 15.2 shows the A/D conversion timing. Table 15.3 shows the
A/D conversion time.
As shown in figure 15.2, the A/D conversion time (tCONV) includes tD and input sampling time (tSPL).
The length of tD varies depending on the timing of the write access to ADCSR. Therefore, the total
conversion time varies within the range shown in table 15.3.
In scan mode, the values given in table 15.3 indicate the first conversion time. The second and
subsequent conversion time is shown in table 15.4. In both cases, set bits CKS1 and CKS0 in
ADCR within the range shown in table 23.7 in section 23, Electrical Characteristics.
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
tD
tSPL
tCONV
[Legend]
(1):
ADCSR write cycle
(2):
ADCSR address
A/D conversion start delay
tD:
Input sampling time
tSPL:
tCONV: A/D conversion time
Figure 15.2 A/D Conversion Timing
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Section 15 A/D Converter
Table 15.3 A/D Conversion Time (Single Mode)
CKS1 = 0
CKS0 = 0
Item
Symbol Min. Typ. Max.
CKS1 = 1
CKS0 = 1
CKS0 = 0
CKS0 = 1
Min. Typ. Max.
Min. Typ. Max.
Min. Typ. Max.
A/D conversion tD
start delay
18

33
10

17
6

9
4

5
Input sampling tSPL
time

127 

63


31


15

A/D conversion tCONV
time
515 
266
131 
134
67

68
530
259 
Note: All values represent the number of states.
Table 15.4 A/D Conversion Time (Scan Mode)
CKS1
CKS0
Conversion Time (State)
0
0
512 (Fixed)
1
256 (Fixed)
1
0
128 (Fixed)
1
64 (Fixed)
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Section 15 A/D Converter
15.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When bits TRGS0 and TRGS1 in ADCR are set to
11, an external trigger is input on the ADTRG pin. At the falling edge of the ADTRG pin, the
ADST bit in ADCSR is set to 1, and the A/D conversion starts. Other operations are the same as
when the ADST bit has been set to 1 by software in both single and scan modes. Figure 15.3
shows the timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 15.3 External Trigger Input Timing
15.5
Interrupt Source
When A/D conversion is completed, the A/D converter generates an A/D conversion end interrupt
(ADI). The ADI interrupt request is enabled when the ADIE bit is set to 1 while the ADF bit in
ADCSR is set to 1 after A/D conversion is completed. The DTC can be activated by an ADI
interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables
continuous conversion without imposing a load on software.
Table 15.5 A/D Converter Interrupt Source
Name
Interrupt Source
Interrupt Source Flag
DTC Activation
ADI
A/D conversion completed
ADF
Possible
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Section 15 A/D Converter
15.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15.4).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'000) to
B'0000000001 (H'001) (see figure 15.5).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see
figure 15.5).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristic between zero voltage and fullscale voltage. Does not include offset error, full-scale error, or quantization error (see figure
15.5).
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
Rev. 2.00 Dec. 05, 2005 Page 486 of 724
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Section 15 A/D Converter
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
Quantization error
001
000
1
2
1024 1024
1022 1023 FS
1024 1024
Analog
input voltage
Figure 15.4 A/D Conversion Accuracy Definitions
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
Offset error
FS
Analog
input voltage
Figure 15.5 A/D Conversion Accuracy Definitions
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Section 15 A/D Converter
15.7
Usage Notes
15.7.1
Module Stop Mode Setting
Operation of the A/D converter can be disabled or enabled using the module stop control register.
The initial setting is for operation of the A/D converter to be halted. Register access is enabled by
clearing module stop mode. For details, refer to section 21, Power-Down Modes.
15.7.2
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal
for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the
A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling
time; if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be
possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with
a large capacitance provided externally, the input load will essentially comprise only the internal
input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass
filter effect is obtained in this case, it may not be possible to follow an analog signal with a large
differential coefficient (e.g., 5 mV/µs or greater) (see figure 15.6). When converting a high-speed
analog signal or converting in scan mode, a low-impedance buffer should be inserted.
15.7.3
Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as
AVss.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board (i.e., acting as antennas).
Rev. 2.00 Dec. 05, 2005 Page 488 of 724
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Section 15 A/D Converter
This LSI
Sensor output
impedance
to 5 kΩ
A/D converter
equivalent circuit
10 kΩ
Sensor input
Low-pass
filter
C to 0.1 µF
Cin =
15 pF
20 pF
Figure 15.6 Example of Analog Input Circuit
15.7.4
Range of Analog Power Supply and Other Pin Settings
If the conditions below are not met, the reliability of the device may be adversely affected.
• Analog input voltage range
The voltage applied to analog input pin ANn during A/D conversion should be in the range
AVss ≤ VNn ≤ AVcc.
• Relationship between AVcc, AVss and Vcc, Vss
Set AVss = Vss as the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is
not used, the AVcc and AVss pins must not be left open.
• Setting range of the Vref pin
The reference voltage set by the Vref pin should be in the range Vref ≤ AVcc.
15.7.5
Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital
circuitry must be isolated from the analog input signals (AN0 to AN15) and analog power supply
(AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one
point to a stable digital ground (Vss) on the board.
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Section 15 A/D Converter
15.7.6
Notes on Noise Countermeasures
A protection circuit should be connected in order to prevent damage due to abnormal voltage, such
as an excessive surge at the analog input pins (AN0 to AN15), between AVcc and AVss, as shown
in figure 15.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to
AN0 to AN15 must be connected to AVss.
If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN15) are
averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in
scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit
in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in
the analog input pin voltage. Careful consideration is therefore required when deciding circuit
constants.
AVCC
Rin*2
100 Ω
AN0 to AN15
*1
0.1 µF
AVSS
Notes: Values are reference values.
1.
10 µF
0.01 µF
2. Rin: Input impedance
Figure 15.7 Example of Analog Input Protection Circuit
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Section 15 A/D Converter
Table 15.6 Analog Pin Specifications
Item
Min.
Max.
Unit
Analog input capacitance

20
pF
Permissible signal source impedance

5
kΩ
10 kΩ
AN0 to AN15
To A/D converter
20 pF
Note: Values are reference values.
Figure 15.8 Analog Input Pin Equivalent Circuit
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Section 15 A/D Converter
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Section 16 Motor Control PWM Timer (PWM)
Section 16 Motor Control PWM Timer (PWM)
This LSI has two channels of on-chip motor control PWM (pulse width modulator) with a
maximum capability of 16 pulse outputs in total.
16.1
Features
• Maximum of 16 pulse outputs
 Two 10-bit PWM channels, each with eight outputs.
 10-bit counter (PWCNT) and cycle register (PWCYR).
 Duty and output polarity can be set for each output.
• Automatic data transfer in every cycle
 Each of four duty registers (PWDTR) is provided with buffer registers (PWBFR), with data
transferred automatically every cycle.
• Duty settings selectable
 A duty cycle of 0% to 100% can be selected by means of a duty register setting.
• Operating clock selectable
 There is a choice of five operating clocks (φ, φ/2, φ/4, φ/8, φ/16).
• High-speed access via internal 16-bit bus
• Two interrupt sources
 An interrupt can be requested independently for each channel by a cycle register compare
match.
• Automatic transfer of register data
 Block transfer and one-word data transfer are available by activating the data transfer
controller (DTC).
• On-chip output driver
 IOL/IOH: 15 mA typ. and 30 mA max.
 Total IOL/IOH: 120 mA max. (target value)
• Module stop mode can be set
MPWM000A_000020020200
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Section 16 Motor Control PWM Timer (PWM)
Figure 16.1 shows a block diagram of PWM.
φ, φ/2, φ/4, φ/8, φ/16
Interrupt
request
PWCR
12 9
0
PWOCR
PWCYR
PWPR
12 9
0
PWBFRA
PWDTRA
PWBFRC
PWDTRC
PWBFRE
PWBFRG
[Legend]
PWCR:
PWOCR:
PWPR:
PWCNT:
PWCYR:
PWDTRA, PWDTRC, PWDTRE, PWDTRG:
PWBFRA, PWBFRC, PWBFRE, PWBFRG:
PWBTCR:
PWBTCR
Internal
data bus
Bus interface
Compare
match
PWCNT
PWDTRE
PWDTRG
PWM control register
PWM output control register
PWM polarity register
PWM counter
PWM cycle register
PWM duty registers A, C, E, G
PWM buffer registers A, C, E, G
PWM buffer transfer control register
Figure 16.1 Block Diagram of PWM
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Port
control
P/N
P/N
PWMA
P/N
PWMC
PWMD
P/N
P/N
P/N
P/N
P/N
PWMB
PWME
PWMF
PWMG
PWMH
Section 16 Motor Control PWM Timer (PWM)
16.2
Input/Output Pins
Table 16.1 shows the PWM pin configuration.
Table 16.1 Pin Configuration
Channel
Name
Abbrev.
I/O
Function
1
PWM output pin 1A
PWM1A
Output
Channel 1A PWM output
PWM output pin 1B
PWM1B
Output
Channel 1B PWM output
PWM output pin 1C
PWM1C
Output
Channel 1C PWM output
PWM output pin 1D
PWM1D
Output
Channel 1D PWM output
PWM output pin 1E
PWM1E
Output
Channel 1E PWM output
PWM output pin 1F
PWM1F
Output
Channel 1F PWM output
PWM output pin 1G
PWM1G
Output
Channel 1G PWM output
PWM output pin 1H
PWM1H
Output
Channel 1H PWM output
PWM output pin 2A
PWM2A
Output
Channel 2A PWM output
PWM output pin 2B
PWM2B
Output
Channel 2B PWM output
PWM output pin 2C
PWM2C
Output
Channel 2C PWM output
PWM output pin 2D
PWM2D
Output
Channel 2D PWM output
PWM output pin 2E
PWM2E
Output
Channel 2E PWM output
PWM output pin 2F
PWM2F
Output
Channel 2F PWM output
PWM output pin 2G
PWM2G
Output
Channel 2G PWM output
PWM output pin 2H
PWM2H
Output
Channel 2H PWM output
2
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Section 16 Motor Control PWM Timer (PWM)
16.3
Register Descriptions
The PWM has the following registers for each channel.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PWM control register (PWCR)
PWM output control register (PWOCR)
PWM polarity register (PWPR)
PWM counter (PWCNT)
PWM cycle register (PWCYR)
PWM duty register A (PWDTRA)
PWM duty register C (PWDTRC)
PWM duty register E (PWDTRE)
PWM duty register G (PWDTRG)
PWM buffer register A (PWBFRA)
PWM buffer register C (PWBFRC)
PWM buffer register E (PWBFRE)
PWM buffer register G (PWBFRG)
PWM buffer transfer control register (PWBTCR)
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Section 16 Motor Control PWM Timer (PWM)
16.3.1
PWM Control Register (PWCR)
PWCR performs interrupt control, starting/stopping of the counter, and counter clock selection. It
also contains a flag that indicates a compare match with PWCYR.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
These bits are always read as 1 and cannot be
modified.
5
IE
0
R/W
Interrupt Enable
Enables or disables an interrupt request in the event of
a compare match with PWCYR of the corresponding
channel.
0: Interrupt disabled
1: Interrupt enabled
4
CMF
0
R/(W)* Compare Match Flag
Indicates the occurrence of a compare match with
PWCYR of the corresponding channel.
[Setting condition]
When PWCNT = PWCYR
[Clearing condition]
3
CST
0
R/W
•
When 0 is written to CMF after reading CMF = 1
•
When the DTC is activated by a compare match
interrupt, and the DISEL bit in MRB of the DTC is 0
Counter Start
Selects starting or stopping of PWCNT of the
corresponding channel.
0: PWCNT is stopped
1: PWCNT is started
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Section 16 Motor Control PWM Timer (PWM)
Bit
Bit Name
Initial
Value
R/W
Description
2
CKS2
0
R/W
Clock Select
1
CKS1
0
R/W
0
CKS0
0
R/W
These bits select the operating clock for PWCNT of the
corresponding channel.
000: Counts on φ/1
001: Counts on φ/2
010: Counts on φ/4
011: Counts on φ/8
1xx: Counts on φ/16
[Legend]
x:
Don't care
Note: * Only 0 can be written, to clear the flag.
16.3.2
PWM Output Control Register (PWOCR)
PWOCR enables or disables PWM output.
Bit
Bit Name
Initial
Value
R/W
Description
7
OEnH
0
R/W
Output Enable
6
OEnG
0
R/W
5
OEnF
0
R/W
Each of these bits enables or disables the
corresponding PWM output.
4
OEnE
0
R/W
3
OEnD
0
R/W
2
OEnC
0
R/W
1
OEnB
0
R/W
0
OEnA
0
R/W
(n = 1, 2)
Rev. 2.00 Dec. 05, 2005 Page 498 of 724
REJ09B0200-0200
0: PWM output disabled
1: PWM output enabled
Section 16 Motor Control PWM Timer (PWM)
16.3.3
PWM Polarity Register (PWPR)
PWPR selects the PWM output polarity.
Initial
Value
R/W
Description
OPSnH
0
R/W
Output Polarity Select
OPSnG
0
R/W
Each of these bits selects the PWM output polarity.
5
OPSnF
0
R/W
0: PWM direct output
4
OPSnE
0
R/W
1: PWM inverse output
3
OPSnD
0
R/W
2
OPSnC
0
R/W
1
OPSnB
0
R/W
0
OPSnA
0
R/W
Bit
Bit Name
7
6
(n = 1, 2)
16.3.4
PWM Counter (PWCNT)
PWCNT is a 10-bit up-counter incremented by the input clock. The input clock is selected by
clock select bits CKS2 to CKS0 in PWCR.
PWCNT can not be directly accessed by the CPU. PWCNT is initialized to H'FC00, when CST bit
in PWCR is 0.
16.3.5
PWM Cycle Register (PWCYR)
PWCYR is a 16-bit readable/writable register that sets the PWM conversion cycle. When a
PWCYR compare match occurs, PWCNT is cleared and data is transferred from the buffer register
(PWBFR) to the duty register (PWDTR).
PWCYR should be written to only while PWCNT is stopped. A value of H'FC00 must not be set.
PWCYR is initialized to H'FFFF.
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Section 16 Motor Control PWM Timer (PWM)
Compare match
PWCNT
(lower 10 bits)
Compare match
0
1
N–2
PWCYR
(lower 10 bits)
N–1
0
1
N
Figure 16.2 Cycle Register Compare Match
16.3.6
PWM Duty Registers A, C, E, G (PWDTRA, PWDTRC, PWDTRE, PWDTRG)
There are four PWDTR registers (PWDTRA, PWDTRC, PWDTRE, and PWDTRG). The
PWDTRA is used for outputs PWMA and PWMB, PWDTRC for outputs PWMC and PWMD,
PWDTRE for outputs PWME and PWMF, and PWDTRG for outputs PWMG and PWMH.
PWDTR can not be directly accessed by the CPU. When a PWCYR compare match occurs, data is
transferred from the buffer register (PWBFR) to the duty register (PWDTR).
Bit
Bit Name
Initial
Value
R/W
Description
15 to 13



Reserved
12
OTS
0

Output Terminal Select
Selects the pin used for PWM output. Unselected pins
output a low level (or a high level when the
corresponding bit in PWPR is set to 1). For details, see
table 16.2.
11, 10



Reserved
9
DT9
0

Duty
8
DT8
0

7
DT7
0

6
DT6
0

5
DT5
0

4
DT4
0

These bits specify the PWM output duty. A high level
(or a low level when the corresponding bit in PWPR is
set to 1) is output from the time PWCNT is cleared by a
PWCYR compare match until a PWDTR compare
match occurs. When all of the bits are 0, there is no
high-level (or low-level when the corresponding bit in
PWPR is set to 1) output period.
3
DT3
0

2
DT2
0

1
DT1
0

0
DT0
0

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Section 16 Motor Control PWM Timer (PWM)
Table 16.2 Output Selection by OTS Bit
Bit 12
Register
OTS
Description
PWDTR1A/
0
PWMA output selected
PWDTR2A
1
PWMB output selected
PWDTR1C/
0
PWMC output selected
PWDTR2C
1
PWMD output selected
PWDTR1E/
0
PWME output selected
PWDTR2E
1
PWMF output selected
PWDTR1G/
0
PWMG output selected
PWDTR2G
1
PWMH output selected
Compare match
PWCNT1/2
(lower 10 bits)
0
1
M–2
PWCYR1/2
(lower 10 bits)
N
PWDTR1/2
(lower 10 bits)
M
M–1
M
N–1
0
PWM output on
selected pin
PWM output on
unselected pin
Figure 16.3 Duty Register Compare Match (OPS = 0 in PWPR)
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Section 16 Motor Control PWM Timer (PWM)
PWCNT1/2
(lower 10 bits)
0
1
N–2
PWCYR1/2
(lower 10 bits)
N
PWDTR1/2
(lower 10 bits)
M
N–1
PWM output
(M = 0)
PWM output
(0 < M < N)
PWM output
(N ≤ M)
Figure 16.4 Differences in PWM Output According to Duty Register Set Value
(OPS = 0 in PWPR)
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0
Section 16 Motor Control PWM Timer (PWM)
16.3.7
PWM Buffer Registers A, C, E, G (PWBFRA, PWBFRC, PWBFRE, PWBFRG)
There are four PWBFR registers (PWBFRA, PWBFRC, PWBFRE, and PWBFRG). When a
PWCYR compare match occurs, data is transferred from the buffer register (PWBFR) to the duty
register (PWDTR).
Bit
Bit Name
Initial
Value
R/W
Description
15 to 13

All 1

Reserved
These bits are always read as 1 and cannot be modified.
12
OTS
0
R/W
Output Terminal Select
Holds the data to be sent to bit 12 in PWDTR.
11, 10

All 1

Reserved
These bits are always read as 1 and cannot be modified.
9
DT9
0
R/W
Duty
8
DT8
0
R/W
7
DT7
0
R/W
These bits hold the data to be sent to bits 9 to 0 in
PWDTR.
6
DT6
0
R/W
5
DT5
0
R/W
4
DT4
0
R/W
3
DT3
0
R/W
2
DT2
0
R/W
1
DT1
0
R/W
0
DT0
0
R/W
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Section 16 Motor Control PWM Timer (PWM)
16.3.8
PWM Buffer Transfer Control Register (PWBTCR)
PWBTCR enables or disables the data transfer from buffer register to duty register with the
compare match of PWM counter and PWM cycle register.
Bit
Bit Name
Initial
Value
R/W
Description
7
BTC2G
0
R/W
6
BTC2E
0
R/W
0: Data transfer from PWBFR to PWDTR enabled with
PWCNT and PWCYR compare match
5
BTC2C
0
R/W
4
BTC2A
0
R/W
3
BTC1G
0
R/W
2
BTC1E
0
R/W
1
BTC1C
0
R/W
0
BTC1A
0
R/W
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1: Data transfer from PWBFR to PWDTR disabled with
PWCNT and PWCYR compare match
Section 16 Motor Control PWM Timer (PWM)
16.4
Bus Master Interface
16.4.1
16-Bit Data Registers
PWCYR and PWBFR are 16-bit registers. These registers are linked to the bus master by a 16-bit
data bus, and can be read or written in 16-bit units. They cannot be read or written by 8-bit access;
16-bit access must always be used.
Internal data bus
H
Bus
master
L
Bus
interface
Module
data bus
PWCYR
Figure 16.5 16-Bit Register Access Operation (Bus Master ↔ PWCYR (16 Bits))
16.4.2
8-Bit Data Registers
PWCR, PWOCR, and PWPR are 8-bit registers that can be read and written to in 8-bit units.
These registers are linked to the bus master by a 16-bit data bus, and can be read or written by 16bit access; in this case, the lower eight bits are read as an undefined value.
Internal data bus
H
Bus
master
L
Bus
interface
Module
data bus
PWCR
Figure 16.6 8-Bit Register Access Operation (Bus Master ↔ PWCR (Upper Eight Bits))
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Section 16 Motor Control PWM Timer (PWM)
16.5
Operation
16.5.1
PWM Operation
PWM waveforms are output from pins PWM1A to PWM1H and PWM2A to PWM2H as shown
in figure 16.7.
Initial Settings: Set the PWM output polarity in PWPR; set the OEn bit in PWOCR to 1 to enable
PWM output from the corresponding pin; select the clock to be input to PWCNT with the CKS2 to
CKS0 bits in PWCR; set the PWM conversion cycle in PWCYR; and set the first frame of data in
PWBFRA, PWBFRC, PWBFRE, and PWBFRG.
Activation: Setting the CST bit in PWCR to 1 starts counting by PWCNT. When a compare
match between PWCNT and PWCYR occurs, data is transferred from the buffer register to the
duty register and the CMF bit in PWCR is set to 1. If the IE bit in PWCR has been set to 1 at this
time, an interrupt can be requested or the DTC can be activated.
Waveform Output: The PWM outputs selected by the OTS bits in PWDTRA, PWDTRC,
PWDTRE, and PWDTRG go high when a compare match occurs between PWCNT and PWCYR.
The PWM outputs not selected by the OTS bit are low. When a compare match occurs between
PWCNT and PWDTRA, PWDTRC, PWDTRE, or PWDTRG, the corresponding PWM output
goes low. If the corresponding bit in PWPR is set to 1, the output is inverted.
PWCYR
PWBFRA
PWDTRA
OTS (PWDTRA) = 0
OTS (PWDTRA) = 1
OTS (PWDTRA) = 0
OTS (PWDTRA) = 1
PWMA
PWMB
Figure 16.7 PWM Operation
Next Frame: When a compare match occurs between PWCNT and PWCYR, data is transferred
from the buffer register to the duty register. PWCNT is reset and starts counting up from H'000.
The CMF bit in PWCR is set, and if the IE bit in PWCR1 or PWCR2 has been set, an interrupt can
be requested or the DTC can be activated.
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Section 16 Motor Control PWM Timer (PWM)
Stopping: When the CST bit in PWCR is cleared to 0, PWCNT is reset and stops. All PWM
outputs go low (or high if the corresponding bit in PWPR is set to 1).
16.5.2
Buffer Transfer Control
Setting a corresponding bit in the PWM buffer transfer control register disables a buffer transfer
on compare match. This prevents the output from changing when compare match occurs while the
buffer register is being changed. A buffer transfer on compare match is resumed after cleaning the
bit.
PWCYR
PWBFR1A
PWDTR1A
PWBFR1C
PWDTR1C
PWCNT
Write
PWBTCR
Buffer updated
(PWBFR1C)
Buffer updated
(PWBFR1A)
Disabled: 1
Buffer updated
(PWBFR1A)
Disabled
Buffer updated
(PWBFR1C)
Enabled
Enabled: 0
Figure 16.8 Disabling Buffer Transfer
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Section 16 Motor Control PWM Timer (PWM)
16.6
Usage Note
Conflict between Buffer Register Write and Compare Match: If a PWBFR write is performed
in the state immediately after a cycle register compare match, the buffer register and duty register
are both modified. PWM output changed by the cycle register compare match is not changed by
modification of the duty register due to conflict. This may result in unanticipated duty output.
Buffer register modification must be completed before automatic transfer by the DTC, exception
handling due to a compare match interrupt, or the occurrence of a cycle register compare match on
detection of the rise of CMF (compare match flag) in PWCR.
T1
Tw
Tw
T2
φ
Address
Buffer register address
Write signal
Compare match
PWCNT
(lower 10 bits)
PWBFR
0
N
PWDTR
M
N
M
PWM output
CMF
Figure 16.9 Conflict between Buffer Register Write and Compare Match
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REJ09B0200-0200
Section 17 LCD Controller/Driver
Section 17 LCD Controller/Driver
This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit,
enabling direct drive of an LCD panel.
17.1
Features
Features of the LCD controller/driver are given below.
• Display capacity
Duty Cycle
Internal Driver
Static
40 SEG
1/2
40 SEG
1/3
40 SEG
1/4
40 SEG
• LCD RAM capacity
8 bits × 20 bytes (160 bits)
Byte or word access to LCD RAM
• The segment output pins can be used as ports.
SEG40 to SEG1 pins can be used as ports in groups of four.
• Common output pins not used because of the duty cycle can be used for common doublebuffering (parallel connection).
With 1/2 duty, parallel connection of COM1 to COM2, and of COM3 to COM4, can be used
In static mode, parallel connection of COM1 to COM2, COM3, and COM4 can be used
• Choice of 11 frame frequencies
• A or B waveform selectable by software
• On-chip power supply split-resistance
• Display possible in operating modes other than standby mode and module stop mode
• Module stop mode
Access to registers and LCD RAM is enabled by clearing module stop mode.
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Section 17 LCD Controller/Driver
Figure 17.1 shows a block diagram of the LCD controller/driver.
LPVCC
M
φ/8 to φ/2048
V1
V2
V3
VSS
CL2
Common
data latch
φw
Internal data bus
LCD drive
power supply
(Built-in step-up
voltage circuit)
Common
driver
COM4
SEG40
SEG39
SEG38
SEG37
SEG36
LPCR
LCR
LCR2
Display timing generator
COM1
40-bit
shift
register
CL1
Segment
driver
LCD RAM
20 bytes
SEG1
SEGn, DO
[Legend]
LPCR: LCD port control register
LCR: LCD control register
LCR2: LCD control register 2
Figure 17.1 Block Diagram of LCD Controller/Driver
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REJ09B0200-0200
Section 17 LCD Controller/Driver
17.2
Input/Output Pins
Table 17.1 shows the LCD controller/driver pin configuration.
Table 17.1 Pin Configuration
Name
Abbreviation
I/O
Function
Segment output
pins
SEG40 to SEG1
Output
LCD segment drive pins
Common output
pins
COM4 to COM1
LCD power supply
pins
V1, V2, V3
All pins are multiplexed with port pins (setting
programmable)
Output
LCD common drive pins
Pins can be used in parallel in static mode or
1/2 duty

Used when a bypass capacitor is connected
externally, and when an external power supply
circuit is used
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Section 17 LCD Controller/Driver
17.3
Register Descriptions
The LCD controller/driver has the following registers.
•
•
•
•
LCD port control register (LPCR)
LCD control register (LCR)
LCD control register 2 (LCR2)
LCDRAM
17.3.1
LCD Port Control Register (LPCR)
LPCR selects the duty cycle, and the LCD driver and pin functions.
Bit
Bit Name
Initial
Value
R/W
Description
7
DTS1
0
R/W
Duty Cycle Select 1 and 0
6
DTS0
0
R/W
Common Function Select
5
CMX
0
R/W
The combination of DTS1 and DTS0 selects static, 1/2,
1/3, or 1/4 duty.
CMX specifies whether or not the same waveform is to be
output from multiple pins to increase the common drive
power when not all common pins are used because of the
duty setting. For details, see table 17.2.
4

0

Reserved
This bit is always read as 0. The write value should
always be 0.
3
SGS3
0
R/W
Segment Driver Select 3 to 0
2
SGS2
0
R/W
These bits select the segment drivers to be used.
1
SGS1
0
R/W
For details, see table 17.3.
0
SGS0
0
R/W
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Section 17 LCD Controller/Driver
Table 17.2 Duty Cycle and Common Function Selection
Bit 7:
DTS1
Bit 6:
DTS0
Bit 5:
CMX
Duty
Cycle
Common
Drivers
0
0
0
Static
COM1
1
0
1
0
0
0
1/2 duty
1
X
COM2 to COM1 COM4 and COM3 can be used as ports
COM4 to COM1 COM4 outputs the same waveform as
COM3, and COM2 outputs the same
waveform as COM1
1/3 duty
1
1
COM4, COM3, and COM2 can be used as
ports
COM4 to COM1 COM4, COM3, and COM2 output the same
waveform as COM1
1
1
Notes
COM3 to COM1 COM4 can be used as a port
COM4 to COM1 Do not use COM4
1/4 duty
COM4 to COM1 
[Legend]
X:
Don't care
Note: COM4 to COM1 function as ports when the setting of SGS3 to SGS0 is B'0000.
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Section 17 LCD Controller/Driver
Table 17.3 Segment Driver Selection
Bit 3
Bit 2
Bit 1
Bit 0
Function of Pins SEG40 to SEG1
SEG40 SEG32 SEG28 SEG24 SEG20 SEG16 SEG12 SEG8 SEG4
to
to
to
to
to
to
to
to
to
SGS3 SGS2 SGS1 SGS0 SEG33 SEG29 SEG25 SEG21 SEG17 SEG13 SEG9 SEG5 SEG1
0
0
0
0
Port
Port
Port
Port
Port
Port
Port
Port
Port
0
0
0
1
SEG
Port
Port
Port
Port
Port
Port
Port
Port
0
0
1
0
SEG
SEG
Port
Port
Port
Port
Port
Port
Port
0
0
1
1
SEG
SEG
SEG
Port
Port
Port
Port
Port
Port
0
1
0
0
SEG
SEG
SEG
SEG
Port
Port
Port
Port
Port
0
1
0
1
SEG
SEG
SEG
SEG
SEG
Port
Port
Port
Port
0
1
1
0
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
Port
0
1
1
1
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
1
X
X
0
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
1
X
X
1
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
[Legend]
X:
Don't care
Notes: 1. The external expanded mode can be used when SGS3 to SGS0 are set to B'0000.
2. The external expanded mode cannot be used when SGS3 to SGS0 are not set to
B'0000.
3. COM4 to COM1 also function as ports when the setting of SGS3 to SGS0 is B'0000.
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Section 17 LCD Controller/Driver
17.3.2
LCD Control Register (LCR)
LCR controls LCD power supply split-resistance connection and display data, and selects the
frame frequency.
Bit
Bit Name
Initial
Value
R/W
Description
7

1
R/W
Reserved
This bit is always read as 1. The write value should
always be 0.
6
PSW
0
R/W
LCD Power Supply Split-Resistance Connection Control
Disconnects the LCD power supply split-resistance from
VCC when LCD display is not required in a power-down
mode, or when an external power supply is used. When
the ACT bit is cleared to 0, and also in standby mode, the
LCD power supply split-resistance is disconnected from
VCC regardless of the setting of this bit.
0: LCD power supply split-resistance is disconnected
from VCC
1: LCD power supply split-resistance is connected to VCC
5
ACT
0
R/W
Display Function Activate
Specifies whether or not the LCD controller/driver is used.
Clearing this bit to 0 halts operation of the LCD
controller/driver. The LCD drive power supply ladder
resistance is also turned off, regardless of the setting of
the PSW bit. However, register contents are retained.
0: LCD controller/driver operation halted
1: LCD controller/driver operation activated
4
DISP
0
R/W
Display Data Control
Specifies whether the LCD RAM contents are displayed
or blank data is displayed regardless of the LCD RAM
contents.
0: Blank data is displayed
1: LCD RAM data is displayed
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REJ09B0200-0200
Section 17 LCD Controller/Driver
Bit
Bit Name
Initial
Value
R/W
Description
3
CKS3
0
R/W
Frame Frequency Select 3 to 0
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
These bits select the operating clock and the frame
frequency. In subactive mode, watch mode, and subsleep
mode, the system clock (φ) is halted, and therefore
display operations are not performed if one of the clocks
from φ/2 to φ/256 is selected. If LCD display is required in
these modes, φSUB, φSUB/2, or φSUB/4 must be selected as
the operating clock.
For details, see table 17.4.
Table 17.4 Frame Frequency Selection
Frame Frequency*1
Bit 3
Bit 2
Bit 1
Bit 0
CKS3
CKS2
CKS1
CKS0
Operating Clock
φ = 20 MHz
0
X
0
0
φSUB
128 Hz*2
1
φSUB/2
64 Hz*2
1
X
φSUB/4
32 Hz*2
0
0
φ/8
4880 Hz
1
φ/16
2440 Hz
0
φ/32
1220 Hz
1
φ/64
610 Hz
0
φ/128
305 Hz
1
φ/256
152.6 Hz
0
φ/512
76.3 Hz
1
φ/1024
38.1 Hz
1
0
1
1
0
1
[Legend]
X:
Don't care
Notes: 1. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
2. This is the frame frequency when φSUB = 32.767 MHz.
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Section 17 LCD Controller/Driver
17.3.3
LCD Control Register 2 (LCR2)
LCR2 controls switching between the A waveform and B waveform.
Bit
Bit Name
Initial
Value
R/W
7
LCDAB
0
R/W
Description
A Waveform/B Waveform Switching Control
Selects the A waveform or B waveform for the LCD drive
waveform.
0: Drive using A waveform
1: Drive using B waveform
6, 5

All 1

Reserved
These bits are always read as 1 and cannot be modified.
4 to 0
—
All 0
—
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Dec. 05, 2005 Page 517 of 724
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Section 17 LCD Controller/Driver
17.4
Operation
17.4.1
Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be
determined.
1. Hardware Settings
A. Using 1/2 duty
When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 17.2.
LPVCC
V1
V2
V3
VSS
Figure 17.2 Handling of LCD Drive Power Supply when Using 1/2 Duty
B. Large-panel display
As the impedance of the built-in power supply split-resistance is large, it may not be
suitable for driving a large panel. If the display lacks sharpness when using a large panel,
see section 17.4.4, Boosting the LCD Drive Power Supply. When static or 1/2 duty is
selected, the common output drive capability can be increased. Set CMX to 1 when
selecting the duty cycle. In this mode, with a static duty cycle, pins COM4 to COM1 output
the same waveform, and with 1/2 duty, the COM1 waveform is output from pins COM2
and COM1, and the COM2 waveform is output from pins COM4 and COM3.
C. LCD drive power supply setting
With this LSI, there are two ways of providing LCD power: by using the on-chip power
supply circuit or by using an external power supply circuit.
When an external power supply circuit is used for the LCD drive power supply, connect the
external power supply to the V1 pin.
Rev. 2.00 Dec. 05, 2005 Page 518 of 724
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Section 17 LCD Controller/Driver
2. Software Settings
A. Duty selection
Any of four duty cyclesstatic, 1/2 duty, 1/3 duty, or 1/4 dutycan be selected with bits
DTS1 and DTS0.
B. Segment driver selection
The segment drivers to be used can be selected with bits SGS3 to SGS0.
3. Frame frequency selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency
should be selected in accordance with the LCD panel specification. For the clock selection
method in watch mode, subactive mode, and subsleep mode, see section 17.4.3, Operation in
Power-Down Modes.
A. A or B waveform selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of
LCDAB.
B. LCD drive power supply selection
When an external power supply circuit is used, turn the LCD drive power supply off with
the PSW bit.
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Section 17 LCD Controller/Driver
17.4.2
Relationship between LCD RAM and Display
The relationship between the LCD RAM and the display segments differs according to the duty
cycle. LCD RAM maps for the different duty cycles are shown in figures 17.3 to 17.6.
After setting the registers required for display, data is written to the part corresponding to the duty
using the same kind of instruction as for ordinary RAM, and display is started automatically when
turned on. Word- or byte-access instructions can be used for RAM setting.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'FC40
SEG2
SEG2
SEG2
SEG2
SEG1
SEG1
SEG1
SEG1
H'FC53
SEG40
SEG40
SEG40
SEG40
SEG39
SEG39
SEG39
SEG39
COM4
COM3
COM2
COM1
COM4
COM3
COM2
COM1
Figure 17.3 LCD RAM Map (1/4 Duty)
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REJ09B0200-0200
Section 17 LCD Controller/Driver
Bit 7
Bit 6
Bit 5
Bit 4
H'FC40
SEG2
SEG2
H'FC53
SEG40
COM3
Bit 3
Bit 2
Bit 1
Bit 0
SEG2
SEG1
SEG1
SEG1
SEG40
SEG40
SEG39
SEG39
SEG39
COM2
COM1
COM3
COM2
COM1
Space not used for display
Figure 17.4 LCD RAM Map (1/3 Duty)
H'FC40
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG4
SEG4
SEG3
SEG3
SEG2
SEG2
SEG1
SEG1
Display space
H'FC49
SEG40
SEG40
SEG39
SEG39
SEG38
SEG38
SEG37
SEG37
Space not used
for display
H'FC53
COM2
COM1
COM2
COM1
COM2
COM1
COM2
COM1
Figure 17.5 LCD RAM Map (1/2 Duty)
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Section 17 LCD Controller/Driver
H'FC40
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Display space
H'FC44
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
Space not used
for display
H'FC53
COM1
COM1
COM1
COM1
COM1
COM1
COM1
COM1
Figure 17.6 LCD RAM Map (Static Mode)
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Section 17 LCD Controller/Driver
1 frame
1 frame
M
M
Data
Data
COM1
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM4
V1
V2
V3
VSS
SEGn
V1
V2
V3
VSS
SEGn
V1
V2
V3
VSS
(a) Waveform with 1/4 duty
(b) Waveform with 1/3 duty
1 frame
1 frame
M
M
Data
Data
COM1
V1
V2,V3
VSS
COM1
V1
COM2
V1
V2,V3
VSS
SEGn
SEGn
V1
V2,V3
VSS
VSS
V1
VSS
(d) Waveform with static output
(c) Waveform with 1/2 duty
Figure 17.7 Output Waveforms for Each Duty Cycle (A Waveform)
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Section 17 LCD Controller/Driver
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
1 frame
1 frame
1 frame
COM1
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM4
V1
V2
V3
VSS
SEGn
V1
V2
V3
VSS
SEGn
V1
V2
V3
VSS
(a) Waveform with 1/4 duty
1 frame
1 frame
1 frame
(b) Waveform with 1/3 duty
1 frame
1 frame
M
M
Data
Data
COM1
V1
V2,V3
VSS
COM1
COM2
V1
V2,V3
VSS
SEGn
V1
V2,V3
VSS
SEGn
1 frame
1 frame
1 frame
V1
VSS
V1
VSS
(d) Waveform with static output
(c) Waveform with 1/2 duty
Figure 17.8 Output Waveforms for Each Duty Cycle (B Waveform)
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Section 17 LCD Controller/Driver
Table 17.5 Output Levels (A Waveform)
Data
0
0
1
1
M
0
1
0
1
Common output
V1
VSS
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V2, V3
V2, V3
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Static
1/2 duty
1/3 duty
1/4 duty
17.4.3
Operation in Power-Down Modes
In this LSI, the LCD controller/driver can be operated even in power-down modes. The operating
state of the LCD controller/driver in the power-down modes is summarized in table 17.6.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless φSUB, φSUB/2, or φSUB/4 has been selected by bits CKS3 to CKS0, the clock will not
be supplied and display will halt. Since a DC voltage may be applied to the LCD panel in this
case, it is essential to ensure that φSUB, φSUB/2, or φSUB/4 is selected. In active (medium-speed) mode,
the system clock is switched. Therefore, the bits CKS3 to CKS0 must be specified appropriately
so that the frame frequency is fixed.
In the software standby mode, the segment output and common output pins switch to I/O ports. In
this case if a port's DDR or PCR bit is set to 1, a DC voltage may be applied to the LCD panel.
Therefore, DDR and PCR must never be set to 1 for ports being used for segment output or
common output.
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Section 17 LCD Controller/Driver
Table 17.6 Power-Down Modes and Display Operation
Software Hardware Module
Mode
Clock
Display
operation
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
standby
Stop
φ
Runs
Runs
Runs
Stops
Stops
Stops
Stops
Stops
Stops*4
φSUB
Runs
Runs
Runs
Runs
Runs
Runs
Stops*1
Stops
Stops*4
ACT = 0 Stops
Stops
Stops
Stops
Stops
Stops
Stops*2
Stops*2
Stops
2
2
Stops
3
ACT = 1 Stops
Functions Functions Functions*
3
Functions*
3
Functions*
Stops*
Stops*
Notes: 1. The subclock oscillator does not stop, but clock supply is halted.
2. The LCD drive power supply is turned off regardless of the setting of the PSW bit.
3. Display operation is performed only if φSUB, φSUB/2, or φSUB/4 is selected as the operating
clock.
4. The clock supplied to the LCD stops.
17.4.4
Boosting the LCD Drive Power Supply
When a large panel is driven, the on-chip power supply capacity may be insufficient. In this case,
the power supply impedance must be reduced. This can be done by connecting bypass capacitors
of around 0.1 to 0.3 µF to pins V1 to V3, as shown in figure 17.9, or by adding a split-resistance
externally.
VCC
VR
V1
R
This LSI
R = several kΩ to
several MΩ
V2
R
C = 0.1 to 0.3 µF
V3
R
VSS
Figure 17.9 Connection of External Split-Resistance
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Section 18 RAM
Section 18 RAM
This LSI has an 8-kbyte on-chip high-speed static RAM. The RAM is connected to the CPU by a
16-bit data bus, enabling one-state access by the CPU to both byte data and word data.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR).
Rev. 2.00 Dec. 05, 2005 Page 527 of 724
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Section 18 RAM
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Section 19 ROM
Section 19 ROM
The features of the flash memory are summarized below.
The block diagram of the flash memory is shown in figure 19.1.
19.1
Features
• Size
Product Type
ROM Size
ROM Address
H8S/2649F
256 kbytes
H'000000 to H'03FFFF
• Programming/erase methods
The flash memory is programmed in 128-byte units at a time. Erase is performed in singleblock units. The flash memory is configured as follows: 64 kbytes × 3 blocks, 32 kbytes × 1
block, and 4 kbytes × 8 blocks. To erase the entire flash memory, each block must be erased in
turn.
• Reprogramming capability
The flash memory can be reprogrammed for 100 times.
• Two on-board programming modes
Boot mode
User program mode
On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program the entire flash memory. In normal user program
mode, individual blocks can be erased or programmed.
• Programmer mode
Flash memory can be programmed/erased in programmer mode using a PROM programmer,
as well as in on-board programming mode.
• Automatic bit rate adjustment
For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the
transfer bit rate of the host.
• Programming/erasing protection
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase operations.
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REJ09B0200-0200
Section 19 ROM
• Emulation function for flash memory in RAM
The real-time emulation for programming of flash memory is possible by overlapping the flash
memory to a part of RAM.
Internal address bus
Module bus
Internal data bus (16 bits)
FLMCR1
FLMCR2
EBR1
Bus interface/controller
Operating
mode
FWE pin
Mode pin
EBR2
RAMER
FLPWCR
Flash memory
[Legend]
FLMCR1:
FLMCR2:
EBR1:
EBR2:
RAMER:
FLPWCR:
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM emulation register
Flash memory power control register
Figure 19.1 Block Diagram of Flash Memory
19.2
Mode Transitions
When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this
LSI enters an operating mode as shown in figure 19.2. In user mode, flash memory can be read but
not programmed or erased.
The boot, user program, and programmer modes are provided as modes to program and erase the
flash memory.
The differences between boot mode and user program mode are shown in table 19.1.
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REJ09B0200-0200
Section 19 ROM
Figure 19.3 shows the operation flow for boot mode and figure 19.4 shows that for user program
mode.
MD1 = 1,
MD2 = 1,
FWE = 0*1
User mode
with on-chip ROM
enabled
FWE = 1
Reset state
RES = 0
MD1 = 1,
MD2 = 1,
FWE = 1
RES = 0
RES = 0
FWE = 0
User
program mode
*2
MD1 = 0
MD2 = 1,
FWE = 1
RES = 0
Programmer
mode
*1
Boot mode
On-board programming mode
Notes: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
1. RAM emulation possible
2. MD0 = 0, MD1 = 0, MD2 = 0, FWE = 1, P14 = 0, P16 = 0, PF0 = 1
Figure 19.2 Flash Memory State Transitions
Table 19.1 Differences between Boot Mode and User Program Mode
Entire erase
Boot Mode
User Program Mode
Yes
Yes
Block erase
No
Yes
Programming control program*
Program/program-verify
Program/program-verify/erase/
erase-verify/emulation
Note:
* To be provided by the user, in accordance with the recommended algorithm.
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REJ09B0200-0200
Section 19 ROM
1. Initial state
The old program version or data remains written
in the flash memory. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program in
this LSI (originally incorporated in the chip) is
started and the programming control program in
the host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically transferred
to the RAM boot program area.
Host
Host
Programming control
program
New application
program
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
RAM
SCI
Boot program
RAM
Flash memory
Boot program area
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, total flash
memory erasure is performed, without regard to
blocks.
Programming control
program
4. Writing new application program
The programming control program transferred
from the host to RAM is executed, and the new
application program in the host is written into the
flash memory.
Host
Host
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
RAM
Flash memory
Boot program area
Flash memory
preprogramming
erase
Programming control
program
SCI
Boot program
RAM
Boot program area
New application
program
Programming control
program
Program execution state
Figure 19.3 Boot Mode
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REJ09B0200-0200
Section 19 ROM
1. Initial state
The FWE assessment program that confirms that
user program mode has been entered, and the
program that will transfer the programming/erase
control program from flash memory to on-chip
RAM should be written into the flash memory by
the user beforehand. The programming/erase
control program should be prepared in the host
or in the flash memory.
2. Programming/erase control program transfer
When user program mode is entered, user
software confirms this fact, executes transfer
program in the flash memory, and transfers the
programming/erase control program to RAM.
Host
Host
Programming/
erase control program
New application
program
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
SCI
Boot program
Flash memory
RAM
RAM
FWE assessment
program
FWE assessment
program
Transfer program
Transfer program
Programming/
erase control program
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Host
Host
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
RAM
FWE assessment
program
Flash memory
RAM
FWE assessment
program
Transfer program
Transfer program
Programming/
erase control program
Flash memory
erase
SCI
Boot program
Programming/
erase control program
New application
program
Program execution state
Figure 19.4 User Program Mode (Example)
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Section 19 ROM
19.3
Block Configuration
Figure 19.5 shows the block configuration of 256-kbyte flash memory. The thick lines indicate
erasing units, the narrow lines indicate programming units, and the values are addresses. The flash
memory is divided into 4 kbytes (8 blocks), 32 kbytes (1 block), and 64 kbytes (3 blocks). Erasing
is performed in these units. Programming is performed in 128-byte units starting from an address
with lower eight bits H'00 or H'80.
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Section 19 ROM
EB0
Erase unit
4 kbytes
H'000000
H'000001
H'000002
Programming unit: 128 bytes
EB1
Erase unit
4 kbytes
H'001000
H'001001
H'001002
Programming unit: 128 bytes
EB2
Erase unit
4 kbytes
H'002000
H'002001
H'002002
Programming unit: 128 bytes
EB3
Erase unit
4 kbytes
H'003000
H'003001
H'003002
Programming unit: 128 bytes
EB4
Erase unit
4 kbytes
H'004000
H'004001
H'004002
Programming unit: 128 bytes
EB5
Erase unit
4 kbytes
H'005000
H'005001
H'005002
Programming unit: 128 bytes
EB6
Erase unit
4 kbytes
H'006000
H'006001
H'006002
Programming unit: 128 bytes
EB7
Erase unit
4 kbytes
H'007000
H'007001
H'007002
Programming unit: 128 bytes
EB8
Erase unit
32 kbytes
H'008000
H'008001
H'008002
Programming unit: 128 bytes
EB9
Erase unit
64 kbytes
H'010000
H'010001
H'010002
Programming unit: 128 bytes
EB10
Erase unit
64 kbytes
H'020000
H'020001
H'020002
Programming unit: 128 bytes
EB11
Erase unit
64 kbytes
H'030000
H'030001
H'030002
Programming unit: 128 bytes
H'00007F
H'000FFF
H'00107F
H'001FFF
H'00207F
H'002FFF
H'00307F
H'003FFF
H'00407F
H'004FFF
H'00507F
H'005FFF
H'00607F
H'006FFF
H'00707F
H'007FFF
H'00807F
H'00FFFF
H'01007F
H'01FFFF
H'02007F
H'02FFFF
H'03007F
H'03FFFF
Figure 19.5 Flash Memory Block Configuration
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Section 19 ROM
19.4
Input/Output Pins
The flash memory is controlled by means of the pins shown in table 19.2.
Table 19.2 Pin Configuration
Pin Name
I/O
Function
RES
Input
Reset
FWE
Input
Flash program/erase protection by hardware
MD2
Input
Sets this LSI's operating mode
MD1
Input
Sets this LSI's operating mode
MD0
Input
Sets this LSI's operating mode
PF0
Input
Sets MCU operating mode in programmer mode
P16
Input
Sets MCU operating mode in programmer mode
P14
Input
Sets MCU operating mode in programmer mode
TxD0
Output
Serial transmit data output
RxD0
Input
Serial receive data input
19.5
Register Descriptions
The flash memory has the following registers.
•
•
•
•
•
•
Flash memory control register 1 (FLMCR1)
Flash memory control register 2 (FLMCR2)
Erase block register 1 (EBR1)
Erase block register 2 (EBR2)
RAM emulation register (RAMER)
Flash memory power control register (FLPWCR)
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Section 19 ROM
19.5.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, see section 19.8, Flash
Memory Programming/Erasing.
Bit
Bit Name
Initial
Value
R/W
Description
7
FWE

R
Flash Write Enable Bit
Reflects the input level at the FWE pin. It is set to 1 when
a low level is input to the FWE pin, and cleared to 0 when
a high level is input. When this bit is cleared to 0, the
flash memory changes to hardware protect mode.
6
SWE
0
R/W
Software Write Enable Bit
When this bit is set to 1 while FWE = 1, flash memory
programming/erasing is enabled. When this bit is cleared
to 0, bits 5 to 0 in FLMCR1 and all EBR1 and EBR2 bits
cannot be set.
5
ESU
0
R/W
Erase Setup Bit
When this bit is set to 1, the flash memory changes to the
erase setup state. When it is cleared to 0, the erase setup
state is cancelled. Set this bit to 1 before setting the E bit
in FLMCR1.
4
PSU
0
R/W
Program Setup Bit
When this bit is set to 1, the flash memory changes to the
program setup state. When it is cleared to 0, the program
setup state is cancelled. Set this bit to 1 before setting the
P bit in FLMCR1.
3
EV
0
R/W
Erase-Verify
When this bit is set to 1, the flash memory changes to
erase-verify mode. When it is cleared to 0, erase-verify
mode is cancelled.
2
PV
0
R/W
Program-Verify
When this bit is set to 1, the flash memory changes to
program-verify mode. When it is cleared to 0, programverify mode is cancelled.
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Section 19 ROM
Bit
Bit Name
Initial
Value
R/W
Description
1
E
0
R/W
Erase
When this bit is set to 1, the flash memory changes to
erase mode. When it is cleared to 0, erase mode is
cancelled.
0
P
0
R/W
Program
When this bit is set to 1, and while the SWE and PSU bits
are 1, the flash memory changes to program mode.
When it is cleared to 0, program mode is cancelled.
19.5.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit
Bit Name
Initial
Value
R/W
7
FLER
0
R
Description
Flash Memory Error
Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When FLER
is set to 1, flash memory goes to the error-protection
state.
See section 19.9.3, Error Protection, for details.
6 to 0

All 0
R
Reserved
These bits are always read as 0.
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Section 19 ROM
19.5.3
Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and
EBR2 to be automatically cleared to 0.
Bit
Bit Name
Initial
Value
R/W
Description
7
EB7
0
R/W
When this bit is set to 1, 4 kbytes of EB7 (H'007000 to
H'007FFF) will be erased.
6
EB6
0
R/W
When this bit is set to 1, 4 kbytes of EB6 (H'006000 to
H'006FFF) will be erased.
5
EB5
0
R/W
When this bit is set to 1, 4 kbytes of EB5 (H'005000 to
H'005FFF) will be erased.
4
EB4
0
R/W
When this bit is set to 1, 4 kbytes of EB4 (H'004000 to
H'004FFF) will be erased.
3
EB3
0
R/W
When this bit is set to 1, 4 kbytes of EB3 (H'003000 to
H'003FFF) will be erased.
2
EB2
0
R/W
When this bit is set to 1, 4 kbytes of EB2 (H'002000 to
H'002FFF) will be erased.
1
EB1
0
R/W
When this bit is set to 1, 4 kbytes of EB1 (H'001000 to
H'001FFF) will be erased.
0
EB0
0
R/W
When this bit is set to 1, 4 kbytes of EB0 (H'000000 to
H'000FFF) will be erased.
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19.5.4
Erase Block Register 2 (EBR2)
EBR2 specifies the flash memory erase area block. EBR2 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and
EBR2 to be automatically cleared to 0.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4

All 0
R/W
Reserved
The write value should always be 0.
3
EB11
0
R/W
When this bit is set to 1, 64 kbytes of EB11 (H'030000 to
H'03FFFF) will be erased.
2
EB10
0
R/W
When this bit is set to 1, 64 kbytes of EB10 (H'020000 to
H'02FFFF) will be erased.
1
EB9
0
R/W
When this bit is set to 1, 64 kbytes of EB9 (H'010000 to
H'01FFFF) will be erased.
0
EB8
0
R/W
When this bit is set to 1, 32 kbytes of EB8 (H'008000 to
H'00FFFF) will be erased.
19.5.5
RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER settings should be made in user mode or user
program mode. To ensure correct operation of the emulation function, the ROM for which RAM
emulation is performed should not be accessed immediately after this register has been modified.
Normal execution of an access immediately after register modification is not guaranteed.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 0
R
Reserved
4

0
R/W
Reserved
These bits are always read as 0.
Always write 0 before read.
3
RAMS
0
R/W
RAM Select
Specifies selection or non-selection of flash memory
emulation in RAM. When RAMS = 1, the flash memory is
overlapped with part of RAM, and all flash memory block
are program/erase-protected.
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Bit
Bit Name
Initial
Value
R/W
Description
2
RAM2
0
R/W
Flash Memory Area Selection
1
RAM1
0
R/W
0
RAM0
0
R/W
When the RAMS bit is set to 1, one of the following flash
memory areas is selected to overlap the RAM area. The
areas correspond with 4-kbyte erase blocks.
000: H'000000 to H'000FFF (EB0)
001: H'001000 to H'001FFF (EB1)
010: H'002000 to H'002FFF (EB2)
011: H'003000 to H'003FFF (EB3)
100: H'004000 to H'004FFF (EB4)
101: H'005000 to H'005FFF (EB5)
110: H'006000 to H'006FFF (EB6)
111: H'007000 to H'007FFF (EB7)
19.5.6
Flash Memory Power Control Register (FLPWCR)
FLPWCR enables/disables transition to power-down modes for the flash memory when this LSI
enters sub-active mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
PDWND
0
R/W
Power Down Disable
Enables/disables transition to power-down modes for the
flash memory when this LSI enters sub-active mode.
0: Transition to power-down modes for the flash memory
enabled.
1: Transition to power-down modes for the flash memory
disabled.
6 to 0

All 0
R
Reserved
These bits are always read as 0.
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19.6
On-Board Programming Modes
When pins are set to on-board programming mode, program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
19.3. For a diagram of the transitions to the various flash memory modes, see figure 19.2.
Table 19.3 Setting On-Board Programming Modes
Mode Setting
Boot mode
Expanded mode
FWE
MD2
MD1
MD0
1
0
1
0
0
1
1
1
1
0
1
1
1
Single-chip mode
User program mode
Expanded mode
Single-chip mode
19.6.1
1
Boot Mode
Table 19.4 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 19.8, Flash Memory Programming/Erasing.
In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
2. SCI_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1
stop bit, and no parity.
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match
that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
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4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 19.5.
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFE800
to H'FFEFBF is the area to which the programming control program is transferred from the
host. The boot program area cannot be used until the execution state in boot mode switches to
the programming control program.
6. Before branching to the programming control program, the chip terminates transfer operations
by SCI_1 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
write data or verify data with the host. The TxD pin is high. The contents of the CPU general
registers are undefined immediately after branching to the programming control program.
These registers must be initialized at the beginning of the programming control program, as the
stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
7. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
the FWE pin and mode pins, and executing reset release. Boot mode is also cleared when a
WDT overflow occurs.
8. All interrupts are disabled during programming or erasing of the flash memory.
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Table 19.4 Boot Mode Operation
Item
Boot mode
start
Host Operation
Processing Contents
LSI Operation
Communications Contents
Processing Contents
Branches to boot program at reset-start.
Boot program initiation
Bit rate
adjustment
Continuously transmits data H'00 at
specified bit rate.
Transmits data H'55 when data H'00
is received error-free.
H'00, H'00 ...... H'00
H'00
· Measures low-level period of receive data
H'00.
· Calculates bit rate and sets it in BRR of
SCI_1.
· Transmits data H'00 to host as adjustment
end indication.
H'55
H'AA
Transmits data H'AA to host when data
H'55 is received.
Receives data H'AA.
Transfer of
programming
control
program
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (lower
byte following upper byte)
Transmits 1-byte of programming
control program (repeated for
N times)
Upper byte and
lower byte
Echobacks the 2-byte data received.
Echoback
H'XX
Echoback
Flash memory
erase
Boot program
erase error
Receives data H'AA.
H'FF
H'AA
Echobacks received data to host and also
transfers it to RAM (repeated for N times)
Checks flash memory data, erases all
flash memory blocks in case of written
data existing, and transmits data H'AA to
host. (If erase could not be done,
transmits data H'FF to host and aborts
operation.)
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Table 19.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate
System Clock Frequency Range of this LSI
19,200 bps
20 MHz
9,600 bps
8 to 20 MHz
4,800 bps
4 to 20 MHz
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19.6.2
Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user
program mode by branching to a user program/erase control program. The user must prepare onboard means for controlling FWE, on-board means of supplying programming data, and branching
conditions. The flash memory must contain the user program/erase control program or a program
that provides the user program/erase control program from external memory. As the flash memory
itself cannot be read during programming/erasing, transfer the user program/erase control program
to on-chip RAM, as in boot mode. Figure 19.6 shows a sample procedure for
programming/erasing in user program mode. Prepare a user program/erase control program in
accordance with the description in section 19.8, Flash Memory Programming/Erasing.
Reset-start
No
Program/erase?
Yes
Transfer user program/erase control
program to RAM
Branch to flash memory application
program
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode
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19.7
Flash Memory Emulation in RAM
A setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto
the flash memory area so that data to be written to flash memory can be emulated in RAM in real
time. Emulation can be performed in user mode or user program mode. Figure 19.7 shows an
example of emulation of real-time flash memory programming.
1. Set RAMER to overlap part of RAM onto the area for which real-time programming is
required.
2. Emulation is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing the RAM
overlap.
4. The data written in the overlapping RAM is written into the flash memory space.
Start of emulation program
Set RAMER
Write tuning data to overlap
RAM
Execute application program
No
Tuning OK?
Yes
Clear RAMER
Write to flash memory
emulation block
End of emulation program
Figure 19.7 Flowchart for Flash Memory Emulation in RAM
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An example in which flash memory block area EB0 is overlapped is shown in figure 19.8.
1. The RAM area to be overlapped is fixed at a 4-kbyte area in the range H'FFD800 to
H'FFE7FF.
2. The flash memory area to be overlapped is selected by RAMER from a 4-kbyte area of the
EB0 to EB7 blocks.
3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM
addresses.
4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash
memory blocks (emulation protection). In this state, setting the P or E bit in FLMCR1 to 1
does not cause a transition to program mode or erase mode.
5. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm.
6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table
is needed in the overlap RAM.
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H'000000
Flash memory
(EB0)
Flash memory
(EB0)
(EB1)
On-chip RAM
(Shadow of
H'FFD000 to
H'FFDFFF)
(EB2)
Flash memory
(EB2)
(EB3)
(EB3)
On-chip RAM
(4 kbytes)
On-chip RAM
(4 kbytes)
Normal memory map
RAM overlap memory map
H'001000
H'002000
H'003000
H'FFD800
H'FFE7FF
Figure 19.8 Example of RAM Overlap Operation
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19.8
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 19.8.1, Program/Program-Verify and section 19.8.2,
Erase/Erase-Verify, respectively.
19.8.1
Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 19.9 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to the flash memory without subjecting the chip to
voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation and additional programming data computation according to
figure 19.10.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Figure 19.10 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (tspsu + tsp200 + tcp + tcpsu) µs as the WDT overflow period.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits
are B'00. Verify data can be read in words from the address to which a dummy write was
performed.
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8. The maximum number of repetitions of the program/program-verify sequence of the same bit
is (N).
Start of programming
Write pulse application subroutine
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
START
Sub-Routine Write Pulse
Set SWE1 bit in FLMCR1
WDT enable
Wait (tsswe) 1µs
Set PSU bit in FLMCR1
Store 128-byte program data in program
data area and reprogram data area
Wait (tspsu) 50µs
Start of programming
Set P bit in FLMCR1
*4
n=1
m=0
Wait tsp10 or 30 or 200
*5
Clear P bit in FLMCR1
End of programming
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
*1
Sub-Routine-Call
Wait (tcp) 5µs
Apply Write pulse tsp30 or 200
Clear PSU bit in FLMCR1
Set PV bit in FLMCR1
See Note 6 for pulse width
Wait (tspv) 4µs
Wait (tcpsu) 5µs
H'FF dummy write to verify address
Disable WDT
n←n+1
tspvr = Wait 2µs
End Sub
Read verify data
*2
Write data =
verify data?
No
Increment address
Note 6: Write Pulse Width
Number of Writes n
Write Time
(tsp30/tsp200) µs
30 *
30 *
30 *
30 *
30 *
30 *
1
2
3
4
5
6
7
8
9
10
11
12
13
200
200
200
200
200
200
200
998
999
1000
200
200
200
m=1
Yes
No
6≥n?
Yes
Additional-programming data computation
Transfer additional-programming data to
additional-programming data area
*4
*3
Reprogram data computation
Transfer reprogram data to reprogram data area
No
*4
128-byte
data verification completed?
Yes
Clear PV bit in FLMCR1
Reprogram
Wait (tcpv) µs
Note: * Use a 10 µs write pulse for additional programming.
No
6 ≥ n?
Yes
Successively write 128-byte data from additional1
programming data area in RAM to flash memory *
RAM
Program data storage
area (128 bytes)
Sub-Routine-Call
Apply Write Pulse (Additional programming)
Reprogram data storage
area (128 bytes)
No
m=0?
Additional-programming
data storage area
(128 bytes)
No
n ≥ 1000?
Yes
Clear SWE bit in FLMCR1
Yes
Clear SWE bit in FLMCR1
Wait (tcswe) 100µs
Wait (tcswe) 100µs
End of programming
Programming failure
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of
additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Additional-Programming Data Computation Table
Reprogram Data Computation Table
Reprogram Data
(X')
Verify Data
Additional(V)
Programming Data (Y)
Original Data
Verify Data
Reprogram Data
(D)
(V)
(X)
0
0
1
Programming completed
0
0
0
Additional programming
to be executed
0
1
0
Programming incomplete;
reprogram
0
1
1
Additional programming
not to be executed
1
0
1
1
0
1
1
1
1
1
1
1
Additional programming
not to be executed
Additional programming
not to be executed
Comments
Still in erased state; no action
Comments
Figure 19.9 Program/Program-Verify Flowchart
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19.8.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.10 should be
followed.
1. Prewriting (setting erase block data to all 0) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in
turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (tsesu + tse + tce + tcesu) ms as the WDT overflow period.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B'00. Verify data can be read in words from the address to which a dummy write was
performed.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is (N).
19.8.3
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed
or erased, or while the boot program is executing, for the following three reasons:
1. Interrupt during programming/erasing may cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
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Erase start
*1
Erasing should be
done to a block
SWE bit in FLMCR1 ← 1
tsswe: Wait 1 µs
n=1
*3
Set EBR1 (2)
Enable WDT
ESU bit in FLMCR1 ← 1
tsesu: Wait 100 µs
E bit in FLMCR1 ← 1
start erasing
tse: Wait 10 ms
E bit in FLMCR1 ← 0
stop erasing
tce: Wait 10 µs
ESU bit in FLMCR1 ← 0
tcesu: Wait 10 µs
Disable WDT
EV bit in FLMCR1 ← 1
tsev: Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
tsevr: Wait 2 µs
n←n+1
Read verify data
Verify data = all 1?
Increment address
*2
No
Yes
No
Last address of block?
Yes
EV bit in FLMCR1 ← 0
EV bit in FLMCR1 ← 0
tcev: Wait 4 µs
tcev: Wait 4 µs
All erase block erased?
n ≥ 100?
*4
No
No
Yes
Yes
SWE bit in FLMCR1 ← 0
SWE bit in FLMCR1 ← 0
tcswe: Wait 100 µs
tcswe: Wait 100 µs
End of erasing
Erase failure
Notes: 1. Pre-writing (all erase block data are cleared to 0) is not necessary.
2. Verify data is read out in 16 bit size (word access).
3. Erasing block register (EBR) can be set about 1 bit at a time.
Do not specify 2 bits or more.
4. Erasing is performed block by block. when multiple blocks must be erased,
erase each lock one by one.
Figure 19.10 Erase/Erase-Verify Flowchart
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19.9
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
19.9.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset or standby mode. Flash memory control register
1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and
erase block register 2 (EBR2) are initialized. In a reset via the RES pin, the reset state is not
entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of
a reset during operation, hold the RES pin low for the RES pulse width specified in the AC
Characteristics section.
19.9.2
Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block
register 1 and 2 (EBR1 and EBR2), erase protection can be set for individual blocks. When EBR1
and EBR2 are set to H'00, erase protection is set for all blocks. By setting bit RAMS in RAMER,
programming/erase protection is set for all blocks.
19.9.3
Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
• When the CPU loses the bus during programming/erasing
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The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase
mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be
re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition
can be made to verify mode. Error protection can be cleared only by a reset or in hardware
standby.
19.10
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI input, are disabled when flash memory is being programmed or
erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot
mode*1, to give priority to the program or erase operation. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the interrupt exception handling sequence during programming or erasing, the vector would
not be read correctly*2, possibly resulting in CPU runaway.
3. If an interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
Notes: 1. Interrupt requests must be disabled inside and outside the CPU until the programming
control program has completed programming.
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased (while the P or E bit is set
in FLMCR1), correct read data will not be obtained (undetermined values will be
returned).
• If the interrupt entry in the vector table has not been programmed yet, interrupt
exception handling will not be executed correctly.
19.11
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as for a discrete flash memory. Use a PROM programmer which supports the
Renesas 256-kbyte flash memory on-chip microcomputer device type (FZTAT256V5A).
Rev. 2.00 Dec. 05, 2005 Page 554 of 724
REJ09B0200-0200
Section 19 ROM
19.12
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Power-down state
The flash memory can be read when part of the power circuit is halted and the LSI operates by
subclocks.
• Standby mode
All flash memory circuits are halted.
Table 19.6 shows the correspondence between the operating modes of this LSI and the flash
memory. When the flash memory returns to its normal operating state from standby mode, a
period to stabilize the power supply circuits that were stopped is needed. When the flash memory
returns to its normal operating state, bits STS2 to STS0 in SBYCR must be set to provide a wait
time of at least 100 µs, even when the external clock is being used.
Table 19.6 Flash Memory Operating States
LSI Operating State
Flash Memory Operating State
Active mode
Normal operating mode
Sleep mode
Normal operating mode
Watch mode
Standby mode
Standby mode
Sub-active mode
PDWND = 0: Power-down mode (read only)
Sub-sleep mode
PDWND = 1: Normal operating mode (read only)
Rev. 2.00 Dec. 05, 2005 Page 555 of 724
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Section 19 ROM
19.13
Usage Notes
Use the specified voltages and timing for programming and erasing: Applied voltages in
excess of the rating can permanently damage the device. Use a PROM programmer that supports
the Renesas 256-kbyte flash memory on-chip microcomputer device type (FZTAT256V3A).
Do not select the HN27C4096 setting for the PROM programmer, and only use the specified
socket adapter. Failure to observe these points may result in damage to the device.
Powering on and off: Do not apply a high level to the FWE pin until VCC has stabilized. Also,
drive the FWE pin low before turning off VCC.
When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in
the hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a power
failure and subsequent recovery.
FWE application/disconnection: FWE application should be carried out when MCU operation is
in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection
state.
The following points must be observed concerning FWE application and disconnection to prevent
unintentional programming or erasing of flash memory:
• Apply FWE when the VCC voltage has stabilized within its rated voltage range.
• In boot mode, apply and disconnect FWE during a reset.
• In user program mode, FWE can be switched between high and low level regardless of the
reset state. FWE input can also be switched during execution of a program in flash memory.
• Do not apply FWE if program runaway has occurred.
• Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 are
cleared.
Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when
applying or disconnecting FWE.
Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only
when programming or erasing flash memory. A system configuration in which a high level is
constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the
FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due
to program runaway, etc.
Rev. 2.00 Dec. 05, 2005 Page 556 of 724
REJ09B0200-0200
Section 19 ROM
Use the recommended algorithm when programming and erasing flash memory: The
recommended algorithm enables programming and erasing to be carried out without subjecting the
device to voltage stress or sacrificing program data reliability. When setting the P or E bit in
FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway,
etc.
Do not set or clear the SWE bit during execution of a program in flash memory: Wait for at
least 100 µs after clearing the SWE bit before executing a program or reading data in flash
memory.
When the SWE bit is set, data in flash memory can be rewritten. Access flash memory only for
verify operations (verification during programming/erasing). Also, do not clear the SWE bit
during programming, erasing, or verifying. Similarly, when using the RAM emulation function
while a high level is being input to the FWE pin, the SWE bit must be cleared before executing a
program or reading data in flash memory.
However, the RAM area overlapping flash memory space can be read and written to regardless of
whether the SWE bit is set or cleared.
Do not use interrupts while flash memory is being programmed or erased: All interrupt
requests, including NMI, should be disabled during FWE application to give priority to
program/erase operations.
Do not perform additional programming. Erase the memory before reprogramming: In onboard programming, perform only one programming operation on a 128-byte programming unit
block. In programmer mode, too, perform only one programming operation on a 128-byte
programming unit block. Programming should be carried out with the entire programming unit
block erased.
Before programming, check that the chip is correctly mounted in the PROM programmer:
Overcurrent damage to the device can result if the index marks on the PROM programmer socket,
socket adapter, and chip are not correctly aligned.
Do not touch the socket adapter or chip during programming: Touching either of these can
cause contact faults and write errors.
Reset the flash memory before turning on the power: To reset the flash memory during
oscillation stabilization period, the reset signal must be input for at least 100 µs.
Apply the reset signal while SWE is low to reset the flash memory during its operation: The
reset signal is applied at least 100 µs after the SWE bit has been cleared.
Rev. 2.00 Dec. 05, 2005 Page 557 of 724
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Section 19 ROM
Note on Switching from F-ZTAT Version to Mask ROM Version: The mask ROM version
does not have the internal registers for flash memory control that are provided in the F-ZTAT
version. Table 19.7 lists the registers that are present in the F-ZTAT version but not in the mask
ROM version. If a register listed in table 19.7 is read in the mask ROM version, an undefined
value will be returned. Therefore, if application software developed on the F-ZTAT version is
switched to a mask ROM version product, it must be modified to ensure that the registers in table
19.7 have no effect.
Table 19.7 Registers Present in F-ZTAT Version but Absent in Mask ROM Version
Register
Abbreviation
Address
Flash memory control register 1
FLMCR1
H'FFA8
Flash memory control register 2
FLMCR2
H'FFA9
Erase block register 1
EBR1
H'FFAA
RAM emulation register
RAMER
H'FEDB
Flash memory power control register
FLPWCR
H'FFAC
Rev. 2.00 Dec. 05, 2005 Page 558 of 724
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Section 20 Clock Pulse Generator
Section 20 Clock Pulse Generator
This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master
clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL circuit, clock
selection circuit, medium-speed clock divider, and bus master clock selection circuit. A block
diagram of the clock pulse generator is shown in figure 20.1.
LPWRCR
SCKCR
STC0, STC1
EXTAL
XTAL
System
clock
oscillator
SCK2 to SCK0
Mediumspeed
clock divider
PLL circuit
(x1, x2, x4)
Clock
selection
circuit
φSUB
OSC1
OSC2
Subclock
oscillator
Waveform
generation
circuit
φ/2 to
φ/32
Bus
master
clock
selection
circuit
φ
System
clock to
φ pin
Internal clock to
peripheral modules
Bus master clock
to CPU and DTC
WDT_1 count clock
[Legend]
LPWRCR: Low-power control register
SCKCR:
System clock control register
Figure 20.1 Block Diagram of Clock Pulse Generator
The frequency can be changed by means of the PLL circuit. Frequency changes are performed by
software by settings in the low-power control register (LPWRCR) and system clock control
register (SCKCR).
Rev. 2.00 Dec. 05, 2005 Page 559 of 724
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Section 20 Clock Pulse Generator
20.1
Register Descriptions
The on-chip clock pulse generator has the following registers. For details on LPWRCR, see
section 21.1.2, Low-Power Control Register (LPWRCR).
• System clock control register (SCKCR)
• Low-power control register (LPWRCR)
20.1.1
System Clock Control Register (SCKCR)
SCKCR performs φ clock output control, selection of operation when the PLL circuit frequency
multiplication factor is changed, and medium-speed mode control.
Bit
Bit Name
Initial
Value
R/W
Description
7
PSTOP
0
R/W
φ Clock Output Disable
Controls φ output.
High-speed Mode, Medium-Speed Mode
0: φ output
1: Fixed high
Sleep Mode
0: φ output
1: Fixed high
Software Standby Mode
0: Fixed high
1: Fixed high
Hardware Standby Mode
0: High impedance
1: High impedance
6 to 4 
All 0

Reserved
These bits are always read as 0.
Rev. 2.00 Dec. 05, 2005 Page 560 of 724
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Section 20 Clock Pulse Generator
Bit
Bit Name
Initial
Value
R/W
Description
3
STCS
0
R/W
Frequency Multiplication Factor Switching Mode Select
Selects the operation when the PLL circuit frequency
multiplication factor is changed.
0: Specified multiplication factor is valid after transition
to software standby mode
1: Specified multiplication factor is valid immediately
after STC1 bit and STC0 bit are rewritten
2
SCK2
0
R/W
System Clock Select 0 to 2
1
SCK1
0
R/W
These bits select the bus master clock.
0
SCK0
0
R/W
000: High-speed mode
001: Medium-speed clock is φ/2
010: Medium-speed clock is φ/4
011: Medium-speed clock is φ/8
100: Medium-speed clock is φ/16
101: Medium-speed clock is φ/32
11X: Setting prohibited
[Legend]
X:
Don't care
Rev. 2.00 Dec. 05, 2005 Page 561 of 724
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Section 20 Clock Pulse Generator
20.2
Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. In
either case, the input clock should not exceed 20 MHz.
20.2.1
Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure
20.2. Select the damping resistance Rd according to table 20.1. An AT-cut parallel-resonance
crystal should be used.
CL1
EXTAL
XTAL
Rd
CL1 = CL2 = 10 to 22 pF
CL2
Figure 20.2 Connection of Crystal Resonator (Example)
Table 20.1 Damping Resistance Value
Frequency (MHz)
4
8
10
12
16
20
Rd (Ω)
500
200
0
0
0
0
Figure 20.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has
the characteristics shown in table 20.2.
CL
XTAL
L
Rs
C0
EXTAL
AT-cut parallel-resonance type
Figure 20.3 Crystal Resonator Equivalent Circuit
Rev. 2.00 Dec. 05, 2005 Page 562 of 724
REJ09B0200-0200
Section 20 Clock Pulse Generator
Table 20.2 Crystal Resonator Characteristics
Frequency (MHz)
4
8
10
12
16
20
RS max (Ω)
120
80
70
60
50
40
C0 max (pF)
7
7
7
7
7
7
20.2.2
External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure
20.4. If the XTAL pin is left open, ensure that stray capacitance does not exceed 10 pF. When
complementary clock is input to the XTAL pin, the external clock input should be fixed high in
standby mode.
External clock input
EXTAL
XTAL
Open
(a) XTAL pin left open
EXTAL
External clock input
XTAL
(b) Complementary clock input at XTAL pin
Figure 20.4 External Clock Input (Examples)
Rev. 2.00 Dec. 05, 2005 Page 563 of 724
REJ09B0200-0200
Section 20 Clock Pulse Generator
Table 20.3 shows the input conditions for the external clock.
Table 20.3 External Clock Input Conditions
VCC = 5.0 V ± 10%
Item
Symbol
Min.
Max.
Unit
Test Conditions
External clock input low
pulse width
tEXL
15

ns
Figure 20.5
External clock input high
pulse width
tEXH
15

ns
External clock rise time
tEXr

5
ns
External clock fall time
tEXf

5
ns
tEXH
tEXL
VCC × 0.5
EXTAL
tEXr
tEXf
Figure 20.5 External Clock Input Timing
Rev. 2.00 Dec. 05, 2005 Page 564 of 724
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Section 20 Clock Pulse Generator
20.3
PLL Circuit
The PLL circuit multiplies the frequency of the clock from the oscillator by a factor of 1, 2, or 4.
The multiplication factor is set by the STC0 bit and the STC1 bit in LPWRCR. The phase of the
rising edge of the internal clock is controlled so as to match that at the EXTAL pin.
When the multiplication factor of the PLL circuit is changed, the operation varies according to the
setting of the STCS bit in SCKCR.
When STCS = 0, the setting becomes valid after a transition to software standby mode. The
transition time count is performed in accordance with the setting of bits STS0 to STS2 in SBYCR.
For details on SBYCR, see section 21.1.1, Standby Control Register (SBYCR).
1.
2.
3.
4.
5.
The initial PLL circuit multiplication factor is 1.
STS0 to STS2 are set to give the specified transition time.
The target value is set in STC0 and STC1, and a transition is made to software standby mode.
The clock pulse generator stops and the value set in STC0 and STC1 becomes valid.
Software standby mode is cleared, and a transition time is secured in accordance with the
setting in STS0 to STS2.
6. After the set transition time has elapsed, this LSI resumes operation using the target
multiplication factor.
If a PC break is set for the SLEEP instruction, software standby mode is entered and break
exception handling is executed after the oscillation settling time. In this case, the instruction
following the SLEEP instruction is executed after execution of the RTE instruction. When STCS =
1, this LSI operates on the changed multiplication factor immediately after bits STC0 and STC1
are rewritten.
20.4
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and
φ/32.
20.5
Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the clock supplied to the bus master by setting the
bits SCK 2 to 0 in SCKCR. The bus master clock can be selected from high-speed mode, or
medium-speed clocks (φ/2, φ/4, φ/8, φ/16, φ/32).
Rev. 2.00 Dec. 05, 2005 Page 565 of 724
REJ09B0200-0200
Section 20 Clock Pulse Generator
20.6
Subclock Oscillator
20.6.1
Connecting 32.768-kHz Crystal Resonator
To supply a clock to the subclock divider, connect a 32.768-kHz crystal resonator, as shown in
figure 20.6. Concerning the note on connection, see section 20.8.2, Note on Board Design.
C1
OSC1
C2
OSC2
C1 = C2 = 15pF (typ) *
Note: * C1 and C2 are reference values including the floating
capacitance of the boad.
Figure 20.6 Connection Example of 32.768-kHz Crystal Resonator
Figure 20.7 shows the equivalent circuit for a 32.768-kHz crystal resonator.
Ls
Cs
Rs
OSC1
OSC2
Co
Figure 20.7 Equivalent Circuit for 32.768-kHz Crystal Resonator
Rev. 2.00 Dec. 05, 2005 Page 566 of 724
REJ09B0200-0200
Section 20 Clock Pulse Generator
20.6.2
Handling Pins when Subclock is not Used
If no subclock is required, connect the OSC1 pin to Vss and leave the OSC2 pin open, as shown in
figure 20.8.
OSC1
OSC2
Open
Figure 20.8 Pin Handling when Subclock is not Used
20.7
Subclock Waveform Generation Circuit
To eliminate noise from the subclock input from the OSC1 pin, the subclock is sampled using the
dividing clock φ. The sampling frequency is set using the NESEL bit in LPWRCR. For details, see
section 21.1.2, Low-Power Control Register (LPWRCR).
No sampling is performed in subactive, subsleep, and watch mode.
20.8
Usage Notes
20.8.1
Note on Crystal Resonator
As various characteristics related to the crystal resonator are closely linked to the user's board
design, thorough evaluation is necessary on the user's part, using the resonator connection
examples shown in this section as a guide. As the resonator circuit ratings will depend on the
floating capacitance of the resonator and the mounting circuit, the ratings should be determined in
consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the
maximum rating is not applied to the oscillator pin.
Rev. 2.00 Dec. 05, 2005 Page 567 of 724
REJ09B0200-0200
Section 20 Clock Pulse Generator
20.8.2
Note on Board Design
When designing the board, place the crystal resonator and its load capacitors as close as possible
to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator
circuit, as shown in figure 20.9. This is to prevent induction from interfering with correct
oscillation.
Signal A Signal B
Avoid
This LSI
CL2
XTAL
EXTAL
CL1
Figure 20.9 Note on Board Design of Oscillator Circuit
Figure 20.10 shows external circuitry recommended to be provided around the PLL circuit. Place
oscillation settling capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other
signal lines cross this line. Separate PLLVss from the other Vcc and Vss lines at the board power
supply source, and be sure to insert bypass capacitors CB close to the pins.
R1 : 3 kΩ
C1 : 470 pF
PLLCAP
PLLVSS
VCL
VCC
CB : 0.1 µF*
CB : 0.1 µF
VSS
(Values are preliminary recommended values.)
Note: * CB is laminated ceramic.
Figure 20.10 External Circuitry Recommended for PLL Circuit
Rev. 2.00 Dec. 05, 2005 Page 568 of 724
REJ09B0200-0200
Section 21 Power-Down Modes
Section 21 Power-Down Modes
In addition to the normal program execution state, this LSI has power-down modes in which
operation of the CPU and oscillator is halted and power consumption is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and
so on.
This LSI's operating modes are as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
High-speed mode
Medium-speed mode
Subactive mode
Sleep mode
Subsleep mode
Watch mode
Module stop mode
Software standby mode
Hardware standby mode
Modes 2. to 9. are power-down modes. Sleep mode and subsleep mode are CPU states, mediumspeed mode is a CPU and bus master state, subactive mode is a CPU, bus master, and on-chip
peripheral function state, and module stop mode is an on-chip peripheral function (including bus
masters other than the CPU) state. Some of these states can be combined.
After a reset, the LSI operates in high-speed mode with on-chip peripheral modules other than the
DTC in module stop mode.
Table 21.1 shows the internal state of the LSI in each mode. Table 21.2 shows the conditions for
shifting between the power-down modes. Figure 21.1 shows the mode transition diagram.
LPWS269A_000020020200
Rev. 2.00 Dec. 05, 2005 Page 569 of 724
REJ09B0200-0200
Section 21 Power-Down Modes
Table 21.1 LSI Internal States in Each Mode
High-
Medium-
Function
Speed
Speed
System clock pulse
generator
Functioning Functioning Functioning Functioning Halted
Subclock generator
Functioning Functioning Functioning Functioning Functioning
CPU
External
interrupts
Module
Sleep
Stop
Watch
Software
Hardware
Subactive
Subsleep
Standby
Standby
Halted
Halted
Halted
Halted
Functioning
Functioning
Halted
Halted
Instructions Functioning Medium-
Halted
High/
Halted
Subclock
Halted
Halted
Halted
Registers
(retained)
mediumspeed
operation
(retained)
operation
(retained)
(retained)
(undefined)
Functioning Functioning Functioning Functioning Functioning
Functioning
Functioning
Functioning Halted
Functioning Functioning Functioning 
Halted
Subclock
Subclock
Halted
Halted
(retained)
operation
operation
(retained)
(reset)
Subclock
Subclock
Subclock
Halted
Halted
operation
operation
operation
(retained)
(reset)
Halted
Halted
Halted
Halted
Halted
(retained)
(retained)
(retained)
(retained)
(reset)
Halted
Halted
Halted
Halted
Halted
(retained)
(retained)
(retained)
(retained)
(reset)
Halted
Subclock
Halted
Halted
Halted
(retained)
operation
(retained)
(retained)
(reset)
Halted
Halted
Halted
Halted
Halted
(retained/
reset)
(retained/
reset)
(retained/
reset)
(reset)
(reset)
Functioning Functioning Functioning Halted
Halted
Halted
Halted
Halted
Halted
(reset)
(reset)
(reset)
(reset)
(reset)
(reset)
Functioning* Functioning* Functioning* Halted
Halted
NMI
speed
operation
IRQ0 to
IRQ5
Peripheral
WDT0
functions
WDT1
DTC
Functioning Functioning Functioning 
Functioning Medium-
Functioning Halted
speed
operation
TPU
(retained)
Functioning Functioning Functioning Halted
(retained)
PPG
PBC
Functioning Functioning Functioning Halted
(retained)
SCI0 to
Functioning Functioning Functioning Halted
SCI2
(retained/
reset)
SCI4
PWM
HCAN
A/D
LCD
Functioning Functioning Functioning Halted
(retained)
RAM
Functioning Functioning Functioning Functioning Retained
(retained)
(reset)
Functioning
Retained
Retained
Retained
Functioning
Retained
Retained
High
(DTC)
I/O
Functioning Functioning Functioning Functioning Retained
impedance
Notes: "Halted (retained)" means that internal register values are retained. The internal state is
"operation suspended. "
"Halted (reset)" means that internal register values and internal states are initialized.
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
* When the LCD is operated in watch mode, subactive mode, or subsleep mode, select
the subclock as the operating clock.
Rev. 2.00 Dec. 05, 2005 Page 570 of 724
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Section 21 Power-Down Modes
Program-halted state
STBY pin = Low
Hardware
standby mode
Reset state
STBY pin = High
RES pin = Low
Program execution state
RES pin = High
SSBY= 0, LSON= 0
SLEEP instruction
High-speed mode
(main clock)
Sleep mode
(main clock)
Any interrupt *3
SCK2 to
SCK0= 0
SCK2 to
SCK0 0
Medium-speed
mode
(main clock)
SSBY= 1,
PSS= 0, LSON= 0
SLEEP
instruction
Software
standby mode
External
interrupt *4
SLEEP
instruction
SSBY= 1,
PSS= 1, DTON= 0
Interrupt *1
LSON bit = 0
SLEEP instruction
SSBY = 1, PSS = 1
DTON = 1, LSON = 0
After the oscillation
stabilization time
(STS2 to STS0),
clock switching
exception handling
SLEEP instruction
SSBY = 1, PSS = 1
DTON = 1, LSON = 1
Clock switching
exception handling
SSBY= 0,
PSS= 1, LSON= 1
Interrupt *1
LSON bit = 1
Subactive mode
(subclock)
SLEEP instruction
Interrupt *2
: Transition after exception processing
Notes: 1.
2.
3.
4.
Watch mode
(subclock)
SLEEP
instruction
Subsleep mode
(subclock)
: Power-down mode
NMI, IRQ0 to IRQ5, and WDT1 interrupts
NMI, IRQ0 to IRQ5, IWDT0 interrupts, and WDT1 interrupts.
All interrupts
NMI and IRQ0 to IRQ5
• When a transition is made between modes by means of an interrupt, the transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the
interrupt request.
• From any state except hardware standby mode, a transition to the reset state occurs when RES is
driven low.
• From any state, a transition to hardware standby mode occurs when STBY is driven low.
• Always select high-speed mode before making a transition to watch mode or subactive mode.
Figure 21.1 Mode Transition Diagram
Rev. 2.00 Dec. 05, 2005 Page 571 of 724
REJ09B0200-0200
Section 21 Power-Down Modes
Table 21.2 Power-Down Mode Transition Conditions
PreTransition
State
Status of Control Bit at
Transition
State after Transition
back from PowerDown Mode Invoked
by Interrupt
PSS
LSON
DTON
State after Transition
Invoked by SLEEP
Instruction
High-speed/ 0
mediumspeed
0
X
0
X
Sleep
High-speed/mediumspeed
X
1
X


1
0
0
X
Software standby
High-speed/mediumspeed
1
0
1
X


1
1
0
0
Watch
High-speed
1
1
1
0
Watch
Subactive
1
1
0
1


1
1
1
1
Subactive

0
0
X
X


0
1
0
X


0
1
1
X
Subsleep
Subactive
1
0
X
X


1
1
0
0
Watch
High-speed
1
1
1
0
Watch
Subactive
Subactive
SSBY
1
1
0
1
High-speed

1
1
1
1


[Legend]
X:
Don't care
:
Setting prohibited
Rev. 2.00 Dec. 05, 2005 Page 572 of 724
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Section 21 Power-Down Modes
21.1
Register Descriptions
Registers related to power-down modes are shown below. For details on SCKCR, see section
20.1.1, System Clock Control Register (SCKCR). For details on TCSR, see section 12.2.2, Timer
Control/Status Register (TCSR).
•
•
•
•
•
•
•
•
Standby control register (SBYCR)
System clock control register (SCKCR)
Low-power control register (LPWRCR)
Timer control/status register (TCSR)
Module stop control register A (MSTPCRA)
Module stop control register B (MSTPCRB)
Module stop control register C (MSTPCRC)
Module stop control register D (MSTPCRD)
21.1.1
Standby Control Register (SBYCR)
SBYCR controls power-down modes.
Bit
Bit Name
Initial
Value
R/W
Description
7
SSBY
0
R/W
Software Standby
This bit in combination with other control bits specifies
the operating mode after executing the SLEEP
instruction. For details, see table 21.2.
0: Shifts to sleep mode when the SLEEP instruction is
executed in high-speed mode or medium-speed
mode, or to subsleep mode when the SLEEP
instruction is executed in subactive mode
1: Shifts to software standby mode, subactive mode, or
watch mode when the SLEEP instruction is executed
in high-speed mode or medium-speed mode, or to
watch mode or high-speed mode when the SLEEP
instruction is executed in subactive mode
This bit does not change when shifting between modes
by using interrupts. 0 should be written to this bit to
clear it.
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Section 21 Power-Down Modes
Bit
Bit Name
Initial
Value
R/W
Description
6
STS2
0
R/W
Standby Timer Select
5
STS1
0
R/W
4
STS0
0
R/W
These bits select the MCU standby time for clock
stabilization when software standby mode, watch mode,
or subactive mode is cancelled by an interrupt or an
instruction to shift to high-speed mode or mediumspeed mode. With a crystal resonator (table 21.3),
select a standby time of 8 ms (oscillation stabilization
time) or more, depending on the operating frequency.
With an external clock, any standby time can be
selected.
000: Standby time = 8192 states
001: Standby time = 16384 states
010: Standby time = 32768 states
011: Standby time = 65536 states
100: Standby time = 131072 states
101: Standby time = 262144 states
110: Reserved
111: Standby time = 16 states
3
OPE
1
R/W
Output Port Enable
Specifies whether the outputs of the address bus and
bus control signals (AS, RD, HWR, LWR) are retained
or set to high-impedance state in software standby
mode or watch mode, or when making a direct
transition.
2 to 0 —
All 0
—
Reserved
These bits are always read as 0 and cannot be
modified.
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Section 21 Power-Down Modes
• With Crystal Resonator
The STS2 to STS0 bits must be specified appropriately so that the standby time (oscillation
stabilization time) is at least 8 ms. Table 21.3 shows the standby time determined by a
combination of the operating frequency and the STS2 to STS0 bit setting.
Table 21.3 Standby Time Settings
Operating Frequency (MHz)
STS2
STS1
STS0
Standby Time
20
16
12
10
8
6
Unit
4
0
0
0
8192 states
0.41
0.51
0.65
0.8
1.0
1.3
2.0
0
0
1
16384 states
0.82
1.0
1.3
1.6
2.0
2.7
4.1
0
1
0
32768 states
1.6
2.0
2.7
3.3
4.1
5.5
8.2
0
1
1
65536 states
3.3
4.1
5.5
6.6
8.2
10.9
16.4
1
0
0
131072 states
6.6
8.2
10.9
13.1
16.4
21.8
32.8
1
0
1
262144 states
13.1
16.4
21.8
26.2
32.8
43.6
65.6
1
1
0
Reserved
—
—
—
—
—
—
—
1
1
1
16 states*
0.8
1.0
1.3
1.6
2.0
1.7
4.0
Notes:
*
ms
µs
: Recommended standby time
Setting prohibited
• With External Clock
The PLL circuit stabilization time must be ensured. Specify 2-ms or more standby time.
Rev. 2.00 Dec. 05, 2005 Page 575 of 724
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Section 21 Power-Down Modes
21.1.2
Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit
Bit Name
Initial
Value
R/W
Description
7
DTON
0
R/W
Direct Transition ON Flag
This bit in combination with the SSBY bit in SBYCR, the
LSON bit in LPWRCR, and the PSS bit in TCSR
specifies the operating mode after executing the SLEEP
instruction. For details, see table 21.2.
6
LSON
0
R/W
Low-Speed ON Flag
This bit in combination with the SSBY bit in SBYCR, the
DTON bit in LPWRCR, and the PSS bit in TCSR
specifies the operating mode after executing the SLEEP
instruction. For details, see table 21.2.
5
NESEL
0
R/W
Noise Elimination Sampling Frequency Select
Selects the frequency of the clock (φ) generated by the
system clock oscillator to be used to sample the
subclock (φSUB) generated by the subclock oscillator. Set
this bit to 0 when φ is 5 MHz or larger.
0: Sampled at φ/32
1: Sampled at φ/4
4
SUBSTP
0
R/W
Subclock Enable
Enables or disables subclock generation
0: Enables subclock generation
1: Disables subclock generation
3
RFCUT
0
R/W
Oscillation Circuit Feedback Resistance Control
Turns the internal feedback resistance of the main clock
oscillator on or off.
0: When the main clock is oscillating, sets the
feedback resistance on. When the main clock is
stopped, sets the feedback resistance off.
1: Sets the feedback resistance off.
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Section 21 Power-Down Modes
Bit
Bit Name
Initial
Value
R/W
Description
2

0
R/W
Reserved
The write value should always be 0.
1
STC1
0
R/W
Frequency Multiplication Factor
0
STC0
0
R/W
These bits specify the frequency multiplication factor of
the PLL circuit.
00: ×1
01: ×2
10: ×4
11: Setting prohibited
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Section 21 Power-Down Modes
21.1.3
Module Stop Control Registers A to D (MSTPCRA to MSTPCRD)
MSTPCR controls module stop mode. Setting a bit to 1 causes the corresponding module to enter
module stop mode. Clearing the bit to 0 clears the module stop mode.
• MSTPCRA
Bit
Initial
Value
Bit Name
7
MSTPA7*
6
MSTPA6
5
MSTPA5
4
MSTPA4*
3
MSTPA3
2
MSTPA2*
1
MSTPA1
0
MSTPA0*
1
2
2
2
R/W
Module
0
R/W
0
R/W
Data transfer controller (DTC)
1
R/W
16-bit timer pulse unit (TPU)
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Programmable pulse generator (PPG)
A/D converter
• MSTPCRB
Bit
Bit Name
Initial
Value
R/W
Module
7
MSTPB7
1
R/W
Serial communication interface_0 (SCI_0)
6
MSTPB6
1
R/W
Serial communication interface_1 (SCI_1)
5
MSTPB5
Serial communication interface_2 (SCI_2)
1
R/W
4
MSTPB4*
2
1
R/W
3
MSTPB3*2
1
R/W
2
2
1
R/W
2
1
R/W
2
1
R/W
1
0
MSTPB2*
MSTPB1*
MSTPB0*
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Section 21 Power-Down Modes
• MSTPCRC
Bit
Bit Name
2
Initial
Value
R/W
7
MSTPC7*
1
R/W
6
MSTPC6
1
R/W
2
Module
Serial communication interface_4 (SCI_4)
5
MSTPC5*
1
R/W
4
MSTPC4
1
R/W
PC break controller (PBC)
3
MSTPC3
1
R/W
Controller area network (HCAN_0)
2
MSTPC2
Controller area network (HCAN_1)
1
0
1
R/W
2
1
R/W
2
1
R/W
MSTPC1*
MSTPC0*
• MSTPCRD
Bit
Bit Name
Initial
Value
R/W
Module
7
MSTPD7
1
R/W
Motor control PWM timer (PWM)
6
MSTPD6
1
R/W
LCD controller/driver (LCD)
5
4
3
3
Undefined 
2
1
3
Undefined 
2
MSTPD5*
MSTPD4*
MSTPD3*
R/W
2
MSTPD2*
1
1
MSTPD1*3
Undefined 
R/W
0
MSTPD0*3
Undefined 
Notes: 1. Although this bit is readable/writable, only 0 should be written to.
2. Although this bit is readable/writable, only 1 should be written to.
3. This bit is read as undefined value and cannot be modified.
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Section 21 Power-Down Modes
21.2
Medium-Speed Mode
When the SCK2 to SCK0 bits in SCKCR are set to 1 in high-speed mode, the operating mode
changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the
CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0
bits. The bus master (DTC) other than the CPU operates in medium-speed mode.
On-chip peripheral modules other than the bus masters always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in four states, and internal I/O registers in eight states.
Medium-speed mode is canceled by clearing all of bits SCK2 to SCK0 to 0. A transition is made
to high-speed mode and medium-speed mode is canceled at the end of the current bus cycle.
If the SLEEP instruction is executed when the SSBY bit in SBYCR = 0 and LSON bit in
LPWRCR = 0, a transition is made to sleep mode. When sleep mode is canceled by an interrupt,
medium-speed mode is restored.
When the SLEEP instruction is executed with the SSBY bit = 1, LSON bit in LPWRCR = 0, and
PSS bit in TCSR (WDT1) = 0, operation shifts to software standby mode. When software standby
mode is canceled by an external interrupt, medium-speed mode is restored.
When the RES pin is driven low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies to a reset caused by an overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 21.2 shows the timing for transition to and clearance of medium-speed mode.
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Section 21 Power-Down Modes
Medium-speed mode
φ,
peripheral module clock
Bus master clock
Internal address bus
SBYCR
SBYCR
Internal write signal
Figure 21.2 Medium-Speed Mode Transition and Clearance Timing
21.3
Sleep Mode
When the SLEEP instruction is executed when the SSBY bit in SBYCR = 0 and the LSON bit in
LPWRCR = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the
contents of the CPU's internal registers are retained. Other peripheral modules do not stop.
Sleep mode is canceled by any interrupt, or signals at the RES or STBY pin.
When an interrupt occurs, sleep mode is canceled and interrupt exception handling starts. Sleep
mode is not canceled if the interrupt is disabled, or if interrupts other than NMI are masked by the
CPU.
When the RES pin is driven low, operation shifts to the reset state. After the stipulated reset input
duration, driving the RES pin high makes the CPU start reset exception handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
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Section 21 Power-Down Modes
21.4
Software Standby Mode
When the SLEEP instruction is executed when the SSBY bit in SBYCR = 1, the LSON bit in
LPWRCR = 0, and the PSS bit in TCSR (WDT1) = 0, a transition is made to software standby
mode. In this mode, the CPU, on-chip peripheral modules, and oscillator all stop. However, the
contents of the CPU internal registers and on-chip RAM data, the states of on-chip peripheral
modules other than the SCI, A/D converter, motor control PWM, and HCAN, and the states of I/O
ports are retained. The address bus and bus control signals are placed in the high-impedance state.
Software standby mode is canceled by an external interrupt (NMI and IRQ5 to IRQ0 pins), or
signals at the RES pin or STBY pin.
When an NMI or IRQ5 to IRQ0 interrupt request signal is input, clock oscillation starts, and after
the time set in bits STS2 to STS0 in SBYCR has elapsed, stable clocks are supplied to the entire
chip, software standby mode is canceled, and interrupt exception handling is started.
When canceling software standby mode with an IRQ5 to IRQ0 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ5 to IRQ0 is
generated. Software standby mode cannot be canceled if the interrupt has been masked on the
CPU side or has been designated as a DTC activation source.
When the RES pin is driven low, clock oscillation starts. At the same time as clock oscillation
starts, the clock is supplied to the entire chip. Note that the RES pin must be held low until clock
oscillation stabilizes. When the RES pin is driven high, the CPU begins reset exception handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 21.3 shows an example in which a transition is made to software standby mode at a falling
edge of the NMI pin, and software standby mode is canceled at a rising edge of the NMI pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then canceled at the rising edge of the NMI pin.
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Section 21 Power-Down Modes
Oscillator
φ
NMI
NMIEG
SSBY
NMI exception
Software standby mode
handling
(power-down mode)
NMIEG=1
SSBY=1
SLEEP instruction
Oscillation
stabilization
time tOSC2
NMI exception
handling
Figure 21.3 Software Standby Mode Application Example
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Section 21 Power-Down Modes
21.5
Hardware Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power consumption. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. The I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low.
Do not change the state of the mode pins (MD2 and MD0) while this LSI is in hardware standby
mode.
Hardware standby mode is canceled by signals at the STBY pin and the RES pin. When the STBY
pin is driven high while the RES pin is low, the reset state is entered and clock oscillation is
started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms
(oscillation stabilization time) when using a crystal oscillator). When the RES pin is subsequently
driven high, a transition is made to the program execution state via the reset exception handling
state.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is canceled by driving the STBY pin high,
waiting for the oscillation stabilization time, then switching the RES pin from low to high.
Oscillator
RES
STBY
Oscillation
stabilization
time
Figure 21.4 Hardware Standby Mode Timing
Rev. 2.00 Dec. 05, 2005 Page 584 of 724
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Reset
exception
handling
Section 21 Power-Down Modes
21.6
Watch Mode
When the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit
in SBYCR = 1, the DTON bit in LPWRCR = 0, and the PSS bit in TCSR (WDT1) = 1, CPU
operation shifts to watch mode.
In watch mode, the CPU stops and peripheral modules other than WDT1 also stop. The contents
of the CPU internal registers and on-chip RAM data, the states of on-chip peripheral modules
other than the SCI, A/D converter, motor control PWM, and HCAN, and the states of I/O ports are
retained.
Watch mode is canceled by any interrupt (WOVI1 interrupt, NMI pin, or IRQ5 to IRQ0 pins), or
signals at the RES or STBY pin.
When an interrupt occurs, watch mode is canceled and a transition is made to high-speed mode or
medium-speed mode when the LSON bit in LPWRCR = 0 or to subactive mode when the LSON
bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to the entire LSI
and interrupt exception handling starts after the time set in the STS2 to STS0 bits of SBYCR has
elapsed. For an IRQ5 to IRQ0 interrupt, watch mode is not canceled if the corresponding enable
bit has been cleared to 0. For an interrupt from an on-chip peripheral module, if the interrupt
enable register has been set to disable the reception of that interrupt or is masked by the CPU,
watch mode is not canceled.
For the setting of the oscillation stabilization time when making a transition from watch mode to
high-speed mode, see table 21.3.
For canceling watch mode by the RES pin, see section 21.4, Software Standby Mode.
When the STBY pin is driven low, a transition is made to hardware standby mode.
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Section 21 Power-Down Modes
21.7
Subsleep Mode
When the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR = 0, the
LSON bit in LPWRCR = 1, and the PSS bit in TCSR (WDT1) = 1, CPU operation shifts to
subsleep mode.
In subsleep mode, the CPU stops and peripheral modules other than WDT0 and WDT1 also stop.
The contents of the CPU internal registers and on-chip RAM data, and the states of on-chip
peripheral modules other than the SCI, A/D converter, motor control PWM, and HCAN, and the
states of I/O ports are retained.
Subsleep mode is canceled by any interrupt (interrupts from on-chip peripheral modules, NMI pin,
or IRQ5 to IRQ0 pins), or signals at the RES or STBY pin.
When an interrupt occurs, subsleep mode is canceled and interrupt exception handling starts.
For an IRQ5 to IRQ0 interrupt, subsleep mode is not canceled if the corresponding enable bit has
been cleared to 0. For an interrupt from an on-chip peripheral module, if the interrupt enable
register has been set to disable the reception of that interrupt or is masked by the CPU, subsleep
mode is not canceled.
For canceling subsleep mode by the RES pin, see section 21.4, Software Standby Mode.
When the STBY pin is driven low, a transition is made to hardware standby mode.
21.8
Subactive Mode
CPU operation shifts to subactive mode when the SLEEP instruction is executed in high-speed
mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1, the LSON bit = 1, and
the PSS bit in TCSR (WDT1) = 1. When an interrupt occurs in watch mode, and if the LSON bit
in LPWRCR is 1, a transition is made to subactive mode. If an interrupt occurs in subsleep mode,
a transition is made to subactive mode.
In subactive mode, the CPU operates at low speed on the subclock, and the program is executed
one after another. Peripheral modules other than WDT0 and WDT1 are also stopped.
When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SCKCR must be set to 0.
Subactive mode is canceled by the SLEEP instruction or signals at the RES or STBY pin.
Rev. 2.00 Dec. 05, 2005 Page 586 of 724
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Section 21 Power-Down Modes
When the SLEEP instruction is executed with the SSBY bit in SBYCR = 1, the DTON bit in
LPWRCR = 0, and the PSS bit in TCSR (WDT1) = 1, subactive mode is canceled and a transition
is made to watch mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR =
0, the LSON bit in LPWRCR = 1, and the PSS bit in TCSR (WDT1) = 1, a transition is made to
subsleep mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR = 1, the
DTON bit in LPWRCR = 1, the LSON bit = 0, and the PSS bit in TCSR (WDT1) = 1, a direct
transition is made to high-speed mode (SCK0 to SCK2 are all 0).
For details on direct transitions, see section 21.10, Direct Transitions
For canceling subactive mode by the RES pin, see section 21.4, Software Standby Mode.
When the STBY pin is driven low, a transition is made to hardware standby mode.
21.9
Module Stop Mode
Module stop mode can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
Table 21.4 shows MSTP bits and the corresponding on-chip supporting modules.
When the corresponding MSTP bit is cleared to 0, module stop mode is canceled and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI*, motor control PWM, A/D converter, and HCAN are retained.
After reset clearance, all modules other than DTC are in module stop mode.
When an on-chip peripheral module is in module stop mode, read/write access to its registers is
disabled.
Note
* Internal states in some part of registers in SCI are retained.
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Section 21 Power-Down Modes
21.10
Direct Transitions
21.10.1 Overview of Direct Transitions
There are three modes, high-speed, medium-speed, and subactive, in which the CPU executes
programs. When a direct transition is made, there is no interruption of program execution in
shifting between high-speed and subactive modes. Direct transitions are enabled by setting the
DTON bit in LPWRCR to 1, then executing the SLEEP instruction. After a transition, direct
transition interrupt exception handling starts.
Direct Transition from High-Speed Mode to Subactive Mode: Execute the SLEEP instruction
in high-speed mode with the SSBY bit in SBYCR = 1, the LSON bit in LPWRCR = 1, the DTON
bit = 1, and the PSS bit in TCSR (WDT1) = 1, to make a direct transition to subactive mode.
Direct Transition from Subactive Mode to High-Speed Mode: Execute the SLEEP instruction
in subactive mode with the SSBY bit in SBYCR = 1, the LSON bit in LPWRCR = 0, the DTON
bit = 1, and the PSS bit in TCSR (WDT_1) = 1, to make a direct transition to high-speed mode
after the time set in the STS2 to STS0 bits in SBYCR has elapsed.
21.11
φ Clock Output Disabling Function
The output of the φ clock can be controlled by means of the PSTOP bit in SCKCR and DDR for
the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus
cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When
DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is
set. Table 21.4 shows the state of the φ pin in each processing state.
Table 21.4 φ Pin State in Each Processing State
PSTOP
High-Speed Mode,
Medium-Speed
Mode, Subactive Sleep Mode,
Mode
Subsleep Mode
0
X
High impedance
High impedance
High impedance
1
0
φ output
φ output
Fixed high
1
1
Fixed high
Fixed high
Register Settings
DDR
[Legend]
X:
Don't care
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Software Standby
Mode, Watch
Mode, Direct
Hardware Standby
Transitions
Mode
High impedance
Section 21 Power-Down Modes
21.12
Usage Notes
21.12.1 I/O Port Status
The status of the I/O ports is retained in software standby mode and watch mode. When the OPE
bit is set to 1, the address bus and bus control signal outputs are also retained. Therefore, when a
high level is output, the current consumption is not diminished by the amount of current to support
the high level output.
21.12.2 Current Consumption during Oscillation Stabilization Wait Period
The current consumption increases during the oscillation stabilization wait period.
21.12.3 DTC Module Stop Setting
The MSTPA6 bits cannot be set to 1 depending on the DTC operating status. Module stop mode
for the DTC must be specified while the DTC is stopped.
For details, see section 8, Data Transfer Controller (DTC).
21.12.4 On-Chip Peripheral Module Interrupts
Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module
stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU
interrupt source activation source. Interrupts should therefore be disabled before entering module
stop mode.
21.12.5 Writing to MSTPCR
MSTPCR should only be written to by the CPU.
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Section 21 Power-Down Modes
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Section 22 List of Registers
Section 22 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1.
•
•
•
2.
•
•
•
Register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified according to functional modules.
The access size is indicated.
Register bits
Bit configurations of the registers are listed in the same order as the register addresses.
Reserved bits are indicated by  in the bit name column.
No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holding data.
3. Register states in each operating mode
• Register states are listed in the same order as the register addresses.
• The register states shown here are for the basic operating modes. If there is a specific reset for
an on-chip module, refer to the section on that on-chip module.
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Section 22 List of Registers
22.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Number
Abbreviation of Bits Address*
Module
Data
Number of
Bus
Access
Width States
Master control register_0
MCR_0
8
H'F800
HCAN_0
16
4
General status register_0
GSR_0
8
H'F801
HCAN_0
16
4
Bit configuration register_0
BCR_0
16
H'F802
HCAN_0
16
4
Mailbox configuration register_0
MBCR_0
16
H'F804
HCAN_0
16
4
Transmit wait register_0
TXPR_0
16
H'F806
HCAN_0
16
4
Transmit wait cancel register_0
TXCR_0
16
H'F808
HCAN_0
16
4
Transmit acknowledge register_0 TXACK_0
16
H'F80A
HCAN_0
16
4
Abort acknowledge register_0
ABACK_0
16
H'F80C
HCAN_0
16
4
Receive complete register_0
RXPR_0
16
H'F80E
HCAN_0
16
4
Remote request register_0
RFPR_0
16
H'F810
HCAN_0
16
4
Interrupt register_0
IRR_0
16
H'F812
HCAN_0
16
4
Mailbox interrupt mask register_0 MBIMR_0
16
H'F814
HCAN_0
16
4
Interrupt mask register_0
IMR_0
16
H'F816
HCAN_0
16
4
Receive error counter_0
REC_0
8
H'F818
HCAN_0
16
4
Transmit error counter_0
TEC_0
8
H'F819
HCAN_0
16
4
Unread message status
register_0
UMSR_0
16
H'F81A
HCAN_0
16
4
Local acceptance filter mask L_0 LAFML_0
16
H'F81C
HCAN_0
16
4
Local acceptance filter mask H_0 LAFMH_0
16
H'F81E
HCAN_0
16
4
Message control 0[1]
MC0[1]
8
H'F820
HCAN_0
16
4
Message control 0[2]
MC0[2]
8
H'F821
HCAN_0
16
4
Message control 0[3]
MC0[3]
8
H'F822
HCAN_0
16
4
Message control 0[4]
MC0[4]
8
H'F823
HCAN_0
16
4
Message control 0[5]
MC0[5]
8
H'F824
HCAN_0
16
4
Message control 0[6]
MC0[6]
8
H'F825
HCAN_0
16
4
Message control 0[7]
MC0[7]
8
H'F826
HCAN_0
16
4
Rev. 2.00 Dec. 05, 2005 Page 592 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message control 0[8]
MC0[8]
8
H'F827
HCAN_0
16
4
Message control 1[1]
MC1[1]
8
H'F828
HCAN_0
16
4
Message control 1[2]
MC1[2]
8
H'F829
HCAN_0
16
4
Message control 1[3]
MC1[3]
8
H'F82A
HCAN_0
16
4
Message control 1[4]
MC1[4]
8
H'F82B
HCAN_0
16
4
Message control 1[5]
MC1[5]
8
H'F82C
HCAN_0
16
4
Message control 1[6]
MC1[6]
8
H'F82D
HCAN_0
16
4
Message control 1[7]
MC1[7]
8
H'F82E
HCAN_0
16
4
Message control 1[8]
MC1[8]
8
H'F82F
HCAN_0
16
4
Message control 2[1]
MC2[1]
8
H'F830
HCAN_0
16
4
Message control 2[2]
MC2[2]
8
H'F831
HCAN_0
16
4
Message control 2[3]
MC2[3]
8
H'F832
HCAN_0
16
4
Message control 2[4]
MC2[4]
8
H'F833
HCAN_0
16
4
Message control 2[5]
MC2[5]
8
H'F834
HCAN_0
16
4
Message control 2[6]
MC2[6]
8
H'F835
HCAN_0
16
4
Message control 2[7]
MC2[7]
8
H'F836
HCAN_0
16
4
Message control 2[8]
MC2[8]
8
H'F837
HCAN_0
16
4
Message control 3[1]
MC3[1]
8
H'F838
HCAN_0
16
4
Message control 3[2]
MC3[2]
8
H'F839
HCAN_0
16
4
Message control 3[3]
MC3[3]
8
H'F83A
HCAN_0
16
4
Message control 3[4]
MC3[4]
8
H'F83B
HCAN_0
16
4
Message control 3[5]
MC3[5]
8
H'F83C
HCAN_0
16
4
Message control 3[6]
MC3[6]
8
H'F83D
HCAN_0
16
4
Message control 3[7]
MC3[7]
8
H'F83E
HCAN_0
16
4
Message control 3[8]
MC3[8]
8
H'F83F
HCAN_0
16
4
Message control 4[1]
MC4[1]
8
H'F840
HCAN_0
16
4
Message control 4[2]
MC4[2]
8
H'F841
HCAN_0
16
4
Message control 4[3]
MC4[3]
8
H'F842
HCAN_0
16
4
Message control 4[4]
MC4[4]
8
H'F843
HCAN_0
16
4
Message control 4[5]
MC4[5]
8
H'F844
HCAN_0
16
4
Rev. 2.00 Dec. 05, 2005 Page 593 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message control 4[6]
MC4[6]
8
H'F845
HCAN_0
16
4
Message control 4[7]
MC4[7]
8
H'F846
HCAN_0
16
4
Message control 4[8]
MC4[8]
8
H'F847
HCAN_0
16
4
Message control 5[1]
MC5[1]
8
H'F848
HCAN_0
16
4
Message control 5[2]
MC5[2]
8
H'F849
HCAN_0
16
4
Message control 5[3]
MC5[3]
8
H'F84A
HCAN_0
16
4
Message control 5[4]
MC5[4]
8
H'F84B
HCAN_0
16
4
Message control 5[5]
MC5[5]
8
H'F84C
HCAN_0
16
4
Message control 5[6]
MC5[6]
8
H'F84D
HCAN_0
16
4
Message control 5[7]
MC5[7]
8
H'F84E
HCAN_0
16
4
Message control 5[8]
MC5[8]
8
H'F84F
HCAN_0
16
4
Message control 6[1]
MC6[1]
8
H'F850
HCAN_0
16
4
Message control 6[2]
MC6[2]
8
H'F851
HCAN_0
16
4
Message control 6[3]
MC6[3]
8
H'F852
HCAN_0
16
4
Message control 6[4]
MC6[4]
8
H'F853
HCAN_0
16
4
Message control 6[5]
MC6[5]
8
H'F854
HCAN_0
16
4
Message control 6[6]
MC6[6]
8
H'F855
HCAN_0
16
4
Message control 6[7]
MC6[7]
8
H'F856
HCAN_0
16
4
Message control 6[8]
MC6[8]
8
H'F857
HCAN_0
16
4
Message control 7[1]
MC7[1]
8
H'F858
HCAN_0
16
4
Message control 7[2]
MC7[2]
8
H'F859
HCAN_0
16
4
Message control 7[3]
MC7[3]
8
H'F85A
HCAN_0
16
4
Message control 7[4]
MC7[4]
8
H'F85B
HCAN_0
16
4
Message control 7[5]
MC7[5]
8
H'F85C
HCAN_0
16
4
Message control 7[6]
MC7[6]
8
H'F85D
HCAN_0
16
4
Message control 7[7]
MC7[7]
8
H'F85E
HCAN_0
16
4
Message control 7[8]
MC7[8]
8
H'F85F
HCAN_0
16
4
Message control 8[1]
MC8[1]
8
H'F860
HCAN_0
16
4
Message control 8[2]
MC8[2]
8
H'F861
HCAN_0
16
4
Message control 8[3]
MC8[3]
8
H'F862
HCAN_0
16
4
Rev. 2.00 Dec. 05, 2005 Page 594 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message control 8[4]
MC8[4]
8
H'F863
HCAN_0
16
4
Message control 8[5]
MC8[5]
8
H'F864
HCAN_0
16
4
Message control 8[6]
MC8[6]
8
H'F865
HCAN_0
16
4
Message control 8[7]
MC8[7]
8
H'F866
HCAN_0
16
4
Message control 8[8]
MC8[8]
8
H'F867
HCAN_0
16
4
Message control 9[1]
MC9[1]
8
H'F868
HCAN_0
16
4
Message control 9[2]
MC9[2]
8
H'F869
HCAN_0
16
4
Message control 9[3]
MC9[3]
8
H'F86A
HCAN_0
16
4
Message control 9[4]
MC9[4]
8
H'F86B
HCAN_0
16
4
Message control 9[5]
MC9[5]
8
H'F86C
HCAN_0
16
4
Message control 9[6]
MC9[6]
8
H'F86D
HCAN_0
16
4
Message control 9[7]
MC9[7]
8
H'F86E
HCAN_0
16
4
Message control 9[8]
MC9[8]
8
H'F86F
HCAN_0
16
4
Message control 10[1]
MC10[1]
8
H'F870
HCAN_0
16
4
Message control 10[2]
MC10[2]
8
H'F871
HCAN_0
16
4
Message control 10[3]
MC10[3]
8
H'F872
HCAN_0
16
4
Message control 10[4]
MC10[4]
8
H'F873
HCAN_0
16
4
Message control 10[5]
MC10[5]
8
H'F874
HCAN_0
16
4
Message control 10[6]
MC10[6]
8
H'F875
HCAN_0
16
4
Message control 10[7]
MC10[7]
8
H'F876
HCAN_0
16
4
Message control 10[8]
MC10[8]
8
H'F877
HCAN_0
16
4
Message control 11[1]
MC11[1]
8
H'F878
HCAN_0
16
4
Message control 11[2]
MC11[2]
8
H'F879
HCAN_0
16
4
Message control 11[3]
MC11[3]
8
H'F87A
HCAN_0
16
4
Message control 11[4]
MC11[4]
8
H'F87B
HCAN_0
16
4
Message control 11[5]
MC11[5]
8
H'F87C
HCAN_0
16
4
Message control 11[6]
MC11[6]
8
H'F87D
HCAN_0
16
4
Message control 11[7]
MC11[7]
8
H'F87E
HCAN_0
16
4
Message control 11[8]
MC11[8]
8
H'F87F
HCAN_0
16
4
Rev. 2.00 Dec. 05, 2005 Page 595 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message control 12[1]
MC12[1]
8
H'F880
HCAN_0
16
4
Message control 12[2]
MC12[2]
8
H'F881
HCAN_0
16
4
Message control 12[3]
MC12[3]
8
H'F882
HCAN_0
16
4
Message control 12[4]
MC12[4]
8
H'F883
HCAN_0
16
4
Message control 12[5]
MC12[5]
8
H'F884
HCAN_0
16
4
Message control 12[6]
MC12[6]
8
H'F885
HCAN_0
16
4
Message control 12[7]
MC12[7]
8
H'F886
HCAN_0
16
4
Message control 12[8]
MC12[8]
8
H'F887
HCAN_0
16
4
Message control 13[1]
MC13[1]
8
H'F888
HCAN_0
16
4
Message control 13[2]
MC13[2]
8
H'F889
HCAN_0
16
4
Message control 13[3]
MC13[3]
8
H'F88A
HCAN_0
16
4
Message control 13[4]
MC13[4]
8
H'F88B
HCAN_0
16
4
Message control 13[5]
MC13[5]
8
H'F88C
HCAN_0
16
4
Message control 13[6]
MC13[6]
8
H'F88D
HCAN_0
16
4
Message control 13[7]
MC13[7]
8
H'F88E
HCAN_0
16
4
Message control 13[8]
MC13[8]
8
H'F88F
HCAN_0
16
4
Message control 14[1]
MC14[1]
8
H'F890
HCAN_0
16
4
Message control 14[2]
MC14[2]
8
H'F891
HCAN_0
16
4
Message control 14[3]
MC14[3]
8
H'F892
HCAN_0
16
4
Message control 14[4]
MC14[4]
8
H'F893
HCAN_0
16
4
Message control 14[5]
MC14[5]
8
H'F894
HCAN_0
16
4
Message control 14[6]
MC14[6]
8
H'F895
HCAN_0
16
4
Message control 14[7]
MC14[7]
8
H'F896
HCAN_0
16
4
Message control 14[8]
MC14[8]
8
H'F897
HCAN_0
16
4
Message control 15[1]
MC15[1]
8
H'F898
HCAN_0
16
4
Message control 15[2]
MC15[2]
8
H'F899
HCAN_0
16
4
Message control 15[3]
MC15[3]
8
H'F89A
HCAN_0
16
4
Message control 15[4]
MC15[4]
8
H'F89B
HCAN_0
16
4
Message control 15[5]
MC15[5]
8
H'F89C
HCAN_0
16
4
Message control 15[6]
MC15[6]
8
H'F89D
HCAN_0
16
4
Rev. 2.00 Dec. 05, 2005 Page 596 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message control 15[7]
MC15[7]
8
H'F89E
HCAN_0
16
4
Message control 15[8]
MC15[8]
8
H'F89F
HCAN_0
16
4
Message data 0[1]
MD0[1]
8
H'F8B0
HCAN_0
16
4
Message data 0[2]
MD0[2]
8
H'F8B1
HCAN_0
16
4
Message data 0[3]
MD0[3]
8
H'F8B2
HCAN_0
16
4
Message data 0[4]
MD0[4]
8
H'F8B3
HCAN_0
16
4
Message data 0[5]
MD0[5]
8
H'F8B4
HCAN_0
16
4
Message data 0[6]
MD0[6]
8
H'F8B5
HCAN_0
16
4
Message data 0[7]
MD0[7]
8
H'F8B6
HCAN_0
16
4
Message data 0[8]
MD0[8]
8
H'F8B7
HCAN_0
16
4
Message data 1[1]
MD1[1]
8
H'F8B8
HCAN_0
16
4
Message data 1[2]
MD1[2]
8
H'F8B9
HCAN_0
16
4
Message data 1[3]
MD1[3]
8
H'F8BA
HCAN_0
16
4
Message data 1[4]
MD1[4]
8
H'F8BB
HCAN_0
16
4
Message data 1[5]
MD1[5]
8
H'F8BC
HCAN_0
16
4
Message data 1[6]
MD1[6]
8
H'F8BD
HCAN_0
16
4
Message data 1[7]
MD1[7]
8
H'F8BE
HCAN_0
16
4
Message data 1[8]
MD1[8]
8
H'F8BF
HCAN_0
16
4
Message data 2[1]
MD2[1]
8
H'F8C0
HCAN_0
16
4
Message data 2[2]
MD2[2]
8
H'F8C1
HCAN_0
16
4
Message data 2[3]
MD2[3]
8
H'F8C2
HCAN_0
16
4
Message data 2[4]
MD2[4]
8
H'F8C3
HCAN_0
16
4
Message data 2[5]
MD2[5]
8
H'F8C4
HCAN_0
16
4
Message data 2[6]
MD2[6]
8
H'F8C5
HCAN_0
16
4
Message data 2[7]
MD2[7]
8
H'F8C6
HCAN_0
16
4
Message data 2[8]
MD2[8]
8
H'F8C7
HCAN_0
16
4
Message data 3[1]
MD3[1]
8
H'F8C8
HCAN_0
16
4
Message data 3[2]
MD3[2]
8
H'F8C9
HCAN_0
16
4
Message data 3[3]
MD3[3]
8
H'F8CA
HCAN_0
16
4
Message data 3[4]
MD3[4]
8
H'F8CB
HCAN_0
16
4
Rev. 2.00 Dec. 05, 2005 Page 597 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message data 3[5]
MD3[5]
8
H'F8CC
HCAN_0
16
4
Message data 3[6]
MD3[6]
8
H'F8CD
HCAN_0
16
4
Message data 3[7]
MD3[7]
8
H'F8CE
HCAN_0
16
4
Message data 3[8]
MD3[8]
8
H'F8CF
HCAN_0
16
4
Message data 4[1]
MD4[1]
8
H'F8D0
HCAN_0
16
4
Message data 4[2]
MD4[2]
8
H'F8D1
HCAN_0
16
4
Message data 4[3]
MD4[3]
8
H'F8D2
HCAN_0
16
4
Message data 4[4]
MD4[4]
8
H'F8D3
HCAN_0
16
4
Message data 4[5]
MD4[5]
8
H'F8D4
HCAN_0
16
4
Message data 4[6]
MD4[6]
8
H'F8D5
HCAN_0
16
4
Message data 4[7]
MD4[7]
8
H'F8D6
HCAN_0
16
4
Message data 4[8]
MD4[8]
8
H'F8D7
HCAN_0
16
4
Message data 5[1]
MD5[1]
8
H'F8D8
HCAN_0
16
4
Message data 5[2]
MD5[2]
8
H'F8D9
HCAN_0
16
4
Message data 5[3]
MD5[3]
8
H'F8DA
HCAN_0
16
4
Message data 5[4]
MD5[4]
8
H'F8DB
HCAN_0
16
4
Message data 5[5]
MD5[5]
8
H'F8DC
HCAN_0
16
4
Message data 5[6]
MD5[6]
8
H'F8DD
HCAN_0
16
4
Message data 5[7]
MD5[7]
8
H'F8DE
HCAN_0
16
4
Message data 5[8]
MD5[8]
8
H'F8DF
HCAN_0
16
4
Message data 6[1]
MD6[1]
8
H'F8E0
HCAN_0
16
4
Message data 6[2]
MD6[2]
8
H'F8E1
HCAN_0
16
4
Message data 6[3]
MD6[3]
8
H'F8E2
HCAN_0
16
4
Message data 6[4]
MD6[4]
8
H'F8E3
HCAN_0
16
4
Message data 6[5]
MD6[5]
8
H'F8E4
HCAN_0
16
4
Message data 6[6]
MD6[6]
8
H'F8E5
HCAN_0
16
4
Message data 6[7]
MD6[7]
8
H'F8E6
HCAN_0
16
4
Message data 6[8]
MD6[8]
8
H'F8E7
HCAN_0
16
4
Message data 7[1]
MD7[1]
8
H'F8E8
HCAN_0
16
4
Message data 7[2]
MD7[2]
8
H'F8E9
HCAN_0
16
4
Rev. 2.00 Dec. 05, 2005 Page 598 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message data 7[3]
MD7[3]
8
H'F8EA
HCAN_0
16
4
Message data 7[4]
MD7[4]
8
H'F8EB
HCAN_0
16
4
Message data 7[5]
MD7[5]
8
H'F8EC
HCAN_0
16
4
Message data 7[6]
MD7[6]
8
H'F8ED
HCAN_0
16
4
Message data 7[7]
MD7[7]
8
H'F8EE
HCAN_0
16
4
Message data 7[8]
MD7[8]
8
H'F8EF
HCAN_0
16
4
Message data 8[1]
MD8[1]
8
H'F8F0
HCAN_0
16
4
Message data 8[2]
MD8[2]
8
H'F8F1
HCAN_0
16
4
Message data 8[3]
MD8[3]
8
H'F8F2
HCAN_0
16
4
Message data 8[4]
MD8[4]
8
H'F8F3
HCAN_0
16
4
Message data 8[5]
MD8[5]
8
H'F8F4
HCAN_0
16
4
Message data 8[6]
MD8[6]
8
H'F8F5
HCAN_0
16
4
Message data 8[7]
MD8[7]
8
H'F8F6
HCAN_0
16
4
Message data 8[8]
MD8[8]
8
H'F8F7
HCAN_0
16
4
Message data 9[1]
MD9[1]
8
H'F8F8
HCAN_0
16
4
Message data 9[2]
MD9[2]
8
H'F8F9
HCAN_0
16
4
Message data 9[3]
MD9[3]
8
H'F8FA
HCAN_0
16
4
Message data 9[4]
MD9[4]
8
H'F8FB
HCAN_0
16
4
Message data 9[5]
MD9[5]
8
H'F8FC
HCAN_0
16
4
Message data 9[6]
MD9[6]
8
H'F8FD
HCAN_0
16
4
Message data 9[7]
MD9[7]
8
H'F8FE
HCAN_0
16
4
Message data 9[8]
MD9[8]
8
H'F8FF
HCAN_0
16
4
Message data 10[1]
MD10[1]
8
H'F900
HCAN_0
16
4
Message data 10[2]
MD10[2]
8
H'F901
HCAN_0
16
4
Message data 10[3]
MD10[3]
8
H'F902
HCAN_0
16
4
Message data 10[4]
MD10[4]
8
H'F903
HCAN_0
16
4
Message data 10[5]
MD10[5]
8
H'F904
HCAN_0
16
4
Message data 10[6]
MD10[6]
8
H'F905
HCAN_0
16
4
Message data 10[7]
MD10[7]
8
H'F906
HCAN_0
16
4
Message data 10[8]
MD10[8]
8
H'F907
HCAN_0
16
4
Rev. 2.00 Dec. 05, 2005 Page 599 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message data 11[1]
MD11[1]
8
H'F908
HCAN_0
16
4
Message data 11[2]
MD11[2]
8
H'F909
HCAN_0
16
4
Message data 11[3]
MD11[3]
8
H'F90A
HCAN_0
16
4
Message data 11[4]
MD11[4]
8
H'F90B
HCAN_0
16
4
Message data 11[5]
MD11[5]
8
H'F90C
HCAN_0
16
4
Message data 11[6]
MD11[6]
8
H'F90D
HCAN_0
16
4
Message data 11[7]
MD11[7]
8
H'F90E
HCAN_0
16
4
Message data 11[8]
MD11[8]
8
H'F90F
HCAN_0
16
4
Message data 12[1]
MD12[1]
8
H'F910
HCAN_0
16
4
Message data 12[2]
MD12[2]
8
H'F911
HCAN_0
16
4
Message data 12[3]
MD12[3]
8
H'F912
HCAN_0
16
4
Message data 12[4]
MD12[4]
8
H'F913
HCAN_0
16
4
Message data 12[5]
MD12[5]
8
H'F914
HCAN_0
16
4
Message data 12[6]
MD12[6]
8
H'F915
HCAN_0
16
4
Message data 12[7]
MD12[7]
8
H'F916
HCAN_0
16
4
Message data 12[8]
MD12[8]
8
H'F917
HCAN_0
16
4
Message data 13[1]
MD13[1]
8
H'F918
HCAN_0
16
4
Message data 13[2]
MD13[2]
8
H'F919
HCAN_0
16
4
Message data 13[3]
MD13[3]
8
H'F91A
HCAN_0
16
4
Message data 13[4]
MD13[4]
8
H'F91B
HCAN_0
16
4
Message data 13[5]
MD13[5]
8
H'F91C
HCAN_0
16
4
Message data 13[6]
MD13[6]
8
H'F91D
HCAN_0
16
4
Message data 13[7]
MD13[7]
8
H'F91E
HCAN_0
16
4
Message data 13[8]
MD13[8]
8
H'F91F
HCAN_0
16
4
Message data 14[1]
MD14[1]
8
H'F920
HCAN_0
16
4
Message data 14[2]
MD14[2]
8
H'F921
HCAN_0
16
4
Message data 14[3]
MD14[3]
8
H'F922
HCAN_0
16
4
Message data 14[4]
MD14[4]
8
H'F923
HCAN_0
16
4
Message data 14[5]
MD14[5]
8
H'F924
HCAN_0
16
4
Message data 14[6]
MD14[6]
8
H'F925
HCAN_0
16
4
Rev. 2.00 Dec. 05, 2005 Page 600 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message data 14[7]
MD14[7]
8
H'F926
HCAN_0
16
4
Message data 14[8]
MD14[8]
8
H'F927
HCAN_0
16
4
Message data 15[1]
MD15[1]
8
H'F928
HCAN_0
16
4
Message data 15[2]
MD15[2]
8
H'F929
HCAN_0
16
4
Message data 15[3]
MD15[3]
8
H'F92A
HCAN_0
16
4
Message data 15[4]
MD15[4]
8
H'F92B
HCAN_0
16
4
Message data 15[5]
MD15[5]
8
H'F92C
HCAN_0
16
4
Message data 15[6]
MD15[6]
8
H'F92D
HCAN_0
16
4
Message data 15[7]
MD15[7]
8
H'F92E
HCAN_0
16
4
Message data 15[8]
MD15[8]
8
H'F92F
HCAN_0
16
4
HCAN monitor register
HCANMON_0 8
H'F930
HCAN_0
16
4
Master control register_1
MCR_1
8
H'FA00
HCAN_1
16
4
General status register_1
GSR_1
8
H'FA01
HCAN_1
16
4
Bit configuration register_1
BCR_1
16
H'FA02
HCAN_1
16
4
Mailbox configuration register_1
MBCR_1
16
H'FA04
HCAN_1
16
4
Transmit wait register_1
TXPR_1
16
H'FA06
HCAN_1
16
4
Transmit wait cancel register_1
TXCR_1
16
H'FA08
HCAN_1
16
4
Transmit acknowledge register_1 TXACK_1
16
H'FA0A
HCAN_1
16
4
Abort acknowledge register_1
ABACK_1
16
H'FA0C
HCAN_1
16
4
Receive complete register_1
RXPR_1
16
H'FA0E
HCAN_1
16
4
Remote request register_1
RFPR_1
16
H'FA10
HCAN_1
16
4
Interrupt register_1
IRR_1
16
H'FA12
HCAN_1
16
4
Mailbox interrupt mask register_1 MBIMR_1
16
H'FA14
HCAN_1
16
4
Interrupt mask register_1
IMR_1
16
H'FA16
HCAN_1
16
4
Receive error counter_1
REC_1
8
H'FA18
HCAN_1
16
4
Transmit error counter_1
TEC_1
8
H'FA19
HCAN_1
16
4
Unread message status
register_1
UMSR_1
16
H'FA1A
HCAN_1
16
4
Local acceptance filter mask L_1 LAFML_1
16
H'FA1C
HCAN_1
16
4
Local acceptance filter mask H_1 LAFMH_1
16
H'FA1E
HCAN_1
16
4
Rev. 2.00 Dec. 05, 2005 Page 601 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message control 0[1]
MC0[1]
8
H'FA20
HCAN_1
16
4
Message control 0[2]
MC0[2]
8
H'FA21
HCAN_1
16
4
Message control 0[3]
MC0[3]
8
H'FA22
HCAN_1
16
4
Message control 0[4]
MC0[4]
8
H'FA23
HCAN_1
16
4
Message control 0[5]
MC0[5]
8
H'FA24
HCAN_1
16
4
Message control 0[6]
MC0[6]
8
H'FA25
HCAN_1
16
4
Message control 0[7]
MC0[7]
8
H'FA26
HCAN_1
16
4
Message control 0[8]
MC0[8]
8
H'FA27
HCAN_1
16
4
Message control 1[1]
MC1[1]
8
H'FA28
HCAN_1
16
4
Message control 1[2]
MC1[2]
8
H'FA29
HCAN_1
16
4
Message control 1[3]
MC1[3]
8
H'FA2A
HCAN_1
16
4
Message control 1[4]
MC1[4]
8
H'FA2B
HCAN_1
16
4
Message control 1[5]
MC1[5]
8
H'FA2C
HCAN_1
16
4
Message control 1[6]
MC1[6]
8
H'FA2D
HCAN_1
16
4
Message control 1[7]
MC1[7]
8
H'FA2E
HCAN_1
16
4
Message control 1[8]
MC1[8]
8
H'FA2F
HCAN_1
16
4
Message control 2[1]
MC2[1]
8
H'FA30
HCAN_1
16
4
Message control 2[2]
MC2[2]
8
H'FA31
HCAN_1
16
4
Message control 2[3]
MC2[3]
8
H'FA32
HCAN_1
16
4
Message control 2[4]
MC2[4]
8
H'FA33
HCAN_1
16
4
Message control 2[5]
MC2[5]
8
H'FA34
HCAN_1
16
4
Message control 2[6]
MC2[6]
8
H'FA35
HCAN_1
16
4
Message control 2[7]
MC2[7]
8
H'FA36
HCAN_1
16
4
Message control 2[8]
MC2[8]
8
H'FA37
HCAN_1
16
4
Message control 3[1]
MC3[1]
8
H'FA38
HCAN_1
16
4
Message control 3[2]
MC3[2]
8
H'FA39
HCAN_1
16
4
Message control 3[3]
MC3[3]
8
H'FA3A
HCAN_1
16
4
Message control 3[4]
MC3[4]
8
H'FA3B
HCAN_1
16
4
Message control 3[5]
MC3[5]
8
H'FA3C
HCAN_1
16
4
Rev. 2.00 Dec. 05, 2005 Page 602 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message control 3[6]
MC3[6]
8
H'FA3D
HCAN_1
16
4
Message control 3[7]
MC3[7]
8
H'FA3E
HCAN_1
16
4
Message control 3[8]
MC3[8]
8
H'FA3F
HCAN_1
16
4
Message control 4[1]
MC4[1]
8
H'FA40
HCAN_1
16
4
Message control 4[2]
MC4[2]
8
H'FA41
HCAN_1
16
4
Message control 4[3]
MC4[3]
8
H'FA42
HCAN_1
16
4
Message control 4[4]
MC4[4]
8
H'FA43
HCAN_1
16
4
Message control 4[5]
MC4[5]
8
H'FA44
HCAN_1
16
4
Message control 4[6]
MC4[6]
8
H'FA45
HCAN_1
16
4
Message control 4[7]
MC4[7]
8
H'FA46
HCAN_1
16
4
Message control 4[8]
MC4[8]
8
H'FA47
HCAN_1
16
4
Message control 5[1]
MC5[1]
8
H'FA48
HCAN_1
16
4
Message control 5[2]
MC5[2]
8
H'FA49
HCAN_1
16
4
Message control 5[3]
MC5[3]
8
H'FA4A
HCAN_1
16
4
Message control 5[4]
MC5[4]
8
H'FA4B
HCAN_1
16
4
Message control 5[5]
MC5[5]
8
H'FA4C
HCAN_1
16
4
Message control 5[6]
MC5[6]
8
H'FA4D
HCAN_1
16
4
Message control 5[7]
MC5[7]
8
H'FA4E
HCAN_1
16
4
Message control 5[8]
MC5[8]
8
H'FA4F
HCAN_1
16
4
Message control 6[1]
MC6[1]
8
H'FA50
HCAN_1
16
4
Message control 6[2]
MC6[2]
8
H'FA51
HCAN_1
16
4
Message control 6[3]
MC6[3]
8
H'FA52
HCAN_1
16
4
Message control 6[4]
MC6[4]
8
H'FA53
HCAN_1
16
4
Message control 6[5]
MC6[5]
8
H'FA54
HCAN_1
16
4
Message control 6[6]
MC6[6]
8
H'FA55
HCAN_1
16
4
Message control 6[7]
MC6[7]
8
H'FA56
HCAN_1
16
4
Message control 6[8]
MC6[8]
8
H'FA57
HCAN_1
16
4
Message control 7[1]
MC7[1]
8
H'FA58
HCAN_1
16
4
Message control 7[2]
MC7[2]
8
H'FA59
HCAN_1
16
4
Message control 7[3]
MC7[3]
8
H'FA5A
HCAN_1
16
4
Rev. 2.00 Dec. 05, 2005 Page 603 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message control 7[4]
MC7[4]
8
H'FA5B
HCAN_1
16
4
Message control 7[5]
MC7[5]
8
H'FA5C
HCAN_1
16
4
Message control 7[6]
MC7[6]
8
H'FA5D
HCAN_1
16
4
Message control 7[7]
MC7[7]
8
H'FA5E
HCAN_1
16
4
Message control 7[8]
MC7[8]
8
H'FA5F
HCAN_1
16
4
Message control 8[1]
MC8[1]
8
H'FA60
HCAN_1
16
4
Message control 8[2]
MC8[2]
8
H'FA61
HCAN_1
16
4
Message control 8[3]
MC8[3]
8
H'FA62
HCAN_1
16
4
Message control 8[4]
MC8[4]
8
H'FA63
HCAN_1
16
4
Message control 8[5]
MC8[5]
8
H'FA64
HCAN_1
16
4
Message control 8[6]
MC8[6]
8
H'FA65
HCAN_1
16
4
Message control 8[7]
MC8[7]
8
H'FA66
HCAN_1
16
4
Message control 8[8]
MC8[8]
8
H'FA67
HCAN_1
16
4
Message control 9[1]
MC9[1]
8
H'FA68
HCAN_1
16
4
Message control 9[2]
MC9[2]
8
H'FA69
HCAN_1
16
4
Message control 9[3]
MC9[3]
8
H'FA6A
HCAN_1
16
4
Message control 9[4]
MC9[4]
8
H'FA6B
HCAN_1
16
4
Message control 9[5]
MC9[5]
8
H'FA6C
HCAN_1
16
4
Message control 9[6]
MC9[6]
8
H'FA6D
HCAN_1
16
4
Message control 9[7]
MC9[7]
8
H'FA6E
HCAN_1
16
4
Message control 9[8]
MC9[8]
8
H'FA6F
HCAN_1
16
4
Message control 10[1]
MC10[1]
8
H'FA70
HCAN_1
16
4
Message control 10[2]
MC10[2]
8
H'FA71
HCAN_1
16
4
Message control 10[3]
MC10[3]
8
H'FA72
HCAN_1
16
4
Message control 10[4]
MC10[4]
8
H'FA73
HCAN_1
16
4
Message control 10[5]
MC10[5]
8
H'FA74
HCAN_1
16
4
Message control 10[6]
MC10[6]
8
H'FA75
HCAN_1
16
4
Message control 10[7]
MC10[7]
8
H'FA76
HCAN_1
16
4
Message control 10[8]
MC10[8]
8
H'FA77
HCAN_1
16
4
Rev. 2.00 Dec. 05, 2005 Page 604 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message control 11[1]
MC11[1]
8
H'FA78
HCAN_1
16
4
Message control 11[2]
MC11[2]
8
H'FA79
HCAN_1
16
4
Message control 11[3]
MC11[3]
8
H'FA7A
HCAN_1
16
4
Message control 11[4]
MC11[4]
8
H'FA7B
HCAN_1
16
4
Message control 11[5]
MC11[5]
8
H'FA7C
HCAN_1
16
4
Message control 11[6]
MC11[6]
8
H'FA7D
HCAN_1
16
4
Message control 11[7]
MC11[7]
8
H'FA7E
HCAN_1
16
4
Message control 11[8]
MC11[8]
8
H'FA7F
HCAN_1
16
4
Message control 12[1]
MC12[1]
8
H'FA80
HCAN_1
16
4
Message control 12[2]
MC12[2]
8
H'FA81
HCAN_1
16
4
Message control 12[3]
MC12[3]
8
H'FA82
HCAN_1
16
4
Message control 12[4]
MC12[4]
8
H'FA83
HCAN_1
16
4
Message control 12[5]
MC12[5]
8
H'FA84
HCAN_1
16
4
Message control 12[6]
MC12[6]
8
H'FA85
HCAN_1
16
4
Message control 12[7]
MC12[7]
8
H'FA86
HCAN_1
16
4
Message control 12[8]
MC12[8]
8
H'FA87
HCAN_1
16
4
Message control 13[1]
MC13[1]
8
H'FA88
HCAN_1
16
4
Message control 13[2]
MC13[2]
8
H'FA89
HCAN_1
16
4
Message control 13[3]
MC13[3]
8
H'FA8A
HCAN_1
16
4
Message control 13[4]
MC13[4]
8
H'FA8B
HCAN_1
16
4
Message control 13[5]
MC13[5]
8
H'FA8C
HCAN_1
16
4
Message control 13[6]
MC13[6]
8
H'FA8D
HCAN_1
16
4
Message control 13[7]
MC13[7]
8
H'FA8E
HCAN_1
16
4
Message control 13[8]
MC13[8]
8
H'FA8F
HCAN_1
16
4
Message control 14[1]
MC14[1]
8
H'FA90
HCAN_1
16
4
Message control 14[2]
MC14[2]
8
H'FA91
HCAN_1
16
4
Message control 14[3]
MC14[3]
8
H'FA92
HCAN_1
16
4
Message control 14[4]
MC14[4]
8
H'FA93
HCAN_1
16
4
Message control 14[5]
MC14[5]
8
H'FA94
HCAN_1
16
4
Message control 14[6]
MC14[6]
8
H'FA95
HCAN_1
16
4
Rev. 2.00 Dec. 05, 2005 Page 605 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message control 14[7]
MC14[7]
8
H'FA96
HCAN_1
16
4
Message control 14[8]
MC14[8]
8
H'FA97
HCAN_1
16
4
Message control 15[1]
MC15[1]
8
H'FA98
HCAN_1
16
4
Message control 15[2]
MC15[2]
8
H'FA99
HCAN_1
16
4
Message control 15[3]
MC15[3]
8
H'FA9A
HCAN_1
16
4
Message control 15[4]
MC15[4]
8
H'FA9B
HCAN_1
16
4
Message control 15[5]
MC15[5]
8
H'FA9C
HCAN_1
16
4
Message control 15[6]
MC15[6]
8
H'FA9D
HCAN_1
16
4
Message control 15[7]
MC15[7]
8
H'FA9E
HCAN_1
16
4
Message control 15[8]
MC15[8]
8
H'FA9F
HCAN_1
16
4
Message data 0[1]
MD0[1]
8
H'FAB0
HCAN_1
16
4
Message data 0[2]
MD0[2]
8
H'FAB1
HCAN_1
16
4
Message data 0[3]
MD0[3]
8
H'FAB2
HCAN_1
16
4
Message data 0[4]
MD0[4]
8
H'FAB3
HCAN_1
16
4
Message data 0[5]
MD0[5]
8
H'FAB4
HCAN_1
16
4
Message data 0[6]
MD0[6]
8
H'FAB5
HCAN_1
16
4
Message data 0[7]
MD0[7]
8
H'FAB6
HCAN_1
16
4
Message data 0[8]
MD0[8]
8
H'FAB7
HCAN_1
16
4
Message data 1[1]
MD1[1]
8
H'FAB8
HCAN_1
16
4
Message data 1[2]
MD1[2]
8
H'FAB9
HCAN_1
16
4
Message data 1[3]
MD1[3]
8
H'FABA
HCAN_1
16
4
Message data 1[4]
MD1[4]
8
H'FABB
HCAN_1
16
4
Message data 1[5]
MD1[5]
8
H'FABC
HCAN_1
16
4
Message data 1[6]
MD1[6]
8
H'FABD
HCAN_1
16
4
Message data 1[7]
MD1[7]
8
H'FABE
HCAN_1
16
4
Message data 1[8]
MD1[8]
8
H'FABF
HCAN_1
16
4
Message data 2[1]
MD2[1]
8
H'FAC0
HCAN_1
16
4
Message data 2[2]
MD2[2]
8
H'FAC1
HCAN_1
16
4
Message data 2[3]
MD2[3]
8
H'FAC2
HCAN_1
16
4
Message data 2[4]
MD2[4]
8
H'FAC3
HCAN_1
16
4
Rev. 2.00 Dec. 05, 2005 Page 606 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message data 2[5]
MD2[5]
8
H'FAC4
HCAN_1
16
4
Message data 2[6]
MD2[6]
8
H'FAC5
HCAN_1
16
4
Message data 2[7]
MD2[7]
8
H'FAC6
HCAN_1
16
4
Message data 2[8]
MD2[8]
8
H'FAC7
HCAN_1
16
4
Message data 3[1]
MD3[1]
8
H'FAC8
HCAN_1
16
4
Message data 3[2]
MD3[2]
8
H'FAC9
HCAN_1
16
4
Message data 3[3]
MD3[3]
8
H'FACA
HCAN_1
16
4
Message data 3[4]
MD3[4]
8
H'FACB
HCAN_1
16
4
Message data 3[5]
MD3[5]
8
H'FACC
HCAN_1
16
4
Message data 3[6]
MD3[6]
8
H'FACD
HCAN_1
16
4
Message data 3[7]
MD3[7]
8
H'FACE
HCAN_1
16
4
Message data 3[8]
MD3[8]
8
H'FACF
HCAN_1
16
4
Message data 4[1]
MD4[1]
8
H'FAD0
HCAN_1
16
4
Message data 4[2]
MD4[2]
8
H'FAD1
HCAN_1
16
4
Message data 4[3]
MD4[3]
8
H'FAD2
HCAN_1
16
4
Message data 4[4]
MD4[4]
8
H'FAD3
HCAN_1
16
4
Message data 4[5]
MD4[5]
8
H'FAD4
HCAN_1
16
4
Message data 4[6]
MD4[6]
8
H'FAD5
HCAN_1
16
4
Message data 4[7]
MD4[7]
8
H'FAD6
HCAN_1
16
4
Message data 4[8]
MD4[8]
8
H'FAD7
HCAN_1
16
4
Message data 5[1]
MD5[1]
8
H'FAD8
HCAN_1
16
4
Message data 5[2]
MD5[2]
8
H'FAD9
HCAN_1
16
4
Message data 5[3]
MD5[3]
8
H'FADA
HCAN_1
16
4
Message data 5[4]
MD5[4]
8
H'FADB
HCAN_1
16
4
Message data 5[5]
MD5[5]
8
H'FADC
HCAN_1
16
4
Message data 5[6]
MD5[6]
8
H'FADD
HCAN_1
16
4
Message data 5[7]
MD5[7]
8
H'FADE
HCAN_1
16
4
Message data 5[8]
MD5[8]
8
H'FADF
HCAN_1
16
4
Message data 6[1]
MD6[1]
8
H'FAE0
HCAN_1
16
4
Message data 6[2]
MD6[2]
8
H'FAE1
HCAN_1
16
4
Rev. 2.00 Dec. 05, 2005 Page 607 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message data 6[3]
MD6[3]
8
H'FAE2
HCAN_1
16
4
Message data 6[4]
MD6[4]
8
H'FAE3
HCAN_1
16
4
Message data 6[5]
MD6[5]
8
H'FAE4
HCAN_1
16
4
Message data 6[6]
MD6[6]
8
H'FAE5
HCAN_1
16
4
Message data 6[7]
MD6[7]
8
H'FAE6
HCAN_1
16
4
Message data 6[8]
MD6[8]
8
H'FAE7
HCAN_1
16
4
Message data 7[1]
MD7[1]
8
H'FAE8
HCAN_1
16
4
Message data 7[2]
MD7[2]
8
H'FAE9
HCAN_1
16
4
Message data 7[3]
MD7[3]
8
H'FAEA
HCAN_1
16
4
Message data 7[4]
MD7[4]
8
H'FAEB
HCAN_1
16
4
Message data 7[5]
MD7[5]
8
H'FAEC
HCAN_1
16
4
Message data 7[6]
MD7[6]
8
H'FAED
HCAN_1
16
4
Message data 7[7]
MD7[7]
8
H'FAEE
HCAN_1
16
4
Message data 7[8]
MD7[8]
8
H'FAEF
HCAN_1
16
4
Message data 8[1]
MD8[1]
8
H'FAF0
HCAN_1
16
4
Message data 8[2]
MD8[2]
8
H'FAF1
HCAN_1
16
4
Message data 8[3]
MD8[3]
8
H'FAF2
HCAN_1
16
4
Message data 8[4]
MD8[4]
8
H'FAF3
HCAN_1
16
4
Message data 8[5]
MD8[5]
8
H'FAF4
HCAN_1
16
4
Message data 8[6]
MD8[6]
8
H'FAF5
HCAN_1
16
4
Message data 8[7]
MD8[7]
8
H'FAF6
HCAN_1
16
4
Message data 8[8]
MD8[8]
8
H'FAF7
HCAN_1
16
4
Message data 9[1]
MD9[1]
8
H'FAF8
HCAN_1
16
4
Message data 9[2]
MD9[2]
8
H'FAF9
HCAN_1
16
4
Message data 9[3]
MD9[3]
8
H'FAFA
HCAN_1
16
4
Message data 9[4]
MD9[4]
8
H'FAFB
HCAN_1
16
4
Message data 9[5]
MD9[5]
8
H'FAFC
HCAN_1
16
4
Message data 9[6]
MD9[6]
8
H'FAFD
HCAN_1
16
4
Message data 9[7]
MD9[7]
8
H'FAFE
HCAN_1
16
4
Message data 9[8]
MD9[8]
8
H'FAFF
HCAN_1
16
4
Rev. 2.00 Dec. 05, 2005 Page 608 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message data 10[1]
MD10[1]
8
H'FB00
HCAN_1
16
4
Message data 10[2]
MD10[2]
8
H'FB01
HCAN_1
16
4
Message data 10[3]
MD10[3]
8
H'FB02
HCAN_1
16
4
Message data 10[4]
MD10[4]
8
H'FB03
HCAN_1
16
4
Message data 10[5]
MD10[5]
8
H'FB04
HCAN_1
16
4
Message data 10[6]
MD10[6]
8
H'FB05
HCAN_1
16
4
Message data 10[7]
MD10[7]
8
H'FB06
HCAN_1
16
4
Message data 10[8]
MD10[8]
8
H'FB07
HCAN_1
16
4
Message data 11[1]
MD11[1]
8
H'FB08
HCAN_1
16
4
Message data 11[2]
MD11[2]
8
H'FB09
HCAN_1
16
4
Message data 11[3]
MD11[3]
8
H'FB0A
HCAN_1
16
4
Message data 11[4]
MD11[4]
8
H'FB0B
HCAN_1
16
4
Message data 11[5]
MD11[5]
8
H'FB0C
HCAN_1
16
4
Message data 11[6]
MD11[6]
8
H'FB0D
HCAN_1
16
4
Message data 11[7]
MD11[7]
8
H'FB0E
HCAN_1
16
4
Message data 11[8]
MD11[8]
8
H'FB0F
HCAN_1
16
4
Message data 12[1]
MD12[1]
8
H'FB10
HCAN_1
16
4
Message data 12[2]
MD12[2]
8
H'FB11
HCAN_1
16
4
Message data 12[3]
MD12[3]
8
H'FB12
HCAN_1
16
4
Message data 12[4]
MD12[4]
8
H'FB13
HCAN_1
16
4
Message data 12[5]
MD12[5]
8
H'FB14
HCAN_1
16
4
Message data 12[6]
MD12[6]
8
H'FB15
HCAN_1
16
4
Message data 12[7]
MD12[7]
8
H'FB16
HCAN_1
16
4
Message data 12[8]
MD12[8]
8
H'FB17
HCAN_1
16
4
Message data 13[1]
MD13[1]
8
H'FB18
HCAN_1
16
4
Message data 13[2]
MD13[2]
8
H'FB19
HCAN_1
16
4
Message data 13[3]
MD13[3]
8
H'FB1A
HCAN_1
16
4
Message data 13[4]
MD13[4]
8
H'FB1B
HCAN_1
16
4
Message data 13[5]
MD13[5]
8
H'FB1C
HCAN_1
16
4
Message data 13[6]
MD13[6]
8
H'FB1D
HCAN_1
16
4
Rev. 2.00 Dec. 05, 2005 Page 609 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Message data 13[7]
MD13[7]
8
H'FB1E
HCAN_1
16
4
Message data 13[8]
MD13[8]
8
H'FB1F
HCAN_1
16
4
Message data 14[1]
MD14[1]
8
H'FB20
HCAN_1
16
4
Message data 14[2]
MD14[2]
8
H'FB21
HCAN_1
16
4
Message data 14[3]
MD14[3]
8
H'FB22
HCAN_1
16
4
Message data 14[4]
MD14[4]
8
H'FB23
HCAN_1
16
4
Message data 14[5]
MD14[5]
8
H'FB24
HCAN_1
16
4
Message data 14[6]
MD14[6]
8
H'FB25
HCAN_1
16
4
Message data 14[7]
MD14[7]
8
H'FB26
HCAN_1
16
4
Message data 14[8]
MD14[8]
8
H'FB27
HCAN_1
16
4
Message data 15[1]
MD15[1]
8
H'FB28
HCAN_1
16
4
Message data 15[2]
MD15[2]
8
H'FB29
HCAN_1
16
4
Message data 15[3]
MD15[3]
8
H'FB2A
HCAN_1
16
4
Message data 15[4]
MD15[4]
8
H'FB2B
HCAN_1
16
4
Message data 15[5]
MD15[5]
8
H'FB2C
HCAN_1
16
4
Message data 15[6]
MD15[6]
8
H'FB2D
HCAN_1
16
4
Message data 15[7]
MD15[7]
8
H'FB2E
HCAN_1
16
4
Message data 15[8]
MD15[8]
8
H'FB2F
HCAN_1
16
4
HCAN monitor register_1
HCANMON_1 8
H'FB30
HCAN_1
16
4
PWM control register_1
PWCR_1
8
H'FC00
PWM_1
16
4
PWM output control register_1
PWOCR_1
8
H'FC02
PWM_1
16
4
PWM polarity register_1
PWPR_1
8
H'FC04
PWM_1
16
4
PWM cycle register_1
PWCYR_1
16
H'FC06
PWM_1
16
4
PWM buffer register_1A
PWBFR_1A 16
H'FC08
PWM_1
16
4
PWM buffer register_1C
PWBFR_1C 16
H'FC0A
PWM_1
16
4
PWM buffer register_1E
PWBFR_1E 16
H'FC0C
PWM_1
16
4
PWM buffer register_1G
PWBFR_1G 16
H'FC0E
PWM_1
16
4
PWM control register_2
PWCR_2
8
H'FC10
PWM_2
16
4
PWM output control register_2
PWOCR_2
8
H'FC12
PWM_2
16
4
PWM polarity register_2
PWPR_2
8
H'FC14
PWM_2
16
4
Rev. 2.00 Dec. 05, 2005 Page 610 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
PWM cycle register_2
PWCYR_2
16
H'FC16
PWM_2
16
4
PWM buffer register_2A
PWBFR_2A 16
H'FC18
PWM_2
16
4
PWM buffer register_2C
PWBFR_2C 16
H'FC1A
PWM_2
16
4
PWM buffer register_2E
PWBFR_2E 16
H'FC1C
PWM_2
16
4
PWM buffer register_2G
PWBFR_2G 16
H'FC1E
PWM_2
16
4
Port H data direction register
PHDDR
8
H'FC20
PORT
16
4
Port J data direction register
PJDDR
8
H'FC21
PORT
16
4
Port K data direction register
PKDDR
8
H'FC22
PORT
16
4
Port H data register
PHDR
8
H'FC24
PORT
16
4
Port J data register
PJDR
8
H'FC25
PORT
16
4
Port K data register
PKDR
8
H'FC26
PORT
16
4
Port H register
PORTH
8
H'FC28
PORT
16
4
Port J register
PORTJ
8
H'FC29
PORT
16
4
Port K register
PORTK
8
H'FC2A
PORT
16
4
LCD Port control register
LPCR
8
H'FC30
LCD
16
4
LCD control register
LCR
8
H'FC31
LCD
16
4
LCD control register 2
LCR2
8
H'FC32
LCD
16
4
Module stop mode control
register_D
MSTPCRD
8
H'FC60
SYSTEM 8
4
PWM buffer transfer control
register
PWBTCR
8
H'FC66
PWM
common
8
4
Serial mode register_4
SMR_4
8
H'FDD8
SCI_4
8
2
Bit rate register_4
BRR_4
8
H'FDD9
SCI_4
8
2
Serial control register_4
SCR_4
8
H'FDDA
SCI_4
8
2
Transmit data register_4
TDR_4
8
H'FDDB
SCI_4
8
2
Serial status register_4
SSR_4
8
H'FDDC
SCI_4
8
2
Receive data register_4
RDR_4
8
H'FDDD
SCI_4
8
2
Smart card mode register_4
SCMR_4
8
H'FDDE
SCI_4
8
2
Standby control register
SBYCR
8
H'FDE4
SYSTEM 8
2
System control register_4
SYSCR
8
H'FDE5
SYSTEM 8
2
System clock control register
SCKCR
8
H'FDE6
SYSTEM 8
2
Rev. 2.00 Dec. 05, 2005 Page 611 of 724
REJ09B0200-0200
Section 22 List of Registers
Number of
Data
Access
Bus
Width States
Register Name
Number
Abbreviation of Bits Address*
Module
Mode control register
MDCR
8
H'FDE7
SYSTEM 8
2
Module stop control register A
MSTPCRA
8
H'FDE8
SYSTEM 8
2
Module stop control register B
MSTPCRB
8
H'FDE9
SYSTEM 8
2
Module stop control register C
MSTPCRC
8
H'FDEA
SYSTEM 8
2
Pin function control register
PFCR
8
H'FDEB
BSC
8
2
Low power control register
LPWRCR
8
H'FDEC
SYSTEM 8
2
Break address register A
BARA
32
H'FE00
PBC
32
2
Break address register B
BARB
32
H'FE04
PBC
32
2
Break control register A
BCRA
8
H'FE08
PBC
8
2
Break control register B
BCRB
8
H'FE09
PBC
8
2
IRQ sense control register H
ISCRH
8
H'FE12
INT
8
2
IRQ sense control register L
ISCRL
8
H'FE13
INT
8
2
IRQ enable register
IER
8
H'FE14
INT
8
2
IRQ status register
ISR
8
H'FE15
INT
8
2
DTC enable register A
DTCERA
8
H'FE16
DTC
8
2
DTC enable register B
DTCERB
8
H'FE17
DTC
8
2
DTC enable register C
DTCERC
8
H'FE18
DTC
8
2
DTC enable register D
DTCERD
8
H'FE19
DTC
8
2
DTC enable register E
DTCERE
8
H'FE1A
DTC
8
2
DTC enable register F
DTCERF
8
H'FE1B
DTC
8
2
DTC enable register G
DTCERG
8
H'FE1C
DTC
8
2
DTC enable register I
DTCERI
8
H'FE1E
DTC
8
2
DTC vector register
DTVECR
8
H'FE1F
DTC
8
2
PPG output control register
PCR
8
H'FE26
PPG
8
2
PPG output mode register
PMR
8
H'FE27
PPG
8
2
Next data enable register H
NDERH
8
H'FE28
PPG
8
2
Next data enable register L
NDERL
8
H'FE29
PPG
8
2
Output data register H
PODRH
8
H'FE2A
PPG
8
2
Output data register L
PODRL
8
H'FE2B
PPG
8
2
Next data register H
NDRH
8
H'FE2C
PPG
8
2
Rev. 2.00 Dec. 05, 2005 Page 612 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Next data register L
NDRL
8
H'FE2D
PPG
8
2
Next data register H
NDRH
8
H'FE2E
PPG
8
2
Next data register L
NDRL
8
H'FE2F
PPG
8
2
Port 1 data direction register
P1DDR
8
H'FE30
PORT
8
2
Port 2 data direction register
P2DDR
8
H'FE31
PORT
8
2
Port 3 data direction register
P3DDR
8
H'FE32
PORT
8
2
Port 5 data direction register
P5DDR
8
H'FE34
PORT
8
2
Port A data direction register
PADDR
8
H'FE39
PORT
8
2
Port B data direction register
PBDDR
8
H'FE3A
PORT
8
2
Port C data direction register
PCDDR
8
H'FE3B
PORT
8
2
Port D data direction register
PDDDR
8
H'FE3C
PORT
8
2
Port E data direction register
PEDDR
8
H'FE3D
PORT
8
2
Port F data direction register
PFDDR
8
H'FE3E
PORT
8
2
Port A pull-up MOS control
register
PAPCR
8
H'FE40
PORT
8
2
Port B pull-up MOS control
register
PBPCR
8
H'FE41
PORT
8
2
Port C pull-up MOS control
register
PCPCR
8
H'FE42
PORT
8
2
Port D pull-up MOS control
register
PDPCR
8
H'FE43
PORT
8
2
Port E pull-up MOS control
register
PEPCR
8
H'FE44
PORT
8
2
Port 3 open-drain control register P3ODR
8
H'FE46
PORT
8
2
Port A open-drain control register PAODR
8
H'FE47
PORT
8
2
Port B open-drain control register PBODR
8
H'FE48
PORT
8
2
Port C open-drain control register PCODR
8
H'FE49
PORT
8
2
Timer control register_3
TCR_3
8
H'FE80
TPU_3
16
2
Timer mode register_3
TMDR_3
8
H'FE81
TPU_3
16
2
Timer I/O control register H_3
TIORH_3
8
H'FE82
TPU_3
16
2
Timer I/O control register L_3
TIORL_3
8
H'FE83
TPU_3
16
2
Rev. 2.00 Dec. 05, 2005 Page 613 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Timer interrupt enable register_3
TIER_3
8
H'FE84
TPU_3
16
2
Timer status register_3
TSR_3
8
H'FE85
TPU_3
16
2
Timer counter H_3
TCNTH_3
8
H'FE86
TPU_3
16
2
Timer counter L_3
TCNTL_3
8
H'FE87
TPU_3
16
2
Timer general register AH_3
TGRAH_3
8
H'FE88
TPU_3
16
2
Timer general register AL_3
TGRAL_3
8
H'FE89
TPU_3
16
2
Timer general register BH_3
TGRBH_3
8
H'FE8A
TPU_3
16
2
Timer general register BL_3
TGRBL_3
8
H'FE8B
TPU_3
16
2
Timer general register CH_3
TGRCH_3
8
H'FE8C
TPU_3
16
2
Timer general register CL_3
TGRCL_3
8
H'FE8D
TPU_3
16
2
Timer general register DH_3
TGRDH_3
8
H'FE8E
TPU_3
16
2
Timer general register DL_3
TGRDL_3
8
H'FE8F
TPU_3
16
2
Timer control register_4
TCR_4
8
H'FE90
TPU_4
16
2
Timer mode register_4
TMDR_4
8
H'FE91
TPU_4
16
2
Timer I/O control register _4
TIOR_4
8
H'FE92
TPU_4
16
2
Timer interrupt enable register_4
TIER_4
8
H'FE94
TPU_4
16
2
Timer status register_4
TSR_4
8
H'FE95
TPU_4
16
2
Timer counter H_4
TCNTH_4
8
H'FE96
TPU_4
16
2
Timer counter L_4
TCNTL_4
8
H'FE97
TPU_4
16
2
Timer general register AH_4
TGRAH_4
8
H'FE98
TPU_4
16
2
Timer general register AL_4
TGRAL_4
8
H'FE99
TPU_4
16
2
Timer general register BH_4
TGRBH_4
8
H'FE9A
TPU_4
16
2
Timer general register BL_4
TGRBL_4
8
H'FE9B
TPU_4
16
2
Timer control register_5
TCR_5
8
H'FEA0
TPU_5
16
2
Timer mode register_5
TMDR_5
8
H'FEA1
TPU_5
16
2
Timer I/O control register _5
TIOR_5
8
H'FEA2
TPU_5
16
2
Timer interrupt enable register_5
TIER_5
8
H'FEA4
TPU_5
16
2
Timer status register_5
TSR_5
8
H'FEA5
TPU_5
16
2
Timer counter H_5
TCNTH_5
8
H'FEA6
TPU_5
16
2
Timer counter L_5
TCNTL_5
8
H'FEA7
TPU_5
16
2
Rev. 2.00 Dec. 05, 2005 Page 614 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Timer general register AH_5
TGRAH_5
8
H'FEA8
TPU_5
16
2
Timer general register AL_5
TGRAL_5
8
H'FEA9
TPU_5
16
2
Timer general register BH_5
TGRBH_5
8
H'FEAA
TPU_5
16
2
Timer general register BL_5
TGRBL_5
8
H'FEAB
TPU_5
16
2
Timer start register
TSTR
8
H'FEB0
TPU
common
16
2
Timer synchro register
TSYR
8
H'FEB1
TPU
common
16
2
Interrupt priority register A
IPRA
8
H'FEC0
INT
8
2
Interrupt priority register B
IPRB
8
H'FEC1
INT
8
2
Interrupt priority register C
IPRC
8
H'FEC2
INT
8
2
Interrupt priority register D
IPRD
8
H'FEC3
INT
8
2
Interrupt priority register E
IPRE
8
H'FEC4
INT
8
2
Interrupt priority register F
IPRF
8
H'FEC5
INT
8
2
Interrupt priority register G
IPRG
8
H'FEC6
INT
8
2
Interrupt priority register H
IPRH
8
H'FEC7
INT
8
2
Interrupt priority register J
IPRJ
8
H'FEC9
INT
8
2
Interrupt priority register K
IPRK
8
H'FECA
INT
8
2
Interrupt priority register M
IPRM
8
H'FECC
INT
8
2
Interrupt priority register O
IPRO
8
H'FECE
INT
8
2
Bus width control register
ABWCR
8
H'FED0
BSC
8
2
Access state control register
ASTCR
8
H'FED1
BSC
8
2
Wait control register H
WCRH
8
H'FED2
BSC
8
2
Wait control register L
WCRL
8
H'FED3
BSC
8
2
Bus control register H
BCRH
8
H'FED4
BSC
8
2
Bus control register L
BCRL
8
H'FED5
BSC
8
2
RAM emulation register
RAMER
8
H'FEDB
FLASH
8
(F-ZTAT)
2
Port 1 data direction register
P1DR
8
H'FF00
PORT
8
2
Port 2 data direction register
P2DR
8
H'FF01
PORT
8
2
Port 3 data direction register
P3DR
8
H'FF02
PORT
8
2
Rev. 2.00 Dec. 05, 2005 Page 615 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Port 5 data direction register
P5DR
8
H'FF04
PORT
8
2
Port A data direction register
PADR
8
H'FF09
PORT
8
2
Port B data direction register
PBDR
8
H'FF0A
PORT
8
2
Port C data direction register
PCDR
8
H'FF0B
PORT
8
2
Port D data direction register
PDDR
8
H'FF0C
PORT
8
2
Port E data direction register
PEDR
8
H'FF0D
PORT
8
2
Port F data direction register
PFDR
8
H'FF0E
PORT
8
2
Timer control register_0
TCR_0
8
H'FF10
TPU_0
16
2
Timer mode register_0
TMDR_0
8
H'FF11
TPU_0
16
2
Timer I/O control register H_0
TIORH_0
8
H'FF12
TPU_0
16
2
Timer I/O control register L_0
TIORL_0
8
H'FF13
TPU_0
16
2
Timer interrupt enable register_0
TIER_0
8
H'FF14
TPU_0
16
2
Timer status register_0
TSR_0
8
H'FF15
TPU_0
16
2
Timer counter H_0
TCNTH_0
8
H'FF16
TPU_0
16
2
Timer counter L_0
TCNTL_0
8
H'FF17
TPU_0
16
2
Timer general register AH_0
TGRAH_0
8
H'FF18
TPU_0
16
2
Timer general register AL_0
TGRAL_0
8
H'FF19
TPU_0
16
2
Timer general register BH_0
TGRBH_0
8
H'FF1A
TPU_0
16
2
Timer general register BL_0
TGRBL_0
8
H'FF1B
TPU_0
16
2
Timer general register CH_0
TGRCH_0
8
H'FF1C
TPU_0
16
2
Timer general register CL_0
TGRCL_0
8
H'FF1D
TPU_0
16
2
Timer general register DH_0
TGRDH_0
8
H'FF1E
TPU_0
16
2
Timer general register DL_0
TGRDL_0
8
H'FF1F
TPU_0
16
2
Timer control register_1
TCR_1
8
H'FF20
TPU_1
16
2
Timer mode register_1
TMDR_1
8
H'FF21
TPU_1
16
2
Timer I/O control register _1
TIOR_1
8
H'FF22
TPU_1
16
2
Timer interrupt enable register_1
TIER_1
8
H'FF24
TPU_1
16
2
Timer status register_1
TSR_1
8
H'FF25
TPU_1
16
2
Timer counter H_1
TCNTH_1
8
H'FF26
TPU_1
16
2
Timer counter L_1
TCNTL_1
8
H'FF27
TPU_1
16
2
Rev. 2.00 Dec. 05, 2005 Page 616 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Timer general register AH_1
TGRAH_1
8
H'FF28
TPU_1
16
2
Timer general register AL_1
TGRAL_1
8
H'FF29
TPU_1
16
2
Timer general register BH_1
TGRBH_1
8
H'FF2A
TPU_1
16
2
Timer general register BL_1
TGRBL_1
8
H'FF2B
TPU_1
16
2
Timer control register_2
TCR_2
8
H'FF30
TPU_2
16
2
Timer mode register_2
TMDR_2
8
H'FF31
TPU_2
16
2
Timer I/O control register_2
TIOR_2
8
H'FF32
TPU_2
16
2
Timer interrupt enable register_2
TIER_2
8
H'FF34
TPU_2
16
2
Timer status register_2
TSR_2
8
H'FF35
TPU_2
16
2
Timer counter H_2
TCNTH_2
8
H'FF36
TPU_2
16
2
Timer counter L_2
TCNTL_2
8
H'FF37
TPU_2
16
2
Timer general register AH_2
TGRAH_2
8
H'FF38
TPU_2
16
2
Timer general register AL_2
TGRAL_2
8
H'FF39
TPU_2
16
2
Timer general register BH_2
TGRBH_2
8
H'FF3A
TPU_2
16
2
Timer general register BL_2
TGRBL_2
8
H'FF3B
TPU_2
16
2
Timer control/status register_0
TCSR_0
8
H'FF74
WDT_0
16
2
Timer counter_0
TCNT_0
8
H'FF75
WDT_0
16
2
Reset control/status register
RSTCSR
8
H'FF77
WDT_0
16
2
Serial mode register_0
SMR_0
8
H'FF78
SCI_0
8
2
Bit rate register_0
BRR_0
8
H'FF79
SCI_0
8
2
Serial control register_0
SCR_0
8
H'FF7A
SCI_0
8
2
Transmit data register_0
TDR_0
8
H'FF7B
SCI_0
8
2
Serial status register_0
SSR_0
8
H'FF7C
SCI_0
8
2
Receive data register_0
RDR_0
8
H'FF7D
SCI_0
8
2
Smart card mode register_0
SCMR_0
8
H'FF7E
SCI_0
8
2
Serial mode register_1
SMR_1
8
H'FF80
SCI_1
8
2
Bit rate register_1
BRR_1
8
H'FF81
SCI_1
8
2
Serial control register_1
SCR_1
8
H'FF82
SCI_1
8
2
Transmit data register_1
TDR_1
8
H'FF83
SCI_1
8
2
Serial status register_1
SSR_1
8
H'FF84
SCI_1
8
2
Rev. 2.00 Dec. 05, 2005 Page 617 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Receive data register_1
RDR_1
8
H'FF85
SCI_1
8
2
Smart card mode register_1
SCMR_1
8
H'FF86
SCI_1
8
2
Serial mode register_2
SMR_2
8
H'FF88
SCI_2
8
2
Bit rate register_2
BRR_2
8
H'FF89
SCI_2
8
2
Serial control register_2
SCR_2
8
H'FF8A
SCI_2
8
2
Transmit data register_2
TDR_2
8
H'FF8B
SCI_2
8
2
Serial status register_2
SSR_2
8
H'FF8C
SCI_2
8
2
Receive data register_2
RDR_2
8
H'FF8D
SCI_2
8
2
Smart card mode register_2
SCMR_2
8
H'FF8E
SCI_2
8
2
A/D data register AH
ADDR AH
8
H'FF90
A/D
8
2
A/D data register AL
ADDRAL
8
H'FF91
A/D
8
2
A/D data register BH
ADDRBH
8
H'FF92
A/D
8
2
A/D data register BL
ADDRBL
8
H'FF93
A/D
8
2
A/D data register CH
ADDRCH
8
H'FF94
A/D
8
2
A/D data register CL
ADDRCL
8
H'FF95
A/D
8
2
A/D data register DH
ADDRDH
8
H'FF96
A/D
8
2
A/D data register DL
ADDRDL
8
H'FF97
A/D
8
2
A/D control/status register
ADCSR
8
H'FF98
A/D
8
2
A/D control register
ADCR
8
H'FF99
A/D
8
2
Timer control/status register_1
TCSR_1
8
H'FFA2
WDT_1
16
2
Timer counter_1
TCNT_1
8
H'FFA3
WDT_1
16
2
Flash memory control register 1
FLMCR1
8
H'FFA8
FLASH
8
(F-ZTAT)
2
Flash memory control register 2
FLMCR2
8
H'FFA9
FLASH
8
(F-ZTAT)
2
Erase block register 1
EBR1
8
H'FFAA
FLASH
8
(F-ZTAT)
2
Erase block register 2
EBR2
8
H'FFAB
FLASH
8
(F-ZTAT)
2
Flash memory power control
register
FLPWCR
8
H'FFAC
FLASH
8
(F-ZTAT)
2
Rev. 2.00 Dec. 05, 2005 Page 618 of 724
REJ09B0200-0200
Section 22 List of Registers
Register Name
Number
Abbreviation of Bits Address*
Module
Number of
Data
Access
Bus
Width States
Port 1 register
PORT1
8
H'FFB0
PORT
8
2
Port 2 register
PORT2
8
H'FFB1
PORT
8
2
Port 3 register
PORT3
8
H'FFB2
PORT
8
2
Port 4 register
PORT4
8
H'FFB3
PORT
8
2
Port 5 register
PORT5
8
H'FFB4
PORT
8
2
Port 9 register
PORT9
8
H'FFB8
PORT
8
2
Port A register
PORTA
8
H'FFB9
PORT
8
2
Port B register
PORTB
8
H'FFBA
PORT
8
2
Port C register
PORTC
8
H'FFBB
PORT
8
2
Port D register
PORTD
8
H'FFBC
PORT
8
2
Port F register
PORTF
8
H'FFBE
PORT
8
2
Note:
*
The lower 16 bits are indicated.
Rev. 2.00 Dec. 05, 2005 Page 619 of 724
REJ09B0200-0200
Section 22 List of Registers
22.2
Register Bits
Register addresses and bit names of the on-chip peripheral modules are described below.
Each line covers eight bits, and 16-bit registers are shown as 2 lines, respectively.
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MCR_0
MCR7

MCR5


MCR2
MCR1
MCR0
HCAN_0
GSR_0




GSR3
GSR2
GSR1
GSR0
BCR_0
BCR7
BCR6
BCR5
BCR4
BCR3
BCR2
BCR1
BCR0
BCR15
BCR14
BCR13
BCR12
BCR11
BCR10
BCR9
BCR8
MBCR7
MBCR6
MBCR5
MBCR4
MBCR3
MBCR2
MBCR1

MBCR15
MBCR14
MBCR13
MBCR12
MBCR11
MBCR10
MBCR9
MBCR8
MBCR_0
TXPR7
TXPR6
TXPR5
TXPR4
TXPR3
TXPR2
TXPR1

TXPR15
TXPR14
TXPR13
TXPR12
TXPR11
TXPR10
TXPR9
TXPR8
TXCR7
TXCR6
TXCR5
TXCR4
TXCR3
TXCR2
TXCR1

TXCR15
TXCR14
TXCR13
TXCR12
TXCR11
TXCR10
TXCR9
TXCR8
TXACK7
TXACK6
TXACK5
TXACK4
TXACK3
TXACK2
TXACK1

TXACK15
TXACK14
TXACK13
TXACK12
TXACK11
TXACK10
TXACK9
TXACK8
ABACK7
ABACK6
ABACK5
ABACK4
ABACK3
ABACK2
ABACK1

ABACK15 ABACK14
ABACK13
ABACK12
ABACK11
ABACK10
ABACK9
ABACK8
RXPR7
RXPR6
RXPR5
RXPR4
RXPR3
RXPR2
RXPR1
RXPR0
RXPR15
RXPR14
RXPR13
RXPR12
RXPR11
RXPR10
RXPR9
RXPR8
RFPR7
RFPR6
RFPR5
RFPR4
RFPR3
RFPR2
RFPR1
RFPR0
RFPR15
RFPR14
RFPR13
RFPR12
RFPR11
RFPR10
RFPR9
RFPR8
IRR7
IRR6
IRR5
IRR4
IRR3
IRR2
IRR1
IRR0



IRR12


IRR9
IRR8
MBIMR7
MBIMR6
MBIMR5
MBIMR4
MBIMR3
MBIMR2
MBIMR1
MBIMR0
MBIMR15
MBIMR14
MBIMR13
MBIMR12
MBIMR11
MBIMR10
MBIMR9
MBIMR8
IMR7
IMR6
IMR5
IMR4
IMR3
IMR2
IMR1




IMR12


IMR9
IMR8
REC_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TEC_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TXPR_0
TXCR_0
TXACK_0
ABACK_0
RXPR_0
RFPR_0
IRR_0
MBIMR_0
IMR_0
Rev. 2.00 Dec. 05, 2005 Page 620 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
UMSR_0
UMSR7
UMSR6
UMSR5
UMSR4
UMSR3
UMSR2
UMSR1
UMSR0
HCAN_0
UMSR15
UMSR14
UMSR13
UMSR12
UMSR11
UMSR10
UMSR9
UMSR8
LAFML7
LAFML6
LAFML5
LAFML4
LAFML3
LAFML2
LAFML1
LAFML0
LAFML15
LAFML14
LAFML13
LAFML12
LAFML11
LAFML10
LAFML9
LAFML8
LAFMH7
LAFMH6
LAFMH5



LAFMH1
LAFMH0
LAFMH15
LAFMH14
LAFMH13
LAFMH12
LAFMH11
LAFMH10
LAFMH9
LAFMH8
MC0[1]




DLC3
DLC2
DLC1
DLC0
MC0[2]








MC0[3]








MC0[4]








MC0[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC0[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
LAFML_0
LAFMH_0
MC0[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC0[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC1[1]




DLC3
DLC2
DLC1
DLC0
MC1[2]








MC1[3]








MC1[4]








MC1[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC1[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC1[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC1[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC2[1]




DLC3
DLC2
DLC1
DLC0
MC2[2]








MC2[3]








MC2[4]








MC2[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC2[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC2[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC2[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
Rev. 2.00 Dec. 05, 2005 Page 621 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
HCAN_0
MC3[1]




DLC3
DLC2
DLC1
DLC0
MC3[2]








MC3[3]








MC3[4]








MC3[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC3[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC3[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC3[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC4[1]




DLC3
DLC2
DLC1
DLC0
MC4[2]








MC4[3]








MC4[4]








MC4[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC4[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC4[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC4[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC5[1]




DLC3
DLC2
DLC1
DLC0
MC5[2]








MC5[3]








MC5[4]








MC5[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC5[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC5[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC5[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC6[1]




DLC3
DLC2
DLC1
DLC0
MC6[2]








MC6[3]








MC6[4]








MC6[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC6[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC6[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
Rev. 2.00 Dec. 05, 2005 Page 622 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MC6[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
HCAN_0
MC7[1]




DLC3
DLC2
DLC1
DLC0
MC7[2]








MC7[3]








MC7[4]








MC7[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC7[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC7[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC7[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC8[1]




DLC3
DLC2
DLC1
DLC0
MC8[2]








MC8[3]








MC8[4]








MC8[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC8[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC8[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC8[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC9[1]




DLC3
DLC2
DLC1
DLC0
MC9[2]








MC9[3]








MC9[4]








MC9[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC9[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC9[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC9[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC10[1]




DLC3
DLC2
DLC1
DLC0
MC10[2]








MC10[3]








MC10[4]








MC10[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC10[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
Rev. 2.00 Dec. 05, 2005 Page 623 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MC10[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
HCAN_0
MC10[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC11[1]




DLC3
DLC2
DLC1
DLC0
MC11[2]








MC11[3]








MC11[4]








MC11[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC11[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC11[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC11[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC12[1]




DLC3
DLC2
DLC1
DLC0
MC12[2]








MC12[3]








MC12[4]








MC12[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC12[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC12[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC12[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC13[1]




DLC3
DLC2
DLC1
DLC0
MC13[2]








MC13[3]








MC13[4]








MC13[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC13[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC13[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC13[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC14[1]




DLC3
DLC2
DLC1
DLC0
MC14[2]








MC14[3]








MC14[4]








MC14[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
Rev. 2.00 Dec. 05, 2005 Page 624 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MC14[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
HCAN_0
MC14[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC14[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC15[1]




DLC3
DLC2
DLC1
DLC0
MC15[2]








MC15[3]








MC15[4]








MC15[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC15[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC15[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC15[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MD0[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 2.00 Dec. 05, 2005 Page 625 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD2[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HCAN_0
MD2[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 2.00 Dec. 05, 2005 Page 626 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD6[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HCAN_0
MD6[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 2.00 Dec. 05, 2005 Page 627 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD10[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HCAN_0
MD10[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 2.00 Dec. 05, 2005 Page 628 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD14[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HCAN_0
MD14[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HCANMON0
RxDIE
TxSTP




TxD
RxD
MCR_1
MCR7

MCR5


MCR2
MCR1
MCR0
GSR_1




GSR3
GSR2
GSR1
GSR0
BCR_1
BCR7
BCR6
BCR5
BCR4
BCR3
BCR2
BCR1
BCR0
BCR15
BCR14
BCR13
BCR12
BCR11
BCR10
BCR9
BCR8
MBCR_1
TXPR_1
TXCR_1
TXACK_1
ABACK_1
MBCR7
MBCR6
MBCR5
MBCR4
MBCR3
MBCR2
MBCR1

MBCR15
MBCR14
MBCR13
MBCR12
MBCR11
MBCR10
MBCR9
MBCR8
TXPR7
TXPR6
TXPR5
TXPR4
TXPR3
TXPR2
TXPR1

TXPR15
TXPR14
TXPR13
TXPR12
TXPR11
TXPR10
TXPR9
TXPR8
TXCR7
TXCR6
TXCR5
TXCR4
TXCR3
TXCR2
TXCR1

TXCR15
TXCR14
TXCR13
TXCR12
TXCR11
TXCR10
TXCR9
TXCR8
TXACK7
TXACK6
TXACK5
TXACK4
TXACK3
TXACK2
TXACK1

TXACK15
TXACK14
TXACK13
TXACK12
TXACK11
TXACK10
TXACK9
TXACK8
ABACK7
ABACK6
ABACK5
ABACK4
ABACK3
ABACK2
ABACK1

ABACK13
ABACK12
ABACK11
ABACK10
ABACK9
ABACK8
ABACK15 ABACK14
HCAN_1
Rev. 2.00 Dec. 05, 2005 Page 629 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
RXPR_1
RXPR7
RXPR6
RXPR5
RXPR4
RXPR3
RXPR2
RXPR1
RXPR0
HCAN_1
RXPR15
RXPR14
RXPR13
RXPR12
RXPR11
RXPR10
RXPR9
RXPR8
RFPR7
RFPR6
RFPR5
RFPR4
RFPR3
RFPR2
RFPR1
RFPR0
RFPR15
RFPR14
RFPR13
RFPR12
RFPR11
RFPR10
RFPR9
RFPR8
RFPR_1
IRR_1
IRR7
IRR6
IRR5
IRR4
IRR3
IRR2
IRR1
IRR0



IRR12


IRR9
IRR8
MBIMR7
MBIMR6
MBIMR5
MBIMR4
MBIMR3
MBIMR2
MBIMR1
MBIMR0
MBIMR15
MBIMR14
MBIMR13
MBIMR12
MBIMR11
MBIMR10
MBIMR9
MBIMR8
IMR7
IMR6
IMR5
IMR4
IMR3
IMR2
IMR1




IMR12


IMR9
IMR8
REC_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TEC_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MBIMR_1
IMR_1
UMSR_1
UMSR7
UMSR6
UMSR5
UMSR4
UMSR3
UMSR2
UMSR1
UMSR0
UMSR15
UMSR14
UMSR13
UMSR12
UMSR11
UMSR10
UMSR9
UMSR8
LAFML7
LAFML6
LAFML5
LAFML4
LAFML3
LAFML2
LAFML1
LAFML0
LAFML15
LAFML14
LAFML13
LAFML12
LAFML11
LAFML10
LAFML9
LAFML8
LAFMH7
LAFMH6
LAFMH5



LAFMH1
LAFMH0
LAFMH15
LAFMH14
LAFMH13
LAFMH12
LAFMH11
LAFMH10
LAFMH9
LAFMH8
MC0[1]




DLC3
DLC2
DLC1
DLC0
MC0[2]








MC0[3]








MC0[4]








MC0[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC0[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC0[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC0[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC1[1]




DLC3
DLC2
DLC1
DLC0
MC1[2]








MC1[3]








MC1[4]








MC1[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
LAFML_1
LAFMH_1
Rev. 2.00 Dec. 05, 2005 Page 630 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MC1[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
HCAN_1
MC1[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC1[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC2[1]




DLC3
DLC2
DLC1
DLC0
MC2[2]








MC2[3]








MC2[4]








MC2[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC2[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC2[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC2[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC3[1]




DLC3
DLC2
DLC1
DLC0
MC3[2]








MC3[3]








MC3[4]








MC3[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC3[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC3[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC3[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC4[1]




DLC3
DLC2
DLC1
DLC0
MC4[2]








MC4[3]








MC4[4]








MC4[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC4[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC4[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC4[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC5[1]




DLC3
DLC2
DLC1
DLC0
MC5[2]








MC5[3]








MC5[4]








Rev. 2.00 Dec. 05, 2005 Page 631 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MC5[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
HCAN_1
MC5[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC5[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC5[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC6[1]




DLC3
DLC2
DLC1
DLC0
MC6[2]








MC6[3]








MC6[4]








MC6[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC6[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC6[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC6[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC7[1]




DLC3
DLC2
DLC1
DLC0
MC7[2]








MC7[3]








MC7[4]








MC7[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC7[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC7[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC7[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC8[1]




DLC3
DLC2
DLC1
DLC0
MC8[2]








MC8[3]








MC8[4]








MC8[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC8[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC8[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC8[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC9[1]




DLC3
DLC2
DLC1
DLC0
MC9[2]








MC9[3]








Rev. 2.00 Dec. 05, 2005 Page 632 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
HCAN_1
MC9[4]








MC9[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC9[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC9[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC9[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC10[1]




DLC3
DLC2
DLC1
DLC0
MC10[2]








MC10[3]








MC10[4]








MC10[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC10[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC10[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC10[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC11[1]




DLC3
DLC2
DLC1
DLC0
MC11[2]








MC11[3]








MC11[4]








MC11[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC11[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC11[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC11[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC12[1]




DLC3
DLC2
DLC1
DLC0
MC12[2]








MC12[3]








MC12[4]








MC12[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC12[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC12[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC12[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC13[1]




DLC3
DLC2
DLC1
DLC0
MC13[2]








Rev. 2.00 Dec. 05, 2005 Page 633 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
HCAN_1
MC13[3]








MC13[4]








MC13[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC13[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC13[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC13[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC14[1]




DLC3
DLC2
DLC1
DLC0
MC14[2]








MC14[3]








MC14[4]








MC14[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC14[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC14[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC14[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MC15[1]




DLC3
DLC2
DLC1
DLC0
MC15[2]








MC15[3]








MC15[4]








MC15[5]
ID-20
ID-19
ID-18
RTR
IDE

ID-17
ID-16
MC15[6]
ID-28
ID-27
ID-26
ID-25
ID-24
ID-23
ID-22
ID-21
MC15[7]
ID-7
ID-6
ID-5
ID-4
ID-3
ID-2
ID-1
ID-0
MC15[8]
ID-15
ID-14
ID-13
ID-12
ID-11
ID-10
ID-9
ID-8
MD0[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD0[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 2.00 Dec. 05, 2005 Page 634 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD1[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HCAN_1
MD1[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD2[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD3[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD4[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 2.00 Dec. 05, 2005 Page 635 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD5[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HCAN_1
MD5[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD5[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD6[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD8[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 2.00 Dec. 05, 2005 Page 636 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD8[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HCAN_1
MD8[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD9[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD10[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD11[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 2.00 Dec. 05, 2005 Page 637 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD12[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HCAN_1
MD12[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD12[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD13[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD14[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[1]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[2]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[3]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[4]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[5]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[6]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[7]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD15[8]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TxSTP
PKFE



TxD
RxD
HCANMON_1 RxDIE
PWCR_1


IE
CMF
CST
CKS2
CKS1
CKS0
PWOCR_1
OE1H
OE1G
OE1F
OE1E
OE1D
OE1C
OE1B
OE1A
PWPR_1
OPS1H
OPS1G
OPS1F
OPS1E
OPS1D
OPS1C
OPS1B
OPS1A
Rev. 2.00 Dec. 05, 2005 Page 638 of 724
REJ09B0200-0200
PWM_1
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module






Bit9
Bit8
PWM_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0



OTS


DT9
DT8
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0



OTS


DT9
DT8
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0



OTS


DT9
DT8
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0



OTS


DT9
DT8
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0
PWCR_2


IE
CMF
CST
CKS2
CKS1
CKS0
PWOCR_2
OE2H
OE2G
OE2F
OE2E
OE2D
OE2C
OE2B
OE2A
PWCYR_1
PWBFR_1A
PWBFR_1C
PWBFR_1E
PWBFR_1G
PWPR_2
OPS2H
OPS2G
OPS2F
OPS2E
OPS2D
OPS2C
OPS2B
OPS2A
PWCYR_2






Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0



TDS


DT9
DT8
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0



TDS


DT9
DT8
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0



TDS


DT9
DT8
PWBFR_2A
PWBFR_2C
PWBFR_2E
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0



TDS


DT9
DT8
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0
PHDDR
PH7DDR
PH6DDR
PH5DDR
PH4DDR
PH3DDR
PH2DDR
PH1DDR
PH0DDR
PJDDR
PJ7DDR
PJ6DDR
PJ5DDR
PJ4DDR
PJ3DDR
PJ2DDR
PJ1DDR
PJ0DDR
PKDDR
PK7DDR
PK6DDR






PHDR
PH7DR
PH6DR
PH5DR
PH4DR
PH3DR
PH2DR
PH1DR
PH0DR
PJDR
PJ7DR
PJ6DR
PJ5DR
PJ4DR
PJ3DR
PJ2DR
PJ1DR
PJ0DR
PKDR
PK7DR
PK6DR






PORTH
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PWBFR_2G
PWM_2
PORT
Rev. 2.00 Dec. 05, 2005 Page 639 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
PORTJ
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
PORT
PORTK
PK7
PK6






LPCR
DTS1
DTS0
CMX

SGS3
SGS2
SGS1
SGS0
LCR

PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
LCR2
LCDAB







MSTPCRD
MSTPD7
MSTPD6
MSTPD5
MSTPD4
MSTPD3
MSTPD2
MSTPD1
MSTPD0
PWBTCR
BTC2G
BTC2E
BTC2C
BTC2A
BTC2G
BTC1E
BTC1C
BTC1A
LCD
SYSTEM
PWM
common
SMR_4*
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
(GM)
(BLK)
(PE)
(O/E)
(BCP1)
(BCP0)
(CKS1)
(CKS0)
BRR_4
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCR_4
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR_4
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SSR_4*
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
(TDRE)
(RDRF)
(ORER)
(ERS)
(PER)
(TEND)
(MPB)
(MPBT)
RDR_4
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCMR_4




SDIR
SINV

SMIF
SBYCR
SSBY
STS2
STS1
STS0
OPE



SYSCR
MACS

INTM1
INTM0
NMIEG


RAME
SCKCR
PSTOP



STCS
SCK2
SCK1
SCK0
MDCR





MDS2
MDS1
MDS0
MSTPCRA
MSTPA7
MSTPA6
MSTPA5
MSTPA4
MSTPA3
MSTPA2
MSTPA1
MSTPA0
MSTPCRB
MSTPB7
MSTPB6
MSTPB5
MSTPB4
MSTPB3
MSTPB2
MSTPB1
MSTPB0
MSTPCRC
MSTPC7
MSTPC6
MSTPC5
MSTPC4
MSTPC3
MSTPC2
MSTPC1
MSTPC0
PFCR




AE3
AE2
AE1
AE0
BSC
LPWRCR
DTON
LSON
NESEL
SUBSTP
RFCUT

STC1
STC0
SYSTEM
BARA








PBC
Bit23
Bit22
Bit21
Bit20
Bit19
Bit18
Bit17
Bit16
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 2.00 Dec. 05, 2005 Page 640 of 724
REJ09B0200-0200
SCI_4
SYSTEM
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module








PBC
Bit23
Bit22
Bit21
Bit20
Bit19
Bit18
Bit17
Bit16
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
BCRA
CMFA
CDA
BAMA2
BAMA1
BAMA0
CSELA1
CSELA0
BIEA
BCRB
CMFB
CDB
BAMB2
BAMB1
BAMB0
CSELB1
CSELB0
BIEB
ISCRH




IRQ5SCB
IRQ5SCA
IRQ4SCB
IRQ4SCA
ISCRL
IRQ3SCB
IRQ3SCA
IRQ2SCB
IRQ2SCA
IRQ1SCB
IRQ1SCA
IRQ0SCB
IRQ0SCA
IER


IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
ISR


IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
DTCERA
DTCEA7
DTCEA6
DTCEA5
DTCEA4
DTCEA3
DTCEA2
DTCEA1
DTCEA0
DTCERB
DTCEB7
DTCEB6
DTCEB5
DTCEB4
DTCEB3
DTCEB2
DTCEB1
DTCEB0
DTCERC
DTCEC7
DTCEC6
DTCEC5
DTCEC4
DTCEC3
DTCEC2
DTCEC1
DTCEC0
DTCERD
DTCED7
DTCED6
DTCED5
DTCED4
DTCED3
DTCED2
DTCED1
DTCED0
DTCERE
DTCEE7
DTCEE6
DTCEE5
DTCEE4
DTCEE3
DTCEE2
DTCEE1
DTCEE0
DTCERF
DTCEF7
DTCEF6
DTCEF5
DTCEF4
DTCEF3
DTCEF2
DTCEF1
DTCEF0
DTCERG
DTCEG7
DTCEG6
DTCEG5
DTCEG4
DTCEG3
DTCEG2
DTCEG1
DTCEG0
DTCERI
DTCEI7
DTCEI6
DTCEI5
DTCEI4
DTCEI3
DTCEI2
DTCEI1
DTCEI0
DTVECR
SWDTE
DTVEC6
DTVEC5
DTVEC4
DTVEC3
DTVEC2
DTVEC1
DTVEC0
PCR
G3CMS1
G3CMS0
G2CMS1
G2CMS0
G1CMS1
G1CMS0
G0CMS1
G0CMS0
PMR
G3INV
G2INV
G1INV
G0INV
G3NOV
G2NOV
G1NOV
G0NOV
NDERH
NDER15
NDER14
NDER13
NDER12
NDER11
NDER10
NDER9
NDER8
NDERL
NDER7
NDER6
NDER5
NDER4
NDER3
NDER2
NDER1
NDER0
PODRH
POD15
POD14
POD13
POD12
POD11
POD10
POD9
POD8
PODRL
POD7
POD6
POD5
POD4
POD3
POD2
POD1
POD0
NDRH
NDR15
NDR14
NDR13
NDR12




NDRL
NDR7
NDR6
NDR5
NDR4




NDRH




NDR11
NDR10
NDR9
NDR8
NDRL




NDR3
NDR2
NDR1
NDR0
BARB
INT
DTC
PPG
Rev. 2.00 Dec. 05, 2005 Page 641 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
P1DDR
P17DDR
P16DDR
P15DDR
P14DDR
P13DDR
P12DDR
P11DDR
P10DDR
PORT
P2DDR
P27DDR
P26DDR
P25DDR
P24DDR
P23DDR
P22DDR
P21DDR
P20DDR
P3DDR
P37DDR
P36DDR
P35DDR
P34DDR
P33DDR
P32DDR
P31DDR
P30DDR
P5DDR





P52DDR
P51DDR
P50DDR
PADDR
PA7DDR
PA6DDR
PA5DDR
PA4DDR
PA3DDR
PA2DDR
PA1DDR
PA0DDR
PBDDR
PB7DDR
PB6DDR
PB5DDR
PB4DDR
PB3DDR
PB2DDR
PB1DDR
PB0DDR
PCDDR
PC7DDR
PC6DDR
PC5DDR
PC4DDR
PC3DDR
PC2DDR
PC1DDR
PC0DDR
PDDDR
PD7DDR
PD6DDR
PD5DDR
PD4DDR
PD3DDR
PD2DDR
PD1DDR
PD0DDR
PEDDR
PE7DDR
PE6DDR
PE5DDR
PE4DDR
PE3DDR
PE2DDR
PE1DDR
PE0DDR
PFDDR
PF7DDR
PF6DDR
PF5DDR
PF4DDR
PF3DDR
PF2DDR

PF0DDR
PAPCR
PA7PCR
PA6PCR
PA5PCR
PA4PCR
PA3PCR
PA2PCR
PA1PCR
PA0PCR
PBPCR
PB7PCR
PB6PCR
PB5PCR
PB4PCR
PB3PCR
PB2PCR
PB1PCR
PB0PCR
PCPCR
PC7PCR
PC6PCR
PC5PCR
PC4PCR
PC3PCR
PC2PCR
PC1PCR
PC0PCR
PDPCR
PD7PCR
PD6PCR
PD5PCR
PD4PCR
PD3PCR
PD2PCR
PD1PCR
PD0PCR
PEPCR
PE7PCR
PE6PCR
PE5PCR
PE4PCR
PE3PCR
PE2PCR
PE1PCR
PE0PCR
P3ODR
P37ODR
P36ODR
P35ODR
P34ODR
P33ODR
P32ODR
P31ODR
P30ODR
PAODR
PA7ODR
PA6ODR
PA5ODR
PA4ODR
PA3ODR
PA2ODR
PA1ODR
PA0ODR
PBODR
PB7ODR
PB6ODR
PB5ODR
PB4ODR
PB3ODR
PB2ODR
PB1ODR
PB0ODR
PCODR
PC7ODR
PC6ODR
PC5ODR
PC4ODR
PC3ODR
PC2ODR
PC1ODR
PC0ODR
TCR_3
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_3


BFB
BFA
MD3
MD2
MD1
MD0
TIORH_3
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIORL_3
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
TIER_3
TTGE


TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_3



TCFV
TGFD
TGFC
TGFB
TGFA
TCNTH_3
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TCNTL_3
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRAH_3
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRAL_3
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRBH_3
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRBL_3
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 2.00 Dec. 05, 2005 Page 642 of 724
REJ09B0200-0200
TPU_3
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TGRCH_3
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TPU_3
TGRCL_3
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRDH_3
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRDL_3
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCR_4

CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_4




MD3
MD2
MD1
MD0
TIOR_4
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_4
TTGE

TCIEU
TCIEV


TGIEB
TGIEA
TSR_4
TCFD

TCFU
TCFV


TGFB
TGFA
TCNTH_4
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TCNTL_4
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRAH_4
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRAL_4
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRBH_4
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRBL_4
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCR_5

CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_5




MD3
MD2
MD1
MD0
TIOR_5
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_5
TTGE

TCIEU
TCIEV


TGIEB
TGIEA
TSR_5
TCFD

TCFU
TCFV


TGFB
TGFA
TCNTH_5
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TCNTL_5
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRAH_5
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRAL_5
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRBH_5
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRBL_5
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TSTR


CST5
CST4
CST3
CST2
CST1
CST0
TSYR


SYNC5
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
IPRA

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
IPRB

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
IPRC

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
TPU_4
TPU_5
TPU
common
INT
Rev. 2.00 Dec. 05, 2005 Page 643 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
INT
IPRD

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
IPRE

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
IPRF

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
IPRG

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
IPRH

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
IPRJ

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
IPRK

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
IPRM

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
IPRO

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
ABWCR
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
ASTCR
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
WCRH
W71
W70
W61
W60
W51
W50
W41
W40
WCRL
W31
W30
W21
W20
W11
W10
W01
W00
BCRH
ICIS1
ICIS0
BRSTRM
BRSTS1
BRSTS0



BCRL






WDBE
WAITE
RAMER




RAMS
RAM2
RAM1
RAM0
BSC
FLASH
(F-ZTAT)
P1DR
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
P2DR
P27DR
P26DR
P25DR
P24DR
P23DR
P22DR
P21DR
P20DR
P3DR
P37DR
P36DR
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
P5DR





P52DR
P51DR
P50DR
PADR
PA7DR
PA6DR
PA5DR
PA4DR
PA3DR
PA2DR
PA1DR
PA0DR
PBDR
PB7DR
PB6DR
PB5DR
PB4DR
PB3DR
PB2DR
PB1DR
PB0DR
PCDR
PC7DR
PC6DR
PC5DR
PC4DR
PC3DR
PC2DR
PC1DR
PC0DR
PDDR
PD7DR
PD6DR
PD5DR
PD4DR
PD3DR
PD2DR
PD1DR
PD0DR
PEDR
PE7DR
PE6DR
PE5DR
PE4DR
PE3DR
PE2DR
PE1DR
PE0DR
PFDR
PF7DR
PF6DR
PF5DR
PF4DR
PF3DR
PF2DR

PF0DR
TCR_0
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_0


BFB
BFA
MD3
MD2
MD1
MD0
TIORH_0
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIORL_0
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
Rev. 2.00 Dec. 05, 2005 Page 644 of 724
REJ09B0200-0200
PORT
TPU_0
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TIER_0
TTGE


TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TPU_0
TSR_0



TCFV
TGFD
TGFC
TGFB
TGFA
TCNTH_0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TCNTL_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRAH_0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRAL_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRBH_0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRBL_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRCH_0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRCL_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRDH_0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRDL_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCR_1

CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_1




MD3
MD2
MD1
MD0
TIOR_1
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_1
TTGE

TCIEU
TCIEV


TGIEB
TGIEA
TSR_1
TCFD

TCFU
TCFV


TGFB
TGFA
TCNTH_1
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TCNTL_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRAH_1
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRAL_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRBH_1
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRBL_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCR_2

CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_2




MD3
MD2
MD1
MD0
TIOR_2
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_2
TTGE

TCIEU
TCIEV


TGIEB
TGIEA
TSR_2
TCFD

TCFU
TCFV


TGFB
TGFA
TCNTH_2
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TCNTL_2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRAH_2
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TPU_1
TPU_2
Rev. 2.00 Dec. 05, 2005 Page 645 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TGRAL_2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TPU_2
TGRBH_2
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TGRBL_2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCSR_0
OVF
WT/IT
TME


CKS2
CKS1
CKS0
TCNT_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RSTCSR
WOVF
RSTE
RSTS





SMR_0*
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
(GM)
(BLK)
(PE)
(O/E)
(BCP1)
(BCP0)
(CKS1)
(CKS0)
BRR_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCR_0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SSR_0*
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
(TDRE)
(RDRF)
(ORER)
(ERS)
(PER)
(TEND)
(MPB)
(MPBT)
RDR_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCMR_0




SDIR
SINV

SMIF
SMR_1*
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
(GM)
(BLK)
(PE)
(O/E)
(BCP1)
(BCP0)
(CKS1)
(CKS0)
BRR_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCR_1
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SSR_1*
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
(TDRE)
(RDRF)
(ORER)
(ERS)
(PER)
(TEND)
(MPB)
(MPBT)
RDR_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCMR_1




SDIR
SINV

SMIF
SMR_2*
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
(GM)
(BLK)
(PE)
(O/E)
(BCP1)
(BCP0)
(CKS1)
(CKS0)
BRR_2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCR_2
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR_2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SSR_2*
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
(TDRE)
(RDRF)
(ORER)
(ERS)
(PER)
(TEND)
(MPB)
(MPBT)
Rev. 2.00 Dec. 05, 2005 Page 646 of 724
REJ09B0200-0200
WDT_0
SCI_0
SCI_1
SCI_2
Section 22 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
RDR_2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCI_2
SCMR_2




SDIR
SINV

SMIF
ADDRAH
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
ADDRAL
AD1
AD0






A/D
ADDRBH
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
ADDRBL
AD1
AD0






ADDRCH
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
ADDRCL
AD1
AD0






ADDRDH
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
ADDRDL
AD1
AD0






ADCSR
ADF
ADIE
ADST
SCAN

CH2
CH1
CH0
ADCR
TRGS1
TRGS0


CKS1
CKS0


TCSR_1
OVF
WT/IT
TME
PSS
RST/NMI
CKS2
CKS1
CKS0
TCNT_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
FLMCR1
FWE
SWE
ESU
PSU
EV
PV
E
P
FLASH
FLMCR2
FLER







(F-ZTAT)
EBR1
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
EBR2




EB11
EB10
EB9
EB8
FLPWCR
PDWND







PORT1
P17
P16
P15
P14
P13
P12
P11
P10
PORT2
P27
P26
P25
P24
P23
P22
P21
P20
PORT3
P37
P36
P35
P34
P33
P32
P31
P30
PORT4
P47
P46
P45
P44
P43
P42
P41
P40
PORT5





P52
P51
P50
PORT9
P97
P96
P95
P94
P93
P92
P91
P90
PORTA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PORTB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PORTC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PORTD
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PORTF
PF7
PF6
PF5
PF4
PF3
PF2

PF1
Note:
*
WDT_1
PORT
Parts of the bit functions differ in normal mode and the smart card interface mode. The
bit function in smart card interface mode is enclosed in parentheses.
Rev. 2.00 Dec. 05, 2005 Page 647 of 724
REJ09B0200-0200
Section 22 List of Registers
22.3
Register States in Each Operating Mode
Register
Abbrevia-
High
Medium
speed
speed
Sleep
Stop
Initialized −
−
−
Initialized Initialized Initialized
Initialized
GSR_0
Initialized −
−
−
Initialized Initialized Initialized
BCR_0
Initialized −
−
−
MBCR_0
Initialized −
−
TXPR_0
Initialized −
TXCR_0
Initialized −
TXACK_0
tion
Reset
MCR_0
Module
Software Hardware
Standby
Module
Initialized
Initialized
HCAN_0
Initialized
Initialized
Initialized
Initialized Initialized Initialized
Initialized
Initialized
Initialized
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
ABACK_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
RXPR_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
RFPR_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
IRR_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
MBIMR_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
IMR_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
REC_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
TEC_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
UMSR_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
LAFML_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
LAFMH_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
MC0[1]
−
−
−
−
−
−
−
−
−
−
MC0[2]
−
−
−
−
−
−
−
−
−
−
MC0[3]
−
−
−
−
−
−
−
−
−
−
MC0[4]
−
−
−
−
−
−
−
−
−
−
MC0[5]
−
−
−
−
−
−
−
−
−
−
MC0[6]
−
−
−
−
−
−
−
−
−
−
MC0[7]
−
−
−
−
−
−
−
−
−
−
MC0[8]
−
−
−
−
−
−
−
−
−
−
MC1[1]
−
−
−
−
−
−
−
−
−
−
MC1[2]
−
−
−
−
−
−
−
−
−
−
Rev. 2.00 Dec. 05, 2005 Page 648 of 724
REJ09B0200-0200
Watch
Subactive Subsleep Standby
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MC1[3]
−
−
−
−
−
−
−
−
−
−
HCAN_0
MC1[4]
−
−
−
−
−
−
−
−
−
−
MC1[5]
−
−
−
−
−
−
−
−
−
−
MC1[6]
−
−
−
−
−
−
−
−
−
−
MC1[7]
−
−
−
−
−
−
−
−
−
−
MC1[8]
−
−
−
−
−
−
−
−
−
−
MC2[1]
−
−
−
−
−
−
−
−
−
−
MC2[2]
−
−
−
−
−
−
−
−
−
−
MC2[3]
−
−
−
−
−
−
−
−
−
−
MC2[4]
−
−
−
−
−
−
−
−
−
−
MC2[5]
−
−
−
−
−
−
−
−
−
−
MC2[6]
−
−
−
−
−
−
−
−
−
−
MC2[7]
−
−
−
−
−
−
−
−
−
−
MC2[8]
−
−
−
−
−
−
−
−
−
−
MC3[1]
−
−
−
−
−
−
−
−
−
−
MC3[2]
−
−
−
−
−
−
−
−
−
−
MC3[3]
−
−
−
−
−
−
−
−
−
−
MC3[4]
−
−
−
−
−
−
−
−
−
−
MC3[5]
−
−
−
−
−
−
−
−
−
−
MC3[6]
−
−
−
−
−
−
−
−
−
−
MC3[7]
−
−
−
−
−
−
−
−
−
−
MC3[8]
−
−
−
−
−
−
−
−
−
−
MC4[1]
−
−
−
−
−
−
−
−
−
−
MC4[2]
−
−
−
−
−
−
−
−
−
−
MC4[3]
−
−
−
−
−
−
−
−
−
−
MC4[4]
−
−
−
−
−
−
−
−
−
−
MC4[5]
−
−
−
−
−
−
−
−
−
−
MC4[6]
−
−
−
−
−
−
−
−
−
−
MC4[7]
−
−
−
−
−
−
−
−
−
−
MC4[8]
−
−
−
−
−
−
−
−
−
−
Software Hardware
Rev. 2.00 Dec. 05, 2005 Page 649 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MC5[1]
−
−
−
−
−
−
−
−
−
−
HCAN_0
MC5[2]
−
−
−
−
−
−
−
−
−
−
MC5[3]
−
−
−
−
−
−
−
−
−
−
MC5[4]
−
−
−
−
−
−
−
−
−
−
MC5[5]
−
−
−
−
−
−
−
−
−
−
MC5[6]
−
−
−
−
−
−
−
−
−
−
MC5[7]
−
−
−
−
−
−
−
−
−
−
MC5[8]
−
−
−
−
−
−
−
−
−
−
MC6[1]
−
−
−
−
−
−
−
−
−
−
MC6[2]
−
−
−
−
−
−
−
−
−
−
MC6[3]
−
−
−
−
−
−
−
−
−
−
MC6[4]
−
−
−
−
−
−
−
−
−
−
MC6[5]
−
−
−
−
−
−
−
−
−
−
MC6[6]
−
−
−
−
−
−
−
−
−
−
MC6[7]
−
−
−
−
−
−
−
−
−
−
MC6[8]
−
−
−
−
−
−
−
−
−
−
MC7[1]
−
−
−
−
−
−
−
−
−
−
MC7[2]
−
−
−
−
−
−
−
−
−
−
MC7[3]
−
−
−
−
−
−
−
−
−
−
MC7[4]
−
−
−
−
−
−
−
−
−
−
MC7[5]
−
−
−
−
−
−
−
−
−
−
MC7[6]
−
−
−
−
−
−
−
−
−
−
MC7[7]
−
−
−
−
−
−
−
−
−
−
MC7[8]
−
−
−
−
−
−
−
−
−
−
MC8[1]
−
−
−
−
−
−
−
−
−
−
MC8[2]
−
−
−
−
−
−
−
−
−
−
MC8[3]
−
−
−
−
−
−
−
−
−
−
MC8[4]
−
−
−
−
−
−
−
−
−
−
MC8[5]
−
−
−
−
−
−
−
−
−
−
MC8[6]
−
−
−
−
−
−
−
−
−
−
Rev. 2.00 Dec. 05, 2005 Page 650 of 724
REJ09B0200-0200
Software Hardware
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MC8[7]
−
−
−
−
−
−
−
−
−
−
HCAN_0
MC8[8]
−
−
−
−
−
−
−
−
−
−
MC9[1]
−
−
−
−
−
−
−
−
−
−
MC9[2]
−
−
−
−
−
−
−
−
−
−
MC9[3]
−
−
−
−
−
−
−
−
−
−
MC9[4]
−
−
−
−
−
−
−
−
−
−
MC9[5]
−
−
−
−
−
−
−
−
−
−
MC9[6]
−
−
−
−
−
−
−
−
−
−
MC9[7]
−
−
−
−
−
−
−
−
−
−
MC9[8]
−
−
−
−
−
−
−
−
−
−
MC10[1]
−
−
−
−
−
−
−
−
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Software Hardware
Rev. 2.00 Dec. 05, 2005 Page 651 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MC12[5]
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MD0[1]
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Rev. 2.00 Dec. 05, 2005 Page 652 of 724
REJ09B0200-0200
Software Hardware
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MD0[3]
−
−
−
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HCAN_0
MD0[4]
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MD0[8]
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MD1[1]
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MD2[1]
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MD3[1]
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Software Hardware
Rev. 2.00 Dec. 05, 2005 Page 653 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MD4[1]
−
−
−
−
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HCAN_0
MD4[2]
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MD4[3]
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MD4[8]
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MD5[1]
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MD5[8]
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MD6[1]
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MD6[8]
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MD7[1]
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MD7[2]
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−
Rev. 2.00 Dec. 05, 2005 Page 654 of 724
REJ09B0200-0200
Software Hardware
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MD7[7]
−
−
−
−
−
−
−
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HCAN_0
MD7[8]
−
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MD8[1]
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MD8[2]
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MD8[3]
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MD8[8]
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MD9[1]
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MD9[2]
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MD9[7]
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MD10[1]
−
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MD10[2]
−
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MD10[3]
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MD10[4]
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MD10[6]
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MD10[7]
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MD10[8]
−
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MD11[1]
−
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MD11[2]
−
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MD11[3]
−
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−
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−
Software Hardware
Rev. 2.00 Dec. 05, 2005 Page 655 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MD11[5]
−
−
−
−
−
−
−
−
−
−
HCAN_0
MD11[6]
−
−
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MD11[7]
−
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MD11[8]
−
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MD12[1]
−
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MD12[2]
−
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MD12[3]
−
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MD12[4]
−
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MD12[5]
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MD12[6]
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MD12[7]
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MD12[8]
−
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MD13[1]
−
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MD13[2]
−
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MD13[3]
−
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MD13[4]
−
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MD13[5]
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MD13[6]
−
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MD13[7]
−
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MD13[8]
−
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MD14[1]
−
−
−
−
−
−
−
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MD14[2]
−
−
−
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MD14[3]
−
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MD14[4]
−
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MD14[5]
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MD14[6]
−
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MD14[7]
−
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MD14[8]
−
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MD15[1]
−
−
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−
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−
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−
MD15[2]
−
−
−
−
−
−
−
−
−
−
Rev. 2.00 Dec. 05, 2005 Page 656 of 724
REJ09B0200-0200
Software Hardware
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MD15[3]
−
−
−
−
−
−
−
−
−
−
HCAN_0
MD15[4]
−
−
−
−
−
−
−
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−
MD15[5]
−
−
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MD15[6]
−
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MD15[7]
−
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MD15[8]
−
−
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−
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−
HCANMON_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
MCR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
GSR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
BCR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
MBCR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
TXPR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
TXCR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
TXACK_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
ABACK_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
RXPR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
RFPR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
IRR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
MBIMR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
IMR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
REC_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
TEC_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
UMSR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
LAFML_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
LAFMH_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
MC0[1]
−
−
−
−
−
−
−
−
−
−
MC0[2]
−
−
−
−
−
−
−
−
−
−
MC0[3]
−
−
−
−
−
−
−
−
−
−
MC0[4]
−
−
−
−
−
−
−
−
−
−
MC0[5]
−
−
−
−
−
−
−
−
−
−
Software Hardware
HCAN_1
Rev. 2.00 Dec. 05, 2005 Page 657 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MC0[6]
−
−
−
−
−
−
−
−
−
−
HCAN_1
MC0[7]
−
−
−
−
−
−
−
−
−
−
MC0[8]
−
−
−
−
−
−
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REJ09B0200-0200
Software Hardware
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Rev. 2.00 Dec. 05, 2005 Page 659 of 724
REJ09B0200-0200
Section 22 List of Registers
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REJ09B0200-0200
Software Hardware
Section 22 List of Registers
Register
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Subactive Subsleep Standby
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Rev. 2.00 Dec. 05, 2005 Page 661 of 724
REJ09B0200-0200
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REJ09B0200-0200
Software Hardware
Section 22 List of Registers
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Rev. 2.00 Dec. 05, 2005 Page 663 of 724
REJ09B0200-0200
Section 22 List of Registers
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Reset
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−
−
−
−
MD10[6]
−
−
−
−
−
−
−
−
−
−
MD10[7]
−
−
−
−
−
−
−
−
−
−
Rev. 2.00 Dec. 05, 2005 Page 664 of 724
REJ09B0200-0200
Software Hardware
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MD10[8]
−
−
−
−
−
−
−
−
−
−
HCAN_1
MD11[1]
−
−
−
−
−
−
−
−
−
−
MD11[2]
−
−
−
−
−
−
−
−
−
−
MD11[3]
−
−
−
−
−
−
−
−
−
−
MD11[4]
−
−
−
−
−
−
−
−
−
−
MD11[5]
−
−
−
−
−
−
−
−
−
−
MD11[6]
−
−
−
−
−
−
−
−
−
−
MD11[7]
−
−
−
−
−
−
−
−
−
−
MD11[8]
−
−
−
−
−
−
−
−
−
−
MD12[1]
−
−
−
−
−
−
−
−
−
−
MD12[2]
−
−
−
−
−
−
−
−
−
−
MD12[3]
−
−
−
−
−
−
−
−
−
−
MD12[4]
−
−
−
−
−
−
−
−
−
−
MD12[5]
−
−
−
−
−
−
−
−
−
−
MD12[6]
−
−
−
−
−
−
−
−
−
−
MD12[7]
−
−
−
−
−
−
−
−
−
−
MD12[8]
−
−
−
−
−
−
−
−
−
−
MD13[1]
−
−
−
−
−
−
−
−
−
−
MD13[2]
−
−
−
−
−
−
−
−
−
−
MD13[3]
−
−
−
−
−
−
−
−
−
−
MD13[4]
−
−
−
−
−
−
−
−
−
−
MD13[5]
−
−
−
−
−
−
−
−
−
−
MD13[6]
−
−
−
−
−
−
−
−
−
−
MD13[7]
−
−
−
−
−
−
−
−
−
−
MD13[8]
−
−
−
−
−
−
−
−
−
−
MD14[1]
−
−
−
−
−
−
−
−
−
−
MD14[2]
−
−
−
−
−
−
−
−
−
−
MD14[3]
−
−
−
−
−
−
−
−
−
−
MD14[4]
−
−
−
−
−
−
−
−
−
−
Software Hardware
MD14[5]
Rev. 2.00 Dec. 05, 2005 Page 665 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbrevia-
High
Medium
tion
Reset
speed
speed
Sleep
Module
Stop
Watch
Subactive Subsleep Standby
Standby
Module
MD14[6]
−
−
−
−
−
−
−
−
−
−
HCAN_1
MD14[7]
−
−
−
−
−
−
−
−
−
−
MD14[8]
−
−
−
−
−
−
−
−
−
−
MD15[1]
−
−
−
−
−
−
−
−
−
−
MD15[2]
−
−
−
−
−
−
−
−
−
−
MD15[3]
−
−
−
−
−
−
−
−
−
−
MD15[4]
−
−
−
−
−
−
−
−
−
−
MD15[5]
−
−
−
−
−
−
−
−
−
−
MD15[6]
−
−
−
−
−
−
−
−
−
−
MD15[7]
−
−
−
−
−
−
−
−
−
−
MD15[8]
−
−
−
−
−
−
−
−
−
−
HCANMON_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWCR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWOCR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWPR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWCYR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWBFR_1A
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWBFR_1C
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWBFR_1E
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWBFR_1G
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWCR_2
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWOCR_2
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWPR_2
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWCYR_2
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWBFR_2A
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWBFR_2C
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWBFR_2E
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
PWBFR_2G
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
Rev. 2.00 Dec. 05, 2005 Page 666 of 724
REJ09B0200-0200
Software Hardware
PWM_1
PWM_2
Section 22 List of Registers
Register
Abbrevia-
High
Medium
speed
speed
Sleep
Stop
Watch
Subactive Subsleep Standby
Standby
Module
Initialized −
−
−
−
−
−
−
−
Initialized
PORT
PJDDR
Initialized −
−
−
−
−
−
−
−
Initialized
PKDDR
Initialized −
−
−
−
−
−
−
−
Initialized
PHDR
Initialized −
−
−
−
−
−
−
−
Initialized
PJDR
Initialized −
−
−
−
−
−
−
−
Initialized
PKDR
Initialized −
−
−
−
−
−
−
−
Initialized
PORTH
Initialized −
−
−
−
−
−
−
−
Initialized
PORTJ
Initialized −
−
−
−
−
−
−
−
Initialized
PORTK
Initialized −
−
−
−
−
−
−
−
Initialized
LPCR
Initialized −
−
−
−
−
−
−
−
Initialized
LCR
Initialized −
−
−
−
−
−
−
−
Initialized
LCR2
Initialized −
−
−
−
−
−
−
−
Initialized
MSTPCRD
Initialized −
−
−
−
−
−
−
−
Initialized
PWBTCR
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
tion
Reset
PHDDR
Module
Software Hardware
LCD
SYSTEM
PWM
common
SMR_4
Initialized −
−
−
−
−
−
−
−
Initialized
BRR_4
Initialized −
−
−
−
−
−
−
−
Initialized
SCR_4
Initialized −
−
−
−
−
−
−
−
Initialized
TDR_4
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
SSR_4
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
RDR_4
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
SCMR_4
Initialized −
−
−
−
−
−
−
−
Initialized
SBYCR
Initialized −
−
−
−
−
−
−
−
Initialized
SYSCR
Initialized −
−
−
−
−
−
−
−
Initialized
SCKCR
Initialized −
−
−
−
−
−
−
−
Initialized
MDCR
Initialized −
−
−
−
−
−
−
−
Initialized
MSTPCRA
Initialized −
−
−
−
−
−
−
−
Initialized
MSTPCRB
Initialized −
−
−
−
−
−
−
−
Initialized
MSTPCRC
Initialized −
−
−
−
−
−
−
−
Initialized
PFCR
Initialized −
−
−
−
−
−
−
−
Initialized
SCI_4
SYSTEM
BSC
Rev. 2.00 Dec. 05, 2005 Page 667 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbrevia-
High
Medium
speed
speed
Sleep
Stop
Watch
Subactive Subsleep Standby
Standby
Module
Initialized −
−
−
−
−
−
−
−
Initialized
SYSTEM
BARA
Initialized −
−
−
−
−
−
−
−
Initialized
PBC
BARB
Initialized −
−
−
−
−
−
−
−
Initialized
BCRA
Initialized −
−
−
−
−
−
−
−
Initialized
BCRB
Initialized −
−
−
−
−
−
−
−
Initialized
ISCRH
Initialized −
−
−
−
−
−
−
−
Initialized
ISCRL
Initialized −
−
−
−
−
−
−
−
Initialized
IER
Initialized −
−
−
−
−
−
−
−
Initialized
ISR
Initialized −
−
−
−
−
−
−
−
Initialized
DTCERA
Initialized −
−
−
−
−
−
−
−
Initialized
DTCERB
Initialized −
−
−
−
−
−
−
−
Initialized
DTCERC
Initialized −
−
−
−
−
−
−
−
Initialized
DTCERD
Initialized −
−
−
−
−
−
−
−
Initialized
DTCERE
Initialized −
−
−
−
−
−
−
−
Initialized
DTCERF
Initialized −
−
−
−
−
−
−
−
Initialized
DTCERG
Initialized −
−
−
−
−
−
−
−
Initialized
DTCERI
Initialized −
−
−
−
−
−
−
−
Initialized
DTVECR
Initialized −
−
−
−
−
−
−
−
Initialized
PCR
Initialized −
−
−
−
−
−
−
−
Initialized
PMR
Initialized −
−
−
−
−
−
−
−
Initialized
NDERH
Initialized −
−
−
−
−
−
−
−
Initialized
NDERL
Initialized −
−
−
−
−
−
−
−
Initialized
PODRH
Initialized −
−
−
−
−
−
−
−
Initialized
PODRL
Initialized −
−
−
−
−
−
−
−
Initialized
NDRH
Initialized −
−
−
−
−
−
−
−
Initialized
NDRL
Initialized −
−
−
−
−
−
−
−
Initialized
NDRH
Initialized −
−
−
−
−
−
−
−
Initialized
NDRL
Initialized −
−
−
−
−
−
−
−
Initialized
tion
Reset
LPWRCR
Module
Rev. 2.00 Dec. 05, 2005 Page 668 of 724
REJ09B0200-0200
Software Hardware
INT
DTC
PPG
Section 22 List of Registers
Register
Abbrevia-
High
Medium
speed
speed
Sleep
Stop
Watch
Subactive Subsleep Standby
Standby
Module
Initialized −
−
−
−
−
−
−
−
Initialized
PORT
P2DDR
Initialized −
−
−
−
−
−
−
−
Initialized
P3DDR
Initialized −
−
−
−
−
−
−
−
Initialized
P5DDR
Initialized −
−
−
−
−
−
−
−
Initialized
PADDR
Initialized −
−
−
−
−
−
−
−
Initialized
PBDDR
Initialized −
−
−
−
−
−
−
−
Initialized
PCDDR
Initialized −
−
−
−
−
−
−
−
Initialized
PDDDR
Initialized −
−
−
−
−
−
−
−
Initialized
PEDDR
Initialized −
−
−
−
−
−
−
−
Initialized
PFDDR
Initialized −
−
−
−
−
−
−
−
Initialized
PAPCR
Initialized −
−
−
−
−
−
−
−
Initialized
PBPCR
Initialized −
−
−
−
−
−
−
−
Initialized
PCPCR
Initialized −
−
−
−
−
−
−
−
Initialized
PDPCR
Initialized −
−
−
−
−
−
−
−
Initialized
PEPCR
Initialized −
−
−
−
−
−
−
−
Initialized
P3ODR
Initialized −
−
−
−
−
−
−
−
Initialized
PAODR
Initialized −
−
−
−
−
−
−
−
Initialized
PBODR
Initialized −
−
−
−
−
−
−
−
Initialized
PCODR
Initialized −
−
−
−
−
−
−
−
Initialized
TCR_3
Initialized −
−
−
−
−
−
−
−
Initialized
TMDR_3
Initialized −
−
−
−
−
−
−
−
Initialized
TIORH_3
Initialized −
−
−
−
−
−
−
−
Initialized
TIORL_3
Initialized −
−
−
−
−
−
−
−
Initialized
TIER_3
Initialized −
−
−
−
−
−
−
−
Initialized
TSR_3
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTH_3
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTL_3
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAH_3
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAL_3
Initialized −
−
−
−
−
−
−
−
Initialized
TGRBH_3
Initialized −
−
−
−
−
−
−
−
Initialized
tion
Reset
P1DDR
Module
Software Hardware
TPU_3
Rev. 2.00 Dec. 05, 2005 Page 669 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbrevia-
High
Medium
speed
speed
Sleep
Stop
Watch
Subactive Subsleep Standby
Standby
Module
Initialized −
−
−
−
−
−
−
−
Initialized
TPU_3
Initialized −
−
−
−
−
−
−
−
Initialized
TGRCL_3
Initialized −
−
−
−
−
−
−
−
Initialized
TGRDH_3
Initialized −
−
−
−
−
−
−
−
Initialized
TGRDL_3
Initialized −
−
−
−
−
−
−
−
Initialized
TCR_4
Initialized −
−
−
−
−
−
−
−
Initialized
TMDR_4
Initialized −
−
−
−
−
−
−
−
Initialized
TIOR_4
Initialized −
−
−
−
−
−
−
−
Initialized
TIER_4
Initialized −
−
−
−
−
−
−
−
Initialized
TSR_4
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTH_4
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTL_4
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAH_4
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAL_4
Initialized −
−
−
−
−
−
−
−
Initialized
TGRBH_4
Initialized −
−
−
−
−
−
−
−
Initialized
TGRBL_4
Initialized −
−
−
−
−
−
−
−
Initialized
TCR_5
Initialized −
−
−
−
−
−
−
−
Initialized
TMDR_5
Initialized −
−
−
−
−
−
−
−
Initialized
TIOR_5
Initialized −
−
−
−
−
−
−
−
Initialized
TIER_5
Initialized −
−
−
−
−
−
−
−
Initialized
TSR_5
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTH_5
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTL_5
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAH_5
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAL_5
Initialized −
−
−
−
−
−
−
−
Initialized
TGRBH_5
Initialized −
−
−
−
−
−
−
−
Initialized
TGRBL_5
Initialized −
−
−
−
−
−
−
−
Initialized
TSTR
Initialized −
−
−
−
−
−
−
−
Initialized
TSYR
Initialized −
−
−
−
−
−
−
−
Initialized
tion
Reset
TGRBL_3
TGRCH_3
Module
Rev. 2.00 Dec. 05, 2005 Page 670 of 724
REJ09B0200-0200
Software Hardware
TPU_4
TPU_5
TPU
common
Section 22 List of Registers
Register
Abbrevia-
High
Medium
speed
speed
Sleep
Stop
Watch
Subactive Subsleep Standby
Standby
Module
Initialized −
−
−
−
−
−
−
−
Initialized
INT
IPRB
Initialized −
−
−
−
−
−
−
−
Initialized
IPRC
Initialized −
−
−
−
−
−
−
−
Initialized
IPRD
Initialized −
−
−
−
−
−
−
−
Initialized
IPRE
Initialized −
−
−
−
−
−
−
−
Initialized
IPRF
Initialized −
−
−
−
−
−
−
−
Initialized
IPRG
Initialized −
−
−
−
−
−
−
−
Initialized
IPRH
Initialized −
−
−
−
−
−
−
−
Initialized
IPRJ
Initialized −
−
−
−
−
−
−
−
Initialized
IPRK
Initialized −
−
−
−
−
−
−
−
Initialized
IPRM
Initialized −
−
−
−
−
−
−
−
Initialized
IPRO
Initialized −
−
−
−
−
−
−
−
Initialized
ABWCR
Initialized −
−
−
−
−
−
−
−
Initialized
ASTCR
Initialized −
−
−
−
−
−
−
−
Initialized
WCRH
Initialized −
−
−
−
−
−
−
−
Initialized
WCRL
Initialized −
−
−
−
−
−
−
−
Initialized
BCRH
Initialized −
−
−
−
−
−
−
−
Initialized
BCRL
Initialized −
−
−
−
−
−
−
−
Initialized
RAMER
Initialized −
−
−
−
−
−
−
−
Initialized
tion
Reset
IPRA
Module
Software Hardware
BSC
FLASH
(F-ZTAT)
P1DR
Initialized −
−
−
−
−
−
−
−
Initialized
P2DR
Initialized −
−
−
−
−
−
−
−
Initialized
P3DR
Initialized −
−
−
−
−
−
−
−
Initialized
P5DR
Initialized −
−
−
−
−
−
−
−
Initialized
PADR
Initialized −
−
−
−
−
−
−
−
Initialized
PBDR
Initialized −
−
−
−
−
−
−
−
Initialized
PCDR
Initialized −
−
−
−
−
−
−
−
Initialized
PDDR
Initialized −
−
−
−
−
−
−
−
Initialized
PEDR
Initialized −
−
−
−
−
−
−
−
Initialized
PFDR
Initialized −
−
−
−
−
−
−
−
Initialized
PORT
Rev. 2.00 Dec. 05, 2005 Page 671 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbrevia-
High
Medium
speed
speed
Sleep
Stop
Watch
Subactive Subsleep Standby
Standby
Module
Initialized −
−
−
−
−
−
−
−
Initialized
TPU_0
TMDR_0
Initialized −
−
−
−
−
−
−
−
Initialized
TIORH_0
Initialized −
−
−
−
−
−
−
−
Initialized
TIORL_0
Initialized −
−
−
−
−
−
−
−
Initialized
TIER_0
Initialized −
−
−
−
−
−
−
−
Initialized
TSR_0
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTH_0
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTL_0
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAH_0
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAL_0
Initialized −
−
−
−
−
−
−
−
Initialized
TGRBH_0
Initialized −
−
−
−
−
−
−
−
Initialized
TGRBL_0
Initialized −
−
−
−
−
−
−
−
Initialized
TGRCH_0
Initialized −
−
−
−
−
−
−
−
Initialized
TGRCL_0
Initialized −
−
−
−
−
−
−
−
Initialized
TGRDH_0
Initialized −
−
−
−
−
−
−
−
Initialized
TGRDL_0
Initialized −
−
−
−
−
−
−
−
Initialized
TCR_1
Initialized −
−
−
−
−
−
−
−
Initialized
TMDR_1
Initialized −
−
−
−
−
−
−
−
Initialized
TIOR_1
Initialized −
−
−
−
−
−
−
−
Initialized
TIER_1
Initialized −
−
−
−
−
−
−
−
Initialized
TSR_1
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTH_1
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTL_1
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAH_1
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAL_1
Initialized −
−
−
−
−
−
−
−
Initialized
TGRBH_1
Initialized −
−
−
−
−
−
−
−
Initialized
TGRBL_1
Initialized −
−
−
−
−
−
−
−
Initialized
TCR_2
Initialized −
−
−
−
−
−
−
−
Initialized
TMDR_2
Initialized −
−
−
−
−
−
−
−
Initialized
TIOR_2
Initialized −
−
−
−
−
−
−
−
Initialized
tion
Reset
TCR_0
Module
Rev. 2.00 Dec. 05, 2005 Page 672 of 724
REJ09B0200-0200
Software Hardware
TPU_1
TPU_2
Section 22 List of Registers
Register
Abbrevia-
High
Medium
speed
speed
Sleep
Stop
Watch
Subactive Subsleep Standby
Standby
Module
Initialized −
−
−
−
−
−
−
−
Initialized
TPU_2
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTH_2
Initialized −
−
−
−
−
−
−
−
Initialized
TCNTL_2
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAH_2
Initialized −
−
−
−
−
−
−
−
Initialized
TGRAL_2
Initialized −
−
−
−
−
−
−
−
Initialized
TGRBH_2
Initialized −
−
−
−
−
−
−
−
Initialized
TGRBL_2
Initialized −
−
−
−
−
−
−
−
Initialized
TCSR_0
Initialized −
−
−
−
−
−
−
−
Initialized
TCNT_0
Initialized −
−
−
−
−
−
−
−
Initialized
RSTCSR
Initialized −
−
−
−
−
−
−
−
Initialized
SMR_0
Initialized −
−
−
−
−
−
−
−
Initialized
BRR_0
Initialized −
−
−
−
−
−
−
−
Initialized
SCR_0
Initialized −
−
−
−
−
−
−
−
Initialized
TDR_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
SSR_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
RDR_0
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
SCMR_0
Initialized −
−
−
−
−
−
−
−
Initialized
SMR_1
Initialized −
−
−
−
−
−
−
−
Initialized
BRR_1
Initialized −
−
−
−
−
−
−
−
Initialized
SCR_1
Initialized −
−
−
−
−
−
−
−
Initialized
TDR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
SSR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
RDR_1
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
SCMR_1
Initialized −
−
−
−
−
−
−
−
Initialized
SMR_2
Initialized −
−
−
−
−
−
−
−
Initialized
BRR_2
Initialized −
−
−
−
−
−
−
−
Initialized
SCR_2
Initialized −
−
−
−
−
−
−
−
Initialized
TDR_2
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
SSR_2
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
tion
Reset
TIER_2
TSR_2
Module
Software Hardware
WDT_0
SCI_0
SCI_1
SCI_2
Rev. 2.00 Dec. 05, 2005 Page 673 of 724
REJ09B0200-0200
Section 22 List of Registers
Register
Abbrevia-
High
Medium
speed
speed
Sleep
Stop
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized −
−
−
−
ADDRAH
Initialized −
−
−
ADDRAL
Initialized −
−
−
ADDRBH
Initialized −
−
ADDRBL
Initialized −
ADDRCH
tion
Reset
RDR_2
SCMR_2
Module
Software Hardware
Standby
Module
Initialized
Initialized
SCI_2
−
−
Initialized
Initialized Initialized Initialized
Initialized
Initialized
Initialized
Initialized Initialized Initialized
Initialized
Initialized
Initialized
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
ADDRCL
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
ADDRDH
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
ADDRDL
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
ADCSR
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
ADCR
Initialized −
−
−
Initialized Initialized Initialized
Initialized
Initialized
Initialized
TCSR_1
Initialized −
−
−
−
−
−
−
−
Initialized
TCNT_1
Initialized −
−
−
−
−
−
−
−
Initialized
FLMCR1
Initialized −
−
−
−
−
−
−
−
Initialized
FLMCR2
Initialized −
−
−
−
−
−
−
−
Initialized
EBR1
Initialized −
−
−
−
−
−
−
−
Initialized
EBR2
Initialized −
−
−
−
−
−
−
−
Initialized
FLPWCR
Initialized −
−
−
−
−
−
−
−
Initialized
PORT1
−
−
−
−
−
−
−
−
−
−
PORT2
−
−
−
−
−
−
−
−
−
−
PORT3
−
−
−
−
−
−
−
−
−
−
PORT4
−
−
−
−
−
−
−
−
−
−
PORT5
−
−
−
−
−
−
−
−
−
−
PORT9
−
−
−
−
−
−
−
−
−
−
PORTA
−
−
−
−
−
−
−
−
−
−
PORTB
−
−
−
−
−
−
−
−
−
−
PORTC
−
−
−
−
−
−
−
−
−
−
PORTD
−
−
−
−
−
−
−
−
−
−
PORTF
−
−
−
−
−
−
−
−
−
−
Note:
 is not initialized.
Rev. 2.00 Dec. 05, 2005 Page 674 of 724
REJ09B0200-0200
Watch
−
Subactive Subsleep Standby
−
A/D
WDT_1
FLASH
(F-ZTAT)
PORT
Section 23 Electrical Characteristics [Preliminary]
Section 23 Electrical Characteristics [Preliminary]
23.1
Absolute Maximum Ratings
Table 23.1 lists the absolute maximum ratings.
Table 23.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
VCC
–0.3 to +7.0
V
LPVCC
–0.3 to +7.0
V
Input voltage (XTAL, EXTAL)
Vin
–0.3 to VCC +0.3
V
Input voltage (OSC1, OSC2)
Vin
–0.3 to +3.5
V
Input voltage (ports A, B, C, D, E, Vin
PF2, PF4 to PF6)
–0.3 to LPVCC +0.3
V
Input voltage (ports H and J)
–0.3 to PWMVCC +0.3
V
Input voltage (except XTAL,
Vin
EXTAL, OSC1, OSC2, ports 4, 9,
A, B, C, D, E, PF2, PF4 to PF6,
H, and J)
–0.3 to VCC +0.3
V
Reference voltage
Vref
–0.3 to AVCC +0.3
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Analog input voltage
VAN
–0.3 to AVCC +0.3
V
Operating temperature
Topr
Regular specifications: –20 to +75
°C
Wide-range specifications: –40 to +85
°C
–55 to +125
°C
Power supply voltage
PMWVCC
Storage temperature
Vin
Tstg
Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded.
Rev. 2.00 Dec. 05, 2005 Page 675 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
23.2
DC Characteristics
Table 23.2 lists the DC characteristics. Table 23.3 lists the permissible output currents.
Table 23.2 DC Characteristics
Conditions: VCC = AVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)*1
Item
Schmitt
trigger input
voltage
Symbol
IRQ0 to IRQ5 VT–
Ports A to E,
PF2, 4 to 6
Unit
V
VCC × 0.2
—
—
—
VCC × 0.7
VT+ – VT–
VCC × 0.05
—
—
LPVCC × 0.2 —
—
—
—
LPVCC × 0.7
LPVCC ×
0.05
—
—
VT–
PWMVCC × —
0.2
—
VT+
—
PWMVCC ×
0.7
VT+ – VT–
PWMVCC × —
0.05
—
AVCC × 0.7
AVCC + 0.3
VT
–
VT – VT
Ports 4, 9
RES, STBY,
NMI, FWE,
MD2 to MD0
Max.
—
+
Input high
voltage
Typ.
VT+
VT+
Ports H, J
Min.
–
—
VCC × 0.9
—
VCC + 0.3
Ports 1 to 3,
5, K, PF0,
PF3, PF7,
EXTAL
VCC × 0.7
—
VCC + 0.3
HRxD0,
HRxD1
VCC × 0.7
—
VCC + 0.3
Ports 4 and 9
AVCC × 0.7
—
AVCC + 0.3
VIH
Rev. 2.00 Dec. 05, 2005 Page 676 of 724
REJ09B0200-0200
V
V
V
Test
Conditions
Section 23 Electrical Characteristics [Preliminary]
Item
Input low
voltage
Output high
voltage
Test
Conditions
Symbol
Min.
Typ.
Max.
Unit
VIL
–0.3
—
VCC × 0.1
V
Ports 1 to 3,
5, K, PF0, 3,
7, EXTAL
–0.3
—
VCC × 0.2
HRxD0,
HRxD1
–0.3
—
VCC × 0.2
Ports 4 and 9
–0.3
—
AVCC × 0.2
VCC – 0.5
—
—
Ports A to E,
PF2, PF4 to
PF6
LPVCC – 0.5 —
—
IOH = –200 µA
Ports H, J
PWMVCC
− 0.5
—
—
IOH = –200 µA
Ports 1 to 3,
5, K, PF0,
PF3, PF7,
HRxD0,
HRxD1
VCC − 1.0
—
—
IOH = –1 mA
Ports A to E,
PF2, PF4 to
PF6
LPVCC − 1.0 —
—
IOH = –1 mA
Ports H, J
PWMVCC
– 1.0
—
—
IOH = –1 mA
PWM1A to
PWM1H,
PWM2A to
PWM2H
PWMVCC
– 0.5
—
—
IOH = –15 mA
RES, STBY,
NMI, FWE,
MD2 to MD0
Ports 1 to 3,
5, K, PF0,
PF3, PF7,
HRxD0,
HRxD1
VOH
V
IOH = –200 µA
Rev. 2.00 Dec. 05, 2005 Page 677 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
Item
Output low
voltage
Symbol Min.
Typ.
Max.
Unit
Test Conditions
—
—
0.4
V
IOL = 1.6 mA
—
—
0.5
—
—
1.0
STBY, NMI,
MD2 to MD0
—
—
1.0
HRxD0,
HRxD1, FWE
—
—
1.0
Ports 4 and 9
—
—
1.0
—
—
1.0
Ports H, J
—
—
1.0
Vin =0.5 to
PWMVCC – 0.5
Ports A to E,
PF2,
PF4 to PF6
—
—
1.0
Vin =
0.5 to LPVCC – 0.5
All output
pins except
PWM1A to
PWM1H,
PWM2A to
PWM2H
VOL
PWM1A to
PWM1H,
PWM2A to
PWM2H
Input
leakage
current
Three-state
leakage
current
(off state)
RES
Ports 1 to 3,
5, K, PF0,
PF3, PF7,
HRxD0,
HRxD1
Iin
ITSI
IOL = 15 mA
µA
Vin =
0.5 to VCC – 0.5
Vin = 0.5 to
AVCC – 0.5
µA
Vin =
0.5 to VCC – 0.5
Input pull-up Ports A to E
MOS
current
–IP
10
—
300
µA
Vin = 0 V
Input
RES
capacitance
NMI
Cin
—
—
30
pF
—
—
30
—
—
15
Vin = 0 V
f = 1 MHz
Ta = 25°C
All input pins
except RES
and NMI
Rev. 2.00 Dec. 05, 2005 Page 678 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
Item
Symbol Min.
Typ.
Max.
Unit
Test Conditions
—
60
80
mA
f = 20 MHz
—
50
65
mA
f = 20 MHz
All modules
stopped
—
40
—
mA
f = 20 MHz
(reference values)
Mediumspeed mode
(φ/32)
—
40
—
mA
f = 20 MHz
(reference values)
Subactive
mode
—
130
220
µA
Using 32.768 kHz
crystal resonator
Subsleep
mode
—
95
160
µA
Using 32.768 kHz
crystal resonator
Watch mode
—
25
60
µA
Using 32.768 kHz
crystal resonator
—
2.0
10
µA
Ta ≤ 50°C
—
—
80
—
10
20
mA
—
0.1
10
µA
—
—
80
—
1.0
2.0
mA
—
—
5.0
µA
—
2.5
4.0
mA
—
—
5.0
µA
2.0
—
—
V
Current
Normal
consumption operation
2
*
Sleep mode
Standby*
LCD power
supply port
power supply
current
3
ICC*
3
During
operation
LPlCC
Standby
mode
Analog
During A/D
power supply conversion
current
Idle
AlCC
Reference
current
AlCC
During A/D
conversion
Idle
RAM standby voltage
VRAM
50°C < Ta
Ta = 50°C
50°C < Ta
AVCC = 5.0 V
Vref = 5.0 V
Notes: 1. If the A/D converter is not used, do not leave the AVCC, Vref , and AVSS pins open.
Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by connecting them to
VCC, for instance. Set Vref ≤ AVCC.
2. Current consumption values are for VIH = VCC, AVCC (port 4, 9), PWMVCC (port H, J),
LPVCC (port A to E), VIL = 0 V with all output pins unloaded and the on-chip pull-up
resistors in the off state.
3. ICC depends on VCC and f as follows:
ICC max. = 31 (mA) + 0.45 (mA/(MHz × V)) × VCC × f (normal operation)
ICC max. = 27 (mA) + 0.35 (mA/(MHz × V)) × VCC × f (sleep mode)
Rev. 2.00 Dec. 05, 2005 Page 679 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
Table 23.3 Permissible Output Currents
Conditions: VCC = AVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C
(regular specifications) , Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Typ.
Max.
Unit
—
—
10
mA
—
—
25
mA
Ta = 75°C to
85°C
—
—
30
mA
Ta = 25°C
—
—
40
mA
Ta = -40°C
Total of all output pins Σ IOL
except PWM1A to
PWM1H, PWM2A to
PWM2H
—
—
80
mA
Σ IOL
—
—
150
mA
Ta = 75°C to
85°C
—
—
180
mA
Ta = 25°C
—
—
220
mA
Ta = -40°C
All output pins except –IOH
PWM1A to PWM1H,
PWM2A to PWM2H
—
—
2.0
mA
PWM1A to PWM1H,
PWM2A to PWM2H
—
—
25
mA
Ta = 75°C to
85°C
—
—
30
mA
Ta = 25°C
—
—
40
mA
Ta = -40°C
Total of all output pins –Σ IOH
except PWM1A to
PWM1H, PWM2A to
PWM2H
—
—
40
mA
Total of PWM1A to
PWM1H, PWM2A to
PWM2H
—
—
150
mA
Ta = 75°C to
85°C
—
—
180
mA
Ta = 25°C
—
—
220
mA
Ta = -40°C
Permissible output All output pins except IOL
low current (per pin) PWM1A to PWM1H,
PWM2A to PWM2H
PWM1A to PWM1H,
PWM2A to PWM2H
Permissible output
low current (total)
Total of PWM1A to
PWM1H, PWM2A to
PWM2H
Permissible output
high current (per
pin)
Permissible output
high current (total)
Test
Conditions
Min.
IOL
–IOH
–Σ IOH
Note: To protect chip reliability, do not exceed the output current values in table 23.3.
Rev. 2.00 Dec. 05, 2005 Page 680 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
23.3
AC Characteristics
Figure 23.1 shows the test conditions for the AC characteristics.
5V
RL
LSI output pin
C
RH
C = 50 pF: Ports A to F
(In case of expansion bus control signal output pin setting)
C = 30 pF: All ports except ports A to F
RL = 2.4 k
RH = 12 k
Input/output timing measurement levels
· Low level : 0.8 V
· High level : 2.0 V
Figure 23.1 Output Load Circuit
Rev. 2.00 Dec. 05, 2005 Page 681 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
23.3.1
Clock Timing
Table 23.4 lists the clock timing
Table 23.4 Clock Timing
Condition: VCC = AVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min.
Max.
Unit
Test Conditions
Clock cycle time
tcyc
50
250
ns
Figure 23.2
Clock high pulse width
tCH
15
—
ns
Clock low pulse width
tCL
15
—
ns
Clock rise time
tCr
—
10
ns
Clock fall time
tCf
—
10
ns
Clock oscillator settling time at
reset (crystal)
tOSC1
20
—
ms
Figure 23.3
Clock oscillator settling time in
software standby (crystal)
tOSC2
8
—
ms
Figure 21.3
External clock output settling time
tDEXT
2
—
ms
Figure 23.3
Subclock oscillator settling time
tOSC3
—
2
s
Subclock oscillator frequency
fSUB
32.768
kHz
Subclock (φSUB) cycle time
tSUB
30.5
µs
tcyc
tCH
tCf
φ
tCL
tCr
Figure 23.2 System Clock Timing
Rev. 2.00 Dec. 05, 2005 Page 682 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
EXTAL
tDEXT
tDEXT
VCC
STBY
tOSC1
tOSC1
RES
φ
Figure 23.3 Oscillator Settling Timing
23.3.2
Control Signal Timing
Table 23.5 lists the control signal timing.
Table 23.5 Control Signal Timing
Condition: VCC = AVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol Min.
Max.
Unit
Test Conditions
RES setup time
tRESS
200
—
ns
Figure 23.4
RES pulse width
tRESW
20
—
tcyc
NMI setup time
tNMIS
150
—
ns
NMI hold time
tNMIH
10
—
ns
NMI pulse width (exiting software
standby mode)
tNMIW
200
—
ns
IRQ setup time
tIRQS
150
—
ns
IRQ hold time
tIRQH
10
—
ns
IRQ pulse width (exiting software
standby mode)
tIRQW
200
—
ns
Figure 23.5
Rev. 2.00 Dec. 05, 2005 Page 683 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
φ
tRESS
tRESS
RES
tRESW
Figure 23.4 Reset Input Timing
φ
tNMIS
tNMIH
NMI
tNMIW
IRQ
tIRQW
tIRQS
tIRQH
IRQ
Edge input
tIRQS
IRQ
Level input
Figure 23.5 Interrupt Input Timing
Rev. 2.00 Dec. 05, 2005 Page 684 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
23.3.3
Bus Timing
Table 23.6 lists the bus timing.
Table 23.6 Bus Timing
Condition: VCC = AVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min.
Max.
Unit
Test Conditions
Address delay time
tAD
—
Address setup time
tAS
45
ns
Figure 23.6 to
0.5 × tcyc – 32
—
ns
Figure 23.10
Address hold time
tAH
0.5 × tcyc – 15
—
ns
AS delay time
tASD
—
45
ns
RD delay time 1
tRSD1
—
45
ns
RD delay time 2
tRSD2
—
45
ns
Read data setup time
tRDS
20
—
ns
Read data hold time
tRDH
10
—
ns
Read data access time 1
tACC1
—
1.0 × tcyc – 60
ns
Read data access time 2
tACC2
—
1.5 × tcyc – 50
ns
Read data access time 3
tACC3
—
2.0 × tcyc – 60
ns
Read data access time 4
tACC4
—
2.5 × tcyc – 50
ns
Read data access time 5
tACC5
—
3.0 × tcyc – 60
ns
WR delay time 1
tWRD1
—
35
ns
WR delay time 2
tWRD2
—
45
ns
WR pulse width 1
tWSW1
1.0 × tcyc – 40
—
ns
WR pulse width 2
tWSW2
1.5 × tcyc – 30
—
ns
Write data delay time
tWDD
—
45
ns
Write data setup time
tWDS
0.5 × tcyc – 20
—
ns
Write data hold time
tWDH
0.5 × tcyc – 10
—
ns
WAIT setup time
tWTS
30
—
ns
WAIT hold time
tWTH
5
—
ns
Rev. 2.00 Dec. 05, 2005 Page 685 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
T1
T2
φ
tAD
A23 to A0
tAS
tAH
tASD
tASD
AS
tRSD1
RD
(read)
tRSD2
tACC2
tAS
tACC3
tRDS
tRDH
D15 to D0
(read)
tWRD2
WR
(write)
tWRD2
tAS
tAH
tWDD
tWSW1
tWDH
D15 to D0
(write)
Figure 23.6 Basic Bus Timing (Two-State Access)
Rev. 2.00 Dec. 05, 2005 Page 686 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
T1
T2
T3
φ
tAD
A23 to A0
tAS
tAH
tASD
tASD
AS
tRSD1
RD
(read)
tRSD2
tACC4
tAS
tRDS
tACC5
tRDH
D15 to D0
(read)
tWRD1
tWRD2
WR
(write)
tAH
tWDD tWDS
tWSW2
tWDH
D15 to D0
(write)
Figure 23.7 Basic Bus Timing (Three-State Access)
Rev. 2.00 Dec. 05, 2005 Page 687 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
T1
T2
Tw
tWTS tWTH
tWTS tWTH
T3
φ
A23 to A0
AS
RD
(read)
D15 to D0
(read)
WR
(write)
D15 to D0
(write)
WAIT
Figure 23.8 Basic Bus Timing (Three-State Access with One Wait State)
Rev. 2.00 Dec. 05, 2005 Page 688 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
T1
T1
T2 or T3
T2
φ
tAD
A23 to A0
tAS
tAH
tASD
tASD
AS
tRSD2
RD
(read)
tACC3
tRDS
tRDH
D15 to D0
(read)
Figure 23.9 Burst ROM Access Timing (Two-State Access)
Rev. 2.00 Dec. 05, 2005 Page 689 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
T1
T2 or T3
T1
φ
tAD
A23 to A0
AS
tRSD2
RD
(read)
tACC1 tRDS tRDH
D15 to D0
(read)
Figure 23.10 Burst ROM Access Timing (Two-State Access)
Rev. 2.00 Dec. 05, 2005 Page 690 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
23.3.4
Timing of On-Chip Peripheral Modules
Table 23.7 lists the timing of on-chip peripheral modules.
Table 23.7 Timing of On-Chip Peripheral Modules
Condition: VCC = AVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min.
Max.
Unit
Test Conditions
Output data delay time
tPWD
—
50
ns
Figure 23.11
Input data setup time
tPRS
30
—
Input data hold time
tPRH
30
—
PPG
Pulse output delay time
tPOD
—
50
ns
Figure 23.12
TPU
Timer output delay time
tTOCD
—
50
ns
Figure 23.13
Timer input setup time
tTICS
30
—
Figure 23.14
I/O port
Timer clock input setup time
Timer clock
pulse width
tTCKS
30
—
ns
Single edge
tTCKWH
1.5
—
tcyc
Both edges
tTCKWL
2.5
—
PWM
Pulse output delay time
tMPWMOD
—
50
ns
Figure 23.15
SCI
Input clock
cycle
tScyc
4
—
tcyc
Figure 23.16
6
—
Asynchronous
Synchronous
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
1.5
tcyc
Input clock fall time
tSCKf
—
1.5
Transmit data delay time
tTXD
—
50
Receive data setup time
(synchronous)
tRXS
50
—
Receive data hold time
(synchronous)
tRXH
50
—
A/D
Trigger input setup time
converter
tTRGS
50
HCAN
Transmit data delay time
tHTXD
Transmit data setup time
Transmit data hold time
ns
Figure 23.17
—
ns
Figure 23.18
—
100
ns
Figure 23.19
tHRXS
100
—
tHRXH
100
—
Rev. 2.00 Dec. 05, 2005 Page 691 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
T2
T1
φ
tPRS
tPRH
Port 1 to 5, 9,
A to F, K
(read)
tPWD
Port 1 to 3, 5,
A to F, K
(write)
T1
T3
T2
T4
φ
tPRS
tPRH
Port H, J
(read)
tPWD
Port H, J
(write)
Figure 23.11 I/O Port Input/Output Timing
φ
tPOD
PO15 to PO8
Figure 23.12 PPG Output Timing
Rev. 2.00 Dec. 05, 2005 Page 692 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
φ
tTOCD
Output compare
output*
tTICS
Input capture
input*
Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3
Figure 23.13 TPU Input/Output Timing
φ
tTCKS
tTCKS
TCLKA to TCLKD
tTCKWL
tTCKWH
Figure 23.14 TPU Clock Input Timing
φ
tMPWMOD
PWM1A to PWM1H,
PWM2A to PWM2H
Figure 23.15 Motor Control PWM Output Timing
Rev. 2.00 Dec. 05, 2005 Page 693 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
tSCKr
tSCKW
tSCKf
SCK0 to SCK4
tScyc
Figure 23.16 SCK Clock Input Timing
SCK0 to SCK2,
SCK4
tTXD
TxD0 to TxD2,
TxD4
(transmit data)
tRXS
tRXH
RxD0 to RxD2,
RxD4
(receive data)
Figure 23.17 SCI Input/Output Timing (Clock Synchronous Mode)
φ
tTRGS
ADTRG
Figure 23.18 A/D Converter External Trigger Input Timing
Rev. 2.00 Dec. 05, 2005 Page 694 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
CK
tHTXD
HTxD
(transmit data)
tHRXS tHRXH
HRxD
(receive data)
Figure 23.19 HCAN Input/Output Timing
Rev. 2.00 Dec. 05, 2005 Page 695 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
23.4
A/D Conversion Characteristics
Table 23.8 lists the A/D conversion characteristics.
Table 23.8 A/D Conversion Characteristics
Condition: VCC = AVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition
Item
Min.
Typ.
Max.
Unit
Resolution
10
10
10
bits
Conversion time
10
—
200
µs
Analog input capacitance
—
—
20
pF
Permissible signal-source impedance
—
—
5
kΩ
Nonlinearity error
—
—
±3.5
LSB
Offset error
—
—
±3.5
LSB
Full-scale error
—
—
±3.5
LSB
Quantization
—
±0.5
—
LSB
Absolute accuracy
—
—
±4.0
LSB
Rev. 2.00 Dec. 05, 2005 Page 696 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
23.5
LCD Characteristics
Table 23.9 LCD Characteristics
Condition: VCC = AVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = –20 to +75°C
(regular specifications), Ta = –40 to +85°C (wide-range specifications)
Applicable
Pins
Test
Conditions
Min.
Typ.
Max.
Unit
Notes
Segment driver
VDS
step-down voltage
SEG1 to
SEG40
ID = 2 µA
—
—
0.6
V
*1
Common driver
VDS
step-down voltage
COM1 to
COM4
ID = 2 µA
—
—
0.3
V
*1
300
1000
kΩ
—
LPVCC V
Item
Symbol
LCD power supply RLCD
split resistor
LCD voltage
VLCD
Between V1 40
and VSS
V1
4.5
*2
Notes: 1. Voltage step-down between power supply pins V1, V2, V3, and VSS, and segment pins,
or common pins.
2. If the LCD voltage is provided by an external power supply, the following relationship
must be maintained: LPVCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
Rev. 2.00 Dec. 05, 2005 Page 697 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
23.6
Flash Memory Characteristics
Table 23.10 shows the flash memory characteristics.
Table 23.10 Flash Memory Characteristics
Conditions: VCC = AVCC = 4.5 V to 5.5 V, LPVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V,
Ta = 0 to +75°C (Programming/erasing operating temperature range)
Item
1, 2, 4
Programming time* * *
1, 3, 5
Erase time* * *
Reprogramming count
1
Programming Wait time after SWE bit setting*
1
Wait time after PSU bit setting*
Symbol
Min.
Typ.
Max.
Unit
tP
—
10
200
ms/
128
bytes
tE
—
100
1200
ms/block
NWEC
—
—
100
Times
tsswe
1
1
—
µs
tspsu
50
50
—
µs
tsp30
28
30
32
µs
Programming
time wait
tsp200
198
200
202
µs
Programming
time wait
tsp10
8
10
12
µs
Additionalprogramming
time wait
tcp
5
5
—
µs
tcpsu
5
5
—
µs
Wait time after PV bit setting*
tspv
4
4
—
µs
Wait time after H'FF dummy
1
write*
tspvr
2
2
—
µs
tcpv
2
2
—
µs
tcswe
100
100
—
µs
1,
4
Wait time after P bit setting* *
1
Wait time after P bit clear*
1
Wait time after PSU bit clear*
1
1
Wait time after PV bit clear*
1
Wait time after SWE bit clear*
1, 4
Maximum programming count* * N
Erase
Test
Conditions
1
—
—
1000
Times
1
1
—
µs
tsesu
100
100
—
µs
tse
10
10
100
ms
tce
10
10
—
µs
Wait time after SWE bit setting*
tsswe
1
Wait time after ESU bit setting*
1,
5
Wait time after E bit setting* *
1
Wait time after E bit clear*
Rev. 2.00 Dec. 05, 2005 Page 698 of 724
REJ09B0200-0200
Erase time
wait
Section 23 Electrical Characteristics [Preliminary]
Item
Erase
Symbol
Min.
Typ.
Max.
Unit
1
tcesu
10
10
—
µs
1
Wait time after EV bit setting*
tsev
20
20
—
µs
Wait time after H'FF dummy
1
write*
tsevr
2
2
—
µs
Wait time after ESU bit clear*
1
Wait time after EV bit clear*
1
Wait time after SWE bit clear*
1, 5
Maximum erase count* *
Test
Conditions
tcev
4
4
—
µs
tcswe
100
100
—
µs
N
12
—
120
Times
Notes: 1. Make each time setting in accordance with the program or erase algorithm.
2. Programming time per 128 bytes (shows the total period for which the P bit in the flash
memory control register (FLMCR1) is set and does not include the programming
verification time.)
3. Block erase time (shows the total period for which the E bit in FLMCR1 is set and does
not include the erase verification time.)
4. To specify the maximum programming time value (tp (max.)) in the 128-byte
programming algorithm, set the max. value (1000) for the maximum programming count
(N).
The wait time after P bit setting should be changed as follows according to the value of
the programming counter (n).
Programming counter (n) = 1 to 6:
tsp30 = 30 µs
Programming counter (n) = 7 to 1000:
tsp200 = 200 µs
[In additional programming]
Programming counter (n)= 1 to 6:
tsp10 = 10 µs
5. For the maximum erase time (tE (max.)), the following relationship applies between the
wait time after E bit setting (tse) and the maximum erase count (N):
tE (max.) = Wait time after E bit setting (tse) x maximum erase count (N)
To specify the maximum erase time, the values of (tse) and (N) should be set so as to
satisfy the above formula.
Examples: When tse = 100 [ms], N = 12 times
When tse = 10 [ms], N = 120 times
Rev. 2.00 Dec. 05, 2005 Page 699 of 724
REJ09B0200-0200
Section 23 Electrical Characteristics [Preliminary]
Rev. 2.00 Dec. 05, 2005 Page 700 of 724
REJ09B0200-0200
Appendix
Appendix
A.
I/O Port States in Each Operating State
Port Name
MCU
Operating
Mode
Hardware
Power-on Standby
Reset
Mode
Program
Execution State,
Software Standby Mode Sleep Mode
Port 1
4 to 7
T
T
Keep
I/O port
Port 2
4 to 7
T
T
Keep
I/O port
Port 3
4 to 7
T
T
Keep
I/O port
Port 4
4 to 7
T
T
T
Input port
Port 5
4 to 7
T
T
Keep
I/O port
Port 9
4 to 7
T
T
T
Input port
Port A
4 and 5
L
T
[Address output, OPE = 0] [Address output]
6
T
T
A23 to A16
[Address output, OPE = 1] [Segment,
common output]
Keep
7
T
T
[Segment, common
output]
SEG40 to
SEG37
Port
COM4 to COM1
[Otherwise]
[Otherwise]
Keep
I/O port
[Segment, common
output]
[Segment,
common output]
Port
[Otherwise]
SEG40 to
SEG37
Keep
COM4 to COM1
[Otherwise]
I/O port
Rev. 2.00 Dec. 05, 2005 Page 701 of 724
REJ09B0200-0200
Appendix
Port Name
MCU
Operating
Mode
Hardware
Power-on Standby
Reset
Mode
Program
Execution State,
Software Standby Mode Sleep Mode
Port B
4 and 5
L
[Address output, OPE = 0] [Address output]
6
T
T
T
A15 to A8
[Address output, OPE = 1] [Segment output]
Keep
[Segment output]
SEG32 to
SEG25
Port
[Otherwise]
[Otherwise]
I/O port
Keep
7
T
T
[Segment output]
[Segment output]
Port
[Otherwise]
SEG32 to
SEG25
Keep
[Otherwise]
I/O port
Port C
4 and 5
L
T
[OPE = 0]
A7 to A0
T
[OPE = 1]
Keep
6
T
T
[Segment output]
[Segment output]
Port
[DDR = 1, OPE = 0]
SEG24 to
SEG17
T
[DDR = 1]
[DDR = 1, OPE = 1]
A7 to A0
Keep
[DDR = 0]
[DDR = 0]
Input port
Keep
7
T
T
[Segment output]
[Segment output]
Port
[Otherwise]
SEG24 to
SEG17
Keep
[Otherwise]
I/O port
Rev. 2.00 Dec. 05, 2005 Page 702 of 724
REJ09B0200-0200
Appendix
Port Name
MCU
Operating
Mode
Hardware
Power-on Standby
Reset
Mode
Program
Execution State,
Software Standby Mode Sleep Mode
Port D
4 to 6
T
T
T
Data bus
7
T
T
[Segment output]
[Segment output]
Port
SEG16 to SEG9
[Otherwise]
[Otherwise]
Keep
I/O port
[Segment output]
[Segment output]
Port
SEG8 to SEG1
[Otherwise]
[Otherwise]
Keep
I/O port
Port E
4 to 6 8-bit
bus
16-bit
bus
7
PF7/φ
4 to 6
7
PF6/AS
4 to 6
T
T
T
T
T
Data bus
T
T
[Segment output]
[Segment output]
Port
SEG8 to SEG1
[Otherwise]
[Otherwise]
Keep
I/O port
[DDR = 0]
[DDR = 0]
T
T
[DDR = 1]
[DDR = 1]
H
Clock output
[OPE = 0]
AS
Clock
output
T
T
H
T
T
[OPE = 1]
H
7
T
T
[Segment output]
[Segment output]
Port
SEG36
[Otherwise]
[Otherwise]
Keep
I/O port
Rev. 2.00 Dec. 05, 2005 Page 703 of 724
REJ09B0200-0200
Appendix
Port Name
PF5/RD,
PF4/HWR
MCU
Operating
Mode
Hardware
Power-on Standby
Reset
Mode
Program
Execution State,
Software Standby Mode Sleep Mode
4 to 6
H
[OPE = 0]
T
RD, HWR
T
[OPE = 1]
H
7
PF3/LWR
4 to 6
T
H
T
T
[Segment output]
[Segment output]
Port
SEG35, SEG34
[Otherwise]
[Otherwise]
Keep
I/O port
[OPE = 0]
LWR
T
[OPE = 1]
H
PF2/WAIT
7
T
T
Keep
I/O port
4 to 6
T
T
[Segment output]
[WAITE = 1]
Port
WAIT
[Otherwise]
Keep
7
T
T
[Segment output]
[Segment output]
Port
SEG33
[Otherwise]
[Otherwise]
Keep
I/O port
PF0
4 to 7
T
T
Keep
I/O port
Port H
4 to 7
T
T
Keep
I/O port
Port J
4 to 7
T
T
Keep
I/O port
Port K
4 to 7
T
T
[PKFE = 0]
[PKFE = 0]
Keep
I/O port
[PKFE = 1]
[PKFE = 1]
PK7:T, PK6:H
PK7:HRxD1
input
PK6:HTxD1
output
Rev. 2.00 Dec. 05, 2005 Page 704 of 724
REJ09B0200-0200
Appendix
Port Name
MCU
Operating
Mode
Hardware
Power-on Standby
Reset
Mode
Program
Execution State,
Software Standby Mode Sleep Mode
RxD
4 to 7
T
T
T
HRxD0 input
TxD
4 to 7
H
T
H
HTxD0 input
[Legend]
H:
High level
L:
Low level
T:
High impedance
Keep: Input port becomes high-impedance, and output port retains state
Port:
Depends on the port setting (input becomes high-impedance)
DDR:
Data direction register
OPE:
Output port enable
WAITE: Wait input enable
Rev. 2.00 Dec. 05, 2005 Page 705 of 724
REJ09B0200-0200
Appendix
B.
Product Code Lineup
Product Code
Mark Code
Package (Renesas
Package Code)
F-ZTAT version
HD64F2649
HD64F2649
144-pin QFP (FP-144G)
Masked ROM
version
HD6432649
HD6432649
Product Type
H8S/2649
Rev. 2.00 Dec. 05, 2005 Page 706 of 724
REJ09B0200-0200
144
e
1
ZD
D
y
*3
bp
36
73
37
72
x
M
ZE
F
Detail F
L
L1
θ
21.8
0.17
bp
θ
L1
L
ZE
ZD
1.0
0.5
1.25
1.25
0.6
0.10
8°
0.10
0.5
y
0.4
0°
0.22
0.27
0.25
3.05
22.2
22.2
Max
x
e
0.15
0.17
c
c1
0.20
0.22
b1
0.12
0.00
A1
0.10
22.0
22.0
21.8
HD
HE
A
20
2.70
A2
20
Nom
Dimension in Millimeters
Min
E
D
Reference
Symbol
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
Terminal cross section
b1
bp
MASS[Typ.]
2.4g
c1
HD
E
*2
109
108
*1
Previous Code
FP-144G/FP-144GV
A2
A1
c
RENESAS Code
PRQP0144KA-A
c
A
HE
C.
JEITA Package Code
P-QFP144-20x20-0.50
Appendix
Package Dimensions
The package dimensions that are shown in the Renesas Semiconductor Package Data Book have
priority.
Figure C.1 FP-144G Package Dimensions
Rev. 2.00 Dec. 05, 2005 Page 707 of 724
REJ09B0200-0200
Appendix
Rev. 2.00 Dec. 05, 2005 Page 708 of 724
REJ09B0200-0200
Main Revisions and Additions in this Edition
Item
Page
Revision (See Manual for Details)
Section 1 Overview
1
Amended
1.1 Features
Body Size
•
20.0 × 20.0 mm
Compact package
Section 12 Watchdog
Timer (WDT)
342
Amended
12.2.2 Timer
Control/Status Register
(TCSR)
Bit
Initial
Bit Name Value
2
CKS2
•
1
0
TCSR_1
R/W
Description
0
R/W
Clock Select 2 to 0
CKS1
0
R/W
CKS0
0
R/W
000: φSUB/2 (cycle: 15.6 ms)
001: φSUB/4 (cycle: 31.3 ms)
010: φSUB/8 (cycle: 62.5 ms)
011: φSUB/16 (cycle: 125 ms)
100: φSUB/32 (cycle: 250 ms)
101: φSUB/64 (cycle: 500 ms)
110: φSUB/128 (cycle: 1 s)
111: φSUB/256 (cycle: 2 s)
Rev. 2.00 Dec. 05, 2005 Page 709 of 724
REJ09B0200-0200
Item
Page
Revision (See Manual for Details)
Section 14 Controller
Area Network (HCAN)
425
Amended
14.3.1 Master Control
Register (MCR)
Bit
Initial
Bit Name Value
R/W
Description
0
MCR0
R/W
Reset Request
1
When this bit is set to 1, the HCAN
requests reset mode transition. For
details, see section 14.4.1, Hardware
and Software Resets.
[Setting conditions]
•
Power-on reset
•
Hardware standby
•
Software standby
•
Writing 1 to this bit (software reset)
[Clearing condition]
•
When 0 is written to this bit while
the GSR3 bit in GSR is 1
14.3.2 General Status
Register (GSR)
427
Amended
Bit
Initial
Bit Name Value
R/W
1
GSR1
R
0
Description
Transmit/Receive Warning Flag
This bit cannot be modified.
[Clearing condition]
•
When TEC < 96 and REC < 96
•
TEC ≥ 256 (bus-off state)
[Setting condition]
•
Rev. 2.00 Dec. 05, 2005 Page 710 of 724
REJ09B0200-0200
When TEC ≥ 96 or REC ≥ 96
Item
Page
14.3.11 Interrupt Register 438
(IRR)
Revision (See Manual for Details)
Amended
Bit
Initial
Bit Name Value
R/W
Description
10
IRR2
R
Remote Frame Request Interrupt Flag
0
Status flag indicating that a remote
frame has been received in a mailbox
(buffer) when the corresponding bit in
MBIMR is 0.
[Setting condition]
•
When remote frame reception is
completed, when corresponding
MBIMR = 0
[Clearing condition]
•
Clearing of all bits in RFPR (remote
request register)
9
IRR1
0
R
Receive Message Interrupt Flag
Status flag indicating that a mailbox
(buffer) has received a message
normally when the corresponding bit in
MBIMR is 0.
[Setting condition]
•
When data frame or remote frame
reception is completed, when
corresponding MBIMR = 0
[Clearing condition]
•
Clearing of all bits in RXPR (receive
complete register)
Rev. 2.00 Dec. 05, 2005 Page 711 of 724
REJ09B0200-0200
Item
Page
14.3.16 Unread Message 444
Status Register (UMSR)
Revision (See Manual for Details)
Amended
Bit
Initial
Bit Name Value
15
UMSR7
0
:
:
:
0
UMSR8
0
R/W
Description
R/(W)* Each bit indicates that the
received message has been
:
overwritten by a new message
R/(W)* before being read.
[Setting condition]
•
When a new message is
received before RXPR is
cleared
[Clearing condition]
•
14.3.18 Message Control 448
(MC0 to MC15)
Writing 1
Amended
Register
Name
MCx[1]
Bit
Bit Name R/W
3 to 0 DLC3 to
DLC0
R/W
Description
Data Length Code
Set the data length of a data
frame or the data length
requested in a remote frame
within the range of 0 to 8 bits.
0000: 0 byte
0001: 1 byte
0010: 2 bytes
0011: 3 bytes
0100: 4 bytes
0101: 5 bytes
0110: 6 bytes
0111: 7 bytes
1xxx: 8 bytes
Rev. 2.00 Dec. 05, 2005 Page 712 of 724
REJ09B0200-0200
Item
Page
Revision (See Manual for Details)
14.4 Operation
454
Amended
14.4.2 Initialization after
Hardware Reset
1-bit time (8–25 time quanta)
Figure 14.8 Detailed
Description of One-Bit
Time
SYNC_SEG
PRSEG
PHSEG2
Time segment 1 (TSEG1)
Time segment 2
(TSEG2)
4–16 time quanta
2–8 time quanta
1 time quantum
Table 14.3 Setting Range 455
for TSEG1 and TSEG2 in
BCR
PHSEG1
Amended
Note: The time quantum values for TSEG1 and TSEG2 are
determined by TSEG value + 1.
* Settable unless BRP = B'000000.
14.8.2 Reset
471
Amended
Therefore, always initialize mailboxes after a power-on reset, a
transition to hardware standby mode, software standby mode,
module stop mode, or watch mode. After a power-on reset,
recovery from software standby mode, or cancellation of
module stop mode, the reset interrupt flag (IRR0) is
automatically set.
Section 16 Motor Control 503
PWM Timer (PWM)
16.3.7 PWM Buffer
Registers A, C, E, G
Amended
Bit
Initial
Bit Name Value
R/W
Description
12
OTS
R/W
Output Terminal Select
0
Holds the data to be sent to bit
12 in PWDTR.
16.5 Operation
16.5.1 PWM Operation
Activation:
506
Amended
Activation: Setting the CST bit in PWCR to 1 starts counting by
PWCNT. When a compare match between PWCNT and
PWCYR occurs, data is transferred from the buffer register to
the duty register and the CMF bit in PWCR is set to 1. If the IE
bit in PWCR has been set to 1 at this time, an interrupt can be
requested or the DTC can be activated.
Rev. 2.00 Dec. 05, 2005 Page 713 of 724
REJ09B0200-0200
Item
Page
Revision (See Manual for Details)
Figure 16.8 Disabling
Buffer Transfer
507
Amended
PWBTCR
Section 17 LCD
Controller/Driver
510
Disabled: 1
Disabled
Enabled
Enabled: 0
Amended
17.1 Features
Figure 17.1 Block
Diagram of LCD
Controller/Driver
17.3.2 LCD Control
Register (LCR)
φ/8 to φ/2048
516
Amended
1
Frame Frequency*
Table 17.4 Frame
Frequency Selection
Section 19 ROM
19.6.1 Boot Mode
CL2
φw
542,
543
Operating Clock
φ = 20 MHz
φ/8
4880 Hz
φ/16
2440 Hz
Amended
2. SCI_1 should be set to asynchronous mode, and the
transfer format as follows: 8-bit data, 1 stop bit, and no
parity.
5. In boot mode, a part of the on-chip RAM area is used by the
boot program. The area H'FFE800 to H'FFEFBF is the area
to which the …
Table 19.5 System Clock 544
Frequencies for which
Automatic Adjustment of
LSI Bit Rate is Possible
19.7 Flash Memory
Emulation in RAM
547
Amended
Host Bit Rate
System Clock Frequency Range
of this LSI
19,200 bps
20 MHz
9,600 bps
8 to 20 MHz
4,800 bps
4 to 20 MHz
Amended
1. The RAM area to be overlapped is fixed at a 4-kbyte area in
the range H'FFD800 to H'FFE7FF.
Rev. 2.00 Dec. 05, 2005 Page 714 of 724
REJ09B0200-0200
Item
Page
Revision (See Manual for Details)
Figure 19.8 Example of
RAM Overlap Operation
548
Amended
H'FFD800
On-chip RAM
(4 kbytes)
On-chip RAM
(4 kbytes)
Normal memory map
RAM overlap memory map
H'FFE7FF
19.11 Programmer Mode 554
Amended
… Use a PROM programmer which supports the Renesas 256kbyte flash memory on-chip microcomputer device type
(FZTAT256V5A).
Section 21 Power-Down
Modes
570
Amended
Medium-
Table 21.1 LSI Internal
States in Each Mode
Function
Peripheral
SCI0 to
functions
SCI2
Module
Software
Hardware
High-Speed
Speed
Sleep
Stop
Watch
Subactive
Subsleep
Standby
Standby
Functioning
Functioning
Functioning
Halted
Halted
Halted
Halted
Halted
Halted
(retained/
(retained/
(retained/
(retained/
(reset)
(reset)
reset)
reset)
reset)
reset)
Halted
Halted
Halted
Halted
Halted
Halted
(reset)
(reset)
(reset)
(reset)
(reset)
(reset)
SCI4
PWM
Functioning
Functioning
Functioning
HCAN
A/D
21.1.1 Standby Control
Register (SBYCR)
575
The column of "2 MHz" removed
579
Amended
Table 21.3 Standby Time
Settings
21.1.3 Module Stop
Control Registers A to D
•
MSTPCRD
Bit
Initial
Value
R/W
2
1
R/W
2
1
R/W
Bit Name
4
MSTPD4*
2
MSTPD2*
Module
Rev. 2.00 Dec. 05, 2005 Page 715 of 724
REJ09B0200-0200
Item
Page
Revision (See Manual for Details)
Section 22 List of
Registers
667,
673,
674
Amended
22.3 Register States in
Each Operating Mode
Register
Abbrevia-
Module
tion
Stop
Watch
Subactive
Subsleep Standby
Standby
Module
SMR_4
−
−
−
−
−
Initialized
SCI_4
BRR_4
−
−
−
−
−
Initialized
SCR_4
−
−
−
−
−
Initialized
SCMR_4
−
−
−
−
−
Initialized
SMR_0
−
−
−
−
−
Initialized
BRR_0
−
−
−
−
−
Initialized
SCR_0
−
−
−
−
−
Initialized
SCMR_0
−
−
−
−
−
Initialized
SMR_1
−
−
−
−
−
Initialized
BRR_1
−
−
−
−
−
Initialized
SCR_1
−
−
−
−
−
Initialized
SCMR_1
−
−
−
−
−
Initialized
SMR_2
−
−
−
−
−
Initialized
BRR_2
−
−
−
−
−
Initialized
SCR_2
−
−
−
−
−
Initialized
SCMR_2
−
−
−
−
−
Initialized
Rev. 2.00 Dec. 05, 2005 Page 716 of 724
REJ09B0200-0200
Software Hardware
SCI_0
SCI_1
SCI_2
Item
Page
Revision (See Manual for Details)
Section 23 Electrical
Characteristics
[Preliminary]
677,
678
Amended
Test
Item
23.2 DC Characteristics
Symbol Min.
Output high PWM1A to PWM1H,
Table 23.2 DC
Characteristics
voltage
PWM2A to PWM2H
Output low
All output pins
voltage
except
VOH
Typ. Max. Unit Conditions
PWMVCC —
—
V
IOH = –15 mA
V
IOL = 1.6 mA
– 0.5
VOL
—
—
0.4
—
—
0.5
PWM1A to PWM1H,
PWM2A to PWM2H
PWM1A to PWM1H,
IOL = 15 mA
PWM2A to PWM2H
679
Amended
Item
Min.
Max.
Current
2
consumption*
Normal operation
—
80
Sleep mode
—
65
LCD power supply
port power supply
current
During operation
—
20
Standby mode
—
10
—
80
2.0
—
RAM standby voltage
Notes: 3. ICC depends on VCC and f as follows:
ICC max. = 31 (mA) + 0.45 (mA/(MHz × V)) × VCC × f
(normal operation)
ICC max. = 27 (mA) + 0.35 (mA/(MHz × V)) × VCC × f
(sleep mode)
Rev. 2.00 Dec. 05, 2005 Page 717 of 724
REJ09B0200-0200
Item
Page
Revision (See Manual for Details)
23.3.1 Clock Timing
682
Amended
Table 23.4 Clock Timing
Item
Symbol
Subclock oscillator settling time
Subclock (φSUB) cycle time
23.4 A/D Conversion
Characteristics
696
23.5 LCD Characteristics 697
Table 23.9 LCD
Characteristics
705
A. I/O Port States in Each
Operating State
C. Package Dimensions
tSUB
Amended
707
Item
Min.
Typ.
Max.
Unit
Resolution
10
10
10
bits
Conversion time
10
—
200
µs
Amended
Item
Max.
Notes
Common driver step-down voltage
0.3
*
Amended
Port Name
Power-on Reset
TxD
H
Replaced
Figure C.1 FP-144G
Package Dimensions
Rev. 2.00 Dec. 05, 2005 Page 718 of 724
REJ09B0200-0200
s
Condition
Table 23.8
A/D Conversion
Characteristics
Appendix
Unit
1
Index
Numerics
B
16-Bit Timer Pulse Unit (TPU) .............. 229
Buffer Operation................................. 276
Cascaded Operation ............................ 280
Free-running count operation.............. 269
Input Capture ...................................... 272
periodic count operation ..................... 269
Phase Counting Mode......................... 287
PWM Modes....................................... 282
Synchronous Operation ...................... 274
toggle output ....................................... 270
Waveform Output
by Compare Match ............................. 270
Bcc ...................................................... 31, 39
Bit Rate ................................................... 454
Break address ...................................... 93, 96
Break conditions ....................................... 96
Bus Controller......................................... 103
Basic Bus Interface ............................. 115
Basic Timing............................... 118, 127
Burst ROM Interface........................... 127
Bus Arbitration.................................... 134
Data Size and Data Alignment............ 115
Idle Cycle............................................ 130
Valid Strobes....................................... 117
Wait Control ....................................... 125
Write Data Buffer Function ................ 133
A
A/D Converter ........................................ 475
A/D Converter Activation................... 295
Conversion Time ................................ 483
External Trigger.................................. 485
Scan Mode .......................................... 482
Single Mode........................................ 482
Address Map............................................. 58
Address Space........................................... 22
Addressing Modes .................................... 43
Absolute Address.................................. 44
Immediate ............................................. 45
Memory Indirect ................................... 45
Program-Counter Relative .................... 45
Register Direct...................................... 43
Register Indirect ................................... 43
Register Indirect
with Displacement ................................ 44
Register Indirect
with Post-Increment.............................. 44
Register Indirect
with Pre-Decrement .............................. 44
C
Clock Pulse Generator ............................ 559
Condition Field ......................................... 42
Condition-Code Register (CCR) ............... 26
CPU Operating Modes.............................. 18
Advanced Mode .................................... 20
Normal Mode ........................................ 18
D
Data Transfer Controller ......................... 137
Activation by Software ....................... 158
Block Transfer Mode .......................... 152
Chain Transfer ............................ 154, 160
DTC Vector Table............................... 146
Normal Mode .............................. 150, 159
Register Information ........................... 146
Repeat Mode ....................................... 151
software activation .............................. 155
Software Activation ............................ 161
Rev. 2.00 Dec. 05, 2005 Page 719 of 724
REJ09B0200-0200
Control field........................................ 458
Data field ............................................ 458
Data frame .......................................... 463
DTC Interface ..................................... 469
HCAN Halt Mode............................... 467
HCAN Sleep Mode............................. 464
mailbox ............................................... 447
Message Control (MC0 to MC15) ...... 447
Message Data (MD0 to MD15) .......... 449
Message transmission cancellation ..... 459
Message Transmission Method........... 456
Remote frame...................................... 463
remote transmission request bit........... 463
Unread message overwrite.................. 463
vector number for the software
activation interrupt.............................. 144
E
Effective Address ............................... 43, 46
Effective Address Extension..................... 42
Exception Handling .................................. 59
Interrupts............................................... 65
Reset Exception Handling .................... 61
Stack Status .......................................... 67
Traces ................................................... 64
Trap Instruction .................................... 66
Extended Control Register (EXR) ............ 25
F
Flash memory ......................................... 529
Boot mode .......................................... 542
Emulation ........................................... 546
Erase/erase-verify ............................... 551
Erasing units ....................................... 534
Error protection .................................. 553
Hardware protection ........................... 553
Program/program-verify..................... 549
Software protection............................. 553
User program mode ............................ 545
G
General Registers...................................... 24
H
HCAN..................................................... 421
11 consecutive recessive bits .............. 451
Arbitration field .......................... 458, 462
buffer segment .................................... 454
Configuration mode............................ 451
Rev. 2.00 Dec. 05, 2005 Page 720 of 724
REJ09B0200-0200
I
Instruction Set ........................................... 31
Arithmetic Operations Instructions....... 34
Bit Manipulation Instructions ............... 37
Block Data Transfer Instructions .......... 41
Branch Instructions ............................... 39
Data Transfer Instructions..................... 33
Logic Operations Instructions............... 36
Shift Instructions................................... 36
System Control Instructions.................. 40
Interrupt Control Modes ........................... 83
Interrupt Controller ................................... 69
Interrupt Exception Handling
Vector Table ............................................. 79
Interrupt Mask Bit..................................... 26
interrupt mask level .................................. 25
interrupt priority register (IPR) ................. 69
Interrupts
ADI ..................................................... 485
ERS0/OVR0........................................ 468
NMI....................................................... 78
RM0 .................................................... 468
RM1 .................................................... 468
SLE0 ................................................... 468
SWDTEND......................................... 155
TCIU_1............................................... 294
TCIU_2............................................... 294
TCIU_4............................................... 294
TCIU_5............................................... 294
TCIV_0............................................... 294
TCIV_1............................................... 294
TCIV_2............................................... 294
TCIV_3............................................... 294
TCIV_4............................................... 294
TCIV_5............................................... 294
TGIA_0............................................... 294
TGIA_1............................................... 294
TGIA_2............................................... 294
TGIA_3............................................... 294
TGIA_4............................................... 294
TGIA_5............................................... 294
TGIB_0............................................... 294
TGIB_1............................................... 294
TGIB_2............................................... 294
TGIB_3............................................... 294
TGIB_4............................................... 294
TGIB_5............................................... 294
TGIC_0............................................... 294
TGIC_3............................................... 294
TGID_0............................................... 294
TGID_3............................................... 294
WOVI ................................................. 346
L
LCD controller/driver ............................. 509
Common drivers ................................. 513
Duty cycle........................................... 509
LCD display........................................ 518
LCD RAM .......................................... 520
List of registers ....................................... 591
M
MAC instruction ....................................... 55
Motor Control PWM Timer .................... 493
PWM Channel..................................... 506
Multiply-Accumulate Register (MAC) ..... 27
O
On-board programming .......................... 542
Operating Mode Selection ........................ 53
Operation Field ......................................... 42
P
PC Break Controller.................................. 93
PLL Circuit ............................................. 565
Power-Down Modes ............................... 569
Direct Transitions................................ 588
Hardware Standby Mode .................... 584
Medium-Speed Mode.......................... 580
Module Stop Mode ............................. 587
Sleep Mode ......................................... 581
Software Standby Mode...................... 582
Subactive Mode .................................. 586
Subsleep Mode.................................... 586
Watch Mode........................................ 585
Program Counter (PC) .............................. 25
Program/erase protection ........................ 553
Programmable Pulse Generator .............. 315
Non-Overlapping Pulse Output........... 329
output trigger....................................... 323
Programmer mode................................... 554
R
Register addresses................................... 592
Register bits ............................................ 620
Register Field............................................ 42
Register states in each operating mode ... 648
Rev. 2.00 Dec. 05, 2005 Page 721 of 724
REJ09B0200-0200
Registers
ABACK .......................434, 592, 620, 648
ABWCR ......................106, 615, 644, 671
ADCR..........................481, 618, 647, 674
ADCSR........................479, 618, 647, 674
ADDR..........................478, 618, 647, 674
ASTCR ........................106, 615, 644, 671
BARA............................94, 612, 640, 668
BARB ............................95, 612, 641, 668
BCR .............................427, 592, 620, 648
BCRA ............................95, 612, 641, 668
BCRB ............................96, 612, 641, 668
BCRH ..........................109, 615, 644, 671
BCRL...........................110, 615, 644, 671
BRR .............................366, 617, 646, 673
CRA.................................................... 142
CRB .................................................... 142
DAR.................................................... 142
DTCER........................143, 612, 641, 668
DTVECR .....................144, 612, 641, 668
EBR1 ...........................539, 618, 647, 674
EBR2 ...........................540, 618, 647, 674
FLMCR1......................537, 618, 647, 674
FLMCR2......................538, 618, 647, 674
FLPWCR .....................541, 618, 647, 674
GSR .............................426, 592, 620, 648
HCANMON ................450, 601, 629, 657
IER.................................74, 612, 641, 668
IMR .............................442, 592, 620, 648
IPR.................................73, 615, 643, 671
IRR ..............................437, 592, 620, 648
ISCR ..............................75, 612, 641, 668
ISR.................................77, 612, 641, 668
LAFM..........................444, 592, 621, 648
LCR .............................515, 611, 640, 667
LCR2 ...........................517, 611, 640, 667
LPCR ...........................512, 611, 640, 667
LPWRCR.....................576, 612, 640, 668
MBCR .........................430, 592, 620, 648
MBIMR .......................441, 592, 620, 648
Rev. 2.00 Dec. 05, 2005 Page 722 of 724
REJ09B0200-0200
MC .............................. 447, 592, 621, 648
MCR ........................... 425, 592, 620, 648
MD.............................. 449, 597, 625, 652
MDCR........................... 54, 612, 640, 667
MRA ................................................... 140
MRB ................................................... 141
MSTPCR..................... 578, 612, 640, 667
NDER ......................... 318, 612, 641, 668
NDR............................ 320, 612, 641, 668
P1DDR........................ 168, 613, 642, 669
P1DR........................... 169, 615, 644, 671
P2DDR........................ 178, 613, 642, 669
P2DR........................... 179, 615, 644, 671
P3DDR........................ 188, 613, 642, 669
P3DR........................... 189, 615, 644, 671
P3ODR........................ 190, 613, 642, 669
P5DDR........................ 194, 613, 642, 669
P5DR........................... 194, 616, 644, 671
PADDR....................... 197, 613, 642, 669
PADR.......................... 198, 616, 644, 671
PAODR....................... 199, 613, 642, 669
PAPCR........................ 199, 613, 642, 669
PBDDR ....................... 202, 613, 642, 669
PBDR.......................... 203, 616, 644, 671
PBODR ....................... 204, 613, 642, 669
PBPCR........................ 204, 613, 642, 669
PCDDR ....................... 206, 613, 642, 669
PCDR.......................... 207, 616, 644, 671
PCODR ....................... 208, 613, 642, 669
PCPCR........................ 208, 613, 642, 669
PCR............................. 323, 612, 641, 668
PDDDR....................... 210, 613, 642, 669
PDDR.......................... 211, 616, 644, 671
PDPCR........................ 212, 613, 642, 669
PEDDR ....................... 214, 613, 642, 669
PEDR .......................... 215, 616, 644, 671
PEPCR ........................ 216, 613, 642, 669
PFCR........................... 111, 612, 640, 667
PFDDR ....................... 218, 613, 642, 669
PFDR .......................... 219, 616, 644, 671
PHDDR....................... 223, 611, 639, 667
PHDR ......................... 224, 611, 639, 667
PJDDR........................ 225, 611, 639, 667
PJDR........................... 226, 611, 639, 667
PKDDR....................... 227, 611, 639, 667
PKDR ......................... 228, 611, 639, 667
PMR............................ 324, 612, 641, 668
PODR ......................... 319, 612, 641, 668
PORT1........................ 169, 619, 647, 674
PORT2........................ 179, 619, 647, 674
PORT3........................ 189, 619, 647, 674
PORT4........................ 193, 619, 647, 674
PORT5........................ 195, 619, 647, 674
PORT9........................ 196, 619, 647, 674
PORTA ....................... 198, 619, 647, 674
PORTB ....................... 203, 619, 647, 674
PORTC ....................... 207, 619, 647, 674
PORTD ....................... 211, 619, 647, 674
PORTE ............................................... 215
PORTF........................ 219, 619, 647, 674
PORTH ....................... 224, 611, 639, 667
PORTJ ........................ 226, 611, 640, 667
PORTK ....................... 228, 611, 640, 667
PWBFR....................... 503, 610, 639, 666
PWBTCR.................... 504, 611, 640, 667
PWCNT .............................................. 499
PWCR......................... 497, 610, 638, 666
PWCYR...................... 499, 610, 639, 666
PWDTR .............................................. 500
PWOCR...................... 498, 610, 638, 666
PWPR ......................... 499, 610, 638, 666
RAMER...................... 540, 615, 644, 671
RDR............................ 354, 617, 646, 673
REC ............................ 443, 592, 620, 648
RFPR .......................... 436, 592, 620, 648
RSR..................................................... 354
RSTCSR ..................... 343, 617, 646, 673
RXPR.......................... 435, 592, 620, 648
SAR .................................................... 142
SBYCR ....................... 573, 611, 640, 667
SCKCR ....................... 560, 611, 640, 667
SCMR ......................... 365, 617, 646, 673
SCR............................. 358, 617, 646, 673
SMR ............................ 355, 617, 646, 673
SSR ............................. 361, 617, 646, 673
SYSCR.......................... 55, 611, 640, 667
TCNT ......................... 266, 339, 616, 617,
645, 646, 672, 673
TCR............................. 237, 616, 644, 672
TCSR .......................... 339, 617, 646, 673
TDR ............................ 355, 617, 646, 673
TEC............................. 443, 592, 620, 648
TGR ............................ 266, 616, 645, 672
TIER............................ 261, 616, 645, 672
TIOR ........................... 244, 616, 644, 672
TMDR......................... 242, 616, 644, 672
TSR ..................... 263, 355, 616, 645, 672
TSTR........................... 266, 615, 643, 670
TSYR .......................... 267, 615, 643, 670
TXACK....................... 433, 592, 620, 648
TXCR.......................... 432, 592, 620, 648
TXPR .......................... 431, 592, 620, 648
UMSR ......................... 444, 592, 621, 648
WCR ........................... 107, 615, 644, 671
Reset ......................................................... 61
S
Serial Communication Interface ............. 351
Asynchronous Mode ........................... 373
bit rate ................................................. 366
Break................................................... 414
framing error ....................................... 380
Mark State........................................... 414
overrun error ....................................... 380
parity error .......................................... 380
Stack pointer (SP) ..................................... 24
Rev. 2.00 Dec. 05, 2005 Page 723 of 724
REJ09B0200-0200
T
W
Time Quanta (TQ) .................................. 455
Trace Bit ................................................... 25
TRAPA instruction ............................. 45, 66
Watchdog Timer
Interval Timer Mode ........................... 346
Overflows ........................................... 344
Watchdog Timer (WDT)......................... 337
Rev. 2.00 Dec. 05, 2005 Page 724 of 724
REJ09B0200-0200
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8S/2649 Group
Publication Date: Rev.1.00, Sep. 17, 2004
Rev.2.00, Dec. 05, 2005
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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Colophon 5.0
H8S/2649 Group
Hardware Manual