MOTOROLA MC56F8345 56f8345 16-bit hybrid controller Datasheet

Freescale Semiconductor, Inc.
MC56F8345/D
Rev. 8.0, 6/2004
56F8345
Preliminary Technical Data
• Up to 60 MIPS at 60MHz core frequency
• Two Quadrature Decoders
• DSP and MCU functionality in a unified,
C-efficient architecture
• FlexCAN module
• 128KB Program Flash
• Two Serial Communication Interfaces (SCIs)
• 4KB Program RAM
• Up to two Serial Peripheral Interface (SPIs)
• 8KB Data Flash
• Up to four general-purpose Quad Timers
• 8KB Data RAM
• Computer Operating Properly (COP)/Watchdog
• 8KB Boot Flash
• Two 6-channel PWM modules
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Four 4-channel, 12-bit ADCs
• Up to 49 GPIO lines
• Temperature Sensor
• 128-pin LQFP Package
• Optional On-Chip Regulator
RSTO
5
RESET
6 PWM Outputs
JTAG/
EOnCE
Port
PWMA
Current Sense Inputs
or GPIOC
3
4
VPP
VCAP
2
4
3
PWMB
Current Sense Inputs
or GPIOD
4
Fault Inputs
4
AD0
ADCA
4
Memory
5
VREF
4
AD0
Program Memory
64K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
4
AD1
TEMP_SENSE
4
4
2
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SP1I or
GPIOC
Quad Timer
C or GPIOE
4
Quad Timer
D or GPIOE
2
FlexCAN
VDDA
VSSA
2
Analog Reg
Low Voltage
Supervisor
Data ALU
16 x 16 + 36 -->36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
AD1
ADCB
5
Digital Reg
Address
Generation Unit
Program Controller
and Hardware
Looping Unit
7
16-Bit
56800E Core
Fault Inputs
6 PWM Outputs
OCR_DIS
VDD
VSS
R/W Control
Data Memory
4K x 16 Flash
4K x 16 RAM
XDB2
XAB1
XAB2
External Bus
Interface Unit
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56F8345 16-bit Hybrid Controller
PAB
System Bus
Control
PDB
CDBR
CDBW
* External
Address Bus
Switch
* External
Data
Bus Switch
* Bus
Control
6
A8-13 or GPIOA0-5
5
GPIOB0-4 or A16-20
4
D7-10 or GPIOF0-3
6
GPIOD0-5 or CS2-7
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
Control
Decoding
Peripherals
IPAB
IPWDB
IPRDB
Clock
resets
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
COP/
Interrupt
Watchdog Controller
P
System
O
Integration R
Module
PLL
Clock O
S
Generator C
2
IRQA IRQB
CLKO
CLKMODE
56F8345 Block Diagram - 128 LQFP
© Motorola, Inc., 2004. All rights reserved.
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* EMI not functional in
this package; use as
GPIO pins
XTAL
EXTAL
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Document Revision History
Version History
Description of Change
Rev 1.0
Pre-Release version, Alpha customers only
Rev 2.0
Initial Public Release
Rev 3.0
Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles.
Addressed additional grammar issues
Rev 4.0
Added “Typical Min” values to Table 10-16
Freescale Semiconductor, Inc...
Editing grammar, spelling, consistency of language throughout family
Updated values in Current Consumption per Power Supply Pin, Table 10-7, Regulator
Parameters, Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI
Timing, Table 10-17, ADC Parameters, Table 10-23, and IO Loading Coefficients at 10MHz,
Table 10-24.
Rev 5.0
Added Section 4.8 Factory Programmed Memory,
added the word “access” to FM Error Interrupt in Table 4-5,
removed min and max numbers; clarified CSBAR 0 and CSBAR 1 reset values in Table 4-10,
removed min and max numbers; only documenting Typ. numbers for LVI in Table 10-6.
Rev 6.0
Updated numbers in Table 10-7 and Table 10-8 with more recent data,
Corrected typo in Table 10-3 in Pd characteristics.
Rev 7.0
Replace any reference to Flash Interface Unit with Flash Memory Module, added note to
Vcap pin in Table 2-3, removed unneccessary notes in Table 10-12; corrected temperature
range in Table 10-14; added ADC calibration information to Table 10-23; and new graphs in
Figure 10-21.
Rev 8.0
Clarification to Table 10-22, corrected Digital Input Current Low (pull-up enabled)
numbers in Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1.
2
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56F8345 Technical Data
Preliminary
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56F8345 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . 4
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1.1. 56F8345 Features . . . . . . . . . . . . . . . . . . 4
1.2. 56F8345 Description . . . . . . . . . . . . . . . . 5
1.3. Award-Winning Development
Environment . . . . . . . . . . . . . . . 6
1.4. Architecture Block Diagram . . . . . . . . . . . 7
1.5. Product Documentation . . . . . . . . . . . . . 10
1.6. Data Sheet Conventions . . . . . . . . . . . . 11
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . 114
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . 114
8.2. Configuration . . . . . . . . . . . . . . . . . . . . 114
8.3. Memory Maps . . . . . . . . . . . . . . . . . . . 118
Part 9: Joint Test Action Group (JTAG) 118
9.1. 56F8345 Information . . . . . . . . . . . . . . 118
Part 2: Signal/Connection Descriptions 12
Part 10: Specifications . . . . . . . . . . . . . 118
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 12
2.2. 56F8345 Signal Pins . . . . . . . . . . . . . . . 14
10.1. General Characteristics . . . . . . . . . . . 118
10.2. DC Electrical Characteristics . . . . . . . 122
10.3. Temperature Sense . . . . . . . . . . . . . . 125
10.4. AC Electrical Characteristics . . . . . . . 125
10.5. Flash Memory Characteristics . . . . . . 126
10.6. External Clock Operation Timing . . . . 127
10.7. Phase Locked Loop Timing . . . . . . . . 127
10.8. Crystal Oscillator Timing . . . . . . . . . . 128
10.9. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . 128
10.10. Serial Peripheral Interface (SPI)
Timing . . . . . . . . . . . . . . . . . . 130
10.11. Quad Timer Timing . . . . . . . . . . . . . 133
10.12. Quadrature Decoder Timing . . . . . . . 133
10.13. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . 134
10.14. Controller Area Network (CAN)
Timing . . . . . . . . . . . . . . . . . . 135
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . 135
10.16. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . 137
10.17. Equivalent Circuit for ADC Inputs . . . 139
10.18. Power Consumptio . . . . . . . . . . . . n 139
Part 3: On-Chip Clock Synthesis (OCCS) 29
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 29
3.2. External Clock Operation . . . . . . . . . . . 30
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . 31
Part 4: Memory Map . . . . . . . . . . . . . . . . 32
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Program Map . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Table . . . . . . . . . . . . . .
Data Map . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Map . . . . . . . . . . . . . . . .
EOnCE Memory Map . . . . . . . . . . . . . .
Peripheral Memory Mapped Registers .
Factory Programmed Memory . . . . . . . .
32
33
34
38
38
40
41
65
Part 5: Interrupt Controller (ITCN) . . . . . 66
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . .
66
66
66
68
68
69
93
Part 6: System Integration Module (SIM) 94
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
Introduction . . . . . . . . . . . . . . . . . . . . . . 94
Features . . . . . . . . . . . . . . . . . . . . . . . . 94
Operating Modes . . . . . . . . . . . . . . . . . . 95
Operating Mode Register . . . . . . . . . . . 95
Register Descriptions . . . . . . . . . . . . . . 96
Clock Generation Overview . . . . . . . . 109
Power-Down Modes Overview . . . . . . 109
Stop and Wait Mode Disable
Function . . . . . . . . . . . . . . . . 110
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . 110
Part 11: Packaging . . . . . . . . . . . . . . . . 141
11.1. Package and Pin-Out Information
56F8345 . . . . . . . . . . . . . . . . 141
Part 12: Design Considerations . . . . . . 144
12.1. Thermal Design Considerations . . . . . 144
12.2. Electrical Design Considerations . . . . 145
12.3. Power Distribution and I/O Ring
Implementation
146
Part 13: Ordering Information . . . . . . . 147
Part 7: Security Features . . . . . . . . . . . 111
7.1. Operation with Security Enabled . . . . . 111
7.2. Flash Access Blocking Mechanisms . . 111
Please see http://www.motorola.com/semiconductors for the most current Data Sheet revision.
56F8345 Technical Data
Preliminary
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Part 1 Overview
1.1 56F8345 Features
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1.1.1
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1.1.2
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Digital Signal Processing Core
Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture
As many as 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security protection feature
On-chip memory, including a low-cost, high-volume Flash solution
— 128KB of Program Flash
— 4KB of Program RAM
— 8KB of Data Flash
— 8KB of Data RAM
— 8KB of Boot Flash
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1.1.3
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4
EEPROM emulation capability
Peripheral Circuits for 56F8345
Two Pulse Width Modulator modules, each with six PWM outputs, three Current Sense inputs, and
four Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and
edge-aligned modes
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions
with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer
C, channels 2 and 3
Two four-input Quadrature Decoders or two additional Quad Timers
Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the
on-chip temperature
Four dedicated general-purpose Quad Timers totaling six dedicated pins: Timer C with two pins and
Timer D with four pins
Optional On-Chip Regulator
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56F8345 Technical Data
Preliminary
Freescale Semiconductor, Inc.
56F8345 Description
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1.1.4
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FlexCAN (CAN Version 2.0 B-compliant) module with 2-pin port for transmit and receive
Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)
Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional
GPIO lines); SPI 1 can also be used as Quadrature Decoder 1 or Quad Timer B
Computer Operating Properly (COP)/Watchdog timer
Two dedicated external interrupt pins
49 General Purpose I/O (GPIO) pins; 21 pins dedicated to GPIO
External reset input pin for hardware reset
External reset output pin for system reset
Integrated low-voltage interrupt module
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent,
real-time debugging
Software-programmable, Phase Lock Loop-based frequency synthesizer for the core clock
Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be
disabled
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
1.2 56F8345 Description
The 56F8345 is a member of the 56800E core-based family of hybrid controllers. It combines, on
a single chip, the processing power of a DSP and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56F8345 is well-suited for many
applications. The 56F8345 includes many peripherals that are especially useful for motion control,
smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,
automotive control, engine management, noise suppression, remote utility metering, industrial
control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient,
compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to
enable rapid development of optimized control applications.
The 56F8345 supports program execution from internal memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. The 56F8345 also provides two
external dedicated interrupt lines and up to 49 General Purpose Input/Output (GPIO) lines,
depending on peripheral configuration.
The 56F8345 hybrid controller includes 128KB of Program Flash and 8KB of Data Flash (each
programmable through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM.
A total of 8KB of Boot Flash is incorporated for easy customer-inclusion of field-programmable
56F8345 Technical Data
Preliminary
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software routines that can be used to program the main Program and Data Flash memory areas.
Both Program and Data Flash memories can be independently bulk erased or erased in pages.
Program Flash page erase size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot
Flash memory can also be either bulk or page erased.
A key application-specific feature of the 56F8345 is the inclusion of two Pulse Width Modulator
(PWM) modules. These modules each incorporate three complementary, individually
programmable PWM signal output pairs (each module is also capable of supporting six
independent PWM functions, for a total of 12 PWM outputs) to enhance motor control
functionality. Complementary operation permits programmable dead time insertion, distortion
correction via current sensing by software, and separate top and bottom output polarity control. The
up-counter value is programmable to support a continuously variable PWM frequency.
Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors);
both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable
Reluctance Motors); and stepper motors. The PWMs incorporate fault protection and
cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard
optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included.
A patented PWM waveform distortion correction circuit is also provided. Each PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable
from 1 to 16. The PWM modules provide reference outputs to synchronize the Analog-to-Digital
Converters through two channels of Quad Timer C.
The 56F8345 incorporates two Quadrature Decoders capable of capturing all four transitions on
the two-phase inputs, permitting generation of a number proportional to actual position. Speed
computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog
timer in the Quadrature Decoder can be programmed with a time-out value to alert when no shaft
motion is detected. Each input is filtered to ensure only true transitions are recorded.
This hybrid controller also provides a full set of standard programmable peripherals that include
two Serial Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and four
Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if
that function is not required. A Flex Controller Area Network (FlexCAN) interface (CAN Version
2.0 B-compliant) and an internal interrupt controller are also a part of the 56F8345.
1.3 Award-Winning Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines
easy-to-use component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development
system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a
complete, scalable tools solution for easy, fast, and efficient development.
6
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56F8345 Technical Data
Preliminary
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Architecture Block Diagram
1.4 Architecture Block Diagram
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The 56F8345 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the
56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-1 lists
the internal buses in the 56800E architecture and provides a brief description of their function.
Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. The figures
do not show the on-board regulator and power and ground signals. They also do not show the
multiplexing between peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection
Descriptions, to see which signals are multiplexed with those of other peripherals.
Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These
connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions.
The Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its
conversions. In another operating mode, the PWM load interrupt (SYNC output) signal is routed
internally to the Timer C input channel as indicated. The timer can then be used to introduce a
controllable delay before generating its output signal. The timer output then triggers the ADC. To
fully understand this interaction, please see the 56F8300 Peripheral User’s Manual for
clarification on the operation of all three of these peripherals.
56F8345 Technical Data
Preliminary
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5
JTAG / EOnCE
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Boot
Flash
pdb_m[15:0]
pab[20:0]
Program
Flash
cdbw[31:0]
Program
RAM
56800E
EMI*
11
Address
CHIP
TAP
Controller
4
Data
6
Control
TAP
Linking
Module
Data RAM
xab1[23:0]
xab2[23:0]
Data Flash
External JTAG
Port
cdbr_m[31:0]
xdb2_m[15:0]
To Flash
Control Logic
IPBus
Bridge
* EMI not functional in this
package; since only part of the
address/data bus is bonded out,
use as GPIO pins
Flash
Memory
Module
IPBus
Figure 1-1 System Bus Interfaces
Note:
Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are
completed between the core and the Flash memories.
Note:
The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
8
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56F8345 Technical Data
Preliminary
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Architecture Block Diagram
To/From IPBus Bridge
Interrupt
Controller
CLKGEN
(OSC / PLL)
Low-Voltage Interrupt
Timer A
POR & LVI
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4
System POR
Quadrature Decoder 0
4
RESET
SIM
Timer D
COP Reset
Timer B
4
COP
2
FlexCAN
Quadrature Decoder 1
SPI1
13
PWMA
GPIOA
SYNC Output
13
PWMB
GPIOB
SYNC Output
GPIOC
ch3i
ch2i
2
Timer C
GPIOD
ch3o
ch2o
GPIOE
GPIOF
4
2
SPI0
8
ADCA
SCI0
TEMP_SENSE
2
8
ADCB
1
SCI1
IPBus
Note: ADC A and ADC B use the same
voltage reference circuit with VREFH,
VREFP, VREFMID, VREFN, and VREFLO
pins.
Figure 1-2 Peripheral Subsystem
56F8345 Technical Data
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Table 1-1 Bus Signal Names
Name
Function
Program Memory Interface
pdb_m[15:0]
Program data bus for instruction word fetches or read operations.
cdbw[15:0]
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
pab[20:0]
Program memory address bus. Data is returned on pdb_m bus.
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Primary Data Memory Interface Bus
cdbr_m[31:0]
Primary core data bus for memory reads. Addressed via xab1 bus.
cdbw[31:0]
Primary core data bus for memory writes. Addressed via xab1 bus.
xab1[23:0]
Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
Secondary Data Memory Interface
xdb2_m[15:0]
Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0]
Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
IPBus [15:0]
Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0.
1.5 Product Documentation
The documents listed in Table 1-2 are required for a complete description and proper design with
the 56F8345. Documentation is available from local Motorola distributors, Motorola
semiconductor sales offices, Motorola Literature Distribution Centers, or online at
http://www.motorola.com/semiconductors.
Table 1-2 56F8345 Chip Documentation
Topic
Description
Order Number
DSP56800E
Reference Manual
Detailed description of the 56800E family architecture,
16-bit hybrid controller core processor, and the
instruction set
DSP56800ERM/D
56F8300 Peripherals
Manual
Detailed description of peripherals of the 56F8300
family of devices
MC56F8300UM/D
56F8300 SCI/CAN
Bootloader User Manual
Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices
MC56F83xxBLUM/D
56F8345
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
device specific peripheral information and package
descriptions (this document)
MC56F8345/D
56F8345
Product Brief
Summary description and block diagram of the
56F8345 core, memory, peripherals and interfaces
MC56F8345PB/D
56F8345
Errata
Details any chip issues that might be present
MC56F8345E/D
10
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56F8345 Technical Data
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Data Sheet Conventions
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted”
A high true (active high) signal is low or a low true (active low) signal is high.
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Examples:
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
VIL/VOL
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
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Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8345 are organized into functional groups, as detailed in
Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or
signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Freescale Semiconductor, Inc...
Functional Group
Number of Pins in Package
Power (VDD or VDDA)
9
Power Option Control
1
Ground (VSS or VSSA)
6
Supply Capacitors1 & VPP
6
PLL and Clock
4
Address Bus
11
Data Bus
4
Bus Control
6
Interrupt and Program Control
4
Pulse Width Modulator (PWM) Ports
26
Serial Peripheral Interface (SPI) Port 0
4
Quadrature Decoder Port 02
4
Quadrature Decoder Port 13
4
Serial Communications Interface (SCI) Ports
4
CAN Ports
2
Analog-to-Digital Converter (ADC) Ports
21
Timer Module Ports
6
JTAG/Enhanced On-Chip Emulation (EOnCE)
5
Temperature Sense
1
1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs
2. Alternately, can function as Quad Timer pins or GPIO
3. Pins in this section can function as Quad Timer, SPI 1, or GPIO
12
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Introduction
Power
VDD_IO
Power
VDDA_ADC
Power
VDDA_OSC_PLL
Ground
VSS
Ground
VSSA_ADC
OCR_DIS
Other
Supply
Ports
VCAP1 - VCAP4
VPP1 & VPP2
Freescale Semiconductor, Inc...
CLKMODE
EXTAL
PLL
and
Clock
XTAL
CLKO
7
1
1
1
1
5
1
1
1
56F8345
1
1
1
4
2
1
1
A8 - A13 (GPIOA0 - 5)
Address
Bus
or GPIO
GPIOB0-4 (A16 - 20)
*External
D7 - D10 (GPIOF0 - 3)
1
1
1
1
1
1
6
5
6
3
4
Data Bus
6
4
3
4
*External
Bus
Control
GPIOD0 - 5(CS2 - 7)
8
6
5
8
1
TXD0 (GPIOE0)
SCI0 or
GPIOE
RXD0 (GPIOE1)
SCI1 or
GPIO
TXD1 (GPIOD6)
RXD1 (GPIOD7)
1
1
1
1
1
JTAG/
EOnCE
Port
TDO
TRST
SPI0 or
GPIO
SS0 (GPIOE7)
PHASEA1(TB0, SCLK1, GPIOC0) Quadrature
PHASEB1 (TB1, MOSI1, GPIOC1) Decoder 1 or
Quad Timer B
INDEX1 (TB2, MISO1, GPIOC2)
or SPI1 or
HOME1 (TB3, SS1, GPIOC3)
GPIO
PWMA0 - 5
ISA0 - 2 (GPIOC8 - 10)
PWMA
FAULTA0 - 3
PWMB0 - 5
ISB0 - 2 (GPIOD10 - 12)
PWMB
FAULTB0-3
ANA0 - 7
VREF
ADCA
ANB0 - 7
ADCB
TEMP_SENSE
Temperature
Sensor
CAN_RX
CAN_TX
CAN
TC0 - 1 (GPIOE8 - 9)
QUAD
TIMER C
and D or
GPIO
1
2
4
TCK
TMS
TDI
SCLK0 (GPIOE4)
MOSI0 (GPIOE5)
MISO0 (GPIOE6)
INDEX0 (TA2, GPIOC6)
1
1
*External
HOME0 (TA3, GPIOC7)
Quadrature
Decoder 0
or Quad
Timer A or
GPIO
PHASEA0 (TA0, GPIOC4)
PHASEB0(TA1, GPIOC5 )
TD0 - 3 (GPIOE10 - 13)
1
1
1
1
1
1
1
1
1
IRQA
IRQB
RESET
INTERRUPT/
PROGRAM
CONTROL
RSTO
* EMI not functional in this package; use
as GPIO pins
Figure 2-1 56F8345 Signals Identified by Functional Group1
(128-Pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
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2.2 56F8345 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality
must be programmed.
EMI is not functional in this package; since only part of the address/data bus is bonded out, use as
GPIO pins.
Freescale Semiconductor, Inc...
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state.
Other states show the reset condition of the alternate function, which you get if the alternate pin
function is selected without changing the configuration of the alternate peripheral. For example,
the A8/GPIOA0 pin shows that it is tri-stated during reset. If the GPIOA_PER is changed to select
the GPIO function of the pin, it will become an input if no other registers are changed.
Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
State
During
Reset
Signal
Name
Pin No.
Type
VDD_IO
4
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O
interface.
VDD_IO
14
VDD_IO
25
VDD_IO
36
VDD_IO
62
VDD_IO
76
VDD_IO
112
VDDA_ADC
94
Supply
ADC Power — This pin supplies 3.3V power to the ADC
modules. It must be connected to a clean analog power
supply.
VDDA_OSC_
72
Supply
Oscillator and PLL Power — This pin supplies 3.3V
power to the OSC and to the internal regulator that in turn
supplies the Phase Locked Loop. It must be connected to
a clean analog power supply.
VSS
3
Supply
Ground — These pins provide ground for chip logic and
I/O drivers.
VSS
21
VSS
35
VSS
59
VSS
65
VSSA_ADC
95
Supply
ADC Analog Ground — This pin supplies an analog
ground to the ADC modules.
PLL
14
Signal Description
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56F8345 Signal Pins
Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
Signal
Name
Pin No.
Type
State
During
Reset
OCR_DIS
71
Input
Input
Signal Description
On-Chip Regulator Disable —
Tie this pin to VSS to enable the on-chip regulator
Tie this pin to VDD to disable the on-chip regulator
Freescale Semiconductor, Inc...
This pin is intended to be a static DC signal from
power-up to shut down. Do not try to toggle this pin
for power savings during operation.
VCAP1
49
VCAP2
122
VCAP3
75
VCAP4
13
Supply
Supply
VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator
enabled), connect each pin to a 2.2µF or greater bypass
capacitor in order to bypass the core logic voltage
regulator, required for proper chip operation. When
OCR_DIS is tied to VDD (regulator disabled), these pins
become VDD_CORE and should be connected to a
regulated 2.5V power supply.
Note: This bypass is required even if the chip is
powered with an external supply.
VPP1
119
VPP2
5
CLKMODE
79
Input
Input
VPP1 - 2 — These pins should be left unconnected as an
open circuit for normal functionality.
Input
Input
Clock Input Mode Selection — This input determines
the function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive
the input clock of the chip. The EXTAL pin should be
grounded.
0 = A crystal or ceramic resonator should be connected
between XTAL and EXTAL.
EXTAL
74
Input
Input
XTAL
73
Input/
Output
Chip-driven
External Crystal Oscillator Input — This input can be
connected to an 8MHz external crystal. Tie this pin low if
XTAL is driven by an external clock source.
Crystal Oscillator Output — This output connects the
internal crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the
input and EXTAL connected to GND.
The input clock can be selected to provide the clock
directly to the core. This input clock can also be selected
as the input clock for the on-chip PLL.
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Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
Signal
Name
Pin No.
Type
State
During
Reset
CLKO
6
Output
Tri-Stated
Signal Description
Clock Output — This pin outputs a buffered clock signal.
Using the SIM CLKO Select Register (SIM_CLKOSR),
this pin can be programmed as any of the following:
disabled, CLK_MSTR (system clock), IPBus clock,
oscillator output, prescaler clock and postscaler clock.
Other signals are also available for test purposes.
Freescale Semiconductor, Inc...
See Section 6.5.7 CLKO Select Register
(SIM_CLKOSR) for details.
A8
15
Output
Tri-stated
Address Bus — A8 - A13 specify six of the address lines
for external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A8 - A13 and EMI control signals
are tri-stated when the external bus is inactive.
Input
A9
(GPIOA1)
16
Schmitt
Input/
Output
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
A10
(GPIOA2)
17
After reset, these pins default to address bus functionality
and must be programmed as GPIO.
A11
(GPIOA3)
18
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOA_PUR register.
A12
(GPIOA4)
19
Example: GPIOA0, clear bit 0 in the GPIOA_PUR
register.
A13
(GPIOA5)
20
Note: Primary function is not available in this package
configuration; GPIO function must be used instead.
GPIOB0
27
(GPIOA0)
(A16)
GPIOB1
28
(A17)
GPIOB2
29
(A18)
GPIOB3
(A19)
16
30
Schmitt
Input/
Output
Input
Port B GPIO — These four GPIO pins can be individually
programmed as an input or output pin.
Output
Tri-stated
Address Bus — A16 - A19 specify four of the address
lines for external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A16 - A19 and EMI control signals
are tri-stated when the external bus is inactive.
After reset, the default state is GPIO.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOB_PUR register.
Example: GPIOB1, clear bit 1 in the GPIOB_PUR
register.
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56F8345 Signal Pins
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Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
State
During
Reset
Signal
Name
Pin No.
Type
GPIOB4
31
Schmitt
Input/
Output
Input
(A20)
Output
Tri-stated
(prescaler_clock)
Output
Output
Signal Description
Port B GPIO — This GPIO pin can be individually
programmed as an input or output pin.
Address Bus — A20 specifies one of the address lines
for external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A20 and EMI control signals are
tri-stated when the external bus is inactive.
Clock Output — can be used to monitor the
prescaler_clock on GPIOB4.
After reset, the default state is GPIO.
This pin can also be used to view the prescaler_clock. In
these cases, the GPIOB_PER can be used to disable the
GPIO. The CLKOSR register in the SIM can then be used
to choose between address and clock functions; see
Section 6.5.7 CLKO Select Register (SIM_CLKOSR) for
details.
To deactivate the internal pull-up resistor, clear bit 4 in the
GPIOB_PUR register.
D7
22
(GPIOF0)
Input/
Output
Tri-stated
Data Bus — D7 - D10 specify part of the data for external
program or data memory accesses. Depending upon the
state of the DRV bit in the EMI bus control register (BCR),
D7 - D10 are tri-stated when the external bus is inactive
Input/
Output
Input
Port F GPIO — These four GPIO pins can be individually
programmed as input or output pins.
D8
(GPIOF1)
23
D9
(GPIOF2)
24
After reset, these pins default to data bus functionality and
should be programmed as GPIO.
D10
(GPIOF3)
26
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOF_PUR register.
Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.
Note: Primary function is not available in this package
configuration; GPIO function must be used instead.
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Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
Pin No.
Type
GPIOD0
42
Input/
Output
Input
Port D GPIO — These six GPIO pins can be individually
programmed as input or output pins.
Output
Input
Chip Select — CS2 - CS7 may be programmed within the
EMI module to act as chip selects for specific areas of the
external memory map. Depending upon the state of the
DRV bit in the EMI bus control register (BCR), CS2 - CS7
are tri-stated when the external bus is inactive.
(CS2)
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State
During
Reset
Signal
Name
GPIOD1
(CS3)
43
GPIOD2
(CS4)
44
GPIOD3
(CS5)
45
GPIOD4
(CS6)
46
GPIOD5
(CS7)
47
TXD0
7
Signal Description
After reset, these pins are configured as GPIO.
(GPIOE0)
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOD_PUR register.
Example: GPIOD0, clear bit 0 in the GPIOD_PUR
register.
Output
Tri-stated
Input/
Output
Input
Transmit Data — SCI0 transmit data output
Port E GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
RXD0
8
(GPIOE1)
Input
Input
Receive Data — SCI0 receive data input
Input/
Output
Input
Port E GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.
TXD1
(GPIOD6)
40
Output
Tri-stated
Input/
Output
Input
Transmit Data — SCI1 transmit data output
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.
18
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56F8345 Signal Pins
Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
Signal
Name
Pin No.
Type
State
During
Reset
RXD1
41
Input
Input
Receive Data — SCI1 receive data input
Input/
Output
Input
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
(GPIOD7)
Signal Description
After reset, the default state is SCI input.
Freescale Semiconductor, Inc...
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
TCK
115
Schmitt
Input
Input,
pulled low
internally
Test Clock Input — This input pin provides a gated clock
to synchronize the test logic and shift serial data to the
JTAG/EOnCE port. The pin is connected internally to a
pull-down resistor.
TMS
116
Schmitt
Input
Input,
pulled high
internally
Test Mode Select Input — This input pin is used to
sequence the JTAG TAP controller’s state machine. It is
sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG
bit in the SIM_PUDR register.
TDI
117
Schmitt
Input
Input,
pulled high
internally
Test Data Input — This input pin provides a serial input
data stream to the JTAG/EOnCE port. It is sampled on the
rising edge of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG
bit in the SIM_PUDR register.
TDO
118
Output
Tri-stated
Test Data Output — This tri-stateable output pin provides
a serial output data stream from the JTAG/EOnCE port. It
is driven in the shift-IR and shift-DR controller states, and
changes on the falling edge of TCK.
TRST
114
Schmitt
Input
Input,
pulled high
internally
Test Reset — As an input, a low signal on this pin
provides a reset signal to the JTAG TAP controller. To
ensure complete hardware reset, TRST should be
asserted whenever RESET is asserted. The only
exception occurs in a debugging environment when a
hardware device reset is required and the JTAG/EOnCE
module must not be reset. In this case, assert RESET, but
do not assert TRST.
To deactivate the internal pull-up resistor, set the JTAG
bit in the SIM_PUDR register.
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Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
State
During
Reset
Signal
Name
Pin No.
Type
PHASEA0
127
Schmitt
Input
Input
Phase A — Quadrature Decoder 0, PHASEA input
(TA0)
Schmitt
Input/
Output
Input
TA0 — Timer A, Channel 0
(GPIOC4)
Schmitt
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually
programmed as an input or output pin.
Signal Description
After reset, the default state is PHASEA0.
To deactivate the internal pull-up resistor, clear bit 4 of the
GPIOC_PUR register.
PHASEB0
128
Schmitt
Input
Input
Phase B — Quadrature Decoder 0, PHASEB input
(TA1)
Schmitt
Input/
Output
Input
TA1 — Timer A, Channel 1
(GPIOC5)
Schmitt
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is PHASEB0.
To deactivate the internal pull-up resistor, clear bit 5 of the
GPIOC_PUR register.
INDEX0
1
Schmitt
Input
Input
Index — Quadrature Decoder 0, INDEX input
(TA2)
Schmitt
Input/
Output
Input
TA2 — Timer A, Channel 2
(GPIOC6)
Schmitt
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is INDEX0.
To deactivate the internal pull-up resistor, clear bit 6 of the
GPIOC_PUR register.
20
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56F8345 Signal Pins
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Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
State
During
Reset
Signal
Name
Pin No.
Type
HOME0
2
Schmitt
Input
Input
Home — Quadrature Decoder 0, HOME input
(TA3)
Schmitt
Input/
Output
Input
TA3 — Timer A ,Channel 3
(GPIOC7)
Schmitt
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually
programmed as an input or output pin.
Signal Description
After reset, the default state is HOME0.
To deactivate the internal pull-up resistor, clear bit 7 of the
GPIOC_PUR register.
SCLK0
124
(GPIOE4)
Schmitt
Input/
Output
Input
SPI 0 Serial Clock — In the master mode, this pin serves
as an output, clocking slaved listeners. In slave mode, this
pin serves as the data clock input.
Schmitt
Input/
Output
Input
Port E GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCLK0.
To deactivate the internal pull-up resistor, clear bit 4 in the
GPIOE_PUR register.
MOSI0
126
(GPIOE5)
Input/
Output
Tri-stated
Input/
Output
Input
SPI 0 Master Out/Slave In — This serial data pin is an
output from a master device and an input to a slave
device. The master device places data on the MOSI line a
half-cycle before the clock edge the slave device uses to
latch the data.
Port E GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is MOSI0.
To deactivate the internal pull-up resistor, clear bit 5 in the
GPIOE_PUR register.
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Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
Pin No.
Type
MISO0
125
Input/
Output
Input
SPI 0 Master In/Slave Out — This serial data pin is an
input to a master device and an output from a slave
device. The MISO line of a slave device is placed in the
high-impedance state if the slave device is not selected.
The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to
latch the data.
Input/
Output
Input
Port E GPIO — This GPIO pin can be individually
programmed as an input or output pin.
(GPIOE6)
Freescale Semiconductor, Inc...
State
During
Reset
Signal
Name
Signal Description
After reset, the default state is MISO0.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOE_PUR register.
SS0
123
(GPIOE7)
Input
Input
SPI 0 Slave Select — SS0 is used in slave mode to
indicate to the SPI module that the current transfer is to
be received.
Input/
Output
Input
Port E GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SS0.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOE_PUR register.
PHASEA1
9
Schmitt
Input
Input
Phase A1 — Quadrature Decoder 1, PHASEA input for
decoder 1.
(TB0)
Schmitt
Input/
Output
Input
TB0 — Timer B, Channel 0
(SCLK1)
Schmitt
Input/
Output
Input
SPI 1 Serial Clock — In the master mode, this pin serves
as an output, clocking slaved listeners. In slave mode, this
pin serves as the data clock input. To activate the SPI
function, set the PHSA_ALT bit in the SIM_GPS register.
For details, see Section 6.5.8 GPIO Peripheral Select
Register (SIM_GPS).
(GPIOC0)
Schmitt
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is PHASEA1.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOC_PUR register.
22
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56F8345 Signal Pins
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Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
State
During
Reset
Signal
Name
Pin No.
Type
PHASEB1
10
Schmitt
Input
Input
Phase B1 — Quadrature Decoder 1, PHASEB input for
decoder 1.
(TB1)
Schmitt
Input/
Output
Input
TB1 — Timer B, Channel 1
(MOSI1)
Schmitt
Input/
Output
Tri-stated
(GPIOC1)
Schmitt
Input/
Output
Input
Signal Description
SPI 1 Master Out/Slave In — This serial data pin is an
output from a master device and an input to a slave
device. The master device places data on the MOSI line a
half-cycle before the clock edge the slave device uses to
latch the data. To activate the SPI function, set the
PHSB_ALT bit in the SIM_GPS register. For details, see
Section 6.5.8 GPIO Peripheral Select Register
(SIM_GPS).
Port C GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is PHASEB1.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOC_PUR register.
INDEX1
11
Schmitt
Input
Input
Index1 — Quadrature Decoder 1, INDEX input
(TB2)
Schmitt
Input/
Output
Input
TB2 — Timer B, Channel 2
(MISO1)
Schmitt
Input/
Output
Input
SPI 1 Master In/Slave Out — This serial data pin is an
input to a master device and output from a slave device.
The MISO line of a slave device is placed in the
high-impedance state if the slave device is not selected.
The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to
latch the data. To activate the SPI function, set the
INDEX_ALT bit in the SIM_GPS register. See Section
6.5.8 GPIO Peripheral Select Register (SIM_GPS) for
details.
(GPIOC2)
Schmitt
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is INDEX1.
To deactivate the internal pull-up resistor, clear bit 2 in the
GPIOC_PUR register.
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Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
State
During
Reset
Signal
Name
Pin No.
Type
HOME1
12
Schmitt
Input
Input
Home — Quadrature Decoder 1, HOME input
(TB3)
Schmitt
Input/
Output
Input
TB3 — Timer B, Channel 3
(SS1)
Schmitt
Input
Input
SPI 1 Slave Select — In the master mode, this pin is
used to arbitrate multiple masters. In slave mode, this pin
is used to select the slave. To activate the SPI function,
set the HOME_ALT bit in the SIM_GPS register. See
Section 6.5.8 GPIO Peripheral Select Register
(SIM_GPS) for details.
(GPIOC3)
Schmitt
Input/
Output
Input
Signal Description
Port C GPIO — This GPIO pin can be individually
programmed as input or output pin.
After reset, the default state is HOME1.
To deactivate the internal pull-up resistor, clear bit 3 in the
GPIOC_PUR register.
PWMA0
58
PWMA1
60
PWMA2
61
PWMA3
63
PWMA4
64
PWMA5
66
ISA0
104
(GPIOC8)
ISA1
(GPIOC9)
105
ISA2
(GPIOC10)
106
24
Output
Tri-State
PWMA0 - 5 — These are six PWMA output pins.
Schmitt
Input
Input
ISA0 - 2 — These three input current status pins are used
for top/bottom pulse width correction in complementary
channel operation for PWMA.
Schmitt
Input/
Output
Input
Port C GPIO — These GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to ISA functionality.
To deactivate the internal pull-up resistor, clear the
appropriate bit of the GPIOC_PUR register. See Section
6.5.6 SIM Pull-up Disable Register (SIM_PUDR) for
details.
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56F8345 Signal Pins
Freescale Semiconductor, Inc...
Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
Signal
Name
Pin No.
Type
FAULTA0
67
FAULTA1
68
Schmitt
Input
FAULTA2
69
FAULTA3
70
State
During
Reset
Input
Signal Description
FAULTA0 - 2 — These three fault input pins are used for
disabling selected PWMA outputs in cases where fault
conditions originate off-chip.
To deactivate the internal pull-up resistor, set the PWMA0
bit in the SIM_PUDR register. See Section 6.5.6 SIM
Pull-up Disable Register (SIM_PUDR) for details.
Schmitt
Input
Input
FAULTA3 — This fault input pin is used for disabling
selected PWMA outputs in cases where fault conditions
originate off-chip.
To deactivate the internal pull-up resistor, set the PWMA1
bit in the SIM_PUDR register. See Section 6.5.6 SIM
Pull-up Disable Register (SIM_PUDR) for details.
PWMB0
32
PWMB1
33
PWMB2
34
PWMB3
37
PWMB4
38
PWMB5
39
ISB0
48
(GPIOD10)
ISB1
(GPIOD11)
50
ISB2
(GPIOD12)
51
FAULTB0
54
FAULTB1
55
FAULTB2
56
FAULTB3
57
ANA0
80
ANA1
81
ANA2
82
ANA3
83
Output
Tri-State
PWMB0 - 5 — Six PWMB output pins.
Schmitt
Input
Input
ISB0 - 2 — These three input current status pins are used
for top/bottom pulse width correction in complementary
channel operation for PWMB.
Schmitt
Input/
Output
Input
Port D GPIO — These GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to ISB functionality.
56F8345 Technical Data
Preliminary
To deactivate the internal pull-up resistor, clear the
appropriate bit of the GPIOD_PUR register. See Section
6.5.6 SIM Pull-up Disable Register (SIM_PUDR) for
details.
Schmitt
Input
Input
FAULTB0 - 3 — These four fault input pins are used for
disabling selected PWMB outputs in cases where fault
conditions originate off-chip.
To deactivate the internal pull-up resistor, set the PWMB
bit in the SIM_PUDR register. See Section 6.5.6 SIM
Pull-up Disable Register (SIM_PUDR) for details.
Input
Input
ANA0 - 3 — Analog inputs to ADC A, channel 0
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Freescale Semiconductor, Inc...
Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
Signal
Name
Pin No.
Type
State
During
Reset
ANA4
84
Input
Input
ANA4 - 7 — Analog inputs to ADC A, channel 1
ANA5
85
ANA6
86
ANA7
87
VREFH
93
Input
Input
VREFH — Analog Reference Voltage High. VREFH must be
less than or equal to VDDA_ADC.
VREFP
92
Input/
Output
Input/
Output
VREFMID
91
VREFP, VREFMID & VREFN — Internal pins for voltage
reference which are brought off-chip so that they can be
bypassed. Connect to a 0.1 µF low ESR capacitor.
VREFN
90
VREFLO
89
Input
Input
VREFLO — Analog Reference Voltage Low. This should
normally be connected to a low-noise VSSA.
ANB0
96
Input
Input
ANB0 - 3 — Analog inputs to ADC B, channel 0
ANB1
97
ANB2
98
ANB3
99
ANB4
100
Input
Input
ANB4 - 7 — Analog inputs to ADC B, channel 1
ANB5
101
ANB6
102
ANB7
103
TEMP_
SENSE
88
CAN_RX
121
Signal Description
Temperature Sense Diode — This signal connects to an
on-chip diode that can be connected to one of the ADC
inputs and is used to monitor the temperature of the die.
Must be bypassed with a 0.01 µF capacitor.
Schmitt
Input
Input
FlexCAN Receive Data — This is the CAN input. This pin
has an internal pull-up resistor.
To deactivate the internal pull-up resistor, set the CAN bit
in the SIM_PUDR register.
CAN_TX
26
120
Open
Drain
Output
Output
FlexCAN Transmit Data — CAN output
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56F8345 Signal Pins
Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
Pin No.
Type
TC0
111
Schmitt
Input/
Output
Input
TC0 - 1 — Timer C, Channels 0 and 1
Schmitt
Input/
Output
Input
Port E GPIO — These GPIO pins can be individually
programmed as input or output pins.
(GPIOE8)
TC1
(GPIOE9)
Freescale Semiconductor, Inc...
State
During
Reset
Signal
Name
113
Signal Description
At reset, these pins default to Timer functionality.
To deactivate the internal pull-up resistor, clear the
appropriate bit of the GPIOE_PUR register. See Section
6.5.6 SIM Pull-up Disable Register (SIM_PUDR) for
details.
TD0
107
(GPIOE10)
TD1
(GPIOE11)
108
TD2
(GPIOE12)
109
TD3
(GPIOE13)
110
IRQA
52
IRQB
53
Schmitt
Input/
Output
Input
TD0 - TD3 — Timer D, Channels 0, 1, 2 and 3
Schmitt
Input/
Output
Input
Port E GPIO — These GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to Timer functionality.
To deactivate the internal pull-up resistor, clear the
appropriate bit of the GPIOE_PUR register. See Section
6.5.6 SIM Pull-up Disable Register (SIM_PUDR) for
details.
Schmitt
Input
Input
External Interrupt Request A and B — The IRQA and
IRQB inputs are asynchronous external interrupt requests
during Stop and Wait mode operation. During other
operating modes, they are synchronized external interrupt
requests, which indicate an external device is requesting
service. They can be programmed to be level-sensitive or
negative-edge triggered.
To deactivate the internal pull-up resistor, set the IRQ bit
in the SIM_PUDR register. See Section 6.5.6 SIM
Pull-up Disable Register (SIM_PUDR) for details.
56F8345 Technical Data
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Table 2-2 56F8345 Signal and Package Information for the 128-Pin LQFP
Signal
Name
Pin No.
Type
RESET
78
Schmitt
Input
State
During
Reset
Input
Signal Description
Reset — This input is a direct hardware reset on the
processor. When RESET is asserted low, the device is
initialized and placed in the reset state. A Schmitt trigger
input is used for noise immunity. The internal reset signal
will be deasserted synchronous with the internal clocks
after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST
should be asserted together. The only exception occurs in
a debugging environment when a hardware device reset
is required and the JTAG/EOnCE module must not be
reset. In this case, assert RESET, but do not assert
TRST.
Note: The internal Power-On Reset will assert on initial
power-up.
To deactivate the internal pull-up resistor, set the RESET
bit in the SIM_PUDR register. See Section 6.5.6 SIM
Pull-up Disable Register (SIM_PUDR). for details.
RSTO
77
Output
Output
EXTBOOT
Internal
Ground
Schmitt
Input
Input
Reset Output — This output reflects the internal reset
state of the chip.
External Boot — This input is tied to VDD to force the
device to boot from off-chip memory (assuming that the
on-chip Flash memory is not in a secure state).
Otherwise, it is tied to ground. For details, see Table 4-4.
Note: When this pin is tied low, the customer boot
software should disable the internal pull-up resistor by
setting the XBOOT bit of the SIM_PUDR; see Section
6.5.6 SIM Pull-up Disable Register (SIM_PUDR).
Note: This pin is internally tied low (to VSS).
EMI_MODE
Internal
Ground
Schmitt
Input
Input
External Memory Mode — This device will boot from
internal Flash memory under normal operation.
This function is also affected by EXTBOOT and the Flash
security mode; see Table 4-4 for details.
Note: When this pin is tied low, the customer boot
software should disable the internal pull-up resistor by
setting the EMI_MODE bit of the SIM_PUDR; see
Section 6.5.6 SIM Pull-up Disable Register
(SIM_PUDR).
Note: This pin is internally tied low (to VSS).
28
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Introduction
Part 3 On-Chip Clock Synthesis (OCCS)
3.1 Introduction
CLKMODE
XTAL
ZSRC
MUX
Crystal
OSC
PLLCID
PLLCOD
PLL
FOUT
x (1 to 128)
FEEDBACK
FREF
PLLDB
Prescaler
÷ (1,2,4,8)
MUX
Prescaler CLK
EXTAL
MSTR_OSC
Freescale Semiconductor, Inc...
Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the
OCCS. The material contained here identifies the specific features of the OCCS design that apply
to the 56F8345 part. Figure 3-1 shows the specific OCCS block diagram to reference in the OCCS
chapter of the 56F8300 Peripheral User Manual.
÷2
FOUT/2 Postscaler
÷ (1,2,4,8)
Postscaler CLK
Bus Interface & Control
Lock
Detector
Loss of
Reference
Clock
Detector
SYS_CLK2
Source to SIM
Bus
Interface
LCK
Loss of Reference
Clock Interrupt
Figure 3-1 OCCS Block Diagram
56F8345 Technical Data
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3.2 External Clock Operation
The 56F8345 system clock can be derived from an external crystal, ceramic resonator, or an
external system clock signal. To generate a reference frequency using the internal oscillator, a
reference crystal or ceramic resonator must be connected between the EXTAL and XTAL pins.
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3.2.1
Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 10-15. A recommended crystal
oscillator circuit is shown in Figure 3-2. Follow the crystal supplier’s recommendations when
selecting a crystal, since crystal parameters determine the component values required to provide
maximum stability and reliable start-up. The crystal and associated components should be mounted
as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up
stabilization time.
Crystal Frequency = 4 - 8MHz (optimized for 8MHz)
EXTAL
XTAL
EXTAL
RZ
RZ
Sample External Crystal Parameters:
Rz = 750 KΩ
Note: If the operating temperature range is limited
to below 85oC (105oC junction), then Rz = 10
Meg Ω
CLKMODE = 0
CL1
XTAL
CL2
Figure 3-2 Connecting to a Crystal Oscillator
Note:
30
The OCCS_COHL bit must be set to 1 when a crystal oscillator is used. The reset condition on
the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL)
register, discussed in the 56F8300 Peripheral User’s Manual.
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Registers
3.2.2
Ceramic Resonator (Default)
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall
system design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown
in Figure 3-3. Refer to the supplier’s recommendations when selecting a ceramic resonator and
associated components. The resonator and components should be mounted as near as possible to
the EXTAL and XTAL pins.
Resonator Frequency = 4 - 8MHz (optimized for 8MHz)
3 Terminal
2 Terminal
Freescale Semiconductor, Inc...
EXTAL XTAL
Rz
CL1
CL2
EXTAL XTAL
Rz
Sample External Ceramic Resonator Parameters:
Rz = 750 KΩ
CLKMODE = 0
C1
C2
Figure 3-3 Connecting a Ceramic Resonator
Note:
The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition
on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL)
register, discussed in the 56F8300 Peripheral User’s Manual.
3.2.3
External Clock Source
The recommended method of connecting an external clock is illustrated in Figure 3-4. The
external clock source is connected to XTAL and the EXTAL pin is grounded. Set OCCS_COHL bit
high when using an external clock source as well.
56F8345
XTAL
EXTAL
External
Clock
VSS
Note: When using an external clocking
source with this configuration, the input
“CLKMODE” should be high and COHL bit in
the OSCTL register should be set to 1.
Figure 3-4 Connecting an External Clock Signal Register
3.3 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual,
use the register definitions without the internal Relaxation Oscillator, since the 56F8345 does
NOT contain this oscillator.
56F8345 Technical Data
Preliminary
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Part 4 Memory Map
4.1 Introduction
The 56F8345 device is a 16-bit motor-control chip based on the 56800E core. It uses a
Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memories are used in both spaces.
This section provides memory maps for:
Freescale Semiconductor, Inc...
•
•
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for each device are summarized in Table 4-1. Flash memories’ restrictions
are identified in the “Use Restrictions” column of Table 4-1.
Table 4-1 Chip Memory Configurations
On-Chip Memory
Program Flash
56F8345
128KB
Use Restrictions
Erase / Program via Flash interface unit and word writes to CDBW
Data Flash
8KB
Erase / Program via Flash interface unit and word writes to CDBW. Data
Flash can be read via either CDBR or XDB2, but not by both simultaneously
Program RAM
4KB
None
Data RAM
8KB
None
Program Boot Flash
8KB
Erase / Program via Flash Interface unit and word writes to CDBW
32
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Program Map
4.2 Program Map
The Program memory map is located in Table 4-4. The operating mode control bits (MA and MB)
in the Operating Mode Register (OMR) control the Program memory map. At reset, these bits are
set as indicated in Table 4-2.
EXT_BOOT = EMI_MODE = 0 and cannot be changed in the 56F8345.
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Table 4-2 OMR MB/MA Value at Reset1
OMR MB =
Flash Secured
State2,3
OMR MA =
EXTBOOT Pin
0
0
Mode 0 – Internal Boot; EMI is configured to use 16 address lines; Flash
Memory is secured; external P-space is not allowed; the EOnCE is disabled
0
1
Not valid; cannot boot externally if the Flash is secured and will actually
configure to 00 state
1
0
Mode 0 – Internal Boot; EMI is configured to use 16 address lines
1
1
Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is
determined by the state of the EMI_MODE pin
Chip Operating Mode
1. Information in shaded areas not applicable to 56F8345.
2. This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset.
3. Changing MB in software will not affect Flash memory security.
After reset, the OMR MA bit can be changed and will have an effect on the P-space memory map,
as shown in Table 4-3. Changing the OMR MB bit will have no effect.
Table 4-3 Changing OMR MA Value During Normal Operation
OMR MA
Chip Operating Mode
0
Use internal P-space memory map configuration
11
Use external P-space memory map configuration – If MB = 0 at reset, changing this bit has no
effect.
1. Setting this bit can cause unpredictable results and is not recommended, since the EMI is not functional in this package.
Table 4-4 shows the memory map options of the 56F8345. The two right columns cannot be used,
since the EMI pins are not provided in the package; therefore, only the Mode 0 column is relevant.
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Table 4-4 Program Memory Map at Reset
Begin/End
Address
Mode 0 (MA = 0)
Mode 11 (MA = 1)
Internal Boot
External Boot
Internal Boot
16-Bit External Address Bus
P:$1F FFFF
P:$10 0000
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P:$0F FFFF
P:$03 0000
P:$02 FFFF
P:$02 F800
EMI_MODE = 02, 3
16-Bit External Address Bus
EMI_MODE = 14
20-Bit External Address Bus
External Program Memory5
External Program Memory5
External Program Memory5
On-Chip Program RAM
4KB
On-Chip Program RAM
4KB
P:$02 F7FF
P:$02 1000
Reserved
116KB
P:$02 0FFF
P:$02 0000
Boot Flash
8KB
COP Reset Address = 02 0002
Boot Location = 02 0000
External Program RAM5
Boot Flash
COP Reset Address = 02 0002
8KB
(Not Used for Boot in this Mode) Boot Location = 02 0000
P:$01 FFFF
P:$01 0000
External Program RAM5
Internal Program Flash
128KB
Internal Program Flash
128KB
External Program RAM5
COP Reset Address = 00 0002
Boot Location = 00 0000
P:$00 FFFF
P:$00 0000
1. Cannot be used since MA = EXTBOOT = 0 and the EMI is not available; information in shaded areas not applicable to
56F8345.
2. This mode provides maximum compatibility with 56F80x parts while operating externally.
3. “EMI_MODE = 0”, EMI_MODE pin is tied to ground at boot up.
4. “EMI_MODE = 1”, EMI_MODE pin is tied to VDD at boot up.
5. Not accessible in this part, since the EMI is not fully pinned out in this package; information in shaded areas not applicable
to 56F8345.
4.3 Interrupt Vector Table
Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The
table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the
table. The priority of an interrupt can be assigned to different levels, as indicated, allowing some
control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For
a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA) register. Please
see Section 5.6.11 Vector Base Address Register (VBA) for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1
of the interrupt vector table. In these instances, the first two locations in the vector table must
contain branch or JMP instructions. All other entries must contain JSR instructions.
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Interrupt Vector Table
Table 4-5 Interrupt Vector Table Contents1
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function
Reserved for Reset Overlay2
Freescale Semiconductor, Inc...
Reserved for COP Reset Overlay2
core
2
3
P:$04
Illegal Instruction
core
3
3
P:$06
SW Interrupt 3
core
4
3
P:$08
HW Stack Overflow
core
5
3
P:$0A
Misaligned Long Word Access
core
6
1-3
P:$0C
OnCE Step Counter
core
7
1-3
P:$0E
OnCE Breakpoint Unit 0
Reserved
core
9
1-3
P:$12
OnCE Trace Buffer
core
10
1-3
P:$14
OnCE Transmit Register Empty
core
11
1-3
P:$16
OnCE Receive Register Full
Reserved
core
14
2
P:$1C
SW Interrupt 2
core
15
1
P:$1E
SW Interrupt 1
core
16
0
P:$20
SW Interrupt 0
core
17
0-2
P:$22
IRQA
core
18
0-2
P:$24
IRQB
Reserved
LVI
20
0-2
P:$28
Low Voltage Detector (power sense)
PLL
21
0-2
P:$2A
PLL
FM
22
0-2
P:$2C
FM Access Error Interrupt
FM
23
0-2
P:$2E
FM Command Complete
FM
24
0-2
P:$30
FM Command, data and address Buffers Empty
Reserved
FLEXCAN
26
0-2
P:$34
FLEXCAN Bus Off
FLEXCAN
27
0-2
P:$36
FLEXCAN Error
FLEXCAN
28
0-2
P:$38
FLEXCAN Wake Up
FLEXCAN
29
0-2
P:$3A
FLEXCAN Message Buffer Interrupt
GPIOF
30
0-2
P:$3C
GPIO F
GPIOE
31
0-2
P:$3E
GPIO E
GPIOD
32
0-2
P:$40
GPIO D
GPIOC
33
0-2
P:$42
GPIO C
GPIOB
34
0-2
P:$44
GPIO B
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Table 4-5 Interrupt Vector Table Contents1 (Continued)
Peripheral
GPIOA
Vector
Number
35
Priority
Level
0-2
Vector Base
Address +
P:$46
Interrupt Function
GPIO A
Freescale Semiconductor, Inc...
Reserved
SPI1
38
0-2
P:$4C
SPI 1 Receiver Full
SPI1
39
0-2
P:$4E
SPI 1 Transmitter Empty
SPI0
40
0-2
P:$50
SPI 0 Receiver Full
SPI0
41
0-2
P:$52
SPI 0 Transmitter Empty
SCI1
42
0-2
P:$54
SCI 1 Transmitter Empty
SCI1
43
0-2
P:$56
SCI 1 Transmitter Idle
Reserved
SCI1
45
0-2
P:$5A
SCI 1 Receiver Error
SCI1
46
0-2
P:$5C
SCI 1 Receiver Full
DEC1
47
0-2
P:$5E
Quadrature Decoder #1 Home Switch or Watchdog
DEC1
48
0-2
P:$60
Quadrature Decoder #1 INDEX Pulse
DEC0
49
0-2
P:$62
Quadrature Decoder #0 Home Switch or Watchdog
DEC0
50
0-2
P:$64
Quadrature Decoder #0 INDEX Pulse
Reserved
TMRD
52
0-2
P:$68
Timer D, Channel 0
TMRD
53
0-2
P:$6A
Timer D, Channel 1
TMRD
54
0-2
P:$6C
Timer D, Channel 2
TMRD
55
0-2
P:$6E
Timer D, Channel 3
TMRC
56
0-2
P:$70
Timer C, Channel 0
TMRC
57
0-2
P:$72
Timer C, Channel 1
TMRC
58
0-2
P:$74
Timer C, Channel 2
TMRC
59
0-2
P:$76
Timer C, Channel 3
TMRB
60
0-2
P:$78
Timer B, Channel 0
TMRB
61
0-2
P:$7A
Timer B, Channel 1
TMRB
62
0-2
P:$7C
Timer B, Channel 2
TMRB
63
0-2
P:$7E
Timer B, Channel 3
TMRA
64
0-2
P:$80
Timer A, Channel 0
TMRA
65
0-2
P:$82
Timer A, Channel 1
TMRA
66
0-2
P:$84
Timer A,Channel 2
TMRA
67
0-2
P:$86
Timer A, Channel 3
SCI0
68
0-2
P:$88
SCI 0 Transmitter Empty
SCI0
69
0-2
P:$8A
SCI 0 Transmitter Idle
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Interrupt Vector Table
Table 4-5 Interrupt Vector Table Contents1 (Continued)
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function
Freescale Semiconductor, Inc...
Reserved
SCI0
71
0-2
P:$8E
SCI 0 Receiver Error
SCI0
72
0-2
P:$90
SCI 0 Receiver Full
ADCB
73
0-2
P:$92
ADC B Conversion Compete
ADCA
74
0-2
P:$94
ADC A Conversion Complete
ADCB
75
0-2
P:$96
ADC B Zero Crossing of Limit Error
ADCA
76
0-2
P:$98
ADC A Zero Crossing of Limit Error
PWMB
77
0-2
P:$9A
Reload PWM B
PWMA
78
0-2
P:$9C
Reload PWM A
PWMB
79
0-2
P:$9E
PWM B Fault
PWMA
80
0-2
P:$A0
PWM A Fault
core
81
-1
P:$A2
SW Interrupt LP
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from
the vector table, providing only 19 bits of address.
2. If the VBA is set to $0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are the
chip reset addresses; therefore, these locations are not interrupt vectors.
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4.4 Data Map
Table 4-6 Data Memory Map1,
Freescale Semiconductor, Inc...
Begin/End
Address
2
EX = 03
EX = 14
X:$FF FFFF
X:$FF FF00
EOnCE
256 locations allocated
EOnCE
256 locations allocated
X:$FF FEFF
X:$01 0000
External Memory
External Memory
X:$00 FFFF
X:$00 F000
On-Chip Peripherals
4096 locations allocated
On-Chip Peripherals
4096 locations allocated
X:$00 EFFF
X:$00 2000
External Memory
X:$00 1FFF
X:$00 1000
On-Chip Data Flash
8KB
X:$00 0FFF
X:$00 0000
On-Chip Data RAM
8KB5
External Memory
1. Information in shaded areas not applicable to 56F8345.
2. All addresses are 16-bit Word addresses, not byte addresses.
3. In the Operation Mode Register.
4. Setting EX = 1 is not recommended in the 56F8345, since the EMI is not functional in this package.
5. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle, long-word operations.
4.5 Flash Memory Map
Figure 4-1 illustrates the Flash Memory (FM) map on the system bus.
The Flash Memory is divided into three functional blocks. The Program and boot memories reside
on the Program Memory buses. They are controlled by one set of banked registers. Data Memory
Flash resides on the Data Memory buses and is controlled separately by its own set of banked
registers.
The top nine words of the Program Memory Flash are treated as special memory locations. The
content of these words is used to control the operation of the Flash Controller. Because these words
are part of the Flash Memory content, their state is maintained during power-down and reset.
During chip initialization, the content of these memory locations is loaded into Flash Memory
control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual.
In the 56F8345, these configuration parameters are located between $00_FFF7 and $00_FFFF.
38
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Flash Memory Map
Data Memory
Program Memory
BOOT_FLASH_START + $1FFF
FM_BASE + $14
8KB
Boot
BOOT_FLASH_START = $02_0000
FM_BASE + $00
Reserved
Banked Registers
Unbanked Registers
DATA_FLASH_START + $0FFF
8KB
DATA_FLASH_START + $0000
Configure Field
FM_PROG_MEM_TOP = $00_FFFF
Block 0 Odd
Block 0 Even
...
Freescale Semiconductor, Inc...
PROG_FLASH_START + $00_FFFF
PROG_FLASH_START + $00_FFF7
PROG_FLASH_START + $00_FFF6
128KB
BLOCK 0 Odd (2 Bytes) $00_0003
BLOCK 0 Even (2 Bytes) $00_0002
BLOCK 0 Odd (2 Bytes) $00_0001
BLOCK 0 Even (2 Bytes) $00_0000
PROG_FLASH_START = $00_0000
Figure 4-1 Flash Array Memory Maps
Table 4-7 shows the page and sector sizes used within each Flash memory block on the chip.
Table 4-7. Flash Memory Partitions
Flash Size
Sectors
Sector Size
Page Size
Program Flash
128KB
16
4K x 16 bits
512 x 16 bits
Data Flash
8KB
16
256 x 16 bits
256 x 16 bits
Boot Flash
8KB
4
1K x 16 bits
256 x 16 bits
Please see the 56F8300 Peripheral User Manual for additional Flash information.
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4.6 EOnCE Memory Map
Table 4-8 EOnCE Memory Map
Address
Register Acronym
Register Name
Reserved
X:$FF FF8A
OESCR
External Signal Control Register
Reserved
X:$FF FF8E
OBCNTR
Breakpoint Unit [0] Counter
Freescale Semiconductor, Inc...
Reserved
X:$FF FF90
OBMSK (32 bits)
Breakpoint 1 Unit [0] Mask Register
X:$FF FF91
—
Breakpoint 1 Unit [0] Mask Register
X:$FF FF92
OBAR2 (32 bits)
Breakpoint 2 Unit [0] Address Register
X:$FF FF93
—
Breakpoint 2 Unit [0] Address Register
X:$FF FF94
OBAR1 (24 bits)
Breakpoint 1 Unit [0] Address Register
X:$FF FF95
—
Breakpoint 1 Unit [0] Address Register
X:$FF FF96
OBCR (24 bits)
Breakpoint Unit [0] Control Register
X:$FF FF97
—
Breakpoint Unit [0] Control Register
X:$FF FF98
OTB (21-24 bits/stage)
Trace Buffer Register Stages
X:$FF FF99
—
Trace Buffer Register Stages
X:$FF FF9A
OTBPR (8 bits)
Trace Buffer Pointer Register
X:$FF FF9B
OTBCR
Trace Buffer Control Register
X:$FF FF9C
OBASE (8 bits)
Peripheral Base Address Register
X:$FF FF9D
OSR
Status Register
X:$FF FF9E
OSCNTR (24 bits)
Instruction Step Counter
X:$FF FF9F
—
Instruction Step Counter
X:$FF FFA0
OCR (bits)
Control Register
Reserved
40
X:$FF FFFC
OCLSR (8 bits)
Core Lock / Unlock Status Register
X:$FF FFFD
OTXRXSR (8 bits)
Transmit and Receive Status and Control Register
X:$FF FFFE
OTX / ORX (32 bits)
Transmit Register / Receive Register
X:$FF FFFF
OTX1 / ORX1
Transmit Register Upper Word
Receive Register Upper Word
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Peripheral Memory Mapped Registers
4.7 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations
may be accessed with the same addressing modes used for ordinary data memory, except all
peripheral registers should be read/written using word accesses only.
Table 4-9 summarizes base addresses for the set of peripherals on the 56F8345 device. Peripherals
are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Freescale Semiconductor, Inc...
Table 4-9 Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
Table Number
External Memory Interface
EMI
X:$00 F020
4-10
Timer A
TMRA
X:$00 F040
4-11
Timer B
TMRB
X:$00 F080
4-12
Timer C
TMRC
X:$00 F0C0
4-13
Timer D
TMRD
X:$00 F100
4-14
PWM A
PWMA
X:$00 F140
4-15
PWM B
PWMB
X:$00 F160
4-16
Quadrature Decoder 0
DEC0
X:$00 F180
4-17
Quadrature Decoder 1
DEC1
X:$00 F190
4-18
ITCN
ITCN
X:$00 F1A0
4-19
ADC A
ADCA
X:$00 F200
4-20
ADC B
ADCB
X:$00 F240
4-21
Temperature Sensor
TSENSOR
X:$00 F270
4-22
SCI #0
SCI0
X:$00 F280
4-23
SCI #1
SCI1
X:$00 F290
4-24
SPI #0
SPI0
X:$00 F2A0
4-25
SPI #1
SPI1
X:$00 F2B0
4-26
COP
COP
X:$00 F2C0
4-27
PLL, OSC
CLKGEN
X:$00 F2D0
4-28
GPIO Port A
GPIOA
X:$00 F2E0
4-29
GPIO Port B
GPIOB
X:$00 F300
4-30
GPIO Port C
GPIOC
X:$00 F310
4-31
GPIO Port D
GPIOD
X:$00 F320
4-32
GPIO Port E
GPIOE
X:$00 F330
4-33
GPIO Port F
GPIOF
X:$00 F340
4-34
SIM
SIM
X:$00 F350
4-35
Power Supervisor
LVI
X:$00 F360
4-36
FM
FM
X:$00 F400
4-37
FlexCAN
FC
X:$00 F800
4-38
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Table 4-10 External Memory Integration Registers Address Map
(EMI_BASE = $00 F020)
Address
Offset
Register Description
Reset Values
CSBAR 0
$0
Chip Select Base Address Register 0
0 x 0004 = 64K since
EXTBOOT = EMI_MODE
=0
CSBAR 1
$1
Chip Select Base Address Register 1
0 x 0004 = 64K since
EMI_MODE = 0
CSBAR 2
$2
Chip Select Base Address Register 2
CSBAR 3
$3
Chip Select Base Address Register 3
CSBAR 4
$4
Chip Select Base Address Register 4
CSBAR 5
$5
Chip Select Base Address Register 5
CSBAR 6
$6
Chip Select Base Address Register 6
CSBAR 7
$7
Chip Select Base Address Register 7
CSOR 0
$8
Chip Select Option Register 0
CSOR 1
$9
Chip Select Option Register 1
CSOR 2
$A
Chip Select Option Register 2
CSOR 3
$B
Chip Select Option Register 3
CSOR 4
$C
Chip Select Option Register 4
CSOR 5
$D
Chip Select Option Register 5
CSOR 6
$E
Chip Select Option Register 6
CSOR 7
$F
Chip Select Option Register 7
CSTC 0
$10
Chip Select Timing Control Register 0
CSTC 1
$11
Chip Select Timing Control Register 1
CSTC 2
$12
Chip Select Timing Control Register 2
CSTC 3
$13
Chip Select Timing Control Register 3
CSTC 4
$14
Chip Select Timing Control Register 4
CSTC 5
$15
Chip Select Timing Control Register 5
CSTC 6
$16
Chip Select Timing Control Register 6
CSTC 7
$17
Chip Select Timing Control Register 7
BCR
$18
Bus Control Register
42
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This table added to provide complete information, but this peripheral
is not functional in the 56F8345 package
Freescale Semiconductor, Inc...
Register
Acronym
56F8345 Technical Data
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Peripheral Memory Mapped Registers
Table 4-11 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F040)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
TMRA0_CMP1
$0
Compare Register 1
TMRA0_CMP2
$1
Compare Register 2
TMRA0_CAP
$2
Capture Register
TMRA0_LOAD
$3
Load Register
TMRA0_HOLD
$4
Hold Register
TMRA0_CNTR
$5
Counter Register
TMRA0_CTRL
$6
Control Register
TMRA0_SCR
$7
Status and Control Register
TMRA0_CMPLD1
$8
Comparator Load Register 1
TMRA0_CMPLD2
$9
Comparator Load Register 2
TMRA0_COMSCR
$A
Comparator Status and Control Register
Reserved
TMRA1_CMP1
$10
Compare Register 1
TMRA1_CMP2
$11
Compare Register 2
TMRA1_CAP
$12
Capture Register
TMRA1_LOAD
$13
Load Register
TMRA1_HOLD
$14
Hold Register
TMRA1_CNTR
$15
Counter Register
TMRA1_CTRL
$16
Control Register
TMRA1_SCR
$17
Status and Control Register
TMRA1_CMPLD1
$18
Comparator Load Register 1
TMRA1_CMPLD2
$19
Comparator Load Register 2
TMRA1_COMSCR
$1A
Comparator Status and Control Register
Reserved
TMRA2_CMP1
$20
Compare Register 1
TMRA2_CMP2
$21
Compare Register 2
TMRA2_CAP
$22
Capture Register
TMRA2_LOAD
$23
Load Register
TMRA2_HOLD
$24
Hold Register
TMRA2_CNTR
$25
Counter Register
TMRA2_CTRL
$26
Control Register
TMRA2_SCR
$27
Status and Control Register
TMRA2_CMPLD1
$28
Comparator Load Register 1
TMRA2_CMPLD2
$29
Comparator Load Register 2
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Table 4-11 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F040) (Continued)
Register Acronym
TMRA2_COMSCR
Address Offset
$2A
Register Description
Comparator Status and Control Register
Freescale Semiconductor, Inc...
Reserved
TMRA3_CMP1
$30
Compare Register 1
TMRA3_CMP2
$31
Compare Register 2
TMRA3_CAP
$32
Capture Register
TMRA3_LOAD
$33
Load Register
TMRA3_HOLD
$34
Hold Register
TMRA3_CNTR
$35
Counter Register
TMRA3_CTRL
$36
Control Register
TMRA3_SCR
$37
Status and Control Register
TMRA3_CMPLD1
$38
Comparator Load Register 1
TMRA3_CMPLD2
$39
Comparator Load Register 2
TMRA3_COMSCR
$3A
Comparator Status and Control Register
Table 4-12 Quad Timer B Registers Address Map
(TMRB_BASE = $00 F080)
Register Acronym
Address Offset
Register Description
TMRB0_CMP1
$0
Compare Register 1
TMRB0_CMP2
$1
Compare Register 2
TMRB0_CAP
$2
Capture Register
TMRB0_LOAD
$3
Load Register
TMRB0_HOLD
$4
Hold Register
TMRB0_CNTR
$5
Counter Register
TMRB0_CTRL
$6
Control Register
TMRB0_SCR
$7
Status and Control Register
TMRB0_CMPLD1
$8
Comparator Load Register 1
TMRB0_CMPLD2
$9
Comparator Load Register 2
TMRB0_COMSCR
$A
Comparator Status and Control Register
Reserved
44
TMRB1_CMP1
$10
Compare Register 1
TMRB1_CMP2
$11
Compare Register 2
TMRB1_CAP
$12
Capture Register
TMRB1_LOAD
$13
Load Register
TMRB1_HOLD
$14
Hold Register
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Peripheral Memory Mapped Registers
Table 4-12 Quad Timer B Registers Address Map
(TMRB_BASE = $00 F080) (Continued)
Register Acronym
Address Offset
Register Description
TMRB1_CNTR
$15
Counter Register
TMRB1_CTRL
$16
Control Register
TMRB1_SCR
$17
Status and Control Register
TMRB1_CMPLD1
$18
Comparator Load Register 1
TMRB1_CMPLD2
$19
Comparator Load Register 2
TMRB1_COMSCR
$1A
Comparator Status and Control Register
Freescale Semiconductor, Inc...
Reserved
TMRB2_CMP1
$20
Compare Register 1
TMRB2_CMP2
$21
Compare Register 2
TMRB2_CAP
$22
Capture Register
TMRB2_LOAD
$23
Load Register
TMRB2_HOLD
$24
Hold Register
TMRB2_CNTR
$25
Counter Register
TMRB2_CTRL
$26
Control Register
TMRB2_SCR
$27
Status and Control Register
TMRB2_CMPLD1
$28
Comparator Load Register 1
TMRB2_CMPLD2
$29
Comparator Load Register 2
TMRB2_COMSCR
$2A
Comparator Status and Control Register
Reserved
TMRB3_CMP1
$30
Compare Register 1
TMRB3_CMP2
$31
Compare Register 2
TMRB3_CAP
$32
Capture Register
TMRB3_LOAD
$33
Load Register
TMRB3_HOLD
$34
Hold Register
TMRB3_CNTR
$35
Counter Register
TMRB3_CTRL
$36
Control Register
TMRB3_SCR
$37
Status and Control Register
TMRB3_CMPLD1
$38
Comparator Load Register 1
TMRB3_CMPLD2
$39
Comparator Load Register 2
TMRB3_COMSCR
$3A
Comparator Status and Control Register
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Table 4-13 Quad Timer C Registers Address Map
(TMRC_BASE = $00 F0C0)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
TMRC0_CMP1
$0
Compare Register 1
TMRC0_CMP2
$1
Compare Register 2
TMRC0_CAP
$2
Capture Register
TMRC0_LOAD
$3
Load Register
TMRC0_HOLD
$4
Hold Register
TMRC0_CNTR
$5
Counter Register
TMRC0_CTRL
$6
Control Register
TMRC0_SCR
$7
Status and Control Register
TMRC0_CMPLD1
$8
Comparator Load Register 1
TMRC0_CMPLD2
$9
Comparator Load Register 2
TMRC0_COMSCR
$A
Comparator Status and Control Register
Reserved
TMRC1_CMP1
$10
Compare Register 1
TMRC1_CMP2
$11
Compare Register 2
TMRC1_CAP
$12
Capture Register
TMRC1_LOAD
$13
Load Register
TMRC1_HOLD
$14
Hold Register
TMRC1_CNTR
$15
Counter Register
TMRC1_CTRL
$16
Control Register
TMRC1_SCR
$17
Status and Control Register
TMRC1_CMPLD1
$18
Comparator Load Register 1
TMRC1_CMPLD2
$19
Comparator Load Register 2
TMRC1_COMSCR
$1A
Comparator Status and Control Register
Reserved
46
TMRC2_CMP1
$20
Compare Register 1
TMRC2_CMP2
$21
Compare Register 2
TMRC2_CAP
$22
Capture Register
TMRC2_LOAD
$23
Load Register
TMRC2_HOLD
$24
Hold Register
TMRC2_CNTR
$25
Counter Register
TMRC2_CTRL
$26
Control Register
TMRC2_SCR
$27
Status and Control Register
TMRC2_CMPLD1
$28
Comparator Load Register 1
TMRC2_CMPLD2
$29
Comparator Load Register 2
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Peripheral Memory Mapped Registers
Table 4-13 Quad Timer C Registers Address Map
(TMRC_BASE = $00 F0C0) (Continued)
Register Acronym
TMRC2_COMSCR
Address Offset
$2A
Register Description
Comparator Status and Control Register
Freescale Semiconductor, Inc...
Reserved
TMRC3_CMP1
$30
Compare Register 1
TMRC3_CMP2
$31
Compare Register 2
TMRC3_CAP
$32
Capture Register
TMRC3_LOAD
$33
Load Register
TMRC3_HOLD
$34
Hold Register
TMRC3_CNTR
$35
Counter Register
TMRC3_CTRL
$36
Control Register
TMRC3_SCR
$37
Status and Control Register
TMRC3_CMPLD1
$38
Comparator Load Register 1
TMRC3_CMPLD2
$39
Comparator Load Register 2
TMRC3_COMSCR
$3A
Comparator Status and Control Register
Table 4-14 Quad Timer D Registers Address Map
(TMRD_BASE = $00 F100)
Register Acronym
Address Offset
Register Description
TMRD0_CMP1
$0
Compare Register 1
TMRD0_CMP2
$1
Compare Register 2
TMRD0_CAP
$2
Capture Register
TMRD0_LOAD
$3
Load Register
TMRD0_HOLD
$4
Hold Register
TMRD0_CNTR
$5
Counter Register
TMRD0_CTRL
$6
Control Register
TMRD0_SCR
$7
Status and Control Register
TMRD0_CMPLD1
$8
Comparator Load Register 1
TMRD0_CMPLD2
$9
Comparator Load Register 2
TMRD0_COMSCR
$A
Comparator Status and Control Register
Reserved
TMRD1_CMP1
$10
Compare Register 1
TMRD1_CMP2
$11
Compare Register 2
TMRD1_CAP
$12
Capture Register
TMRD1_LOAD
$13
Load Register
TMRD1_HOLD
$14
Hold Register
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Table 4-14 Quad Timer D Registers Address Map
(TMRD_BASE = $00 F100) (Continued)
Register Acronym
Address Offset
Register Description
TMRD1_CNTR
$15
Counter Register
TMRD1_CTRL
$16
Control Register
TMRD1_SCR
$17
Status and Control Register
TMRD1_CMPLD1
$18
Comparator Load Register 1
TMRD1_CMPLD2
$19
Comparator Load Register 2
TMRD1_COMSCR
$1A
Comparator Status and Control Register
Freescale Semiconductor, Inc...
Reserved
TMRD2_CMP1
$20
Compare Register 1
TMRD2_CMP2
$21
Compare Register 2
TMRD2_CAP
$22
Capture Register
TMRD2_LOAD
$23
Load Register
TMRD2_HOLD
$24
Hold Register
TMRD2_CNTR
$25
Counter Register
TMRD2_CTRL
$26
Control Register
TMRD2_SCR
$27
Status and Control Register
TMRD2_CMPLD1
$28
Comparator Load Register 1
TMRD2_CMPLD2
$29
Comparator Load Register 2
TMRD2_COMSCR
$2A
Comparator Status and Control Register
Reserved
48
TMRD3_CMP1
$30
Compare Register 1
TMRD3_CMP2
$31
Compare Register 2
TMRD3_CAP
$32
Capture Register
TMRD3_LOAD
$33
Load Register
TMRD3_HOLD
$34
Hold Register
TMRD3_CNTR
$35
Counter Register
TMRD3_CTRL
$36
Control Register
TMRD3_SCR
$37
Status and Control Register
TMRD3_CMPLD1
$38
Comparator Load Register 1
TMRD3_CMPLD2
$39
Comparator Load Register 2
TMRD3_COMSCR
$3A
Comparator Status and Control Register
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Peripheral Memory Mapped Registers
Table 4-15 Pulse Width Modulator A Registers Address Map
(PWMA_BASE = $00 F140)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
PWMA_PMCTL
$0
Control Register
PWMA_PMFCTL
$1
Fault Control Register
PWMA_PMFSA
$2
Fault Status Acknowledge Register
PWMA_PMOUT
$3
Output Control Register
PWMA_PMCNT
$4
Counter Register
PWMA_PWMCM
$5
Counter Modulo Register
PWMA_PWMVAL0
$6
Value Register 0
PWMA_PWMVAL1
$7
Value Register 1
PWMA_PWMVAL2
$8
Value Register 2
PWMA_PWMVAL3
$9
Value Register 3
PWMA_PWMVAL4
$A
Value Register 4
PWMA_PWMVAL5
$B
Value Register 5
PWMA_PMDEADTM
$C
Dead Time Register
PWMA_PMDISMAP1
$D
Disable Mapping Register 1
PWMA_PMDISMAP2
$E
Disable Mapping Register 2
PWMA_PMCFG
$F
Configure Register
PWMA_PMCCR
$10
Channel Control Register
PWMA_PMPORT
$11
Port Register
PWMA_PMICCR
$12
PWM Internal Correction Control Register
Table 4-16 Pulse Width Modulator B Registers Address Map
(PWMB_BASE = $00 F160)
Register Acronym
Address Offset
Register Description
PWMB_PMCTL
$0
Control Register
PWMB_PMFCTL
$1
Fault Control Register
PWMB_PMFSA
$2
Fault Status Acknowledge Register
PWMB_PMOUT
$3
Output Control Register
PWMB_PMCNT
$4
Counter Register
PWMB_PWMCM
$5
Counter Modulo Register
PWMB_PWMVAL0
$6
Value Register 0
PWMB_PWMVAL1
$7
Value Register 1
PWMB_PWMVAL2
$8
Value Register 2
PWMB_PWMVAL3
$9
Value Register 3
PWMB_PWMVAL4
$A
Value Register 4
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Table 4-16 Pulse Width Modulator B Registers Address Map
(PWMB_BASE = $00 F160) (Continued)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
PWMB_PWMVAL5
$B
Value Register 5
PWMB_PMDEADTM
$C
Dead Time Register
PWMB_PMDISMAP1
$D
Disable Mapping Register 1
PWMB_PMDISMAP2
$E
Disable Mapping Register 2
PWMB_PMCFG
$F
Configure Register
PWMB_PMCCR
$10
Channel Control Register
PWMB_PMPORT
$11
Port Register
PWMB_PMICCR
$12
PWM Internal Correction Control Register
Table 4-17 Quadrature Decoder 0 Registers Address Map
(DEC0_BASE = $00 F180)
Register Acronym
50
Address Offset
Register Description
DEC0_DECCR
$0
Decoder Control Register
DEC0_FIR
$1
Filter Interval Register
DEC0_WTR
$2
Watchdog Time-out Register
DEC0_POSD
$3
Position Difference Counter Register
DEC0_POSDH
$4
Position Difference Counter Hold Register
DEC0_REV
$5
Revolution Counter Register
DEC0_REVH
$6
Revolution Hold Register
DEC0_UPOS
$7
Upper Position Counter Register
DEC0_LPOS
$8
Lower Position Counter Register
DEC0_UPOSH
$9
Upper Position Hold Register
DEC0_LPOSH
$A
Lower Position Hold Register
DEC0_UIR
$B
Upper Initialization Register
DEC0_LIR
$C
Lower Initialization Register
DEC0_IMR
$D
Input Monitor Register
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Peripheral Memory Mapped Registers
Table 4-18 Quadrature Decoder 1 Registers Address Map
(DEC1_BASE = $00 F190)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
DEC1_DECCR
$0
Decoder Control Register
DEC1_FIR
$1
Filter Interval Register
DEC1_WTR
$2
Watchdog Time-out Register
DEC1_POSD
$3
Position Difference Counter Register
DEC1_POSDH
$4
Position Difference Counter Hold Register
DEC1_REV
$5
Revolution Counter Register
DEC1_REVH
$6
Revolution Hold Register
DEC1_UPOS
$7
Upper Position Counter Register
DEC1_LPOS
$8
Lower Position Counter Register
DEC1_UPOSH
$9
Upper Position Hold Register
DEC1_LPOSH
$A
Lower Position Hold Register
DEC1_UIR
$B
Upper Initialization Register
DEC1_LIR
$C
Lower Initialization Register
DEC1_IMR
$D
Input Monitor Register
Table 4-19 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F1A0)
Register Acronym
Address Offset
Register Description
IPR 0
$0
Interrupt Priority Register 0
IPR 1
$1
Interrupt Priority Register 1
IPR 2
$2
Interrupt Priority Register 2
IPR 3
$3
Interrupt Priority Register 3
IPR 4
$4
Interrupt Priority Register 4
IPR 5
$5
Interrupt Priority Register 5
IPR 6
$6
Interrupt Priority Register 6
IPR 7
$7
Interrupt Priority Register 7
IPR 8
$8
Interrupt Priority Register 8
IPR 9
$9
Interrupt Priority Register 9
VBA
$A
Vector Base Address Register
FIM0
$B
Fast Interrupt Match Register 0
FIVAL0
$C
Fast Interrupt Vector Address Low 0 Register
FIVAH0
$D
Fast Interrupt Vector Address High 0 Register
FIM1
$E
Fast Interrupt Match Register 1
FIVAL1
$F
Fast Interrupt Vector Address Low 1 Register
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Table 4-19 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F1A0) (Continued)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
FIVAH1
$10
Fast Interrupt Vector Address High 1 Register
IRQP 0
$11
IRQ Pending Register 0
IRQP 1
$12
IRQ Pending Register 1
IRQP 2
$13
IRQ Pending Register 2
IRQP 3
$14
IRQ Pending Register 3
IRQP 4
$15
IRQ Pending Register 4
IRQP 5
$16
IRQ Pending Register 5
Reserved
ICTL
$1D
Interrupt Control Register
Table 4-20 Analog-to-Digital Converter Registers Address Map
(ADCA_BASE = $00 F200)
Register Acronym
52
Address Offset
Register Description
ADCA_CR1
$0
Control Register 1
ADCA_CR2
$1
Control Register 2
ADCA_ZCC
$2
Zero Crossing Control Register
ADCA_LST 1
$3
Channel List Register 1
ADCA_LST 2
$4
Channel List Register 2
ADCA_SDIS
$5
Sample Disable Register
ADCA_STAT
$6
Status Register
ADCA_LSTAT
$7
Limit Status Register
ADCA_ZCSTAT
$8
Zero Crossing Status Register
ADCA_RSLT 0
$9
Result Register 0
ADCA_RSLT 1
$A
Result Register 1
ADCA_RSLT 2
$B
Result Register 2
ADCA_RSLT 3
$C
Result Register 3
ADCA_RSLT 4
$D
Result Register 4
ADCA_RSLT 5
$E
Result Register 5
ADCA_RSLT 6
$F
Result Register 6
ADCA_RSLT 7
$10
Result Register 7
ADCA_LLMT 0
$11
Low Limit Register 0
ADCA_LLMT 1
$12
Low Limit Register 1
ADCA_LLMT 2
$13
Low Limit Register 2
ADCA_LLMT 3
$14
Low Limit Register 3
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Peripheral Memory Mapped Registers
Table 4-20 Analog-to-Digital Converter Registers Address Map
(ADCA_BASE = $00 F200) (Continued)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
ADCA_LLMT 4
$15
Low Limit Register 4
ADCA_LLMT 5
$16
Low Limit Register 5
ADCA_LLMT 6
$17
Low Limit Register 6
ADCA_LLMT 7
$18
Low Limit Register 7
ADCA_HLMT 0
$19
High Limit Register 0
ADCA_HLMT 1
$1A
High Limit Register 1
ADCA_HLMT 2
$1B
High Limit Register 2
ADCA_HLMT 3
$1C
High Limit Register 3
ADCA_HLMT 4
$1D
High Limit Register 4
ADCA_HLMT 5
$1E
High Limit Register 5
ADCA_HLMT 6
$1F
High Limit Register 6
ADCA_HLMT 7
$20
High Limit Register 7
ADCA_OFS 0
$21
Offset Register 0
ADCA_OFS 1
$22
Offset Register 1
ADCA_OFS 2
$23
Offset Register 2
ADCA_OFS 3
$24
Offset Register 3
ADCA_OFS 4
$25
Offset Register 4
ADCA_OFS 5
$26
Offset Register 5
ADCA_OFS 6
$27
Offset Register 6
ADCA_OFS 7
$28
Offset Register 7
ADCA_POWER
$29
Power Control Register
ADCA_CAL
$2A
ADC Calibration Register
Table 4-21 Analog-to-Digital Converter Registers Address Map
(ADCB_BASE = $00 F240)
Register Acronym
Address Offset
Register Description
ADCB_CR1
$0
Control Register 1
ADCB_CR2
$1
Control Register 2
ADCB_ZCC
$2
Zero Crossing Control Register
ADCB_LST 1
$3
Channel List Register 1
ADCB_LST 2
$4
Channel List Register 2
ADCB_SDIS
$5
Sample Disable Register
ADCB_STAT
$6
Status Register
ADCB_LSTAT
$7
Limit Status Register
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Freescale Semiconductor, Inc.
Table 4-21 Analog-to-Digital Converter Registers Address Map
(ADCB_BASE = $00 F240) (Continued)
Freescale Semiconductor, Inc...
Register Acronym
54
Address Offset
Register Description
ADCB_ZCSTAT
$8
Zero Crossing Status Register
ADCB_RSLT 0
$9
Result Register 0
ADCB_RSLT 1
$A
Result Register 1
ADCB_RSLT 2
$B
Result Register 2
ADCB_RSLT 3
$C
Result Register 3
ADCB_RSLT 4
$D
Result Register 4
ADCB_RSLT 5
$E
Result Register 5
ADCB_RSLT 6
$F
Result Register 6
ADCB_RSLT 7
$10
Result Register 7
ADCB_LLMT 0
$11
Low Limit Register 0
ADCB_LLMT 1
$12
Low Limit Register 1
ADCB_LLMT 2
$13
Low Limit Register 2
ADCB_LLMT 3
$14
Low Limit Register 3
ADCB_LLMT 4
$15
Low Limit Register 4
ADCB_LLMT 5
$16
Low Limit Register 5
ADCB_LLMT 6
$17
Low Limit Register 6
ADCB_LLMT 7
$18
Low Limit Register 7
ADCB_HLMT 0
$19
High Limit Register 0
ADCB_HLMT 1
$1A
High Limit Register 1
ADCB_HLMT 2
$1B
High Limit Register 2
ADCB_HLMT 3
$1C
High Limit Register 3
ADCB_HLMT 4
$1D
High Limit Register 4
ADCB_HLMT 5
$1E
High Limit Register 5
ADCB_HLMT 6
$1F
High Limit Register 6
ADCB_HLMT 7
$20
High Limit Register 7
ADCB_OFS 0
$21
Offset Register 0
ADCB_OFS 1
$22
Offset Register 1
ADCB_OFS 2
$23
Offset Register 2
ADCB_OFS 3
$24
Offset Register 3
ADCB_OFS 4
$25
Offset Register 4
ADCB_OFS 5
$26
Offset Register 5
ADCB_OFS 6
$27
Offset Register 6
ADCB_OFS 7
$28
Offset Register 7
ADCB_POWER
$29
Power Control Register
ADCB_CAL
$2A
ADC Calibration Register
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Freescale Semiconductor, Inc.
Peripheral Memory Mapped Registers
Table 4-22 Temperature Sensor Register Address Map
(TSENSOR_BASE = $00 F270)
Register Acronym
TSENSOR_CNTL
Address Offset
$0
Register Description
Control Register
Table 4-23 Serial Communication Interface 0 Registers Address Map
(SCI0_BASE = $00 F280)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
SCI0_SCIBR
$0
Baud Rate Register
SCI0_SCICR
$1
Control Register
Reserved
SCI0_SCISR
$3
Status Register
SCI0_SCIDR
$4
Data Register
Table 4-24 Serial Communication Interface 1 Registers Address Map
(SCI1_BASE = $00 F290)
Register Acronym
Address Offset
Register Description
SCI1_SCIBR
$0
Baud Rate Register
SCI1_SCICR
$1
Control Register
Reserved
SCI1_SCISR
$3
Status Register
SCI1_SCIDR
$4
Data Register
Table 4-25 Serial Peripheral Interface 0 Registers Address Map
(SPI0_BASE = $00 F2A0)
Register Acronym
Address Offset
Register Description
SPI0_SPSCR
$0
Status and Control Register
SPI0_SPDSR
$1
Data Size Register
SPI0_SPDRR
$2
Data Receive Register
SPI0_SPDTR
$3
Data Transmitter Register
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Table 4-26 Serial Peripheral Interface 1 Registers Address Map
(SPI1_BASE = $00 F2B0)
Register Acronym
Address Offset
Register Description
SPI1_SPSCR
$0
Status and Control Register
SPI1_SPDSR
$1
Data Size Register
SPI1_SPDRR
$2
Data Receive Register
SPI1_SPDTR
$3
Data Transmitter Register
Freescale Semiconductor, Inc...
Table 4-27 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F2C0)
Register Acronym
Address Offset
Register Description
COPCTL
$0
Control Register
COPTO
$1
Time-Out Register
COPCTR
$2
Counter Register
Table 4-28 Clock Generation Module Registers Address Map
(CLKGEN_BASE = $00 F2D0)
Register Acronym
Address Offset
Register Description
PLLCR
$0
Control Register
PLLDB
$1
Divide-By Register
PLLSR
$2
Status Register
Reserved
SHUTDOWN
$4
Shutdown Register
OSCTL
$5
Oscillator Control Register
Table 4-29 GPIOA Registers Address Map
(GPIOA_BASE = $00 F2E0)
Register Acronym
56
Address Offset
Register Description
Reset Value
GPIOA_PUR
$0
Pull-up Enable Register
0 x 3FFF
GPIOA_DR
$1
Data Register
0 x 0000
GPIOA_DDR
$2
Data Direction Register
0 x 0000
GPIOA_PER
$3
Peripheral Enable Register
0 x 3FFF
GPIOA_IAR
$4
Interrupt Assert Register
0 x 0000
GPIOA_IENR
$5
Interrupt Enable Register
0 x 0000
GPIOA_IPOLR
$6
Interrupt Polarity Register
0 x 0000
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Freescale Semiconductor, Inc.
Peripheral Memory Mapped Registers
Table 4-29 GPIOA Registers Address Map
(GPIOA_BASE = $00 F2E0)
Register Acronym
Address Offset
Register Description
Reset Value
GPIOA_IPR
$7
Interrupt Pending Register
0 x 0000
GPIOA_IESR
$8
Interrupt Edge-Sensitive Register
0 x 0000
GPIOA_PPMODE
$9
Push-Pull Mode Register
0 x 3FFF
GPIOA_RAWDATA
$A
Raw Data Input Register
—
Freescale Semiconductor, Inc...
Table 4-30 GPIOB Registers Address Map
(GPIOB_BASE = $00 F300)
Register Acronym
Address Offset
Register Description
Reset Value
GPIOB_PUR
$0
Pull-up Enable Register
0 x 00FF
GPIOB_DR
$1
Data Register
0 x 0000
GPIOB_DDR
$2
Data Direction Register
0 x 0000
GPIOB_PER
$3
Peripheral Enable Register
0 x 0000
GPIOB_IAR
$4
Interrupt Assert Register
0 x 0000
GPIOB_IENR
$5
Interrupt Enable Register
0 x 0000
GPIOB_IPOLR
$6
Interrupt Polarity Register
0 x 0000
GPIOB_IPR
$7
Interrupt Pending Register
0 x 0000
GPIOB_IESR
$8
Interrupt Edge-Sensitive Register
0 x 0000
GPIOB_PPMODE
$9
Push-Pull Mode Register
0 x 00FF
GPIOB_RAWDATA
$A
Raw Data Input Register
—
Table 4-31 GPIOC Registers Address Map
(GPIOC_BASE = $00 F310)
Register Acronym
Address Offset
Register Description
Reset Value
GPIOC_PUR
$0
Pull-up Enable Register
0 x 07FF
GPIOC_DR
$1
Data Register
0 x 0000
GPIOC_DDR
$2
Data Direction Register
0 x 0000
GPIOC_PER
$3
Peripheral Enable Register
0 x 07FF
GPIOC_IAR
$4
Interrupt Assert Register
0 x 0000
GPIOC_IENR
$5
Interrupt Enable Register
0 x 0000
GPIOC_IPOLR
$6
Interrupt Polarity Register
0 x 0000
GPIOC_IPR
$7
Interrupt Pending Register
0 x 0000
GPIOC_IESR
$8
Interrupt Edge-Sensitive Register
0 x 0000
GPIOC_PPMODE
$9
Push-Pull Mode Register
0 x 07FF
GPIOC_RAWDATA
$A
Raw Data Input Register
—
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Table 4-32 GPIOD Registers Address Map
(GPIOD_BASE = $00 F320)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
Reset Value
GPIOD_PUR
$0
Pull-up Enable Register
0 x 1FFF
GPIOD_DR
$1
Data Register
0 x 0000
GPIOD_DDR
$2
Data Direction Register
0 x 0000
GPIOD_PER
$3
Peripheral Enable Register
0 x 1FC0
GPIOD_IAR
$4
Interrupt Assert Register
0 x 0000
GPIOD_IENR
$5
Interrupt Enable Register
0 x 0000
GPIOD_IPOLR
$6
Interrupt Polarity Register
0 x 0000
GPIOD_IPR
$7
Interrupt Pending Register
0 x 0000
GPIOD_IESR
$8
Interrupt Edge-Sensitive Register
0 x 0000
GPIOD_PPMODE
$9
Push-Pull Mode Register
0 x 1FFF
GPIOD_RAWDATA
$A
Raw Data Input Register
—
Table 4-33 GPIOE Registers Address Map
(GPIOE_BASE = $00 F330)
Register Acronym
58
Address Offset
Register Description
Reset Value
GPIOE_PUR
$0
Pull-up Enable Register
0 x 3FFF
GPIOE_DR
$1
Data Register
0 x 0000
GPIOE_DDR
$2
Data Direction Register
0 x 0000
GPIOE_PER
$3
Peripheral Enable Register
0 x 3FFF
GPIOE_IAR
$4
Interrupt Assert Register
0 x 0000
GPIOE_IENR
$5
Interrupt Enable Register
0 x 0000
GPIOE_IPOLR
$6
Interrupt Polarity Register
0 x 0000
GPIOE_IPR
$7
Interrupt Pending Register
0 x 0000
GPIOE_IESR
$8
Interrupt Edge-Sensitive Register
0 x 0000
GPIOE_PPMODE
$9
Push-Pull Mode Register
0 x 3FFF
GPIOE_RAWDATA
$A
Raw Data Input Register
—
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Freescale Semiconductor, Inc.
Peripheral Memory Mapped Registers
Table 4-34 GPIOF Registers Address Map
(GPIOF_BASE = $00 F340)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
Reset Value
GPIOF_PUR
$0
Pull-up Enable Register
0 x FFFF
GPIOF_DR
$1
Data Register
0 x 0000
GPIOF_DDR
$2
Data Direction Register
0 x 0000
GPIOF_PER
$3
Peripheral Enable Register
0 x FFFF
GPIOF_IAR
$4
Interrupt Assert Register
0 x 0000
GPIOF_IENR
$5
Interrupt Enable Register
0 x 0000
GPIOF_IPOLR
$6
Interrupt Polarity Register
0 x 0000
GPIOF_IPR
$7
Interrupt Pending Register
0 x 0000
GPIOF_IESR
$8
Interrupt Edge-Sensitive Register
0 x 0000
GPIOF_PPMODE
$9
Push-Pull Mode Register
0 x FFFF
GPIOF_RAWDATA
$A
Raw Data Input Register
—
Table 4-35 System Integration Module Registers Address Map
(SIM_BASE = $00 F350)
Register Acronym
Address Offset
Register Description
SIM_CONTROL
$0
Control Register
SIM_RSTSTS
$1
Reset Status Register
SIM_SCR0
$2
Software Control Register 0
SIM_SCR1
$3
Software Control Register 1
SIM_SCR2
$4
Software Control Register 2
SIM_SCR3
$5
Software Control Register 3
SIM_MSH_ID
$6
Most Significant Half JTAG ID
SIM_LSH_ID
$7
Least Significant Half JTAG ID
SIM_PUDR
$8
Pull-up Disable Register
Reserved
SIM_CLKOSR
$A
Clock Out Select Register
SIM_GPS
$B
Quad Decoder 1 / Timer B / SPI 1 Select Register
SIM_PCE
$C
Peripheral Clock Enable Register
SIM_ISALH
$D
I/O Short Address Location High Register
SIM_ISALL
$E
I/O Short Address Location Low Register
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Table 4-36 Power Supervisor Registers Address Map
(LVI_BASE = $00 F360)
Register Acronym
Address Offset
Register Description
LVI_CONTROL
$0
Control Register
LVI_STATUS
$1
Status Register
Table 4-37 Flash Module Registers Address Map
(FM_BASE = $00 F400)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
FMCLKD
$0
Clock Divider Register
FMMCR
$1
Module Control Register
Reserved
FMSECH
$3
Security High Half Register
FMSECL
$4
Security Low Half Register
FMMNTR
$5
Monitor Data Register
Reserved
FMPROT
$10
Protection Register (Banked)
FMPROTB
$11
Protection Boot Register (Banked)
Reserved
FMUSTAT
$13
User Status Register (Banked)
FMCMD
$14
Command Register (Banked)
FMCTL
$15
Control Register (Banked)
Reserved
60
FMIFROPT 0
$1A
16-Bit Information Option Register 0
Hot temperature ADC reading of Temperature Sensor;
value set during factory test
FMIFROPT 1
$1B
16-Bit Information Option Register 1
Not used
FMIFROPT 2
$1C
16-Bit Information Option Register 2
Room temperature ADC reading of Temperature Sensor;
value set during factory test
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Freescale Semiconductor, Inc.
Peripheral Memory Mapped Registers
Table 4-38 FlexCAN Registers Address Map
(FC_BASE = $00 F800)
Register Acronym
FCMCR
Address Offset
$0
Register Description
Module Configuration Register
Freescale Semiconductor, Inc...
Reserved
FCCTL0
$3
Control Register 0 Register
FCCTL1
$4
Control Register 1 Register
FCTMR
$5
Free-Running Timer Register
FCMAXMB
$6
Maximum Message Buffer Configuration Register
FCIMASK2
$7
Interrupt Masks 2 Register
FCRXGMASK_H
$8
Receive Global Mask High Register
FCRXGMASK_L
$9
Receive Global Mask Low Register
FCRX14MASK_H
$A
Receive Buffer 14 Mask High Register
FCRX14MASK_L
$B
Receive Buffer 14 Mask Low Register
FCRX15MASK_H
$C
Receive Buffer 15 Mask High Register
FCRX15MASK_L
$D
Receive Buffer 15 Mask Low Register
Reserved
FCSTATUS
$10
Error and Status Register
FCIMASK1
$11
Interrupt Masks 1 Register
FCIFLAG1
$12
Interrupt Flags 1 Register
FCR/T_ERROR_CNTRS
$13
Receive and Transmit Error Counters Register
Reserved
FCIFLAG 2
$1B
Interrupt Flags 2 Register
Reserved
FCMB0_CONTROL
$40
Message Buffer 0 Control / Status Register
FCMB0_ID_HIGH
$41
Message Buffer 0 ID High Register
FCMB0_ID_LOW
$42
Message Buffer 0 ID Low Register
FCMB0_DATA
$43
Message Buffer 0 Data Register
FCMB0_DATA
$44
Message Buffer 0 Data Register
FCMB0_DATA
$45
Message Buffer 0 Data Register
FCMB0_DATA
$46
Message Buffer 0 Data Register
Reserved
FCMSB1_CONTROL
$48
Message Buffer 1 Control / Status Register
FCMSB1_ID_HIGH
$49
Message Buffer 1 ID High Register
FCMSB1_ID_LOW
$4A
Message Buffer 1 ID Low Register
FCMB1_DATA
$4B
Message Buffer 1 Data Register
FCMB1_DATA
$4C
Message Buffer 1 Data Register
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Table 4-38 FlexCAN Registers Address Map
(FC_BASE = $00 F800) (Continued)
Register Acronym
Address Offset
Register Description
FCMB1_DATA
$4D
Message Buffer 1 Data Register
FCMB1_DATA
$4E
Message Buffer 1 Data Register
Freescale Semiconductor, Inc...
Reserved
FCMB2_CONTROL
$50
Message Buffer 2 Control / Status Register
FCMB2_ID_HIGH
$51
Message Buffer 2 ID High Register
FCMB2_ID_LOW
$52
Message Buffer 2 ID Low Register
FCMB2_DATA
$53
Message Buffer 2 Data Register
FCMB2_DATA
$54
Message Buffer 2 Data Register
FCMB2_DATA
$55
Message Buffer 2 Data Register
FCMB2_DATA
$56
Message Buffer 2 Data Register
Reserved
FCMB3_CONTROL
$58
Message Buffer 3 Control / Status Register
FCMB3_ID_HIGH
$59
Message Buffer 3 ID High Register
FCMB3_ID_LOW
$5A
Message Buffer 3 ID Low Register
FCMB3_DATA
$5B
Message Buffer 3 Data Register
FCMB3_DATA
$5C
Message Buffer 3 Data Register
FCMB3_DATA
$5D
Message Buffer 3 Data Register
FCMB3_DATA
$5E
Message Buffer 3 Data Register
Reserved
FCMB4_CONTROL
$60
Message Buffer 4 Control / Status Register
FCMB4_ID_HIGH
$61
Message Buffer 4 ID High Register
FCMB4_ID_LOW
$62
Message Buffer 4 ID Low Register
FCMB4_DATA
$63
Message Buffer 4 Data Register
FCMB4_DATA
$64
Message Buffer 4 Data Register
FCMB4_DATA
$65
Message Buffer 4 Data Register
FCMB4_DATA
$66
Message Buffer 4 Data Register
Reserved
FCMB5_CONTROL
$68
Message Buffer 5 Control / Status Register
FCMB5_ID_HIGH
$69
Message Buffer 5 ID High Register
FCMB5_ID_LOW
$6A
Message Buffer 5 ID Low Register
FCMB5_DATA
$6B
Message Buffer 5 Data Register
FCMB5_DATA
$6C
Message Buffer 5 Data Register
FCMB5_DATA
$6D
Message Buffer 5 Data Register
FCMB5_DATA
$6E
Message Buffer 5 Data Register
Reserved
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Peripheral Memory Mapped Registers
Table 4-38 FlexCAN Registers Address Map
(FC_BASE = $00 F800) (Continued)
Freescale Semiconductor, Inc...
Register Acronym
Address Offset
Register Description
FCMB6_CONTROL
$70
Message Buffer 6 Control / Status Register
FCMB6_ID_HIGH
$71
Message Buffer 6 ID High Register
FCMB6_ID_LOW
$72
Message Buffer 6 ID Low Register
FCMB6_DATA
$73
Message Buffer 6 Data Register
FCMB6_DATA
$74
Message Buffer 6 Data Register
FCMB6_DATA
$75
Message Buffer 6 Data Register
FCMB6_DATA
$76
Message Buffer 6 Data Register
Reserved
FCMB7_CONTROL
$78
Message Buffer 7 Control / Status Register
FCMB7_ID_HIGH
$79
Message Buffer 7 ID High Register
FCMB7_ID_LOW
$7A
Message Buffer 7 ID Low Register
FCMB7_DATA
$7B
Message Buffer 7 Data Register
FCMB7_DATA
$7C
Message Buffer 7 Data Register
FCMB7_DATA
$7D
Message Buffer 7 Data Register
FCMB7_DATA
$7E
Message Buffer 7 Data Register
Reserved
FCMB8_CONTROL
$80
Message Buffer 8 Control / Status Register
FCMB8_ID_HIGH
$81
Message Buffer 8 ID High Register
FCMB8_ID_LOW
$82
Message Buffer 8 ID Low Register
FCMB8_DATA
$83
Message Buffer 8 Data Register
FCMB8_DATA
$84
Message Buffer 8 Data Register
FCMB8_DATA
$85
Message Buffer 8 Data Register
FCMB8_DATA
$86
Message Buffer 8 Data Register
Reserved
FCMB9_CONTROL
$88
Message Buffer 9 Control / Status Register
FCMB9_ID_HIGH
$89
Message Buffer 9 ID High Register
FCMB9_ID_LOW
$8A
Message Buffer 9 ID Low Register
FCMB9_DATA
$8B
Message Buffer 9 Data Register
FCMB9_DATA
$8C
Message Buffer 9 Data Register
FCMB9_DATA
$8D
Message Buffer 9 Data Register
FCMB9_DATA
$8E
Message Buffer 9 Data Register
Reserved
FCMB10_CONTROL
$90
Message Buffer 10 Control / Status Register
FCMB10_ID_HIGH
$91
Message Buffer 10 ID High Register
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Table 4-38 FlexCAN Registers Address Map
(FC_BASE = $00 F800) (Continued)
Register Acronym
Address Offset
Register Description
FCMB10_ID_LOW
$92
Message Buffer 10 ID Low Register
FCMB10_DATA
$93
Message Buffer 10 Data Register
FCMB10_DATA
$94
Message Buffer 10 Data Register
FCMB10_DATA
$95
Message Buffer 10 Data Register
FCMB10_DATA
$96
Message Buffer 10 Data Register
Freescale Semiconductor, Inc...
Reserved
FCMB11_CONTROL
$98
Message Buffer 11 Control / Status Register
FCMB11_ID_HIGH
$99
Message Buffer 11 ID High Register
FCMB11_ID_LOW
$9A
Message Buffer 11 ID Low Register
FCMB11_DATA
$9B
Message Buffer 11 Data Register
FCMB11_DATA
$9C
Message Buffer 11 Data Register
FCMB11_DATA
$9D
Message Buffer 11 Data Register
FCMB11_DATA
$9E
Message Buffer 11 Data Register
Reserved
FCMB12_CONTROL
$A0
Message Buffer 12 Control / Status Register
FCMB12_ID_HIGH
$A1
Message Buffer 12 ID High Register
FCMB12_ID_LOW
$A2
Message Buffer 12 ID Low Register
FCMB12_DATA
$A3
Message Buffer 12 Data Register
FCMB12_DATA
$A4
Message Buffer 12 Data Register
FCMB12_DATA
$A5
Message Buffer 12 Data Register
FCMB12_DATA
$A6
Message Buffer 12 Data Register
Reserved
FCMB13_CONTROL
$A8
Message Buffer 13 Control / Status Register
FCMB13_ID_HIGH
$A9
Message Buffer 13 ID High Register
FCMB13_ID_LOW
$AA
Message Buffer 13 ID Low Register
FCMB13_DATA
$AB
Message Buffer 13 Data Register
FCMB13_DATA
$AC
Message Buffer 13 Data Register
FCMB13_DATA
$AD
Message Buffer 13 Data Register
FCMB13_DATA
$AE
Message Buffer 13 Data Register
Reserved
64
FCMB14_CONTROL
$B0
Message Buffer 14 Control / Status Register
FCMB14_ID_HIGH
$B1
Message Buffer 14 ID High Register
FCMB14_ID_LOW
$B2
Message Buffer 14 ID Low Register
FCMB14_DATA
$B3
Message Buffer 14 Data Register
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Factory Programmed Memory
Table 4-38 FlexCAN Registers Address Map
(FC_BASE = $00 F800) (Continued)
Register Acronym
Address Offset
Register Description
FCMB14_DATA
$B4
Message Buffer 14 Data Register
FCMB14_DATA
$B5
Message Buffer 14 Data Register
FCMB14_DATA
$B6
Message Buffer 14 Data Register
Freescale Semiconductor, Inc...
Reserved
FCMB15_CONTROL
$B8
Message Buffer 15 Control / Status Register
FCMB15_ID_HIGH
$B9
Message Buffer 15 ID High Register
FCMB15_ID_LOW
$BA
Message Buffer 15 ID Low Register
FCMB15_DATA
$BB
Message Buffer 15 Data Register
FCMB15_DATA
$BC
Message Buffer 15 Data Register
FCMB15_DATA
$BD
Message Buffer 15 Data Register
FCMB15_DATA
$BE
Message Buffer 15 Data Register
Reserved
4.8 Factory Programmed Memory
During manufacturing the Boot Flash memory block is programmed with a default Serial
Bootloader program. The Serial Bootloader application can be used to load a user application into
the Program and Data Flash memories of the device. The document MC56F83xxBLUM/D,
56F83xx SCI/CAN Bootloader User Manual provides detailed information on this firmware.
The application note AN1973/D, Production Flash Programming provides additional
information on how the Serial Bootloader program can be used to perform production flash
programming of the on board flash memories as well as other potential methods.
Like all the flash memory blocks the Boot Flash can be erased and programmed by the user. The
Serial Bootloader application is programmed as an aid to the end user, but is not required to be used
or maintained in the Boot Flash memory.
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Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests
(IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and to what
address to jump in order to service this interrupt.
5.2 Features
Freescale Semiconductor, Inc...
The ITCN module design includes these distinctive features:
•
•
•
•
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Drives initial address on the address bus after reset
For further information, see Table 4-5, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82
interrupt sources to be set to one of four priority levels, excluding certain interrupts of fixed
priority. Next, all of the interrupt requests of a given level are priority encoded to determine the
lowest numerical value of the active interrupt requests for that level. Within a given priority level,
0 is the highest priority, while number 81 is the lowest.
5.3.1
Normal Interrupt Handling
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the
highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates
the VBA and the vector number to determine the vector address. In this way, an offset is generated
into the vector table for each interrupt.
5.3.2
Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to
be serviced. The following tables define the nesting requirements for each priority level.
Table 5-1 Interrupt Mask Bit Definition
SR[9]1
SR[8]1
0
0
Priorities 0, 1, 2, 3
None
0
1
Priorities 1, 2, 3
Priority 0
1
0
Priorities 2, 3
Priorities 0, 1
1
1
Priority 3
Priorities 0, 1, 2
Permitted Exceptions
Masked Exceptions
1. Core status register bits indicating current interrupt mask within the core.
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Functional Description
Table 5-2. Interrupt Priority Encoding
IPIC_LEVEL[1:0]1
Current Interrupt
Priority Level
Required Nested
Exception Priority
00
No Interrupt or SWILP
Priorities 0, 1, 2, 3
01
Priority 0
Priorities 1, 2, 3
10
Priority 1
Priorities 2, 3
11
Priorities 2 or 3
Priority 3
Freescale Semiconductor, Inc...
1. See IPIC field definition in Section 5.6.30.2 Interrupt Priority Level (IPIC)—Bits
14–13
5.3.3
Fast Interrupt Handling
Fast interrupts are described in the DSP56F800E Reference Manual. The interrupt controller
recognizes fast interrupts before the core does.
A fast interrupt is defined (to the ITCN) by:
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values.
If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN
takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating
an address that is an offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the
core starts its fast interrupt handling.
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5.4 Block Diagram
any0
Priority
Level
INT1
Level 0
82 -> 7
Priority
Encoder
2 -> 4
Decode
7
Freescale Semiconductor, Inc...
INT
VAB
CONTROL
any3
Level 3
IACK
SR[9:8]
Priority
Level
INT82
IPIC
82 -> 7
Priority
Encoder
7
PIC_EN
2 -> 4
Decode
Figure 5-1 Interrupt Controller Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
•
•
Functional Mode
The ITCN is in this mode by default.
Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will
signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the
IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop
mode. Also, the IRQA and IRQB signals automatically become low-level sensitive in these modes,
even if the control register bits are set to make them falling-edge sensitive. This is because there is
no clock available to detect the falling edge.
A peripheral which requires a clock to generate interrupts will not be able to generate interrupts
during Stop mode. The FlexCAN module can wake the device from Stop mode, and a reset will do
just that, or IRQA and IRQB can wake it up.
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Register Descriptions
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined
at the system level and the address offset is defined at the module level. The ITCN peripheral has
24 registers.
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00F1A0)
Freescale Semiconductor, Inc...
Register
Acronym
Base Address +
Register Name
Section Location
IPR0
$0
Interrupt Priority Register 0
5.6.1
IPR1
$1
Interrupt Priority Register 1
5.6.2
IPR2
$2
Interrupt Priority Register 2
5.6.3
IPR3
$3
Interrupt Priority Register 3
5.6.4
IPR4
$4
Interrupt Priority Register 4
5.6.5
IPR5
$5
Interrupt Priority Register 5
5.6.6
IPR6
$6
Interrupt Priority Register 6
5.6.7
IPR7
$7
Interrupt Priority Register 7
5.6.8
IPR8
$8
Interrupt Priority Register 8
5.6.9
IPR9
$9
Interrupt Priority Register 9
5.6.10
VBA
$A
Vector Base Address Register
5.6.11
FIM0
$B
Fast Interrupt 0 Match Register
5.6.12
FIVAL0
$C
Fast Interrupt 0 Vector Address Low Register
5.6.13
FIVAH0
$D
Fast Interrupt 0 Vector Address High Register
5.6.14
FIM1
$E
Fast Interrupt 1 Match Register
5.6.15
FIVAL1
$F
Fast Interrupt 1 Vector Address Low Register
5.6.16
FIVAH1
$10
Fast Interrupt 1 Vector Address High Register
5.6.17
IRQP0
$11
IRQ Pending Register 0
5.6.18
IRQP1
$12
IRQ Pending Register 1
5.6.19
IRQP2
$13
IRQ Pending Register 2
5.6.20
IRQP3
$14
IRQ Pending Register 3
5.6.21
IRQP4
$15
IRQ Pending Register 4
5.6.22
IRQP5
$16
IRQ Pending Register 5
5.6.23
Reserved
ICTL
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$1D
Interrupt Control Register
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5.6.30
69
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Freescale Semiconductor, Inc...
Add. Register
Offset Name
$0
IPR0
$1
IPR1
$2
IPR2
$3
IPR3
$4
IPR4
$5
IPR5
$6
IPR6
$7
IPR7
$8
IPR8
$9
IPR9
$A
VBA
$B
FIM0
$C
FIVAL0
$D
FIVAH0
$E
FIM1
$F
FIVAL1
$10
FIVAH1
$11
IRQP0
$12
IRQP1
$13
IRQP2
$14
IRQP3
$15
IRQP4
$16
IRQP5
R
15
14
0
0
0
0
13
BKPT_U0 IPL
W
R
12
0
0
11
10
STPCNT IPL
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
FMCBE IPL
R
R
R
W
R
W
R
W
R
W
R
W
R
FMERR IPL
GPIOD
IPL
GPIOE
IPL
GPIOF
IPL
SPI0_RCV
IPL
SPI1_XMIT
IPL
SPI1_RCV
IPL
W
W
FMCC IPL
DEC1_XIRQ IPL DEC1_HIRQ IPL
LOCK IPL
FCMSGBUF IPL
0
0
SCI1_RCV
IPL
SCI1_RERR
IPL
RX_REG IPL
0
LVI IPL
FCWKUP IPL
0
0
0
0
0
TX_REG IPL
IRQB IPL
TRBUF IPL
IRQA IPL
0
0
FCERR IPL
FCBOFF IPL
GPIOA IPL
GPIOB IPL
GPIOC IPL
SCI1_TIDL
IPL
SCI1_XMIT
IPL
SPI0_XMIT
IPL
DEC0_XIRQ IPL
DEC0_HIRQ
IPL
0
0
TMRC0 IPL
TMRD3 IPL
TMRD2 IPL
TMRD1 IPL
TMRD0 IPL
TMRA0 IPL
TMRB3 IPL
TMRB2 IPL
TMRB1 IPL
TMRB0 IPL
TMRC3 IPL
TMRC2 IPL
TMRC1 IPL
SCI0_RCV IPL
SCI0_RERR IPL
SCI0_TIDL IPL
SCI0_XMIT IPL
TMRA3 IPL
TMRA2 IPL
TMRA1 IPL
PWMA_F IPL
PWMB_F IPL
PWMB_RL IPL
ADCA_ZC IPL
ABCB_ZC IPL
ADCA_CC IPL
ADCB_CC IPL
0
0
0
0
0
0
0
0
PWMA_RL
IPL
VECTOR BASE ADDRESS
W
R
0
0
0
0
0
0
FAST INTERRUPT 0
W
R
FAST INTERRUPT 0
VECTOR ADDRESS LOW
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 0
VECTOR ADDRESS HIGH
W
R
FAST INTERRUPT 1
W
R
FAST INTERRUPT 1
VECTOR ADDRESS LOW
W
R
0
0
0
0
0
0
0
0
0
0
0
W
0
0
0
0
0
0
0
0
0
0
0
R
FAST INTERRUPT 1
VECTOR ADDRESS HIGH
PENDING [16:2]
1
W
R
PENDING [32:17]
W
R
PENDING [48:33]
W
R
PENDING [64:49]
W
R
PENDING [80:65]
W
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PENDING
[81]
W
Reserved
$1D
ICTL
R
INT
IPIC
VAB
INT_DIS
W
1
IRQA
IRQB
STATE STATE IRQB
EDG
IRQA
EDG
= Reserved
Figure 5-2 ITCN Register Map Summary
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Register Descriptions
5.6.1
Interrupt Priority Register 0 (IPR0)
Base + $0
15
14
Read
0
0
13
12
BKPT_U0IPL
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STPCNT IPL
Write
RESET
0
0
0
0
0
0
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1
Reserved—Bits 15–14
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This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.1.2
EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)—
Bits13–12
This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.3
EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.4
Reserved—Bits 9–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2
Interrupt Priority Register 1 (IPR1)
Base + $1
15
14
13
12
11
10
9
8
7
6
Read
0
0
0
0
0
0
0
0
0
0
5
4
RX_REG IPL
3
2
TX_REG IPL
1
0
TRBUF IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-4 Interrupt Priority Register 1 (IPR1)
5.6.2.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
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5.6.2.2
EOnCE Receive Register Full Interrupt Priority Level
(RX_REG IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
Freescale Semiconductor, Inc...
5.6.2.3
EOnCE Transmit Register Empty Interrupt Priority Level
(TX_REG IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.2.4
EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)—
Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.3
Interrupt Priority Register 2 (IPR2)
Base + $2
15
14
13
12
11
10
9
8
7
6
Read
FMCBE IPL
FMCC IPL
FMERR IPL
LOCK IPL
5
4
0
0
LVI IPL
3
2
1
0
IRQB IPL
IRQA IPL
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-5 Interrupt Priority Register 2 (IPR2)
5.6.3.1
Flash Memory Command, Data, Address Buffers Empty Interrupt
Priority Level (FMCBE IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.
•
•
•
•
72
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Register Descriptions
5.6.3.2
Flash Memory Command Complete Priority Level
(FMCC IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
Freescale Semiconductor, Inc...
5.6.3.3
Flash Memory Error Interrupt Priority Level
(FMERR IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.4
PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.5
Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.6
Reserved—Bits 5–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
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5.6.3.7
External IRQ B Interrupt Priority Level (IRQB IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.8
External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0
Freescale Semiconductor, Inc...
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4
Interrupt Priority Register 3 (IPR3)
Base + $3
Read
Write
RESET
15
14
13
12
11
10
GPIOD
IPL
GPIOE
IPL
GPIOF
IPL
0
0
0
0
0
0
9
8
FCMSGBUF IPL
0
0
7
6
FCWKUP IPL
0
0
5
4
3
FCERR IPL
0
2
1
0
0
0
0
0
FCBOFF IPL
0
0
0
Figure 5-6 Interrupt Priority Register 3 (IPR3)
5.6.4.1
GPIO D Interrupt Priority Level (GPIOD IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.2
GPIO E Interrupt Priority Level (GPIOE IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
74
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Register Descriptions
5.6.4.3
GPIO F Interrupt Priority Level (GPIOF IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
Freescale Semiconductor, Inc...
5.6.4.4
FlexCAN Message Buffer Interrupt Priority Level
(FCMSGBUF IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.5
FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.6
FlexCAN Error Interrupt Priority Level (FCERR IPL)—
Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.7
FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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5.6.4.8
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5
Interrupt Priority Register 4 (IPR4)
Base + $4
Read
Write
RESET
15
14
SPI0_RCV
IPL
0
0
13
12
SPI1_XMIT
IPL
0
0
11
10
9
8
7
6
SPI1_RCV
IPL
0
0
0
0
0
0
0
0
0
0
5
4
GPIOA
IPL
0
0
3
2
1
GPIOB
IPL
0
0
0
GPIOC
IPL
0
0
Freescale Semiconductor, Inc...
Figure 5-7 Interrupt Priority Register 4 (IPR4)
5.6.5.1
SPI 0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.2
SPI 1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.3
SPI 1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.4
Reserved—Bits 9–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
76
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Register Descriptions
5.6.5.5
GPIO A Interrupt Priority Level (GPIOA IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.6
GPIO B Interrupt Priority Level (GPIOB IPL)—Bits 3–2
Freescale Semiconductor, Inc...
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.7
GPIO C Interrupt Priority Level (GPIOC IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6
Interrupt Priority Register 5 (IPR5)
Base + $5
Read
Write
RESET
15
14
13
DEC1_XIRQ
IPL
0
0
12
DEC1_HIRQ
IPL
0
0
11
10
SCI1_RCV
IPL
0
0
9
8
SCI1_RERR
IPL
0
0
7
6
0
0
0
0
5
4
SCI1_TIDL
IPL
0
0
3
2
SCI1_XMIT
IPL
0
0
1
0
SPI0_XMIT
IPL
0
0
Figure 5-8 Interrupt Priority Register 5 (IPR5)
5.6.6.1
Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level
(DEC1_XIRQ IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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5.6.6.2
Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer
Interrupt Priority Level (DEC1_HIRQ IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
Freescale Semiconductor, Inc...
5.6.6.3
SCI 1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.4
SCI 1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.5
Reserved—Bits 7–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.6.6
SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—
Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
78
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Register Descriptions
5.6.6.7
SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)—
Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
Freescale Semiconductor, Inc...
5.6.6.8
SPI 0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)—
Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7
Interrupt Priority Register 6 (IPR6)
Base + $6
Read
Write
RESET
15
14
13
TMRC0
IPL
0
12
TMRD3
IPL
0
0
0
11
10
TMRD2
IPL
0
0
9
8
TMRD1
IPL
0
0
7
6
TMRD0
IPL
0
0
5
4
0
0
0
0
3
2
DEC0_XIRQ
IPL
0
0
1
0
DEC0_HIRQ
IPL
0
0
Figure 5-9 Interrupt Priority Register 6 (IPR6)
5.6.7.1
Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.2
Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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5.6.7.3
Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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5.6.7.4
Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.5
Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.6
Reserved—Bits 5–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.7.7
Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level
(DEC0_XIRQ IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
80
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Register Descriptions
5.6.7.8
Quadrature Decoder 0, HOME Signal Transition or Watchdog
Timer Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
Freescale Semiconductor, Inc...
5.6.8
Interrupt Priority Register 7 (IPR7)
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
TMRA0 IPL
TMRB3 IPL
TMRB2 IPL
TMRB1 IPL
TMRB0 IPL
TMRC3 IPL
TMRC2 IPL
TMRC1 IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-10 Interrupt Priority Register (IPR7)
5.6.8.1
Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.2
Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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5.6.8.3
Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
Freescale Semiconductor, Inc...
5.6.8.4
Timer B, Channel 1 Interrupt Priority Level (TMRB1 IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.5
Timer B, Channel 0 Interrupt Priority Level (TMRB0 IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.6
Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.7
Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
82
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Register Descriptions
5.6.8.8
Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9
Interrupt Priority Register 8 (IPR8)
Freescale Semiconductor, Inc...
Base + $8
Read
Write
RESET
15
14
SCI0_RCV
IPL
0
0
13
12
SCI0_RERR
IPL
0
0
11
10
0
0
0
0
9
8
SCI0_TIDL
IPL
0
0
7
6
SCI0_XMIT
IPL
0
0
5
4
TMRA3 IPL
0
0
3
2
TMRA2 IPL
0
0
1
0
TMRA1 IPL
0
0
Figure 5-11 Interrupt Priority Register 8 (IPR8)
5.6.9.1
SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.2
SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.3
Reserved—Bits 11–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
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5.6.9.4
SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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5.6.9.5
SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.6
Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.7
Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.8
Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
84
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Register Descriptions
5.6.10
Base + $9
Interrupt Priority Register 9 (IPR9)
15
14
13
12
Read
PWMA_F IPL
PWMB_F IPL
Write
RESET
0
0
0
0
11
10
PWMA_RL
IPL
0
0
9
8
PWMB_RL
IPL
0
0
7
6
5
4
ADCA_ZC IPL ABCB_ZC IPL
0
0
0
0
3
2
1
0
ADCA_CC
IPL
ADCB_CC
IPL
0
0
0
0
Figure 5-12 Interrupt Priority Register 9 (IPR9)
5.6.10.1
PWM A Fault Interrupt Priority Level (PWMA_F IPL)—Bits 15–14
Freescale Semiconductor, Inc...
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.2
PWM B Fault Interrupt Priority Level (PWMB_F IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.3
Reload PWM A Interrupt Priority Level (PWMA_RL IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.4
Reload PWM B Interrupt Priority Level (PWMB_RL IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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5.6.10.5
ADC A Zero Crossing Interrupt Priority Level (ADCA_ZC IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
Freescale Semiconductor, Inc...
5.6.10.6
ADC B Zero Crossing Interrupt Priority Level (ADCB_ZC IPL)—
Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.7
ADC A Conversion Complete Interrupt Priority Level
(ADCA_CC IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.8
ADC B Conversion Complete Interrupt Priority Level
(ADCB_CC IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.11
Vector Base Address Register (VBA)
Base + $A
15
14
13
Read
0
0
0
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
VECTOR BASE ADDRESS
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
Figure 5-13 Vector Base Address Register (VBA)
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Register Descriptions
5.6.11.1
Reserved—Bits 15–13
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.11.2
Interrupt Vector Base Address (VECTOR BASE ADDRESS)—
Bits 12–0
Freescale Semiconductor, Inc...
The contents of this register determine the location of the Vector Address Table. The value in this
register is used as the upper 13 bits of the interrupt Vector Address Bus (VAB[20:0]). The lower
eight bits are determined based upon the highest-priority interrupt. They are then appended onto
VBA before presenting the full interrupt address to the 56800E core; see Section 5.3.1 Normal
Interrupt Handling for details.
5.6.12
Fast Interrupt 0 Match Register (FIM0)
Base + $B
15
14
13
12
11
10
9
8
7
Read
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
FAST INTERRUPT 0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-14 Fast Interrupt 0 Match Register (FIM0)
5.6.12.1
Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.12.2
Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0
This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a
service routine based on values in the Fast Interrupt Vector Address registers without having to go
to a jump table first; see Section 5.3.3 Fast Interrupt Handling. IRQs used as fast interrupts must
be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other
priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of
their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has
priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-5.
5.6.13
Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Base + $C
15
14
13
12
11
10
Read
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
FAST INTERRUPT 0
VECTOR ADDRESS LOW
Write
RESET
0
0
0
0
0
0
0
0
0
0
Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.6.13.1
Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with
FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
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5.6.14
Fast Interrupt 0 Vector Address High Register (FIVAH0)
Base + $D
15
14
13
12
11
10
9
8
7
6
5
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
2
1
0
FAST INTERRUPT 0
VECTOR ADDRESS HIGH
Write
RESET
3
0
0
0
0
0
Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.6.14.1
Reserved—Bits 15–5
Freescale Semiconductor, Inc...
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.14.2
Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with
FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.15
Fast Interrupt 1 Match Register (FIM1)
Base + $E
15
14
13
12
11
10
9
8
7
Read
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
FAST INTERRUPT 1
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-17 Fast Interrupt 1 Match Register (FIM1)
5.6.15.1
Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.
5.6.15.2
Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0
This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a
service routine based on values in the Fast Interrupt Vector Address registers without having to go
to a jump table first; see Section 5.3.3 Fast Interrupt Handling. IRQs used as fast interrupts must
be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other
priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of
their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has
priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-5.
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Register Descriptions
5.6.16
Fast Interrupt 1 Vector Address Low Register (FIVAL1)
Base + $F
15
14
13
12
11
10
Read
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
FAST INTERRUPT 1
VECTOR ADDRESS LOW
Write
RESET
0
0
0
0
0
0
0
0
0
0
Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
5.6.16.1
Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0
Freescale Semiconductor, Inc...
The lower 16 bits of the vector address are used for Fast Interrupt 1. This register is combined with
FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.17
Fast Interrupt 1 Vector Address High Register (FIVAH1)
Base + $10
15
14
13
12
11
10
9
8
7
6
5
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
2
1
0
FAST INTERRUPT 1
VECTOR ADDRESS HIGH
Write
RESET
3
0
0
0
0
0
Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.17.1
Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.17.2
Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined
with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.18
Base + $11
IRQ Pending 0 Register (IRQP0)
15
14
13
12
11
10
9
Read
8
7
6
5
4
3
2
1
PENDING [16:2]
0
1
Write
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-20 IRQ Pending 0 Register (IRQP0)
5.6.18.1
IRQ Pending (PENDING)—Bits 16–2
This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.18.2
Reserved—Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.
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5.6.19
IRQ Pending 1 Register (IRQP1)
$Base + $12
15
14
13
12
11
10
9
Read
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
PENDING [32:17]
Write
RESET
1
1
1
1
1
1
1
1
1
Figure 5-21 IRQ Pending 1 Register (IRQP1)
5.6.19.1
IRQ Pending (PENDING)—Bits 32–17
Freescale Semiconductor, Inc...
This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.20
Base + $13
IRQ Pending 2 Register (IRQP2)
15
14
13
12
11
10
9
Read
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
PENDING [48:33]
Write
RESET
1
1
1
1
1
1
1
1
1
Figure 5-22 IRQ Pending 2 Register (IRQP2)
5.6.20.1
IRQ Pending (PENDING)—Bits 48–33
This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.21
Base + $14
IRQ Pending 3 Register (IRQP3)
15
14
13
12
11
10
9
Read
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
PENDING [64:49]
Write
RESET
1
1
1
1
1
1
1
1
1
Figure 5-23 IRQ Pending 3 Register (IRQP3)
5.6.21.1
IRQ Pending (PENDING)—Bits 64–49
This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.
•
•
90
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
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Register Descriptions
5.6.22
Base + $15
IRQ Pending 4 Register (IRQP4)
15
14
13
12
11
10
9
Read
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
PENDING [80:65]
Write
RESET
1
1
1
1
1
1
1
1
1
Figure 5-24 IRQ Pending 4 Register (IRQP4)
5.6.22.1
IRQ Pending (PENDING)—Bits 80–65
Freescale Semiconductor, Inc...
This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.23
IRQ Pending 5 Register (IRQP5)
Base + $16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PENDING
[81]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Write
RESET
Figure 5-25 IRQ Pending Register 5 (IRQP5)
5.6.23.1
Reserved—Bits 96–82
This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by
writing.
5.6.23.2
IRQ Pending (PENDING)—Bit 81
This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.24
Reserved—Base + 17
5.6.25
Reserved—Base + 18
5.6.26
Reserved—Base + 19
5.6.27
Reserved—Base + 1A
5.6.28
Reserved—Base + 1B
5.6.29
Reserved—Base + 1C
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5.6.30
ITCN Control Register (ICTL)
Base + $1D
15
Read
INT
14
13
12 11 10
IPIC
9
8
7
6
5
VAB
4
3
2
1
0
1
IRQB STATE
IRQA STATE
IRQB
EDG
IRQA
EDG
1
1
1
0
0
INT_DIS
Write
RESET
0
0
0
1
0
0
0
0
0
0
0
Figure 5-26 ITCN Control Register (ICTL)
5.6.30.1
Interrupt (INT)—Bit 15
Freescale Semiconductor, Inc...
This read-only bit reflects the state of the interrupt to the 56800E core.
•
•
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.6.30.2
Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the
56800E core at the time the last IRQ was taken. This field is only updated when the 56800E core
jumps to a new interrupt service routine.
Nested interrupts may cause this field to be updated before the original interrupt service
routine can read it.
Note:
•
•
•
•
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
5.6.30.3
Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken.
This field is only updated when the 56800E core jumps to a new interrupt service routine.
Nested interrupts may cause this field to be updated before the original interrupt service
routine can read it.
Note:
5.6.30.4
Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
•
•
0 = Normal operation (default)
1 = All interrupts disabled
5.6.30.5
Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.30.6
IRQB State Pin (IRQB STATE)—Bit 3
This read-only bit reflects the state of the external IRQB pin.
5.6.30.7
IRQA State Pin (IRQA STATE)—Bit 2
This read-only bit reflects the state of the external IRQA pin.
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Resets
5.6.30.8
IRQB Edge Pin (IRQB Edg)—Bit 1
This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and
Wait modes, it is automatically level-sensitive.
•
•
0 = IRQB interrupt is a low-level sensitive (default)
1 = IRQB interrupt is falling-edge sensitive.
5.6.30.9
IRQA Edge Pin (IRQA Edg)—Bit 0
Freescale Semiconductor, Inc...
This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and
Wait modes, it is automatically level-sensitive.
•
•
0 = IRQA interrupt is a low-level sensitive (default)
1 = IRQA interrupt is falling-edge sensitive.
5.7 Resets
5.7.1
Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The
reset vector will be presented until the second rising clock edge after RESET is released.
5.7.2
ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled
except the core IRQs with fixed priorities:
•
•
•
•
•
•
•
•
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
SW Interrupt LP
These interrupts are enabled at their fixed priority levels.
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Part 6 System Integration Module (SIM)
6.1 Introduction
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The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It
controls distribution of resets and clocks and provides a number of control features. The system
integration module is responsible for the following functions:
•
•
•
•
•
•
•
Reset sequencing
Clock generation & distribution
Stop/Wait control
Pull-up enables for selected peripherals
System status registers
Registers for software access to the JTAG ID of the chip
Enforcing Flash security
These are discussed in more detail in the sections that follow.
6.2 Features
The SIM has the following features:
•
•
•
Flash security feature prevents unauthorized access to code/data contained in on-chip Flash
memory
Power-saving clock gating for peripheral
Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation
— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be
done explicitly
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full part operation
•
•
•
•
•
•
•
94
Controls to enable/disable the 56800E core WAIT and STOP instructions
Calculates base delay for reset extension based upon POR or RESET operations. Reset delay will
be 3 x 32 clocks (phased release of reset) for reset, except for POR, which is 221 clock cycles.
Controls reset sequencing after reset
Software-initiated reset
Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control
System Control Register
Registers for software access to the JTAG ID of the chip
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Operating Modes
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand
the various chip operating modes and take appropriate action. These are:
•
Reset Mode, which has two submodes:
— POR and RESET operation
The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or
the RESET pin is asserted.
Freescale Semiconductor, Inc...
— COP reset and software reset operation
The 56800E core and all peripherals are reset. The MA bit within the OMR is not changed. This
allows the software to determine the boot mode (internal or external boot) to be used on the next
reset.
•
•
•
•
Run Mode
This is the primary mode of operation for this device. In this mode, the 56800E controls chip
operation.
Debug Mode
The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP
and PWMs, continue to run. COP is disabled and PWM outputs are optionally switched off to
disable any motor from being driven; see the PWM chapter in the 56F8300 Peripheral User
Manual for details.
Wait Mode
In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.
Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All
other peripherals continue to run.
Stop Mode
When in Stop mode, the 56800E core, memory and most peripheral clocks are shut down.
Optionally, the COP and CAN can be stopped. For lowest power consumption in Stop mode, the
PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no
automatic mechanism for this. The CAN (along with any non-gated interrupt) is capable of waking
the chip up from Stop mode, but is not fully functional in Stop mode.
6.4 Operating Mode Register
Bit
15
NL
CM
XP
SD
R
Type
R/W
R/W
R/W
R/W
R/W
RESET
0
0
0
0
0
0
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
SA
EX
0
R/W
R/W
0
1
0
MB
MA
R/W
R/W
0
0
Figure 6-1 OMR
See Section 4.2 Program Map for detailed information on how the Operating Mode Register
(OMR) MA and MB bits operate in this device. For additional information on the EX bit, see
Section 4.4 Data Map. For all other bits, see the DSP56F800E Reference Manual.
Note:
The OMR is not a Memory Map register; it is directly accessible in code through the acronym
OMR.
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6.5 Register Descriptions
Table 6-1 SIM Registers (SIM_BASE = $00 F350)
Freescale Semiconductor, Inc...
Address Offset
Address Acronym
Register Name
Section Location
Base + $0
SIM_CONTROL
Control Register
6.5.1
Base + $1
SIM_RSTSTS
Reset Status Register
6.5.2
Base + $2
SIM_SCR0
Software Control Register 0
6.5.3
Base + $3
SIM_SCR1
Software Control Register 1
6.5.3
Base + $4
SIM_SCR2
Software Control Register 2
6.5.3
Base + $5
SIM_SCR3
Software Control Register 3
6.5.3
Base + $6
SIM_MSH_ID
Most Significant Half of JTAG ID
6.5.4
Base + $7
SIM_LSH_ID
Least Significant Half of JTAG ID
6.5.5
Base + $8
SIM_PUDR
Pull-up Disable Register
6.5.6
Reserved
96
Base + $A
SIM_CLKOSR
CLKO Select Register
6.5.7
Base + $B
SIM_GPS
GPIO Peripheral Select Register
6.5.8
Base + $C
SIM_PCE
Peripheral Clock Enable Register
6.5.9
Base + $D
SIM_ISALH
I/O Short Address Location High Register
6.5.10
Base + $E
SIM_ISALL
I/O Short Address Location Low Register
6.5.10
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Register Descriptions
Add.
Offset
Register
Name
$0
SIM_
CONTROL
W
$1
SIM_
RSTSTS
W
$2
SIM_SCR0
$3
SIM_SCR1
Freescale Semiconductor, Inc...
$4
R
R
SIM_SCR2
$5
SIM_SCR3
$6
SIM_MSH_
ID
$7
SIM_LSH_ID
$8
SIM_PUDR
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
ONCE
EBL0
SW
RST
0
0
0
0
0
0
0
0
0
0
SWR
COPR
EXTR
POR
R
2
1
STOP_
DISABLE
0
WAIT_
DISABLE
0
0
FIELD
W
R
FIELD
W
R
FIELD
W
R
FIELD
W
R
3
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
PWMA1
CAN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C1
C0
EMI
ADCB
ADCA
CAN
1
1
1
1
W
R
W
R
0
W
EMI_
RESET
MODE
IRQ
0
XBOOT PWMB PWMA0
0
CTRL
JTAG
Reserved
$A
SIM_
CLKOSR
$B
SIM_GPS
$C
SIM_PCE
R
A23
A22
A21
A20
CLKDIS
0
0
0
0
0
0
0
DEC1
DEC 0
TMRD
TMRC
TMRB
TMRA
SCI1
1
1
1
1
1
1
1
W
R
CLKOSEL
C3
C2
SCI0
SPI1
SPI0
1
1
1
W
R
W
$D
SIM_ISALH
$E
SIM_ISALL
R
W
R
PWMB PWMA
ISAL[23:22]
ISAL[21:6]
W
= Reserved
Figure 6-2 SIM Register Map Summary
6.5.1
SIM Control Register (SIM_CONTROL)
Base + $0
15
14
13
12
11
10
9
8
7
6
5
4
Read
0
0
0
0
0
0
0
0
0
0
ONCE
EBL
SW
RST
0
0
0
0
0
0
0
0
0
0
0
0
Write
RESET
3
2
1
0
STOP_
DISABLE
WAIT_
DISABLE
0
0
0
0
Figure 6-3 SIM Control Register (SIM_CONTROL)
6.5.1.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.1.2
•
•
OnCE Enable (OnCE EBL)—Bit 5
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
6.5.1.3
Software Reset (SW RST)—Bit 4
This bit is always read as 0. Writing 1 to this field will cause the part to reset.
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6.5.1.4
•
•
•
•
00 = Stop mode will be entered when the 56800E core executes a STOP instruction
01 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future
10 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then
only be changed by resetting the device
11 = Same operation as 10
6.5.1.5
Freescale Semiconductor, Inc...
•
•
•
•
Stop Disable (STOP_DISABLE)—Bits 3–2
Wait Disable (WAIT_DISABLE)—Bits 1–0
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
01 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be
reprogrammed in the future
10 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then
only be changed by resetting the device
11 = Same operation as 10
6.5.2
SIM Reset Status Register (SIM_RSTSTS)
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset
(POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Only software
should clear this register.
Base + $1
15
14
13
12
11
10
9
8
7
6
Read
0
0
0
0
0
0
0
0
0
0
5
4
3
2
SWR
COPR
EXTR
POR
1
0
0
0
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
6.5.2.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.2.2
Software Reset (SWR)—Bit 5
When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to
SW RST bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by
software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.
6.5.2.3
COP Reset (COPR)—Bit 4
When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has
occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit
position will set the bit, while writing a 1 to the bit will clear it.
6.5.2.4
External Reset (EXTR)—Bit 3
If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a
Power-On Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to
the bit position will clear it. Basically, when the EXTR bit is 1, the previous system reset was
caused by the external RESET pin being asserted low.
98
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Register Descriptions
6.5.2.5
Power-On Reset (POR)—Bit 2
When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be
cleared only by software or by another type of reset. Writing a 0 to this bit will set the bit, while
writing a 1 to the bit position will clear the bit. In summary, if the bit is 1, the previous system reset
was due to a Power-On Reset.
6.5.2.6
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Freescale Semiconductor, Inc...
6.5.3
SIM Software Control Registers (SIM_SCR0, SIM_SCR1,
SIM_SCR2, and SIM_SCR3)
Only SIM_SCR0 is shown in this section. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical
in functionality.
Base + $2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read
FIELD
Write
POR
0
0
0
0
0
0
0
0
Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)
6.5.3.1
Software Control Data 1 (FIELD)—Bits 15–0
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and
is intended for use by a software developer to contain data that will be unaffected by the other reset
sources (RESET pin, software reset, and COP reset).
6.5.4
Most Significant Half of JTAG ID (SIM_MSH_ID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register
reads $01F4.
Base + $6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
Write
RESET
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
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6.5.5
Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register
reads $401D.
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
Write
RESET
Freescale Semiconductor, Inc...
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can
have these resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups
disabled by setting the appropriate bit in this register. Disabling pull-ups is done on a
peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see
Figure 6-8) corresponds to a functional group of pins. See Table 2-2 to identify which pins can
deactivate the internal pull-up resistor.
Base + $8
15
Read
0
14
13
0
11
10
9
8
7
6
5
0
PWMA1
CAN
EMI_
MODE
RESET
IRQ
XBOOT
0
0
0
0
0
0
Write
RESET
12
PWMB PWMA0
0
0
4
CTRL
0
3
0
0
2
1
0
0
0
0
0
0
0
JTAG
0
0
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1
Reserved—Bit 15
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
PWMA1—Bit 14
This bit controls the pull-up resistors on the FAULTA3 pin.
6.5.6.3
CAN—Bit 13
This bit controls the pull-up resistors on the CAN_RX pin.
6.5.6.4
EMI_MODE—Bit 12
This bit controls the pull-up resistors on the EMI_MODE pin.
Note:
6.5.6.5
In this package, this input pin is double-bonded with the adjacent VSS pin and this bit should
be changed to a 1 in order to reduce power consumption.
RESET—Bit 11
This bit controls the pull-up resistors on the RESET pin.
100
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Register Descriptions
6.5.6.6
IRQ—Bit 10
This bit controls the pull-up resistors on the IRQA and IRQB pins.
6.5.6.7
XBOOT—Bit 9
This bit controls the pull-up resistors on the EXTBOOT pin.
Note:
6.5.6.8
In this package, this input pin is double-bonded with the adjacent VSS pin and this bit should
be changed to a 1 in order to reduce power consumption.
PWMB—Bit 8
Freescale Semiconductor, Inc...
This bit controls the pull-up resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3
pins.
6.5.6.9
PWMA0—Bit 7
This bit controls the pull-up resistors on the FAULTA0, FAULTA1, and FAULTA2 pins.
6.5.6.10
Reserved—Bit 6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.11
CTRL—Bit 5
This bit controls the pull-up resistors on the WR and RD pins.
6.5.6.12
Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.13
JTAG—Bit 3
This bit controls the pull-up resistors on the TRST, TMS and TDI pins.
6.5.6.14
Reserved—Bit 2–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7
CLKO Select Register (SIM_CLKOSR)
The CLKO select register can be used to multiplex out any one of the clocks generated inside the
clock generation and SIM modules. The default value is SYS_CLK. This path has been optimized
in order to minimize any delay and clock duty cycle distortion. All other clocks primarily muxed
out are for test purposes only, and are subject to significant phase shift at high frequencies.
The upper four bits of the GPIO B register can function as GPIO A23 through A20, or as additional
clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIO
B[7:4] are programmed to operate as peripheral outputs, then the choice between A23 through A20
and additional clock outputs is done here in the CLKOSR. The default state is for the peripheral
function of GPIO B[7:4] to be programmed as A23 through A20. This can be changed by altering
A23 through A20, as shown in Figure 6-9.
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Base + $A
15
14
13
12
11
10
Read
0
0
0
0
0
0
9
8
7
6
5
A23
A22
A21
A20
CLK
DIS
0
0
0
0
1
Write
RESET
0
0
0
0
0
0
4
3
2
1
0
0
0
CLKOSEL
0
0
0
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
6.5.7.1
Reserved—Bits 15–10
Freescale Semiconductor, Inc...
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7.2
•
•
0 = Peripheral output function of GPIO B[7] is defined to be A[23]
1 = Peripheral output function of GPIO B[7] is defined to be the oscillator clock (MSTR_OSC, see
Figure 3-4)
6.5.7.3
•
•
Alternate GPIO_B Peripheral Function for A20 (A20)—Bit 6
0 = Peripheral output function of GPIO B[4] is defined to be A[20]
1 = Peripheral output function of GPIO B[4] is defined to be the prescaler clock (FREF, see
Figure 3-4)
6.5.7.6
•
•
Alternate GPIO_B Peripheral Function for A21 (A21)—Bit 7
0 = Peripheral output function of GPIO B[5] is defined to be A[21]
1 = Peripheral output function of GPIO B[5] is defined to be SYS_CLK
6.5.7.5
•
•
Alternate GPIO_B Peripheral Function for A22 (A22)—Bit 8
0 = Peripheral output function of GPIO B[6] is defined to be A[22]
1 = Peripheral output function of GPIO B[6] is defined to be SYS_CLK2
6.5.7.4
•
•
Alternate GPIO_B Peripheral Function for A23 (A23)—Bit 9
Clockout Disable (CLKDIS)—Bit 5
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT is tri-stated
6.5.7.7
CLockout Select (CLKOSEL)—Bits 4–0
Selects clock to be muxed out on the CLKO pin.
102
•
•
•
•
•
•
•
•
•
00000 = SYS_CLK (from OCCS - DEFAULT)
00001 = Reserved for factory test—56800E clock
00010 = Reserved for factory test—XRAM clock
00011 = Reserved for factory test—PFLASH odd clock
00100 = Reserved for factory test—PFLASH even clock
00101 = Reserved for factory test—BFLASH clock
00110 = Reserved for factory test—DFLASH clock
00111 = Oscillator output
01000 = Fout (from OCCS)
•
01001 = Reserved for factory test—IPB clock
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Register Descriptions
•
•
•
•
•
•
•
•
Freescale Semiconductor, Inc...
6.5.8
01010 = Reserved for factory test—Feedback (from OCCS, this is path to PLL)
01011 = Reserved for factory test—Prescaler clock (from OCCS)
01100 = Reserved for factory test—Postscaler clock (from OCCS)
01101 = Reserved for factory test—SYS_CLK2 (from OCCS)
01110 = Reserved for factory test—SYS_CLK_DIV2
01111 = Reserved for factory test—SYS_CLK_D
10000 = ADCA clock
10001 = ADCB clock
GPIO Peripheral Select Register (SIM_GPS)
The GPIO Peripheral Select Register can be used to multiplex out any one of the three alternate
peripherals for GPIO_C. The default peripheral is Quad Decoder 1 and Quad Timer B; these
peripherals work together.
The four I/O pins associated with GPIO C can function as GPIO, Quad Decoder 1/Quad Timer B,
or as SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown
in Figure 6-10 and Table 6-2. When GPIO C[3:0] are programmed to operate as peripheral I/O,
then the choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS and in
conjunction with the Quad Timer Status and Control Registers (SCR). The default state is for the
peripheral function of GPIO C[3:0] to be programmed as decoder functions. This can be changed
by altering the appropriate controls in the indicated registers.
GPIOC_PER Register
GPIO Controlled
0
I/O Pad Control
1
SIM_ GPS Register
Quad Timer Controlled
SPI Controlled
0
1
Figure 6-10 Overall Control of Pads Using SIM_GPS Control
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Table 6-2 Control of Pads Using SIM_GPS Control 1
GPIOC_PER
GPIOC_DTR
SIM_GPS
Quad Timer
SCR Register
OEN bits
Control Registers
GPIO Input
0
0
—
—
GPIO Output
0
1
—
—
Quad Timer Input /
Quad Decoder
Input 2
1
—
0
0
Quad Timer
Output / Quad
Decoder Input 3
1
—
0
1
SPI input
1
—
1
—
SPI output
1
—
1
—
Freescale Semiconductor, Inc...
Pin Function
Comments
See the “Switch Matrix for Inputs to the Timer”
table in the 56F8300 Peripheral User Manual
for the definition of timer inputs based on the
Quad Decoder mode configuration.
See SPI controls for determining the direction
of each of the SPI pins.
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control
bits is used for each pin.
2. Reset configuration
3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
Base + $B
15
14
13
12
11
10
9
8
7
6
5
4
Read
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
C3
C2
C1
C0
0
0
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
6.5.8.1
Reserved—Bits 15–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.8.2
GPIO C3 (C3)—Bit 3
This bit selects the alternate function for GPIO C3.
•
•
0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register
in the 56F8300 Peripheral User’s Manual)
1 = SS1
6.5.8.3
GPIO C2 (C2)—Bit 2
This bit selects the alternate function for GPIO C2.
•
•
104
0 = INDEX1/TB2 (default)
1 = MISO1
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Register Descriptions
6.5.8.4
GPIO C1 (C1)—Bit 1
This bit selects the alternate function for GPIO C1.
•
•
0 = PHASEB1/TB1 (default)
1 = MOSI1
6.5.8.5
GPIO C0 (C0)—Bit 0
This bit selects the alternate function for GPIO C0.
•
•
0 = PHASEA1/TB0 (default)
1 = SCLK1
Freescale Semiconductor, Inc...
6.5.9
Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a
power savings feature. The clocks can be individually controlled for each peripheral on the chip.
Base + $C
15
14
13
12
11
10
9
8
TMRD
TMRC
1
1
7
6
5
4
3
2
SCI1
SCI0
SPI1
SPI0
1
1
1
1
1
0
Read
EMI
ADCB ADCA CAN
DEC1 DEC0
TMRB TMRA
PWMB PWMA
Write
RESET
1
1
1
1
1
1
1
1
1
1
Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)
6.5.9.1
External Memory Interface Enable (EMI)—Bit 15
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.2
Analog-to-Digital Converter B Enable (ADCB)—Bit 14
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.3
Analog-to-Digital Converter A Enable (ADCA)—Bit 13
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.4
FlexCAN Enable (CAN)—Bit 12
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
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6.5.9.5
Decoder 1 Enable (DEC1)—Bit 11
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.6
Decoder 0 Enable (DEC0)—Bit 10
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
Freescale Semiconductor, Inc...
6.5.9.7
Quad Timer D Enable (TMRD)—Bit 9
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.8
Quad Timer C Enable (TMRC)—Bit 8
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.9
Quad Timer B Enable (TMRB)—Bit 7
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.10
Quad Timer A Enable (TMRA)—Bit 6
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.11
Serial Communications Interface 1 Enable (SCI1)—Bit 5
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.12
Serial Communications Interface 0 Enable (SCI0)—Bit 4
Each bit controls clocks to the indicated peripheral.
•
•
106
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
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Register Descriptions
6.5.9.13
Serial Peripheral Interface 1 Enable (SPI1)—Bit 3
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.14
Serial Peripheral Interface 0 Enable (SPI0)—Bit 2
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
Freescale Semiconductor, Inc...
6.5.9.15
Pulse Width Modulator B Enable (PWMB)—Bit 1
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.16
Pulse Width Modulator A Enable (PWMA)—Bit 0
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.10
I/O Short Address Location Register (SIM_ISALH and
SIM_ISALL)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O
short address mode. The I/O short address mode allows the instruction to specify the lower six bits
of address; the upper address bits are not directly controllable. This register set allows limited
control of the full address, as shown in Figure 6-13.
Note:
If this register is set to something other than the top of memory (EOnCE register space) and
the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers,
and debug functions will be affected.
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Instruction Portion
“Hard Coded” Address Portion
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_ISALL Register
Freescale Semiconductor, Inc...
2 Bits from SIM_ISALH Register
Full 24-Bit for Short I/O Address
Figure 6-13 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its
peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should
restore this register to its previous contents prior to returning from interrupt.
Note:
The default value of this register set points to the EOnCE registers.
Note:
The pipeline delay between setting this register set and using short I/O addressing with the
new value is three cycles.
Base + $D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Read
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
ISAL[23:22]
Write
1
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)
6.5.10.1
Input/Output Short Address Low (ISAL[23:22])—Bit 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
Base + $E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
Read
ISAL[21:6]
Write
RESET
1
1
1
1
1
1
1
1
1
Figure 6-15 I/O Short Address Location Low Register (SIM_ISAL)
6.5.10.2
Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
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Clock Generation Overview
6.6 Clock Generation Overview
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The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the
peripheral and system (core and memory) clocks. The maximum master clock frequency is
120MHz. Peripheral and system clocks are generated at half the master clock frequency and
therefore at a maximum 60MHz. The SIM provides power modes (Stop, Wait) and clock enables
(SIM_PCE register, CLK_DIS, ONCE_EBL) to control which clocks are in operation. The OCCS,
power modes, and clock enables provide a flexible means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may
be shut down when not in use. When the PLL is in use, its prescaler and postscaler can be used to
limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks to be
disabled when unused. Clock enables provide the means to disable individual clocks. Some
peripherals provide further controls to disable unused subfunctions. Refer to Part 3 On-Chip
Clock Synthesis (OCCS) and the 56F8300 Peripheral User Manual for further details.
6.7 Power-Down Modes Overview
The 56F8345 operates in one of three power-down modes, as shown in Table 6-3.
Table 6-3 Clock Operation in Power-Down Modes
Mode
Core Clocks
Peripheral Clocks
Description
Run
Active
Active
Device is fully functional
Wait
Core and memory
clocks disabled
Active
Peripherals are active and can produce interrupts if
they have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
Stop
System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.
The only possible recoveries from Stop mode are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
4. External reset
5. Power-on reset
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the
same as the main processor frequency in this architecture. The maximum frequency of operation
is SYS_CLK = 60MHz.
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6.8 Stop and Wait Mode Disable Function
Permanent
Disable
D
Q
D-FLOP
C
56800E
Reprogrammable Disable
STOP_DIS
Freescale Semiconductor, Inc...
D
Q
D-FLOP
Clock
Select
C
RESET
R
Note: Wait disable circuit is similar
Figure 6-16 Internal Stop Disable Circuit
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For
lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly
before entering Stop mode, since there is no automatic mechanism for this. When the PLL is shut
down, the 56800E system clock must be set equal to the oscillator output.
Some applications require the 56800E STOP and WAIT instructions to be disabled. To disable
those instructions, write to the SIM control register (SIM_CONTROL), described in Section 6.5.1
SIM Control Register (SIM_CONTROL). This procedure can be on either a permanent or
temporary basis. Permanently assigned applications last only until their next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin
and the Power-On Reset (POR). The two synchronous sources are the software reset, which is
generated within the SIM itself by writing to the SIM_CONTROL register, and the COP reset.
Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is
sequenced to permit proper operation of the device. A POR reset is first extended for 221 clock
cycles to permit stabilization of the clock source, followed by a 32 clock window in which SIM
clocking is initiated. It is then followed by a 32 clock window in which peripherals are released to
implement Flash security, and, finally, followed by a 32 clock window in which the core is
initialized. After completion of the described reset sequence, application code will begin
execution.
Resets may be asserted asynchronously, but are always released internally on a rising edge of the
system clock.
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Operation with Security Enabled
Part 7 Security Features
The 56F8345 offers security features intended to prevent unauthorized users from reading the
contents of the Flash Memory (FM) array. The 56F8345’s Flash security consists of several
hardware interlocks that block the means by which an unauthorized user could gain access to the
Flash array.
Freescale Semiconductor, Inc...
However, part of the security must lie with the user’s code. An extreme example would be user’s
code that dumps the contents of the internal program, as this code would defeat the purpose of
security. At the same time, the user may also wish to put a “backdoor” in his program. As an
example, the user downloads a security key through the SCI, allowing access to a programming
routine that updates parameters stored in another section of the Flash.
7.1 Operation with Security Enabled
Once the user has programmed the Flash with his application code, the 56F8345 can be secured by
programming the security bytes located in the FM configuration field, which occupies a portion of
the FM array. These non-volatile bytes will keep the part secured through reset and through
power-down of the device. Only two bytes within this field are used to enable or disable security.
Refer to the Flash Memory section in the 56F8300 Peripheral User Manual for the state of the
security bytes and the resulting state of security. When Flash security mode is enabled in
accordance with the method described in the Flash Memory module specification, the 56F8345
will disable the core EOnCE debug capabilities. Normal program execution is otherwise
unaffected.
7.2 Flash Access Blocking Mechanisms
The 56F8345 has several operating functional and test modes. Effective Flash security must
address operating mode selection and anticipate modes in which the on-chip Flash can be
compromised and read without explicit user permission. Methods to block these are outlined in the
next subsections.
7.2.1
Forced Operating Mode Selection
At boot time, the SIM determines in which functional modes the 56F8345 will operate. These are:
•
•
Unsecured Mode
Secure Mode (EOnCE disabled)
When Flash security is enabled as described in the Flash Memory module specification, the
56F8345 will disable the EOnCE debug interface.
7.2.2
Disabling EOnCE Access
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug
interface for the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG
interface onto which the EOnCE port functionality is mapped. When the 56F8345 boots, the
chip-level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability
and access to the ID register.
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Proper implementation of Flash security requires that no access to the EOnCE port is provided
when security is enabled. The 56800E core has an input which disables reading of internal memory
via the JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the
FM security bytes.
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7.2.3
Flash LOCKOUT_RECOVERY
If a user inadvertently enables security on the 56F8345, a lockout recovery mechanism is provided
which allows the complete erasure of the internal Flash contents, including the configuration field,
and thus disables security (the protection register is cleared). This does not compromise security,
as the entire contents of the user’s secured code stored in Flash are erased before security is
disabled on the 56F8345 on the next reset or power-up sequence. To start the lockout recovery
sequence, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the
chip-level TAP controller’s instruction register.
The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used
to control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used
to control the period of the clock used for timed events in the FM erase algorithm. This register
must be set with appropriate values before the lockout sequence can begin. Refer to the JTAG
section of the 56F8300 Peripheral User Manual for more details on setting this register value.
The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that
divides down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will
map to the PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of
PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz-200kHz. The
“Writing the FMCLKD Register” section in the Flash Memory chapter of the 56F8300
Peripheral User Manual gives specific equations for calculating the correct values.
Flash Memory
SYS_CLK
input
2
clock
DIVIDER
7
FMCLKD
7
FM_CLKDIV
JTAG
7
FM_ERASE
Figure 7-1 JTAG to FM Connection for LOCKOUT_RECOVERY
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Flash Access Blocking Mechanisms
Two examples of FM_CLKDIV calculations follow.
EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been
set up, the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[6] = 0. Using the
following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a
clock of 190kHz. This translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively.
Freescale Semiconductor, Inc...
150[kHz]
(
<
SYS_CLK
(2)
(DIV + 1)
)<
200[kHz]
EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making
the FM input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8 = FM_CLKDIV[6] =
1. Using the following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of
10 for a clock of 181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A,
respectively.
150[kHz]
<
(
SYS_CLK
(2)
(DIV + 1)
)
<
200[kHz]
Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the
clock divider value must be shifted into the corresponding 7-bit data register. After the data register
has been updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for
the lockout sequence to commence. The controller must remain in this state until the erase
sequence has completed. For details, see the JTAG Section in the 56F8300 Peripheral User
Manual.
Note:
When the lockout recovery sequence has completed, the user must reset both the JTAG TAP
controller (by asserting TRST) and the 56F8345 (by asserting external chip reset) to return to
normal unsecured operation.
7.2.4
Product Analysis
The recommended method of unsecuring a programmed 56F8345 for product analysis of field
failures is via the backdoor key access. The customer would need to supply Motorola with the
backdoor key and the protocol to access the backdoor routine in the Flash. Additionally, the
KEYEN bit that allows backdoor key access must be set.
An alternative method for performing analysis on a secured hybrid controller would be to
mass-erase and reprogram the Flash with the original code, but to modify the security bytes.
To insure that a customer does not inadvertently lock himself out of the 56F8345 during
programming, it is recommended that he program the backdoor access key first, his application
code second, and the security bytes within the FM configuration field last.
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Part 8 General Purpose Input/Output (GPIO)
8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F8300 Peripheral
User Manual and contains only chip-specific information. This information supercedes the
generic information in the 56F8300 Peripheral User Manual.
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8.2 Configuration
There are six GPIO ports defined on the 56F8345. The width of each port and the associated
peripheral function is shown in Table 8-1. The specific mapping of GPIO port pins is shown in
Table 8-2.
Table 8-1 GPIO Ports Configuration
GPIO Port
Port
Width
Available
Pins in
56F8345
A
14
6
B
5
Reset Function
6 pins - EMI Address pins - Can only be used as
GPIO
8 pins - EMI Address pins - Not available in this
package
EMI Address
5 pins - EMI Address pins - Can only be used as
GPIO
3 pins - EMI Address pins - Not available in this
package
GPIO
N/A
N/A
C
11
11
4 pins -DEC1 / TMRB / SPI1
4 pins -DEC0 / TMRA
3 pins -PWMA current sense
DEC1 / TMRB
DEC0 / TMRA
PWMA current
sense
D
13
11
2 pins - EMI CSn
4 pins - EMI CSn - Can only be used as GPIO
2 pins - SCI1
2 pins - EMI CSn - Not available in this package
3 pins -PWMB current sense
EMI Chip Selects
EMI Chip Selects
SCI1
N/A
PWMB current
sense
E
14
12
2 pins - SCI0
2 pins - EMI Address pins - Not available in this
package
4 pins - SPI0
2 pins - TMRC
4 pins - TMRD
SCI0
N/A
4 pins - EMI Data - Can only be used as GPIO
12 pins - EMI Data - Not available in this package
EMI Data
N/A
F
114
8
Peripheral Function
16
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SPI0
TMRC
TMRD
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Configuration
Table 8-2 GPIO External Signals Map
Pins in shaded rows are not available in 56F8345
Freescale Semiconductor, Inc...
GPIO Port
GPIOA
GPIOB
56F8345 Technical Data
Preliminary
GPIO Bit
Reset Function
Functional Signal
Package Pin #
0
Peripheral
A81
15
1
Peripheral
A91
16
2
Peripheral
A101
17
3
Peripheral
A111
18
4
Peripheral
A121
19
5
Peripheral
A131
20
6
N/A
7
N/A
8
N/A
9
N/A
10
N/A
11
N/A
12
N/A
13
N/A
0
GPIO
A161
27
1
GPIO
A171
28
2
GPIO
A181
29
3
GPIO
A191
30
4
GPIO
A20 / Prescaler_clock
31
5
N/A
6
N/A
7
N/A
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Table 8-2 GPIO External Signals Map (Continued)
Pins in shaded rows are not available in 56F8345
GPIO Port
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GPIOC
GPIOD
116
GPIO Bit
Reset Function
Functional Signal
Package Pin #
0
Peripheral
PhaseA1 / TB0 / SCLK12
9
1
Peripheral
PhaseB1 / TB1 / MOSI12
10
2
Peripheral
Index1 / TB2 / MISO12
11
3
Peripheral
Home1 / TB3 / SS12
12
4
Peripheral
PhaseA0 / TA0
127
5
Peripheral
PhaseB0 / TA1
128
6
Peripheral
Index0 / TA2
1
7
Peripheral
Home0 / TA3
2
8
Peripheral
ISA0
104
9
Peripheral
ISA1
105
10
Peripheral
ISA2
106
0
GPIO
CS21
42
1
GPIO
CS31
43
2
GPIO
CS41
44
3
GPIO
CS51
45
4
GPIO
CS61
46
5
GPIO
CS71
47
6
Peripheral
TXD1
40
7
Peripheral
RXD1
41
8
N/A
9
N/A
10
Peripheral
ISB0
48
11
Peripheral
ISB1
50
12
Peripheral
ISB2
51
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Configuration
Table 8-2 GPIO External Signals Map (Continued)
Pins in shaded rows are not available in 56F8345
Freescale Semiconductor, Inc...
GPIO Port
GPIO Bit
Reset Function
Functional Signal
Package Pin #
0
Peripheral
TXD0
7
1
Peripheral
RXD0
8
2
N/A
3
N/A
4
Peripheral
SCLK0
124
5
Peripheral
MOSI0
126
6
Peripheral
MISO0
125
7
Peripheral
SS0
123
8
Peripheral
TC0
111
9
Peripheral
TC1
113
10
Peripheral
TD0
107
11
Peripheral
TD1
108
12
Peripheral
TD2
109
13
Peripheral
TD3
110
0
Peripheral
D71
22
1
Peripheral
D81
23
2
Peripheral
D91
24
3
Peripheral
D101
26
4
N/A
5
N/A
6
N/A
7
N/A
8
N/A
9
N/A
10
N/A
11
N/A
12
N/A
13
N/A
14
N/A
15
N/A
GPIOE
GPIOF
1. Not useful in reset configuration in this package - reconfigure as GPIO
2. See Section 6.5.8 GPIO Peripheral Select Register (SIM_GPS) to determine how to select peripherals from this set;
DEC1 is the selected peripheral at reset
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8.3 Memory Maps
The width of the GPIO port defines how many bits are implemented in each of the GPIO registers.
Based on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR
and GPIOx_PER registers change from port to port. Tables 4-29 through 4-34 define the actual
reset values of these registers for the 56F8345.
Part 9 Joint Test Action Group (JTAG)
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9.1 56F8345 Information
Please contact your Motorola marketing representative for device/package-specific BSDL
information.
Part 10 Specifications
10.1 General Characteristics
The 56F8345 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs.
The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a
mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both
3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a
maximum voltage of 3.3V ± 10% during normal operation without causing damage). This
5V-tolerant capability therefore offers the power savings of 3.3V I/O levels combined with the
ability to receive 5V levels without damage.
Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause
permanent damage to the device.
Note:
All specifications meet both Automotive and Industrial requirements unless individual
specifications are listed.
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
118
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General Characteristics
Table 10-1 Absolute Maximum Ratings
(VSS = VSSA_ADC = 0)
Characteristic
Symbol
Supply voltage
VDD_IO
ADC Supply Voltage
VDDA_ADC,
VREFH
Oscillator / PLL Supply Voltage
VREFH must be
Min
Max
Unit
- 0.3
4.0
V
- 0.3
4.0
V
- 0.3
4.0
V
less than or equal
to VDDA_ADC
VDDA_OSC_PLL
Internal Logic Core Supply Voltage
Freescale Semiconductor, Inc...
Notes
VDDA_CORE
OCR_DIS is High
- 0.3
3.0
V
Input Voltage (digital)
VIN
Pin Groups
1, 2, 5, 6, 9, 10
-0.3
6.0
V
Input Voltage (analog)
VINA
Pin Groups
11, 12, 13
-0.3
4.0
V
Output Voltage
VOUT
Pin Groups
1, 2, 3, 4, 5, 6, 7, 8
-0.3
4.0
V
Output Voltage (open drain)
VOD
Pin Group 4
-0.3
6.0
V
Ambient Temperature (Automotive)
TA
-40
125
°C
Ambient Temperature (Industrial)
TA
-40
105
°C
Junction Temperature (Automotive)
TJ
-40
150
°C
Junction Temperature (Industrial)
TJ
-40
125
°C
Storage Temperature (Automotive)
TSTG
-55
150
°C
Storage Temperature (Industrial)
TSTG
-55
150
°C
Note: The overall life of this device may be reduced if subjected to extended use over 110°C
junction. For additional information, please contact your sales representative.
Pin Group 1: TXD0-1, RXD0-1, SS0, MISO0, MOSI0
Pin Group 2: PHASEA0-1, PHASEB0-1,
INDEX0-1, HOME0-1, ISB0-2, RSTO,
ISA0-2, TD2-3, TC0-1, TDO, SCLK0
Pin Group 3: RSTO, TDO
Pin Group 4: CAN_TX
Pin Group 5: D0-15, GPIOD0-5
Pin Group 6: A8-15, GPIOB0-4, TD0-1
Pin Group 7: CLKO
56F8345 Technical Data
Preliminary
Pin Group 8: PWMA0-5, PWMB0-5
Pin Group 9: IRQA, IRQB, RESET, EXTBOOT, TRST,
TMS, TDI, CAN_RX, EMI_MODE,
FAULTA0-3, FAULTB0-3
Pin Group 10: TCK
Pin Group 11: XTAL, EXTAL
Pin Group 12: ANA0-7, ANB0-7
Pin Group 13: OCR_DIS, CLKMODE
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Table 10-2 Electrostatic Discharge Protection
Characteristic
Min
Typ
Max
Unit
ESD for Human Body Model (HBM)
2000
—
—
V
ESD for Machine Model (MM)
200
—
—
V
ESD for Charge Device Model (CDM)
500
—
—
V
Freescale Semiconductor, Inc...
Table 10-3 Thermal Characteristics6
Value
Characteristic
Comments
Symbol
Unit
Notes
128-pin LQFP
Junction to ambient
Natural convection
Junction to ambient (@1m/sec)
RθJA
50.8
°C/W
2
RθJMA
46.5
°C/W
2
Junction to ambient
Natural convection
Four layer board
(2s2p)
RθJMA
(2s2p)
43.9
°C/W
1,2
Junction to ambient (@1m/sec)
Four layer board
(2s2p)
RθJMA
41.7
°C/W
1,2
Junction to case
RθJC
13.9
°C/W
3
Junction to center of case
ΨJT
1.2
°C/W
4, 5
I/O pin power dissipation
P I/O
User-determined
W
Power dissipation
PD
P D = (IDD x VDD + P I/O)
W
PDMAX
(TJ - TA) / θJA
°C
Maximum allowed PD
Notes:
1.
2.
3.
4.
5.
6.
120
Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equivalent to the JEDEC
specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a
thermal test board with two internal planes (2s2p, where “s” is the number of signal layers and “p” is the number
of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the
non-single layer boards is Theta-JMA.
Junction to case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the measured values
using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold
plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal performance when the package is being used with a heat sink.
Thermal Characterization Parameter, Psi-JT (ΨJT ), is the "resistance" from junction to reference point
thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction
temperature in steady-state customer environments.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.
See Section 12.1 Thermal Design Considerations for more details on thermal design considerations.
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General Characteristics
Table 10-4 Recommended Operating Conditions
(VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL )
Characteristic
Symbol
Supply voltage
Notes
VDD_IO
ADC Supply Voltage
VDDA_ADC,
VREFH
Oscillator / PLL Supply Voltage
VDDA_OSC
VREFH must be
less than or equal
to VDDA_ADC
Min
Typ
Max
Unit
3
3.3
3.6
V
3
3.3
3.6
V
3
3.3
3.6
V
2.25
2.5
2.75
V
0
—
60
MHz
Freescale Semiconductor, Inc...
_PLL
Internal Logic Core Supply
Voltage
VDD_CORE
Device Clock Frequency
FSYSCLK
OCR_DIS is High
Input High Voltage (digital)
VIN
Pin Groups
1, 2, 5, 6, 9, 10
2
—
5.5
V
Input High Voltage (analog)
VIHA
Pin Group 13
2
—
VDDA+0.3
V
Input High Voltage (XTAL/EXTAL,
VIHC
Pin Group 11
VDDA-0.8
—
VDDA+0.3
V
VIHC
Pin Group 11
2
—
VDDA+0.3
V
Input Low Voltage
VIL
Pin Groups
1, 2, 5, 6, 9, 10,
11, 13
-0.3
—
.8
V
Output High Source Current
VOH = 2.4V (VOH min.)
IOH
Pin Groups 1, 2, 3
—
—
-4
mA
Pin Groups 5, 6, 7
—
—
-8
Pin Groups 8
—
—
-12
Pin Groups
1, 2, 3, 4
—
—
4
Pin Groups 5, 6, 7
—
—
8
Pin Group 8
—
—
12
XTAL is not driven by an external
clock)
Input high voltage (XTAL/EXTAL,
XTAL is driven by an external clock)
Output Low Sink Current
VOL = 0.4V (VOL max)
IOL
mA
Ambient Operating Temperature
(Automotive)
TA
-40
—
125 (RθJA X PD)
°C
Ambient Operating Temperature
(Industrial)
TA
-40
—
105 (RθJA X PD)
°C
Flash Endurance (Automotive)
(Program Erase Cycles)
NF
TA = -40°C to
125°C
10,000
—
—
Cycles
Flash Endurance (Industrial)
(Program Erase Cycles)
NF
TA = -40°C to
105°C
10,000
—
—
Cycles
Flash Data Retention
(Automotive)
TR
TJ <= 70°C avg
15
—
—
Years
Note: Total chip source or sink current cannot exceed 200mA
See Pin Groups listed in Table 10-1
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10.2 DC Electrical Characteristics
Table 10-5 DC Electrical Characteristics
Over Recommended Operating Conditions, VDDA = VDDA_ADC, VDDA_OSC_PLL
Characteristic
Symbol
Min
Typ
Max
Unit
Test Conditions
Output High Voltage
VOH
2.4
—
—
V
IOH = IOHmax
Output Low Voltage
VOL
—
—
0.4
V
IOL = IOLmax
IIH
Pin Groups
1, 2, 5, 6, 9
—
0
+/- 2.5
µA
VIN = 3.0V to 5.5V
IIH
Pin Group 10
40
80
160
µA
VIN = 3.0V to 5.5V
IIHA
Pin Group 13
—
0
+/- 2.5
µA
VIN = VDDA
ADC Input Current High
IIHADC
Pin Group 12
—
0
+/- 3.5
µA
VIN = VDDA
Digital Input Current Low
IIL
Pin Groups
1, 2, 5, 6, 9
-200
-100
-50
µA
VIN = 0V
IIL
Pin Groups
1, 2, 5, 6, 9
—
0
+/- 2.5
µA
VIN = 0V
IIL
Pin Group 10
—
0
+/- 2.5
µA
VIN = 0V
IILA
Pin Group 13
—
0
+/- 2.5
µA
VIN = 0V
ADC Input Current Low
IILADC
Pin Group 12
—
0
+/- 3.5
µA
VIN = 0V
EXTAL Input Current Low
IEXTAL
—
0
+/- 2.5
µA
VIN = VDD or 0V
CLKMODE =
High
—
0
+/- 2.5
µA
VIN = VDDA or 0V
CLKMODE =
Low
—
—
200
µA
VIN = VDDA or 0V
IOZ
Pin Groups
1, 2, 3, 4, 5,
6, 7, 8
—
0
+/- 2.5
µA
VOUT = 3.0V to
5.5V or 0V
Schmitt Trigger Input
Hysteresis
VHYS
Pin Groups
2, 6, 9,10
—
0.3
—
V
—
Input Capacitance
(EXTAL/XTAL)
CINC
—
4.5
—
pF
—
COUTC
—
5.5
—
pF
—
CIN
—
6
—
pF
—
COUT
—
6
—
pF
—
Digital Input Current High
pull-up enabled or disabled
Freescale Semiconductor, Inc...
Notes
Digital Input Current High
with pull-down
Analog Input Current High
pull-up enabled
Digital Input Current Low
pull-up disabled
Digital Input Current Low
with pull-down
Analog Input Current Low
clock input
XTAL Input Current Low
IXTAL
clock input
Output Current
High Impedance State
Output Capacitance
(EXTAL/XTAL)
Input Capacitance
Output Capacitance
Note: See Pin Groups listed in Table 10-1
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DC Electrical Characteristics
Table 10-6 Power-On Reset Low Voltage Parameters
Characteristic
Symbol
Min
Typ
Max
Units
POR Trip Point
POR
1.75
1.8
1.9
V
LVI, 2.5 volt Supply, trip point1
VEI2.5
—
2.14
—
V
LVI, 3.3 volt supply, trip point2
VEI3.3
—
2.7
—
V
Bias Current
I bias
—
110
130
µA
1. When VDD drops below VEI2.5, an interrupt is generated.
Freescale Semiconductor, Inc...
2. When VDD drops below VEI3.3, an interrupt is generated.
Table 10-7 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Enabled (OCR_DIS = Low)
Mode
RUN1_MAC
IDD_IO1
IDD_ADC
IDD_OSC_PLL
155mA
50mA
2.5mA
Test Conditions
• 60MHz Device Clock
• All peripheral clocks are enabled
• All peripherals running
• Continuous MAC instructions with fetches from
Data RAM
• ADC powered on and clocked
Wait3
91mA
65µA
2.5mA
• 60MHz Device Clock
• All peripheral clocks are enabled
• ADC powered off
Stop1
5.8mA
0µA
155µA
• 8MHz Device Clock
• All peripheral clocks are off
• ADC powered off
• PLL powered off
Stop2
5.1mA
0µA
145µA
• External Clock is off
• All peripheral clocks are off
• ADC powered off
• PLL powered off
1. No Output Switching
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Table 10-8 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Disabled (OCR_DIS = High)
Mode
RUN1_MAC
IDD_Core
IDD_IO1
IDD_ADC
IDD_OSC_PLL
150mA
13µA
50mA
2.5mA
Test Conditions
• 60MHz Device Clock
• All peripheral clocks are enabled
• All peripherals running
• Continuous MAC instructions with
fetches from Data RAM
• ADC powered on and clocked
Wait3
86mA
13µA
65µA
2.5mA
• 60MHz Device Clock
Freescale Semiconductor, Inc...
• All peripheral clocks are enabled
• All peripherals running
• ADC powered off
Stop1
800µA
13µA
0µA
155µA
• 8MHz Device Clock
• All peripheral clocks are off
• ADC powered off
• PLL powered off
Stop2
100µA
13µA
0µA
145µA
• External Clock is off
• All peripheral clocks are off
• ADC powered off
• PLL powered off
1. No Output Switching
Table 10-9. Regulator Parameters
Characteristic
Symbol
Min
Typical
Max
Unit
Unloaded Output Voltage
(0mA Load)
VRNL
2.25
—
2.75
V
Loaded Output Voltage
(250mA load)
VRL
2.25
—
2.75
V
Line Regulation @ 250mA load
(VDD33 ranges from 3.0V to 3.6V)
VR
2.25
—
2.75
V
Short Circuit Current
(output shorted to ground)
Iss
—
—
700
mA
I bias
—
5.8
7
mA
Ipd
—
0
2
µA
TRSC
—
—
30
minutes
Bias Current
Power-down Current
Short-Circuit Tolerance
(output shorted to ground)
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Temperature Sense
Table 10-10. PLL Parameters
Freescale Semiconductor, Inc...
Characteristics
Symbol
Min
Typical
Max
Unit
PLL Start-up time
TPS
0.3
0.5
10
ms
Resonator Start-up time
TRS
0.1
0.18
1
ms
Min-Max Period Variation
TPV
120
—
200
ps
Peak-to-Peak Jitter
TPJ
—
—
175
ps
Bias Current
IBIAS
—
1.5
2
mA
IPD
—
100
150
µA
Quiescent Current, power-down mode
10.3 Temperature Sense
Table 10-11 Temperature Sense Parametrics
Characteristics
Symbol
Min
Typical
Max
Unit
K
—
7.2
—
mV/°C
VDDA
3.0
3.3
3.6
V
Supply Current - OFF
IDD-OFF
—
—
10
µA
Supply Current - ON
IDD-ON
—
—
250
µA
Accuracy
TACC
TBD
—
TBD
°C
Resolution
RES
TBD
—
TBD
°C / bit2
K-factor1
Supply Voltage
1. This is the inverse of the parameter “m” found in the Functional Description of the Temperature Sensor section in the
56F8300 Peripheral User Manual.
2. Assuming a 10-bit range from 0V to 3.6V.
10.4 AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified,
propagation delays are measured from the 50% to the 50% point, and rise and fall times are
measured between the 10% and 90% points, as shown in Figure 10-1.
VIH
Input Signal
Low
High
90%
50%
10%
Midpoint1
Fall Time
VIL
Rise Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 10-1 Input Signal Measurement References
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Figure 10-2 shows the definitions of the following signal states:
•
•
•
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
•
Data Invalid state, when a signal level is in transition between VOL and VOH
Data2 Valid
Data1 Valid
Data1
Data3 Valid
Data2
Data3
Data
Tri-stated
Freescale Semiconductor, Inc...
Data Invalid State
Data Active
Data Active
Figure 10-2 Signal States
10.5 Flash Memory Characteristics
Table 10-12 Flash Timing Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Program time1
Tprog
20
—
—
µs
Erase time2
Terase
20
—
—
ms
Tme
100
—
—
ms
Mass erase time
1. There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual for
details. Program time is per 16-bit word in Flash memory. Two words at a time can be programmed within the Program Flash
module, as it contains two interleaved memories.
2. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes.
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External Clock Operation Timing
10.6 External Clock Operation Timing
Table 10-13 External Clock Operation Timing Requirements1
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)2
fosc
0
—
120
MHz
Clock Pulse Width3
tPW
3.0
—
—
ns
External clock input rise time4
trise
—
—
10
ns
External clock input fall time5
tfall
—
—
10
ns
Freescale Semiconductor, Inc...
1. Parameters listed are guaranteed by design.
2. See Figure 10-3 for details on using the recommended connection of an external clock driver.
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.
VIH
External
Clock
90%
50%
10%
90%
50%
10%
tfall
tPW
tPW
trise
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 10-3 External Clock Timing
10.7 Phase Locked Loop Timing
Table 10-14 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
fosc
4
8
8
MHz
PLL output frequency2 (fOUT)
fop
160
—
260
MHz
PLL stabilization time3 -40° to +125°C
tplls
—
1
10
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (fOUT/2), please refer to the OCCS chapter in the
56F8300 Peripheral User Manual.
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
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10.8 Crystal Oscillator Timing
Table 10-15 Crystal Oscillator Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Crystal Start-up time
TCS
4
5
10
ms
Resonator Start-up time
TRS
0.1
0.18
1
ms
RESR
—
—
120
ohms
Crystal Peak-to-Peak Jitter
TD
70
—
250
ps
Crystal Min-Max Period Variation
TPV
0.12
—
1.5
ns
Resonator Peak-to-Peak Jitter
TRJ
—
—
300
ps
Resonator Min-Max Period Variation
TRP
—
—
300
ps
Bias Current, high-drive mode
IBIASH
—
250
290
µA
Bias Current, low-drive mode
IBIASL
—
80
110
µA
IPD
—
0
1
µA
Freescale Semiconductor, Inc...
Crystal ESR
Quiescent Current, power-down mode
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 10-16 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
Symbol
Typical
Min
Typical
Max
Unit
See Figure
Minimum RESET Assertion Duration
tRA
16T
—
ns
10-4
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
10-5
tIG
18
—
ns
10-6
tIG - FAST
14
—
tIW
1.5T
—
ns
10-8
Characteristic
IRQA, IRQB Assertion to General Purpose
Output Valid, caused by first instruction
execution in the interrupt service routine
IRQA Width Assertion to Recover from Stop
State3
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop
modes), T = 125ns.
2. Parameters listed are guaranteed by design.
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
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Reset, Stop, Wait, Mode Select, and Interrupt Timing
RESET
tRA
tRAZ
tRDA
A0–A15,
D0–D15
First Fetch
Figure 10-4 Asynchronous Reset Timing
Freescale Semiconductor, Inc...
IRQA,
IRQB
tIRW
Figure 10-5 External Interrupt Timing (Negative Edge-Sensitive)
A0–A15
First Interrupt Instruction Execution
tIDM
IRQA,
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA,
IRQB
b) General Purpose I/O
Figure 10-6 External Level-Sensitive Interrupt Timing
IRQA,
IRQB
tIRI
A0–A15
First Interrupt Vector
Instruction Fetch
Figure 10-7 Interrupt from Wait State Timing
tIW
IRQA
tIF
A0–A15
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing
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10.10 Serial Peripheral Interface (SPI) Timing
Table 10-17 SPI Timing1
Characteristic
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Cycle time
Master
Slave
Symbol
Min
Max
Unit
50
50
—
—
ns
ns
—
25
—
—
ns
ns
—
100
—
—
ns
ns
17.6
25
—
—
ns
ns
24.1
25
—
—
ns
ns
20
0
—
—
ns
ns
0
2
—
—
ns
ns
4.8
15
ns
3.7
15.2
ns
—
—
4.5
20.4
ns
ns
0
0
—
—
ns
ns
—
—
11.5
10.0
ns
ns
—
—
9.7
9.0
ns
ns
tC
Enable lead time
Master
Slave
tELD
Enable lag time
Master
Slave
tELG
Clock (SCK) high time
Master
Slave
tCH
Clock (SCK) low time
Master
Slave
tCL
Data set up time required for inputs
Master
Slave
tDS
Data hold time required for inputs
Master
Slave
tDH
Access time (time to data active from
high-impedance state)
Slave
tA
Disable time (hold time to high-impedance state)
Slave
tD
Data Valid for outputs
Master
Slave (after enable edge)
tDV
Data invalid
Master
Slave
tDI
Rise time
Master
Slave
tR
Fall time
Master
Slave
tF
See Figure
10-9, 10-10,
10-11, 10-12
10-12
10-12
10-9, 10-10,
10-11, 10-12
10-12
10-9, 10-10,
10-11, 10-12
10-9, 10-10,
10-11, 10-12
10-12
10-12
10-9, 10-10,
10-11, 10-12
10-9, 10-10,
10-11
10-9, 10-10,
10-11, 10-12
10-9, 10-10,
10-11, 10-12
1. Parameters listed are guaranteed by design.
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Serial Peripheral Interface (SPI) Timing
SS
SS is held High on master
(Input)
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
Freescale Semiconductor, Inc...
tDH
tCH
tDS
MISO
(Input)
MSB in
Bits 14–1
tDI
MOSI
(Output)
LSB in
tDI(ref)
tDV
Master MSB out
Bits 14–1
Master LSB out
tR
tF
Figure 10-9 SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tR
MISO
(Input)
MSB in
tDI
tDV(ref)
MOSI
(Output)
Master MSB out
tDH
Bits 14–1
tDV
Bits 14– 1
tF
LSB in
tDI(ref)
Master LSB out
tR
Figure 10-10 SPI Master Timing (CPHA = 1)
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SS
(Input)
tC
tF
tCL
SCLK (CPOL = 0)
(Input)
tELG
tR
tCH
tELD
tCL
Freescale Semiconductor, Inc...
SCLK (CPOL = 1)
(Input)
tCH
tA
MISO
(Output)
Slave MSB out
tF
tR
Bits 14–1
tDS
Slave LSB out
tDV
tDI
tDH
MOSI
(Input)
MSB in
tD
Bits 14–1
tDI
LSB in
Figure 10-11 SPI Slave Timing (CPHA = 0)
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tA
MISO
(Output)
Slave MSB out
Bits 14–1
tDS
tDV
tDH
MOSI
(Input)
tD
tF
MSB in
Bits 14–1
Slave LSB out
tDI
LSB in
Figure 10-12 SPI Slave Timing (CPHA = 1)
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Quad Timer Timing
10.11 Quad Timer Timing
Table 10-18 Timer Timing1, 2
Characteristic
Symbol
Min
Max
Unit
See Figure
PIN
2T + 6
—
ns
10-13
Timer input high / low period
PINHL
1T + 3
—
ns
10-13
Timer output period
POUT
1T - 3
—
ns
10-13
POUTHL
0.5T - 3
—
ns
10-13
Timer input period
Freescale Semiconductor, Inc...
Timer output high / low period
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PIN
PINHL
PINHL
POUT
POUTHL
POUTHL
Timer Outputs
Figure 10-13 Timer Timing
10.12 Quadrature Decoder Timing
Table 10-19 Quadrature Decoder Timing1, 2
Characteristic
Symbol
Min
Max
Unit
See Figure
Quadrature input period
PIN
4T + 12
—
ns
10-14
Quadrature input high / low period
PHL
2T + 6
—
ns
10-14
Quadrature phase period
PPH
1T + 3
—
ns
10-14
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns.
2. Parameters listed are guaranteed by design.
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PPH
PPH
PPH
PPH
Phase A
(Input)
PHL
PIN
PHL
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Phase B
PHL
(Input)
PIN
PHL
Figure 10-14 Quadrature Decoder Timing
10.13 Serial Communication Interface (SCI) Timing
Table 10-20 SCI Timing1
Characteristic
Symbol
Min
Max
Unit
See Figure
BR
—
(fMAX/16)
Mbps
—
RXD3 Pulse Width
RXDPW
0.965/BR
1.04/BR
ns
10-15
TXD4 Pulse Width
TXDPW
0.965/BR
1.04/BR
ns
10-16
Baud Rate2
1. Parameters listed are guaranteed by design.
2. fMAX is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8345 device.
3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
RXD
SCI receive
data pin
(Input)
RXDPW
Figure 10-15 RXD Pulse Width
TXD
SCI receive
data pin
(Input)
TXDPW
Figure 10-16 TXD Pulse Width
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Controller Area Network (CAN) Timing
10.14 Controller Area Network (CAN) Timing
Table 10-21 CAN Timing1
Characteristic
Baud Rate
Bus Wake Up detection
Symbol
Min
Max
Unit
See Figure
BRCAN
—
1
Mbps
—
T WAKEUP
5
—
µs
10-17
Freescale Semiconductor, Inc...
1. Parameters listed are guaranteed by design
CAN_RX
CAN receive
data pin
(Input)
T WAKEUP
Figure 10-17 Bus Wake Up Detection
10.15 JTAG Timing
Table 10-22 JTAG Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
TCK frequency of operation
using EOnCE1
fOP
DC
SYS_CLK/8
MHz
10-18
TCK frequency of operation not
using EOnCE1
fOP
DC
SYS_CLK/4
MHz
10-18
TCK clock pulse width
tPW
50
—
ns
10-18
TMS, TDI data set-up time
tDS
5
—
ns
10-19
TMS, TDI data hold time
tDH
5
—
ns
10-19
TCK low to TDO data valid
tDV
—
30
ns
10-19
TCK low to TDO tri-state
tTS
—
30
ns
10-19
tTRST
2T2
—
ns
10-20
TRST assertion time
1. TCK frequency of operation must be less than 1/8 the processor rate.
2. T = processor clock period (nominally 1/60MHz)
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1/fOP
tPW
tPW
VM
VM
VIH
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2
Figure 10-18 Test Clock Input Timing Diagram
Freescale Semiconductor, Inc...
TCK
(Input)
tDS
TDI
TMS
(Input)
tDH
Input Data Valid
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 10-19 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 10-20 TRST Timing Diagram
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Analog-to-Digital Converter (ADC) Parameters
10.16 Analog-to-Digital Converter (ADC) Parameters
Table 10-23 ADC Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
VADIN
VREFL
—
VREFH
V
Resolution
RES
12
—
12
Bits
Integral Non-Linearity1
INL
+/- 1
+/- 2.4
+/- 3.2
LSB2
Differential Non-Linearity
DNL
> -1
+/- 0.7
< +1
LSB2
Input voltages
Freescale Semiconductor, Inc...
Monotonicity
GUARANTEED
ADC internal clock
fADIC
0.5
—
5
MHz
Conversion range
RAD
VREFL
—
VREFH
V
ADC channel power-up time
tADPU
5
6
16
tAIC cycles3
ADC reference circuit power-up time4
tVREF
—
—
25
ms
Conversion time
tADC
—
6
—
tAIC cycles3
Sample time
tADS
—
1
—
tAIC cycles3
Input capacitance
CADI
—
5
—
pF
Input injection current5, per pin
IADI
—
—
3
mA
Input injection current, total
IADIT
—
—
20
mA
VREFH current
IVREFH
—
1.2
3
mA
ADC A current
IADCA
—
25
—
mA
ADC B current
IADCB
—
25
—
mA
Quiescent current
IADCQ
—
0
10
µA
Uncalibrated Gain Error
EGAIN
.99
.996 to 1.004
1.01
—
Uncalibrated Offset Voltage
VOFFSET
—
+/- 18
+/- 30
mV
Calibrated Absolute Error6
AECAL
—
See Figure 10-21
—
LSBs
Calibration Factor 17
CF1
—
-0.003141
—
—
Calibration Factor 27
CF2
—
-17.6
—
—
—
—
-60
—
dB
Vcommon
—
(VREFH - VREFLO) / 2
—
V
SNR
—
64.6
—
db
SINAD
—
59.1
—
db
THD
—
60.6
—
db
Spurious Free Dynamic Range
SFDR
—
61.1
—
db
Effective Number Of Bits8
ENOB
—
9.6
—
Bits
Crosstalk between channels
Common Mode Voltage
Signal-to-noise ratio
Signal-to-noise plus distortion ratio
Total Harmonic Distortion
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1. INL measured from Vin = .1VREFH to Vin = .9VREFH
10% to 90% Input Signal Range
2. LSB = Least Significant Bit
3. ADC clock cycles
4. Assumes each voltage reference pin is bypassed with 0.1µF ceramic capacitors to ground
5. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of
the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.
6. Absolute error includes the effects of both gain error and offset error.
7. Please see the 56F8300 Peripheral User’s Manual for additional information on ADC calibration.
Freescale Semiconductor, Inc...
8. ENOB = (SINAD - 1.76)/6.02
Figure 10-21 ADC Absolute Error Over Processing and Temperature Extremes
Before and After Calibration for VDCin = 0.60V and 2.70V
Note: The absolute error data shown in the graphs above reflects the effects of both gain error and
offset error. The data was taken on 15 parts: three each from four processing corner lots as well as
three from one nominally processed lot, each at three temperatures: -40°C, 27°C, and 150°C
(giving the 45 data points shown above), for two input DC voltages: 0.60V and 2.70V. The data
indicates that for the given population of parts, calibration significantly reduced (by as much as
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Equivalent Circuit for ADC Inputs
39%) the collective variation (spread) of the absolute error of the population. It also significantly
reduced (by as much as 80%) the mean (average) of the absolute error and thereby brought it
significantly closer to the ideal value of zero. Although not guaranteed, it is believed that
calibration will produce results similar to those shown above for any population of parts including
those which represent processing and temperature extremes.
Freescale Semiconductor, Inc...
10.17 Equivalent Circuit for ADC Inputs
Figure 10-22 illustrates the ADC input circuit during sample and hold. S1 and S2 are always
open/closed at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input
of the sample and hold circuit moves to VREFH - VREFH / 2, while the other charges to the analog
input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with
the result that a single-ended analog input is switched to a differential voltage centered about
VREFH - VREFH / 2. The switches switch on every cycle of the ADC clock (open one-half ADC
clock, closed one-half ADC clock). Note that there are additional capacitances associated with the
analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides
isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog
input voltage, VREF and the ADC clock frequency.
3
Analog Input
4
S1
(VREFH - VREFLO) / 2
2
1
1.
2.
3.
4.
S2
C1
S/H
S3
C2
C1 = C2 = 1pF
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf
Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is
only connected to it at sampling time; 1pf
Figure 10-22 Equivalent Circuit for A/D Loading
10.18 Power Consumption
This section provides additional detail which can be used to optimize power consumption for a
given application.
Power consumption is given by the following equation:
Total power =
+
+
+
+
A: internal [static component]
B: internal [state-dependent component]
C: internal [dynamic component]
D: external [dynamic component]
E: external [static]
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A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage
current, PLL, and voltage references. These sources operate independently of processor state or
operating frequency.
B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
Freescale Semiconductor, Inc...
C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding
to the 56800E core and standard cell logic.
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive
loading on the external pins of the chip. This is also commonly described as C*V2*F, although
simulations on two of the IO cell types used on the 56F8345 reveal that the power-versus-load
curve does have a non-zero Y-intercept.
Table 10-24 IO Loading Coefficients at 10MHz
Intercept
Slope
PDU08DGZ_ME
1.3
0.11mW / pF
PDU04DGZ_ME
1.15mW
0.11mW / pF
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and
frequency at which the outputs change. Table 10-24 provides coefficients for calculating power
dissipated in the IO cells as a function of capacitive load. In these cases:
Total Power = Σ((Intercept +Slope*Cload)*frequency/10MHz)
where:
•
•
•
Summation is performed over all output pins with capacitive loads
Total Power is expressed in mW
Cload is expressed in pF
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was
found to be fairly low when averaged over a period of time.
E, the external [static component], reflects the effects of placing resistive loads on the outputs of
the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power.
Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of eight
PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW.
In previous discussions, power consumption due to parasitics associated with pure input pins is
ignored, as it is assumed to be negligible.
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Package and Pin-Out Information 56F8345
Part 11 Packaging
11.1 Package and Pin-Out Information 56F8345
PHASEB0
PHASEA0
MOSI0
MISO0
SCLK0
SS0
VCAP2
CAN_RX
CAN_TX
VPP1
TDO
TDI
TMS
TCK
TRST
TC1
VDD_IO
TC0
TD3
TD2
TD1
TD0
ISA2
ISA1
ISA0
ANB7
INDEX0
HOME0
VSS
VDD_IO
VPP2
CLKO
TXD0
RXD0
PHASEA1
PHASEB1
INDEX1
HOME1
VCAP4
VDD_IO
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
VSS
GPIOF0
GPIOF1
GPIOF2
VDD_IO
GPIOF3
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
PWMB0
PWMB1
PWMB2
VSS
VDD_IO
PWMB3
PWMB4
Orientation
Mark
PIN 1
103
Motorola
56F8345
65
39
ANB6
ANB5
ANB4
ANB3
ANB2
ANB1
ANB0
VSSA_ADC
VDDA_ADC
VREFH
VREFP
VREFMID
VREFN
VREFLO
TEMP_SENSE
ANA7
ANA6
ANA5
ANA4
ANA3
ANA2
ANA1
ANA0
CLKMODE
RESET
RSTO
VDD_IO
VCAP3
EXTAL
XTAL
VDDA_OSC_PLL
OCR_DIS
FAULTA3
FAULTA2
FAULTA1
FAULTA0
PWMA5
VSS
PWMB5
TXD1
RXD1
GPIOD0
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
ISB0
VCAP1
ISB1
ISB2
IRQA
IRQB
FAULTB0
FAULTB1
FAULTB2
FAULTB3
PWMA0
VSS
PWMA1
PWMA2
VDD_IO
PWMA3
PWMA4
Freescale Semiconductor, Inc...
This section contains package and pin-out information for the 56F8345. This device comes in a
128-pin Low-profile Quad Flat Pack (LQFP). Figure 11-1. shows the package outline for the
128-pin LQFP, Figure 11-2 shows the mechanical parameters for this package, and Table 11-1
lists the pin-out for the 128-pin LQFP.
Figure 11-1 Top View, 56F8345 128-pin LQFP Package
56F8345 Technical Data
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Freescale Semiconductor, Inc...
Table 11-1 56F8345 128-Pin LQFP Package Identification by Pin Number
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
INDEX0
33
PWMB1
65
VSS
97
ANB1
2
HOME0
34
PWMB2
66
PWMA5
98
ANB2
3
VSS
35
VSS
67
FAULTA0
99
ANB3
4
VDD_IO
36
VDD_IO
68
FAULTA1
100
ANB4
5
VPP2
37
PWMB3
69
FAULTA2
101
ANB5
6
CLKO
38
PWMB4
70
FAULTA3
102
ANB6
7
TXD0
39
PWMB5
71
OCR_DIS
103
ANB7
8
RXD0
40
TXD1
72
VDDA_OSC_PLL
104
ISA0
9
PHASEA1
41
RXD1
73
XTAL
105
ISA1
10
PHASEB1
42
GPIOD0
74
EXTAL
106
ISA2
11
INDEX1
43
GPIOD1
75
VCAP3
107
TD0
12
HOME1
44
GPIOD2
76
VDD_IO
108
TD1
13
VCAP4
45
GPIOD3
77
RSTO
109
TD2
14
VDD_IO
46
GPIOD4
78
RESET
110
TD3
15
GPIOA01
47
GPIOD5
79
CLKMODE
111
TC0
16
GPIOA11
48
ISB0
80
ANA0
112
VDD_IO
17
GPIOA21
49
VCAP1
81
ANA1
113
TC1
18
GPIOA31
50
ISB1
82
ANA2
114
TRST
19
GPIOA41
51
ISB2
83
ANA3
115
TCK
20
GPIOA51
52
IRQA
84
ANA4
116
TMS
21
VSS
53
IRQB
85
AN5
117
TDI
220
GPIOF01
54
FAULTB0
86
ANA6
118
TDO
23
GPIOF11
55
FAULTB1
87
ANA7
119
VPP1
24
GPIOF21
56
FAULTB2
88
TEMP_SENSE
120
CAN_TX
25
VDD_IO
57
FAULTB3
89
VREFLO
121
CAN_RX
26
GPIOF31
58
PWMA0
90
VREFN
122
VCAP2
27
GPIOB0
59
VSS
91
VREFMID
123
SS0
28
GPIOB1
60
PWMA1
92
VREFP
124
SCLK0
29
GPIOB2
61
PWMA2
93
VREFH
125
MISO0
30
GPIOB3
62
VDD_IO
94
VDDA_ADC
126
MOSI0
31
GPIOB4
63
PWMA3
95
VSSA_ADC
127
PHASEA0
32
PWMB0
64
PWMA4
96
ANB0
128
PHASEB0
1. Primary function is not available in this package configuration; GPIO function must be used instead.
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Package and Pin-Out Information 56F8345
102
65
103
64
128
39
Freescale Semiconductor, Inc...
38
DIM
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD
AND IS COINCIDENT WITH THE LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF
THE PARTING LINE.
4. DATUMS A, B, AND D TO BE DETERMINED AT DATUM
PLANE H.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER
SIDE. DIMENSIONS D1 AND E1 DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT DATUM
PLANE H.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE b DIMENSION TO EXCEED 0.35.
Case Outline - 1129-01
A
A1
A2
b
b1
c
c1
D
D1
e
E
E1
L
L1
L2
S
R1
R2
0
MILLIMETERS
MIN
MAX
--1.60
0.05
0.15
1.35
1.45
0.17
0.27
0.17
0.23
0.09
0.20
0.09
0.16
22.00 BSC
20.00BSC
0.50 BSC
16.00 BSC
14.00 BSC
0.45
0.75
1.00 REF
0.50 REF
0.20
--0.08
--0.08
0.20
0o
01
0o
7o
---
02
11o
13o
Figure 11-2 56F8345 128-pin LQFP Mechanical Information
56F8345 Technical Data
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Part 12 Design Considerations
12.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RθJΑ x PD)
where:
Freescale Semiconductor, Inc...
TA = Ambient temperature for the package (oC)
RθJΑ = Junction-to-ambient thermal resistance (oC/W)
PD = Power dissipation in the package (W)
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and
easy estimation of thermal performance. Unfortunately, there are two values in common usage: the
value determined on a single-layer board and the value obtained on a board with two planes. For
packages such as the PBGA, these values can be different by a factor of two. Which value is closer
to the application depends on the power dissipated by other components on the board. The value
obtained on a single-layer board is appropriate for the tightly packed printed circuit board. The
value obtained on the board with the internal planes is usually appropriate if the board has
low-power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case
thermal resistance and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = Package junction-to-ambient thermal resistance °C/W
RθJC = Package junction-to-case thermal resistance °C/W
RθCA = Package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal
environment to change the case-to-ambient thermal resistance, RθCA . For instance, the user can
change the size of the heat sink, the air flow around the device, the interface material, the mounting
arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board
surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used,
the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature
with a measurement of the temperature at the top center of the package case using the following
equation:
TJ = TT + (ΨJT x PD)
where:
TT
ΨJT
PD
144
= Thermocouple temperature on top of package (oC)
= Thermal characterization parameter (oC)/W
= Power dissipation in package (W)
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Electrical Design Considerations
Freescale Semiconductor, Inc...
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge
type T thermocouple epoxied to the top center of the package case. The thermocouple should be
positioned so that the thermocouple junction rests on the package. A small amount of epoxy is
placed over the thermocouple junction and over about 1mm of wire extending from the junction.
The thermocouple wire is placed flat against the package case to avoid measurement errors caused
by cooling effects of the thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is
normally required in the heat sink. Minimizing the size of the clearance is important to minimize
the change in thermal performance caused by removing part of the thermal interface to the heat
sink. Because of the experimental difficulties with this technique, many engineers measure the heat
sink temperature and then back-calculate the case temperature using a separate measurement of the
thermal resistance of the interface. From this case temperature, the junction temperature is
determined from the junction-to-case thermal resistance.
12.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the 56F8345:
•
Provide a low-impedance path from the board power supply to each VDD pin on the 56F8345, and
from the board ground to each VSS (GND) pin
•
The minimum bypass requirement is to place six 0.01–0.1µF capacitors positioned as close as
possible to the package supply pins. The recommended bypass configuration is to place one bypass
capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors
tend to provide better performance tolerances.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and
VSS (GND) pins are less than 0.5 inch per capacitor lead
•
•
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS
•
Bypass the VDD and VSS layers of the PCB with approximately 100µF, preferably with a high-grade
capacitor such as a tantalum capacitor
Because the 56F8345’s output signals have fast rise and fall times, PCB trace lengths should be
minimal
•
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•
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the VDD and VSS circuits.
•
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins
•
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. Designs that do not require
debugging functionality, such as consumer products, should tie these pins together.
Because the Flash memory is programmed through the JTAG/OnCE port, the designer should
provide an interface to this port to allow in-circuit Flash programming
•
Freescale Semiconductor, Inc...
12.3 Power Distribution and I/O Ring Implementation
Figure 12-1 illustrates the general power control incorporated in the 56F8345. This chip contains
an internal regulator which cannot be disabled. The regulator takes regulated 3.3V power from the
VDD_IO pins and provides 2.5V to the internal logic of the chip. This means the entire part is
powered from the 3.3V supply.
Notes:
•
•
Flash, RAM and internal logic are powered from the core regulator output
VPP1 and VPP2 are not connected in the customer system
•
All circuitry, analog and digital, shares a common VSS bus
VDDA_OSC_PLL
OCS
VDD
REG
VDDA_ADC
VCAP
REG
I/O
ADC
CORE
ROSC
VSS
VREFH
VREFP
VREFMID
VREFN
VREFLO
VSSA_ADC
Figure 12-1 56F8345 Power Management
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Power Distribution and I/O Ring Implementation
Part 13 Ordering Information
Table 13-1 lists the pertinent information needed to place an order. Consult a Motorola
Semiconductor sales office or authorized distributor to determine availability and to order parts.
Table 13-1 56F8345 Ordering Information
Supply
Voltage
Package Type
Pin
Count
Frequency
(MHz)
Temperature
Range
Order Number
MC56F8345
3.0–3.6 V
Low-Profile Quad Flat Pack (LQFP)
128
60
-40° to + 105° C
MC56F8345VFG60
MC56F8345
3.0–3.6 V
Low-Profile Quad Flat Pack (LQFP)
128
60
-40° to + 125° C
MC56F8345MFG60
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Part
56F8345 Technical Data
Preliminary
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MC56F8345/D
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