Qimonda HYS72T1G042ER 240-pin dual die registered ddr2 sdram module Datasheet

April 2007
HYS72T1G042ER–5–B
240-Pin Dual Die Registered DDR2 SDRAM Modules
RDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.0
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
HYS72T1G042ER–5–B
Revision History: 2007-04, Rev. 1.0
Page
Subjects (major changes since last revision)
All
Adapted internet edition
All
Final document
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
04242007-NQ2Z-YM3O
2
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 240-Pin Dual Die Registered DDR2 SDRAM Modules product family and describes its
main characteristics.
1.1
Features
• Average Refresh Period 7.8 µs at a TCASE lower than 85°C,
3.9µs between 85°C and 95°C.
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• DCC enabling via EMRS2 setting
• All inputs and outputs SSTL_1.8 compatible
• Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
• Serial Presence Detect with E2PROM
• RDIMM Dimensions (nominal):
42mm high and 133.35 mm wide
• Based on standard reference layouts Raw Card “Z”
• RoHS compliant products1)
• 240-Pin PC2–3200 DDR2 SDRAM memory modules.
• 1024M ×72 module organization and 2 × 256M × 4 chip
organization
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• 8 GB built with 1Gbit DDR2 SDRAMs in P-TFBGA-71
chipsize packages
• All speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications.
• Programmable CAS Latencies (3, 4 and 5), Burst Length
(8 & 4) and Burst Type
• Auto Refresh (CBR) and Self Refresh
TABLE 1
Performance Table
Product Type Speed Code
–5
Unit
Speed Grade
PC2–3200 3–3–3
—
200
MHz
200
MHz
200
MHz
15
ns
15
ns
40
ns
55
ns
Max. Clock Frequency
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
3
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
1.2
Description
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The QIMONDA HYS72T1G042ER–5–B module family are
Registered DIMM modules “RDIMMs” with 42 mm height
based on DDR2 technology. DIMMs are available ECC
modules in 1024M × 72 (8 GB) organization and density,
intended for mounting into 240-pin connector sockets.
The memory array is designed with stacked 1-Gbit DoubleData-Rate-Two (DDR2) Synchronous DRAMs. All control
and address signals are re-driven on the DIMM using
register devices and a PLL for the clock distribution.
This reduces capacitive loading to the system bus, but
adds one cycle to the SDRAM timing. Decoupling
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
2)
Compliance Code
Description
SDRAM
Technology
8 GB 4R×4 PC2–3200R–333–12–ZZ
4 Ranks, ECC
2 × 256Mbit( × 4 )
PC2–3200
HYS72T1G042ER–5–B
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T1G042ER–5–B, indicating Rev.
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “4R×4 PC2–3200R–333–12–ZZ”, where
3200R means Registered DIMM modules with 3.2 GB/sec Module Bandwidth and “333-12” means Column Address Strobe (CAS) latency
= 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced
on the Raw Card “Z”.
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
8 GByte
1024M × 72
4
ECC
36
Z
14/3/11
TABLE 4
Components on Modules
Product Type
1)
HYS72T1G042ER
1)
DRAM Components
DRAM Density
DRAM Organisation
HYB18T2G402BF
1 Gbit
2 × 256M × 4
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
4
Note2)
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
2
Pin Configuration
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in Table 5 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 6
and Table 7 respectively. The pin numbering is depicted in
Figure 1.
TABLE 5
Pin Configuration of RDIMM
Ball No.
Name
Pin
Type
Buffer
Type
Function
185
CK0
I
SSTL
Clock Signal CK0, Complementary Clock Signal CK0
186
CK0
I
SSTL
52
CKE0
I
SSTL
171
CKE1
I
SSTL
NC
NC
—
Not Connected
Note: 1-Rank module
193
S0
I
SSTL
76
S1
I
SSTL
Chip Select
Note: 2-Ranks module
NC
NC
—
S2
I
SSTL
Clock Signals
Clock Enables 1:0
Note: 2-Ranks module
Control Signals
220,
Not Connected
Note: 1-Rank module
Rank 2 is selected by S2
221
NC
NC
—
S3
I
SSTL
Not Connected
Note: 1-Rank, 2-Ranks module
Rank 3 is selected by S3
NC
NC
—
Not Connected
Note: 1-Rank, 2-Ranks module
192
RAS
I
SSTL
74
CAS
I
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
73
WE
I
SSTL
18
RESET
I
CMOS
Register Reset
71
BA0
I
SSTL
Bank Address Bus 1:0
190
BA1
I
SSTL
54
BA2
I
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
I
SSTL
Not Connected
Less than 1Gb DDR2 SDRAMS
Address Signals
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
5
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Ball No.
Name
Pin
Type
Buffer
Type
Function
188
A0
I
SSTL
Address Bus 12:0, Address Signal 10/AutoPrecharge
183
A1
I
SSTL
63
A2
I
SSTL
182
A3
I
SSTL
61
A4
I
SSTL
60
A5
I
SSTL
180
A6
I
SSTL
58
A7
I
SSTL
179
A8
I
SSTL
177
A9
I
SSTL
70
A10
I
SSTL
AP
I
SSTL
57
A11
I
SSTL
176
A12
I
SSTL
196
A13
I
SSTL
Address Signal 13
NC
NC
—
Not Connected
Note: Non CA parity modules based on 256 Mbit component
A14
I
SSTL
Address Signal 14
Note: CA Parity module
NC
NC
—
Not Connected
Note: Non CA parity module. Less than 1 GBit per DRAM die.
A15
I
SSTL
Address Signal 14
Note: CA Parity module
NC
NC
—
Not Connected
Note: Non CA parity module. Less than 1 GBit per DRAM die.
174
173
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
6
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Ball No.
Name
Pin
Type
Buffer
Type
Function
3
DQ0
I/O
SSTL
4
DQ1
I/O
SSTL
Data Bus 63:0
Data Input/Output pins
9
DQ2
I/O
SSTL
10
DQ3
I/O
SSTL
122
DQ4
I/O
SSTL
123
DQ5
I/O
SSTL
128
DQ6
I/O
SSTL
129
DQ7
I/O
SSTL
12
DQ8
I/O
SSTL
13
DQ9
I/O
SSTL
21
DQ10
I/O
SSTL
22
DQ11
I/O
SSTL
131
DQ12
I/O
SSTL
132
DQ13
I/O
SSTL
140
DQ14
I/O
SSTL
141
DQ15
I/O
SSTL
24
DQ16
I/O
SSTL
25
DQ17
I/O
SSTL
30
DQ18
I/O
SSTL
31
DQ19
I/O
SSTL
143
DQ20
I/O
SSTL
144
DQ21
I/O
SSTL
149
DQ22
I/O
SSTL
150
DQ23
I/O
SSTL
33
DQ24
I/O
SSTL
34
DQ25
I/O
SSTL
39
DQ26
I/O
SSTL
40
DQ27
I/O
SSTL
152
DQ28
I/O
SSTL
153
DQ29
I/O
SSTL
158
DQ30
I/O
SSTL
Data Signals
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
7
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Ball No.
Name
Pin
Type
Buffer
Type
Function
159
DQ31
I/O
SSTL
80
DQ32
I/O
SSTL
Data Bus 63:0
Data Input/Output pins
81
DQ33
I/O
SSTL
86
DQ34
I/O
SSTL
87
DQ35
I/O
SSTL
199
DQ36
I/O
SSTL
200
DQ37
I/O
SSTL
205
DQ38
I/O
SSTL
206
DQ39
I/O
SSTL
89
DQ40
I/O
SSTL
90
DQ41
I/O
SSTL
95
DQ42
I/O
SSTL
96
DQ43
I/O
SSTL
208
DQ44
I/O
SSTL
209
DQ45
I/O
SSTL
214
DQ46
I/O
SSTL
215
DQ47
I/O
SSTL
98
DQ48
I/O
SSTL
99
DQ49
I/O
SSTL
107
DQ50
I/O
SSTL
108
DQ51
I/O
SSTL
217
DQ52
I/O
SSTL
218
DQ53
I/O
SSTL
226
DQ54
I/O
SSTL
227
DQ55
I/O
SSTL
110
DQ56
I/O
SSTL
111
DQ57
I/O
SSTL
116
DQ58
I/O
SSTL
117
DQ59
I/O
SSTL
229
DQ60
I/O
SSTL
230
DQ61
I/O
SSTL
235
DQ62
I/O
SSTL
236
DQ63
I/O
SSTL
42
CB0
I/O
SSTL
43
CB1
I/O
SSTL
48
CB2
I/O
SSTL
49
CB3
I/O
SSTL
Check Bits
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
Check Bits 7:0
Check Bit Input / Output pins
Note: NC on Non-ECC module
8
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Ball No.
Name
Pin
Type
Buffer
Type
Function
161
CB4
I/O
SSTL
162
CB5
I/O
SSTL
167
CB6
I/O
SSTL
Check Bits 7:0
Check Bit Input / Output pins
Note: NC on Non-ECC module
168
CB7
I/O
SSTL
7
DQS0
I/O
SSTL
6
DQS0
I/O
SSTL
16
DQS1
I/O
SSTL
15
DQS1
I/O
SSTL
28
DQS2
I/O
SSTL
27
DQS2
I/O
SSTL
37
DQS3
I/O
SSTL
36
DQS3
I/O
SSTL
84
DQS4
I/O
SSTL
83
DQS4
I/O
SSTL
93
DQS5
I/O
SSTL
92
DQS5
I/O
SSTL
105
DQS6
I/O
SSTL
104
DQS6
I/O
SSTL
114
DQS7
I/O
SSTL
113
DQS7
I/O
SSTL
46
DQS8
I/O
SSTL
45
DQS8
I/O
SSTL
125
DQS9
I/O
SSTL
126
DQS9
I/O
SSTL
134
DQS10
I/O
SSTL
135
DQS10
I/O
SSTL
146
DQS11
I/O
SSTL
147
DQS11
I/O
SSTL
155
DQS12
I/O
SSTL
156
DQS12
I/O
SSTL
202
DQS13
I/O
SSTL
203
DQS13
I/O
SSTL
211
DQS14
I/O
SSTL
212
DQS14
I/O
SSTL
223
DQS15
I/O
SSTL
224
DQS15
I/O
SSTL
232
DQS16
I/O
SSTL
Data Strobe Bus
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
Data Strobes 17:0
9
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Ball No.
Name
Pin
Type
Buffer
Type
Function
233
DQS16
I/O
SSTL
Data Strobes 17:0
164
DQS17
I/O
SSTL
165
DQS17
I/O
SSTL
125
DM0
I
SSTL
134
DM1
I
SSTL
146
DM2
I
SSTL
155
DM3
I
SSTL
202
DM4
I
SSTL
211
DM5
I
SSTL
223
DM6
I
SSTL
232
DM7
I
SSTL
164
DM8
I
SSTL
120
SCL
I
CMOS
Serial Bus Clock
119
SDA
I/O
OD
Serial Bus Data
239
SA0
I
CMOS
Serial Address Select Bus 2:0
240
SA1
I
CMOS
101
SA2
I
CMOS
Data Mask
Data Masks 8:0
Note: ×8 based module
EEPROM
Parity
55
ERR_OUT
O
CMOS
68
PAR_IN
I
CMOS
VREF
VDDSPD
VDDQ
AI
—
I/O Reference Voltage
PWR
—
EEPROM Power Supply
PWR
—
I/O Driver Power Supply
PWR
—
Power Supply
Parity bits
Power Supplies
1
238
51, 56, 62, 72, 75,
78, 170, 175, 181,
191, 194
53, 59, 64, 67, 69, VDD
172, 178, 184, 187,
189, 197
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
10
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Ball No.
Name
2, 5, 8, 11, 14, 17, VSS
20, 23, 26, 29, 32,
35, 38, 41, 44, 47,
50, 65, 66, 79, 82,
85, 88, 91, 94, 97,
100, 103, 106, 109,
112, 115, 118, 121,
124, 127, 130, 133,
136, 139, 142, 145,
148, 151, 154, 157,
160, 163, 166, 169,
198, 201, 204, 207,
210, 213, 216, 219,
222, 225, 228, 231,
234, 237
Pin
Type
Buffer
Type
Function
GND
—
Ground Plane
Other Pins
19, 102, 137, 138,
NC
NC
—
Not connected
195
ODT0
I
SSTL
77
ODT1
I
SSTL
On-Die Termination Control 1:0
Note: 2-Ranks module
NC
NC
—
Note: 1-Rank modules
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
TABLE 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NU
Not Usable
NC
Not Connected
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
11
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
FIGURE 1
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
966
9''
9''
%$
:(
9''4
1&2'7 966
'4
'46
966
'4
'4
966
'46
'4
966
'4
6$
966
'46
'4
966
'4
'46
966
'4
6'$
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
1&(35B287
$
9''
$
$
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
966
'4
'46 966
'4
'4
966
'46 5(6(7 966
'4 '4 966
'46 '4 966
'4 '46 966
'4 &%
966
'46 &%
966
&.( 1&%$ 9''4
$
$
9''4
9''
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
$$3 9''4
&$6
1&6 9''4
'4 966
'46 '4 966
'4 '46 966
'4 '4 966
1&
'46 966
'4 '4 966
'46 '4 966
6&/
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
966
1&3$5B,1
%$&.6,'(
95()
'4
966
'46
'4
966
'4
'46
966
1&
'4
966
'4
'46
966
'4
'4
966
'46
'4
966
&%
'46
966
&%
9''4
9''
)52176,'(
Pin Configuration for RDIMM (240 pins)
12
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
'4
966
1&'46
'4
966
'4
'0'46
966
1&
'4
966
'4
'0'46
966
'4
'4
966
1&'46
'4
966
&%
'0'46
966
&%
9''4
9''
1&$
$
9''
$
$
9''
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
&.
$
%$
5$6
9''4
1&$
966
'4
'0'46
966
'4
'4
966
1&'46
'4
966
'4
1&6
966
1&'46
'4
966
'4
'0'46
966
'4
9''63'
6$
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
966
'4
'0'46
966
'4
'4
966
1&'46
1&
966
'4
'4
966
1&'46
'4
966
'4
'0'46
966
'4
&%
966
1&'46
&%
966
1&&.(
1&$
9''4
$
$
9''4
$
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
3LQ
&.
9''
9''
9''4
6
2'7
9''
'4
966
1&'46
'4
966
'4
'0'46
966
'4
'4
966
1&6
'0'46
966
'4
'4
966
1&'46
'4
966
6$
0337
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
3
Electrical Characteristics
This chapter lists the electrical characteristics.
3.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.
TABLE 8
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
Parameter
Rating
Unit
Note
Min.
Max.
Voltage on VDD pin relative to VSS
–1.0
+2.3
V
1)
Voltage on VDDQ pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on VDDL pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on any pin relative to VSS
–0.5
+2.3
V
1)
°C
1)2)
Storage Temperature
–55
+100
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
DRAM Component Operating Temperature Range
Symbol
TOPER
Parameter
Rating
Operating Temperature
Min.
Max.
0
95
Unit
Note
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
13
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
3.2
DC Operating Conditions
This chapter contains the DC operating conditions tables.
TABLE 10
Operating Conditions
Parameter
Symbol
Operating temperature (ambient)
DRAM Case Temperature
Storage Temperature
Barometric Pressure (operating & storage)
Operating Humidity (relative)
TOPR
TCASE
TSTG
PBar
HOPR
Values
Unit
Min.
Max.
0
+65
°C
0
+95
°C
– 50
+100
°C
+69
+105
kPa
10
90
%
Note
1)2)3)4)
5)
1)
2)
3)
4)
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs
When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %.
5) Up to 3000 m.
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
DC Input Logic High
DC Input Logic Low
Symbol
VDD
VDDQ
VREF
VDDSPD
VIH(DC)
VIL (DC)
IL
Values
Unit
Min.
Typ.
Max.
1.7
1.8
1.9
V
1.7
1.8
1.9
V
1)
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
2)
1.7
—
3.6
V
VREF + 0.125
—
V
– 0.30
—
VDDQ + 0.3
VREF – 0.125
V
In / Output Leakage Current
–5
—
5
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2 % VREF (DC).VREF is also expected to track noise in VDDQ.
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
Note
14
3)
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
3.3
Timing Characteristics
This chapter describes the timing characteristics.
3.3.1
Speed Grade Definitions
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(tCK = 5ns with tRAS = 40ns).
Speed Grade Definitions: Table 12 for DDR2–400B
TABLE 12
Speed Grade Definition Speed Bins for DDR2-400B
Speed Grade
DDR2–400B
QAG Sort Name
–5
CAS-RCD-RP latencies
3–3–3
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
ns
1)2)3)4)
5
8
ns
1)2)3)4)
5
8
ns
1)2)3)4)
40
70000
ns
1)2)3)4)5)
55
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
15
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
3.3.2
Component AC Timing Parameters
Timing Parameters: Table 13 for DDR2–400B
TABLE 13
DRAM Component Timing Parameter by Speed Grade - DDR2-400
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
tAC
tCCD
tCH
tCKE
tCL
tDAL
–600
+600
ps
2
—
0.45
0.55
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
tDELAY
tIS + tCK + tIH
––
ns
9)
tDH(base)
275
––
ps
10)
–25
—
ps
11)
0.35
—
tCK
–500
+500
ps
0.35
—
tCK
—
350
ps
– 0.25
+ 0.25
tCK
DQ and DM input hold time (single ended data tDH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
tDIPW
tDQSCK
tDQSL,H
tDQSQ
Write command to 1st DQS latching transition tDQSS
8)21)
11)
DQ and DM input setup time (differential data
strobe)
tDS(base)
150
—
ps
11)
DQ and DM input setup time (single ended
data strobe)
tDS1(base)
–25
—
ps
11)
DQS falling edge hold time from CK (write
cycle)
tDSH
0.2
—
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
tCK
37.5
—
ns
50
—
ns
Four Activate Window period
Four Activate Window period
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
tFAW
tFAW
tHP
tHZ
tIH(base)
tIPW
12)
MIN. (tCL, tCH)
tIS(base)
tLZ(DQ)
tLZ(DQS)
—
tAC.MAX
ps
13)
475
—
ps
11)
0.6
—
tCK
350
—
ps
11)
2 × tAC.MIN
tAC.MAX
tAC.MAX
ps
14)
ps
14)
tAC.MIN
16
13)
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
2
—
tCK
0
12
ns
tHP –tQHS
—
—
450
ps
—
7.8
µs
14)15)
—
3.9
µs
16)18)
127.5
—
ns
17)
tRP
tRP
tRPRE
tRPST
tRRD
tRP + 1tCK
15 + 1tCK
—
ns
—
ns
0.9
1.1
14)
0.40
0.60
tCK
tCK
7.5
—
ns
14)18)
Active bank A to Active bank B command
period
tRRD
10
—
ns
16)22)
Internal Read to Precharge command delay
tRTP
tWPRE
tWPST
tWR
7.5
—
ns
0.25
—
0.40
0.60
tCK
tCK
15
—
ns
tWTR
tXARD
10
—
ns
20)
2
—
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
—
tCK
21)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
200
—
WR
tWR/tCK
—
tCK
tCK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Average periodic refresh Interval
tMRD
tOIT
tQH
tQHS
tREFI
tREFI
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Write preamble
Write postamble
Write recovery time for write without AutoPrecharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to Read command
Write recovery time for write with AutoPrecharge
14)
19)
22)
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
17
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
3.3.3
ODT AC Electrical Characteristics
TABLE 14
ODT AC Electrical Characteristics and Operating Conditions for DDR2-400
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Min.
Max.
ODT turn-on delay
2
2
tCK
ODT turn-on
tAC.MIN
tAC.MIN + 2 ns
tAC.MAX + 1 ns
2 tCK + tAC.MAX + 1 ns
ns
ODT turn-on (Power-Down Modes)
Note
1)
ns
ODT turn-off delay
2.5
2.5
tCK
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT to Power Down Mode Entry Latency
3
—
ODT Power Down Exit Latency
8
—
tCK
tCK
2)
ns
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measure from tAOND.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD.
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
18
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
3.4
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions.
• Table 15 “IDD Measurement Conditions” on Page 19
• Table 16 “Definitions for IDD” on Page 20
• Table 17 “IDD Specification for HYS72T1G042ER–5–B” on Page 21
TABLE 15
IDD Measurement Conditions
Parameter
Symbol Note
1)2)3)4)5)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN,
tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
6)
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
IDD2Q
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3N
Active Power-Down Current
IDD3P(0)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
IDD3P(1)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
IDD4R
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX;
tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5B
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
19
6)
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Parameter
Symbol Note
1)2)3)4)5)
Distributed Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5D
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 16
4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6)
5) For details and notes see the relevant Qimonda component data sheet
6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 16
Definitions for IDD
Parameter
Description
LOW
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
STABLE
Inputs are stable at a HIGH or LOW level
FLOATING
Inputs are VREF = VDDQ /2
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
20
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
TABLE 17
IDD Specification for HYS72T1G042ER–5–B
Units
Note1)
3330
mA
2)
3420
mA
2)
1840
mA
3)
4580
mA
3)
4220
mA
3)
3500
mA
3)
2060
mA
3)4)
4940
mA
3)5)
4050
mA
2)
4050
mA
2)
5040
mA
2)
1910
mA
3)6)
720
mA
3)6)
5490
mA
2)
Product Type
HYS72T1G042ER–5–B
Organization
8 GB
×72
4 Ranks
–5
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
1) Module IDDis calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R, and IDD7, are
defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
21
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
• Table 18 “HYS72T1G042ER-5-B” on Page 22
TABLE 18
Product Type
HYS72T1G042ER–5–B
HYS72T1G042ER-5-B
Organization
8 GByte
×72
4 Ranks (×4)
Label Code
PC2–3200R–333
JEDEC SPD Revision
Rev. 1.2
Byte#
Description
HEX
0
Programmed SPD Bytes in EEPROM
80
1
Total number of Bytes in EEPROM
08
2
Memory Type (DDR2)
08
3
Number of Row Addresses
0E
4
Number of Column Addresses
0B
5
DIMM Rank and Stacking Information
63
6
Data Width
48
7
Not used
00
8
Interface Voltage Level
05
9
50
10
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
11
Error Correction Support (non-ECC, ECC)
02
12
Refresh Rate and Type
82
13
Primary SDRAM Width
04
14
Error Checking SDRAM Width
04
15
Not used
00
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
60
22
Internet Data Sheet
Product Type
HYS72T1G042ER–5–B
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Organization
8 GByte
×72
4 Ranks (×4)
Label Code
PC2–3200R–333
JEDEC SPD Revision
Rev. 1.2
Byte#
Description
HEX
16
Burst Length Supported
0C
17
Number of Banks on SDRAM Device
08
18
Supported CAS Latencies
38
19
DIMM Mechanical Characteristics
01
20
DIMM Type Information
01
21
DIMM Attributes
05
22
Component Attributes
07
23
50
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
31
Module Density per Rank
02
32
35
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
39
Analysis Characteristics
00
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
06
24
25
26
27
28
29
33
34
35
36
37
41
42
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
60
50
60
3C
1E
3C
28
47
15
27
3C
28
1E
37
7F
23
Internet Data Sheet
Product Type
HYS72T1G042ER–5–B
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Organization
8 GByte
×72
4 Ranks (×4)
Label Code
PC2–3200R–333
JEDEC SPD Revision
Rev. 1.2
Byte#
Description
HEX
43
80
45
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
2D
46
PLL Relock Time
0F
47
TCASE.MAX Delta / ∆T4R4W Delta
50
48
Psi(T-A) DRAM
00
49
∆T0 (DT0)
00
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
00
51
∆T2P (DT2P)
00
52
∆T3N (DT3N)
00
53
∆T3P.fast (DT3P fast)
00
54
∆T3P.slow (DT3P slow)
00
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
00
56
∆T5B (DT5B)
00
44
23
57
∆T7 (DT7)
00
58
Psi(ca) PLL
00
59
Psi(ca) REG
00
60
∆TPLL (DTPLL)
00
61
∆TREG (DTREG) / Toggle Rate
00
62
SPD Revision
12
63
Checksum of Bytes 0-62
46
64
Manufacturer’s JEDEC ID Code (1)
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
69
Manufacturer’s JEDEC ID Code (6)
51
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
24
Internet Data Sheet
Product Type
HYS72T1G042ER–5–B
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Organization
8 GByte
×72
4 Ranks (×4)
Label Code
PC2–3200R–333
JEDEC SPD Revision
Rev. 1.2
Byte#
Description
HEX
70
Manufacturer’s JEDEC ID Code (7)
00
71
Manufacturer’s JEDEC ID Code (8)
00
72
Module Manufacturer Location
xx
73
Product Type, Char 1
37
74
Product Type, Char 2
32
75
Product Type, Char 3
54
76
Product Type, Char 4
31
77
Product Type, Char 5
47
78
Product Type, Char 6
30
79
Product Type, Char 7
34
80
Product Type, Char 8
32
81
Product Type, Char 9
45
82
Product Type, Char 10
52
83
Product Type, Char 11
35
84
Product Type, Char 12
42
85
Product Type, Char 13
20
86
Product Type, Char 14
20
87
Product Type, Char 15
20
88
Product Type, Char 16
20
89
Product Type, Char 17
20
90
Product Type, Char 18
20
91
Module Revision Code
0x
92
Test Program Revision Code
xx
93
Module Manufacturing Date Year
xx
94
Module Manufacturing Date Week
xx
95 - 98
Module Serial Number
xx
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
25
Internet Data Sheet
Product Type
HYS72T1G042ER–5–B
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Organization
8 GByte
×72
4 Ranks (×4)
Label Code
PC2–3200R–333
JEDEC SPD Revision
Rev. 1.2
Byte#
Description
HEX
99 - 127
Not used
00
128 - 255
Blank for customer use
FF
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
26
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
5
Package Outlines
This chapter contains the package outlines of the products.
FIGURE 2
Package Outline Raw Card Z L-DIM-240-46
0
$;
¡$%&[
%
&
“
$
“
“
%
0,
1
“
'
H
W
D
L
ORI
FR
Q
W
D
F
W
V
“
$%&
%
X
U
UP
D
[
DO
O
R
Z
H
G
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
27
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
6
Product Type Nomenclature
Qimonda´s nomenclature uses simple coding combined with some propriatory coding. Table 19 provides examples for module
and component product type number as well as the field number. The detailed field description together with possible values
and coding explanation is listed for modules in Table 20 and for components in Table 21.
TABLE 19
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
HYS
64
T
64/128
0
2
0
K
M
–5
–A
DDR2 DRAM
HYB
18
T
512/1G 16
0
A
C
–5
—
TABLE 20
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
Qimonda Module Prefix
HYS
Constant
2
Module Data Width [bit]
64
Non-ECC
72
ECC
3
DRAM Technology
T
DDR2
4
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
64
512 MByte
128
1 GByte
256
2 GByte
512
4 GByte
5
Raw Card Generation
0 .. 9
Look up table
6
Number of Module Ranks
0, 2, 4
1, 2, 4
7
Product Variations
0 .. 9
Look up table
8
Package, Lead-Free Status
A .. Z
Look up table
9
Module Type
D
SO-DIMM
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
M
Micro-DIMM
R
Registered
U
Unbuffered
F
Fully Buffered
28
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Field
Description
Values
Coding
10
Speed Grade
–2.5F
PC2–6400 5–5–5
–2.5
PC2–6400 6–6–6
11
Die Revision
–3
PC2–5300 4–4–4
–3S
PC2–5300 5–5–5
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
–A
First
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 21
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
Qimonda Component Prefix
HYB
Constant
Interface Voltage [V]
18
SSTL_18
3
DRAM Technology
T
DDR2
4
Component Density [Mbit]
256
256 Mbit
512
512 Mbit
1G
1 Gbit
2G
2 Gbit
40
×4
80
×8
16
×16
0 .. 9
Look up table
5+6
Number of I/Os
7
Product Variations
8
Die Revision
9
10
Package, Lead-Free Status
Speed Grade
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
A
First
B
Second
C
FBGA, lead-containing
F
FBGA, lead-free
–25F
DDR2-800 5-5-5
–2.5
DDR2-800 6-6-6
–3
DDR2-667 4-4-4
–3S
DDR2-667 5-5-5
–3.7
DDR2-533 4-4-4
–5
DDR2-400 3-3-3
29
Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
15
15
16
18
19
4
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Rev. 1.0, 2007-04
04242007-NQ2Z-YM3O
30
Internet Data Sheet
Edition 2007-04
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
www.qimonda.com