ADS1204 www.ti.com........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009 Four 1-Bit, 10MHz, 2nd-Order Delta-Sigma Modulators FEATURES 1 • 16-Bit Resolution • 14-Bit Linearity • Resolution/Speed Trade-Off: 10-Bit Effective Resolution with 10µs Signal Delay (12-Bit with 19µs) • ±2.5V Input Range at 2.5V • Internal Reference Voltage: 2% • Gain Error: 0.5% • Four Independent Delta-Sigma Modulators • Four Input Reference Buffers • Onboard 20MHz Oscillator • Selectable Internal or External Clock • Operating Temperature Range: –40°C to +105°C • QFN-32 (5×5) Package 2 APPLICATIONS • • • • • • • • Motor Control Current Measurement Industrial Process Control Instrumentation Smart Transmitters Portable Instruments Weight Scales Pressure Transducers DESCRIPTION The ADS1204 is a four-channel, high-performance device, with four delta-sigma (ΔΣ) modulators with 100dB dynamic range, operating from a single +5V supply. The differential inputs are ideal for direct connection to transducers in an industrial environment. With the appropriate digital filter and modulator rate, the device can be used to achieve 16-bit analog-to-digital (A/D) conversion with no missing code. Effective resolution of 12 bits can be obtained with a digital filter data rate of 160kHz at a modulator rate of 10MHz. The ADS1204 is designed for use in medium- to high-resolution measurement applications including current measurements, smart transmitters, industrial process control, weight scales, chromatography, and portable instrumentation. It is available in a QFN-32 (5×5) package. AVDD CH A+ CH A- 2nd-Order DS Modulator BVDD OUT A Output Interface Circuit REFIN A OUT B OUT C OUT D CLKOUT CH B+ CH B- 2nd-Order DS Modulator REFIN B Divider CH C+ CH C- 2nd-Order DS Modulator Clock Select REFIN C CH D+ CH D- 2nd-Order DS Modulator CLKSEL EN RC Oscillator 20MHz REFIN D REFOUT Out CLKIN Reference Voltage 2.5V AGND BGND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2009, Texas Instruments Incorporated ADS1204 SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009........................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) MAXIMUM GAIN ERROR (%) PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS1204 ±3 ±0.5 QFN-32 RHB –40°C to +105°C ADS1204I (1) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS1204IRHBT Tape and Reel, 250 ADS1204IRHBR Tape and Reel, 3000 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Supply voltage, AVDD to AGND Supply voltage, BVDD to BGND ADS1204 UNIT –0.3 to 6 V –0.3 to 6 V Analog input voltage with respect to AGND AGND – 0.3 to AVDD + 0.3 V Reference input voltage with respect to AGND AGND – 0.3 to AVDD + 0.3 V Digital input voltage with respect to BGND BGND – 0.3 to BVDD + 0.3 V ±0.3 V Ground voltage difference, AGND to BGND Voltage differences, BVDD to AGND Input current to any pin except supply Power dissipation –0.3 to 6 V ±10 mA See Dissipation Ratings table Operating virtual junction temperature range, TJ –40 to +150 °C Storage temperature range, TSTG –65 to +150 °C 260 °C Lead temperature (1.6mm or 1/16″ from case for 10s) (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS PARAMETER MIN NOM MAX UNIT Supply voltage, AVDD to AGND 4.75 5 5.25 V 3.6 V Supply voltage, BVDD to BGND Low-voltage levels 2.7 5V logic levels 4.5 5 5.5 V 0.5 2.5 2.6 V AVDD V Reference input voltage Operating common-mode signal Analog inputs 0 +IN – (–IN) 0 ±REFIN V 24 MHz –40 +125 °C –40 +105 °C External clock (1) 16 Operating free-air temperature range, TA Specified free-air temperature range, TA (1) 2 20 With reduced accuracy, clock can go from 1MHz up to 32MHz; see Typical Characteristic curves. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 ADS1204 www.ti.com........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009 DISSIPATION RATINGS (1) PACKAGE TA ≤ +25°C POWER RATING DERATING FACTOR ABOVE TA = +25°C (1) TA = +70°C POWER RATING TA = +85°C POWER RATING TA = +105°C POWER RATING QFN-32 (5×5) 3406mW 27.25mW/°C 2180mW 1771mW 1226mW This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). Thermal resistances are not production tested and are for informational purposes only. ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at –40°C to +105°C, AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x– = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted. ADS1204 PARAMETER TEST CONDITIONS RESOLUTION MIN TYP (1) MAX 16 UNIT Bits DC ACCURACY Integral linearity error (2) INL ±1 ±3 ±0.001 ±0.005 ±6 Integral linearity match DNL Differential nonlinearity (3) VOS Input offset error ±0.009 –1.4 Input offset error match TCVOS Input offset error drift GERR Gain error (4) Referenced to VREF Gain error match TCGERR Gain error drift PSRR Power-supply rejection ratio 4.75V < AVDD < 5.25V LSB % FSR LSB % FSR ±1 LSB ±3 mV ±2 mV ±2 ±8 µV/°C ±0.08 ±0.5 % FSR ±0.185 ±0.5 % FSR ±2 ppm/°C 78 dB ANALOG INPUT FSR Full-scale differential range (CH x+) – (CH x–); CH x– = 2.5V Specified differential range (CH x+) – (CH x–); CH x– = 2.5V Maximum operating input range (3) 0 Input capacitance Common-mode Input leakage current CLK turned off ±2.5 V ±2 V AVDD 1.5 V pF ±1 nA Differential input resistance 100 Differential input capacitance 2.5 pF At DC 100 dB VIN = ±1.25VPP at 40kHz 110 dB 50 MHz CMRR Common-mode rejection ratio BW Bandwidth FS sine wave, –3dB kΩ SAMPLING DYNAMICS CLKIN (1) (2) (3) (4) Internal clock frequency CLKSEL = 1 8 10 12 MHz External clock frequency CLKSEL = 0 1 20 24 MHz All typical values are at TA = +25°C. Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for CH x+ = –2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V). Specified by design. Maximum values, including temperature drift, are specified over the full specified temperature range. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 3 ADS1204 SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009........................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range at –40°C to +105°C, AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x– = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted. ADS1204 PARAMETER TYP (1) MAX UNIT VIN = ±2VPP at 5kHz; –40°C ≤ TA ≤ +85°C –96 –88 dB VIN = ±2VPP at 5kHz; –40°C ≤ TA ≤ +105°C –96 –87 dB TEST CONDITIONS MIN AC ACCURACY THD Total harmonic distortion SFDR Spurious-free dynamic range VIN = ±2VPP at 5kHz 92 100 dB SNR Signal-to-noise ratio VIN = ±2VPP at 5kHz 86 89 dB SINAD Signal-to-noise + distortion VIN = ±2VPP at 5kHz 85 89 dB Channel-to-channel isolation (5) VIN = ±2VPP at 50kHz 85 dB 14.5 Bits ENOB Effective number of bits 14 VOLTAGE REFERENCE OUTPUT VOUT Reference voltage output dVOUT/dT Output voltage temperature drift Output voltage noise 2.450 2.5 2.550 V ±20 ppm/°C f = 0.1Hz to 10Hz, CL = 10µF 10 µVrms f = 10Hz to 10kHz, CL = 10µF 12 µVrms 60 dB PSRR Power-supply rejection ratio IOUT Output current 10 µA ISC Short-circuit current 0.5 mA 100 µs Turn-on settling time to 0.1% at CL = 0 VOLTAGE REFERENCE INPUT VIN Reference voltage input 0.5 Reference input resistance Reference input capacitance 2.5 2.6 V 100 MΩ 5 pF Reference input current 1 µA V DIGITAL INPUTS (6) Logic family CMOS with Schmitt Trigger VIH High-level input voltage 0.7 × BVDD BVDD + 0.3 VIL Low-level input voltage –0.3 0.3 × BVDD V IIN Input current ±50 nA CI Input capacitance VI = BVDD or GND 5 pF DIGITAL OUTPUTS (6) Logic family CMOS VOH High-level output voltage BVDD = 4.5V, IOH = –100µA VOL Low-level output voltage BVDD = 4.5V, IOL = +100µA CO Output capacitance CL Load capacitance 4 V 0.5 5 V pF 30 Data format (5) (6) 4.44 pF Bit stream Specified by design. Applicable for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 ADS1204 www.ti.com........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range at –40°C to +105°C, AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x– = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted. ADS1204 PARAMETER DIGITAL INPUTS TEST CONDITIONS MIN TYP (1) MAX UNIT (7) Logic family LVCMOS VIH High-level input voltage BVDD = 3.6V 2 BVDD + 0.3 VIL Low-level input voltage BVDD = 2.7V –0.3 0.8 V IIN Input current VI = BVDD or GND ±50 nA CI Input capacitance DIGITAL OUTPUTS 5 V pF (7) Logic family LVCMOS VOH High-level output voltage BVDD = 2.7V, IOH = –100µA VOL Low-level output voltage BVDD = 2.7V, IOL = +100µA CO Output capacitance CL Load capacitance BVDD – 0.2 V 0.2 5 Data format V pF 30 pF Bit stream POWER SUPPLY AVDD BVDD Analog supply voltage Buffer I/O supply voltage AIDD Analog operating supply current BIDD Buffer I/O operating supply current Power dissipation (7) 4.5 5.5 V Low-voltage levels 2.7 3.6 V 5V logic levels 4.5 5.5 V CLKSEL = 1 22.5 30 mA CLKSEL = 0 22.4 29 mA BVDD = 3V, CLKOUT = 10MHz 4 mA BVDD = 5V, CLKOUT = 10MHz 4 mA CLKSEL = 0 122 145 mW CLKSEL = 1 112.5 150 mW Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. EQUIVALENT INPUT CIRCUITS BVDD AVDD RON 650W C(SAMPLE) 1pF AIN DIN Diode Turn-On Voltage: 0.35V AGND BGND Equivalent Analog Input Circuit Equivalent Digital Input Circuit NOTE: The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 5 ADS1204 SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009........................................................................................................................................... www.ti.com PIN ASSIGNMENTS REFIN A REFIN B AGND AVDD REFOUT AVDD AGND NC 32 31 30 29 28 27 26 25 RHB PACKAGE(1) QFN-32 (TOP VIEW) CH A+ 1 24 OUT A CH A- 2 23 OUT B CH B+ 3 22 OUT C CH B- 4 21 OUT D CH C- 5 20 CLKOUT CH C+ 6 19 BGND CH D- 7 18 BVDD CH D+ 8 17 CLKIN 9 10 11 12 13 14 15 16 REFIN D REFIN C AGND AVDD NC AVDD AGND CLKSEL ADS1204 (1) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O (1) CH A+ 1 AI Analog input of channel A: noninverting input CH A– 2 AI Analog input of channel A: inverting input CH B+ 3 AI Analog input of channel B: noninverting input CH B– 4 AI Analog input of channel B: inverting input CH C– 5 AI Analog input of channel C: inverting input CH C+ 6 AI Analog input of channel C: noninverting input CH D– 7 AI Analog input of channel D: inverting input CH D+ 8 AI Analog input of channel D: noninverting input REFIN D 9 AI Reference voltage input of channel D: pin for external reference voltage REFIN C 10 AI Reference voltage input of channel C: pin for external reference voltage AGND 11 — Analog ground AVDD 12 P Analog power supply; nominal 5V NC 13 — No connection; this pin is left unconnected AVDD 14 P Analog power supply; nominal 5V AGND 15 — Analog ground CLKSEL 16 I Clock select between internal clock (CLKSEL = 1) or external clock (CLKSEL = 0) CLKIN 17 I External clock input BVDD 18 P Digital interface power supply; from 2.7V to 5.5V BGND 19 — Interface ground CLKOUT 20 O System clock output (1) 6 DESCRIPTION AI = Analog Input; AO = Analog Output; I = Input; O = Output; P = Power Supply. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 ADS1204 www.ti.com........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O (1) OUT D 21 O Bit stream from channel D modulator OUT C 22 O Bit stream from channel C modulator OUT B 23 O Bit stream from channel B modulator OUT A 24 O Bit stream from channel A modulator NC 25 — No connection; this pin is left unconnected AGND 26 — Analog ground AVDD 27 P Analog power supply; nominal 5V REFOUT 28 AO AVDD 29 P Analog power supply; nominal 5V AGND 30 — Analog ground REFIN B 31 AI Reference voltage input of channel B: pin for external reference voltage REFIN A 32 AI Reference voltage input of channel A: pin for external reference voltage DESCRIPTION Reference voltage output: output pin of the internal reference source; nominal 2.5V Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 7 ADS1204 SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009........................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION tC1 CLKIN tW1 tC2 tD1 tD2 CLKOUT tD3 tW2 tD4 OUT x Figure 1. ADS1204 Timing Diagram TIMING REQUIREMENTS: 5.0V (1) Over recommended operating free-air temperature range at –40°C to +105°C, AVDD = 5V, and BVDD = 5V, unless otherwise noted. PARAMETER MIN MAX UNIT 41.6 1000 ns CLKIN high time 10 tC1 – 10 ns CLKOUT period using internal oscillator (CLKSEL = 1) 83 125 ns tC1 CLKIN period tW1 tC2 CLKOUT period using external clock (CLKSEL = 0) tW2 CLKOUT high time tD1 tD2 tD3 tD4 (1) 2 × tC1 ns (tC2/2) – 5 (tC2/2) + 5 ns CLKOUT rising edge delay after CLKIN rising edge 0 10 ns CLKOUT falling edge delay after CLKIN rising edge 0 10 ns Data valid delay after rising edge of CLKOUT (CLKSEL = 1) (tC2/4) – 8 (tC2/4) + 8 ns Data valid delay after rising edge of CLKOUT (CLKSEL = 0) tW1 – 3 tW1 + 7 ns Applicable for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 1. TIMING REQUIREMENTS: 3.0V (1) Over recommended operating free-air temperature range at –40°C to +105°C, AVDD = 5V, and BVDD = 5V, unless otherwise noted. PARAMETER tC1 CLKIN period tW1 CLKIN high time tC2 CLKOUT period using internal oscillator (CLKSEL = 1) CLKOUT period using external clock (CLKSEL = 0) tW2 CLKOUT high time tD1 tD2 tD3 tD4 (1) 8 MIN MAX UNIT 41.6 1000 ns 10 tC1 – 10 ns 83 125 ns 2 × tC1 ns (tC2/2) – 5 (tC2/2) + 5 ns CLKOUT rising edge delay after CLKIN rising edge 0 10 ns CLKOUT falling edge delay after CLKIN rising edge 0 10 ns Data valid delay after rising edge of CLKOUT (CLKSEL = 1) (tC2/4) – 8 (tC2/4) + 8 ns Data valid delay after rising edge of CLKOUT (CLKSEL = 0) tW1 – 3 tW1 + 7 ns Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 1. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 ADS1204 www.ti.com........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009 TYPICAL CHARACTERISTICS AVDD = 5V, BVDD = 3V, CH x+ = +0.5V to +4.5V, CH x– = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. INTEGRAL NONLINEARITY vs INPUT SIGNAL (CLKIN = 20MHz) INTEGRAL NONLINEARITY vs INPUT SIGNAL (CLKIN = 32MHz) 1.0 1.0 0.5 0.5 INL (LSB) 1.5 INL (LSB) 1.5 0 -0.5 -0.5 +25°C -40°C +85°C -1.0 -1.5 -2.0 -1.5 +105°C +125°C -1.0 -1.0 -0.5 0 0.5 1.0 Differential Input Voltage (V) 1.5 +105°C +125°C -1.0 -0.5 0 0.5 1.0 Differential Input Voltage (V) -1.5 INTEGRAL LINEARITY MATCH OF CHANNELS vs INPUT SIGNAL MAXIMUM INTEGRAL NONLINEARITY vs TEMPERATURE 0.3 0.00046 1.2 0 -0.1 -0.00015 -0.2 -0.00031 -0.3 -0.00046 -1.5 -1.0 -0.5 0 0.5 1.0 Differential Input Voltage (V) External 20MHz Clock INL (LSB) CLKIN = 20MHz INL (%) 0.00015 0.1 0.9 0.6 External 32MHz Clock 0.3 -0.00061 2.0 1.5 0 -40 -25 -10 5 Figure 4. 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 5. OFFSET vs TEMPERATURE OFFSET MATCH vs TEMPERATURE -1.20 0.45 -1.25 0.44 0.43 -1.30 Offset Match (mV) Offset Voltage (mV) 2.0 1.5 0.00031 CLKIN = 32MHz -1.35 1.5 Figure 3. 0.00061 -0.4 -2.0 +25°C -40°C +85°C Figure 2. 0.2 INL (LSB) -1.5 -2.0 2.0 0.4 0 0 External 20MHz Clock -1.40 -1.45 External 32MHz Clock -1.50 -1.60 -40 -25 -10 0.41 0.40 0.39 0.38 0.37 -1.55 External 20MHz Clock 0.42 External 32MHz Clock 0.36 5 20 35 50 65 Temperature (°C) 80 95 110 125 0.35 -40 -25 -10 Figure 6. 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 7. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 9 ADS1204 SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009........................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD = 5V, BVDD = 3V, CH x+ = +0.5V to +4.5V, CH x– = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. OFFSET vs POWER SUPPLY INTERNAL REFERENCE vs TEMPERATURE 2.530 -1.2 2.528 Reference Voltage (V) Offset (mV) -1.3 CLKIN = 20MHz -1.4 -1.5 CLKIN = 32MHz 2.526 2.524 2.522 2.520 2.518 2.516 2.514 -1.6 2.512 -1.7 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 2.510 -40 -25 -10 5.5 5 Power Supply (V) 20 35 50 65 Temperature (°C) Figure 8. 0.9 0.23 0.8 0.22 0.7 0.6 0.5 External 32MHz Clock 0.3 0.21 0.20 External 32MHz Clock 0.19 0.18 0.17 0.2 External 20MHz Clock External 20MHz Clock 0.1 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 0.16 95 0.15 -40 -25 -10 110 125 5 Figure 10. SNR vs TEMPERATURE 80 95 110 125 95 110 125 SINAD vs TEMPERATURE 89.2 CLKIN = 32MHz Signal-to-Noise + Distortion (dB) 89.4 Signal-to-Noise Ratio (dB) 20 35 50 65 Temperature (°C) Figure 11. 89.5 CLKIN = 32MHz 89.3 89.2 89.1 89.0 CLKIN = 20MHz 88.9 88.8 88.7 4VPP 5kHz 88.5 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 89.0 88.8 88.6 CLKIN = 20MHz 88.4 88.2 88.0 87.8 4VPP 5kHz 87.6 -40 -25 -10 Figure 12. 10 110 125 GAIN MATCH vs TEMPERATURE 0.24 Gain Match (%) Gain Error (%) GAIN ERROR vs TEMPERATURE 88.6 95 Figure 9. 1.0 0.4 80 5 20 35 50 65 Temperature (°C) 80 Figure 13. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 ADS1204 www.ti.com........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009 TYPICAL CHARACTERISTICS (continued) AVDD = 5V, BVDD = 3V, CH x+ = +0.5V to +4.5V, CH x– = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. THD vs TEMPERATURE SFDR vs TEMPERATURE 105 Spurious-Free Dynamic Range (dB) Total Harmonic Distortion (dB) -85 -87 -89 -91 CLKIN = 20MHz -93 -95 -97 -99 CLKIN = 32MHz -101 4VPP 5kHz -103 -105 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 103 CLKIN = 32MHz 101 99 CLKIN = 20MHz 97 95 93 91 89 4VPP 5kHz 87 85 -40 -25 -10 110 125 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 14. Figure 15. SFDR AND THD vs INPUT FREQUENCY (CLKIN = 20MHz) SFDR AND THD vs INPUT FREQUENCY (CLKIN = 32MHz) 120 120 -120 -120 SFDR 110 -110 110 -100 100 -110 -90 -100 THD 90 -90 80 -80 80 -80 70 -70 70 -70 -60 100 60 60 10 Frequency (kHz) 1 -60 100 10 Frequency (kHz) Figure 16. Figure 17. FREQUENCY SPECTRUM (4096 Point FFT, fIN = 1kHz, 4VPP) FREQUENCY SPECTRUM (4096 Point FFT, fIN = 5kHz, 4VPP) 0 0 -20 -20 -40 -40 Magnitude (dB) Magnitude (dB) 1 -60 -80 -100 -120 -60 -80 -100 -120 -140 -140 -160 -160 -180 THD (dB) THD 90 SFDR (dB) 100 THD (dB) SFDR (dB) SFDR -180 0 2 4 6 8 10 12 14 16 18 19 0 Frequency (kHz) 2 4 6 8 10 12 14 16 18 19 Frequency (kHz) Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 11 ADS1204 SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009........................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD = 5V, BVDD = 3V, CH x+ = +0.5V to +4.5V, CH x– = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. ANALOG POWER-SUPPLY CURRENT vs TEMPERATURE ENOB vs DECIMATION RATIO 18 30 110 3 Sinc Filter 16 External 32MHz Clock 98 27 12 74 2 Sinc Filter 10 62 8 50 6 38 Current (mA) 86 SNR (dB) ENOB (Bits) 14 24 21 External 20MHz Clock Internal Clock 18 4 10 26 10k 100 1k Decimation Ratio (OSR) 15 -40 -25 -10 5 Figure 20. 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 21. CMRR vs FREQUENCY PSRR vs FREQUENCY 110 110 105 100 100 PSRR (dB) CMRR (dB) 95 90 85 80 90 80 70 75 70 60 65 50 100 60 1 10 Input Frequency (kHz) 100 1k 10k Frequency of Power Supply (Hz) Figure 22. 100k Figure 23. CLOCK FREQUENCY vs TEMPERATURE CLOCK FREQUENCY vs POWER SUPPLY 10.0 9.8 9.8 9.7 9.4 CLKOUT (MHz) Frequency (MHz) 9.6 9.2 9.0 8.8 8.6 8.4 9.6 9.5 9.4 9.3 8.2 8.0 -40 -25 -10 9.2 5 20 35 50 65 Temperature (°C) 80 95 110 125 4.5 Figure 24. 12 4.7 4.9 5.1 Power Supply (V) 5.3 5.5 Figure 25. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 ADS1204 www.ti.com........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009 GENERAL DESCRIPTION The ADS1204 is a four-channel, second-order, CMOS device with four delta-sigma (ΔΣ) modulators, designed for medium- to high-resolution A/D signal conversions from dc to 39kHz (filter response –3dB) if an oversampling ratio (OSR) of 64 is chosen. The output of the converter (OUTX) provides a stream of digital ones and zeros. The time average of this serial output is proportional to the analog input voltage. The modulator shifts the quantization noise to high frequencies. A low-pass digital filter should be used at the output of the ΔΣ modulator. The filter serves two functions. First, it filters out high-frequency noise. Second, the filter converts the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). An application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA) could be used to implement the digital filter. Figure 26 and Figure 27 show typical application circuits with the ADS1204 connected to an FPGA. The overall performance (that is, speed and accuracy) depends on the selection of an appropriate OSR and filter type. A higher OSR produces greater output accuracy while operating at a lower refresh rate. Alternatively, a lower OSR produces lower output accuracy, but operates at a higher refresh rate. This system allows flexibility with the digital filter design and is capable of A/D conversion results that have a dynamic range exceeding 100dB with an OSR equal to 256. 2 kW 5kW AVDD +5V ±5V BVDD 27W 0.1mF CH A+ OPA4350 0.1nF 5kW CH A- OUT A 2nd-Order DS Modulator Output Interface Circuit 2kW REFIN A OUT B OUT C OUT D CLKOUT 2kW 5kW CH B+ CH B- +5V ±5V 0.1mF REFIN B OPA4350 Divider 0.1nF 5kW CH C+ 2kW CH C- 2nd-Order DS Modulator Clock Select REFIN C 2kW 5kW CH D+ +5V ±5V CH D- 27W 0.1mF 5kW REFOUT 2kW +3V CLKSEL AVDD Out Reference Voltage 2.5V +5V EN RC Oscillator 20MHz REFIN D 2kW CLKIN +5V 2nd-Order DS Modulator OPA4350 0.1nF 5kW +3V BVDD BGND 27W 0.1mF 2nd-Order DS Modulator FPGA or ASIC AVDD AVDD +5V +5V AVDD AGND AGND AGND AGND 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF +5V ±5V 27W 0.1mF OPA4350 +5V 0.1nF 5kW 2kW OPA336 0.1mF Figure 26. Single-Ended Connection Diagram for the ADS1204 ΔΣ Modulator Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 13 ADS1204 SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009........................................................................................................................................... www.ti.com +5V 27W R1 OPA4354 IN+ 0.1nF R2 +5V 27W R1 OPA4354 INR2 AVDD +5V BVDD 27W R1 CH A+ OPA4354 IN+ CH A- 0.1nF 2nd-Order DS Modulator R2 OUT A Output Interface Circuit REFIN A OUT D CLKOUT +5V CH B+ 27W R1 OUT B OUT C CH B- OPA4354 2nd-Order DS Modulator FPGA or ASIC +3V BVDD 0.1mF BGND INREFIN B R2 Divider CH C+ +5V CH C- 2nd-Order DS Modulator 27W R1 OPA4354 Clock Select REFIN C IN+ 0.1nF R2 CH D+ CH D- OPA4354 INREFOUT R2 +5V AVDD Out Reference Voltage 2.5V +5V EN RC Oscillator 20MHz REFIN D 27W CLKSEL +5V 2nd-Order DS Modulator +5V R1 +3V CLKIN AVDD AVDD +5V +5V AVDD AGND AGND AGND AGND 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF 27W R1 OPA4354 IN+ 0.1nF R2 +5V 27W R1 +5V OPA4354 INR2 OPA336 0.1mF Figure 27. Differential Connection Diagram for the ADS1204 ΔΣ Modulator 14 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 ADS1204 www.ti.com........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009 THEORY OF OPERATION The differential analog input of the ADS1204 is implemented with a switched-capacitor circuit. This circuit implements a second-order modulator stage, which digitizes the analog input signal into a 1-bit output stream. The clock source can be internal as well as external. Different frequencies for this clock allow for a variety of solutions and signal bandwidths. Every analog input signal is continuously sampled by the modulator and compared to a reference voltage that is applied to the REFINx pin. A digital stream, which accurately represents the analog input voltage over time, appears at the output of the corresponding converter. ANALOG INPUT STAGE Analog Input The topology of the analog inputs of ADS1204 is based on fully differential switched-capacitor architecture. This input stage provides the mechanism to achieve low system noise, high common-mode rejection (100dB), and excellent power-supply rejection. which is also the sampling frequency of the modulator. Figure 28 shows the basic input structure of one channel of the ADS1204. The relationship between the input impedance of the ADS1204 and the modulator clock frequency is shown in Equation 1: 100kW ZIN = fMOD/10MHz (1) The input impedance becomes a consideration in designs where the source impedance of the input signal is high. This high impedance may cause degradation in gain, linearity, and THD. The importance of this effect depends on the desired system performance. There are two restrictions on the analog input signals, CH x+ and CH x–. If the input voltage exceeds the range (GND – 0.3V) to (VDD + 0.3V), the input current must be limited to 10mA because the input protection diodes on the front end of the converter will begin to turn on. In addition, the linearity and the noise performance of the device are ensured only when the differential analog voltage resides within ±2V (with VREF as a midpoint); however, the FSR input voltage is ±2.5V. The input impedance of the analog input is dependent on the modulator clock frequency (fCLK), 650W AIN+ 1.2pF 0.4pF High Impedance > 1GW VCM Switching Frequency = CLK 0.4pF 650W 1.2pF AIN- High Impedance > 1GW Figure 28. Input Impedance of the ADS1204 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 15 ADS1204 SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009........................................................................................................................................... www.ti.com Modulator The ADS1204 can be operated in two modes. When CKLSEL = 1, the four modulators operate using the internal clock, which is fixed at 20MHz. When CKLSEL = 0, the modulators operate using an external clock . In both modes, the clock is divided by two internally and functions as the modulator clock. The frequency of the external clock can vary from 1MHz to 32MHz to adjust for the clock requirements of the application. The modulator topology is fundamentally a second-order, switched-capacitor, ΔΣ modulator, such as the one conceptualized in Figure 29. The analog input voltage and the output of the 1-bit digital-to-analog converter (DAC) are differentiated, providing analog voltages at X2 and X3. The voltages at X2 and X3 are presented to their individual integrators. The output of these integrators progresses in a negative or positive direction. When the value of the signal at X4 equals the comparator reference voltage, the output of the comparator switches from negative to positive, or positive to negative, depending on its original state. When the output value of the comparator switches from high to low or vice versa, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage at X6, causing the integrators to progress in the opposite direction. The feedback of the modulator to the front end of the integrators forces the value of the integrator output to track the average of the input. DIGITAL OUTPUT A differential input signal of 0V will ideally produce a stream of ones and zeros that are high 50% of the time and low 50% of the time. A differential input of +2V produces a stream of ones and zeros that are high 80% of the time. A differential input of –2V produces a stream of ones and zeros that are high 20% of the time. The input voltage versus the output modulator signal is shown in Figure 30. fCLK X(t) X2 X3 Integrator 1 Integrator 2 X4 DATA fS VREF Comparator X6 D/A Converter Figure 29. Block Diagram of the Second-Order Modulator Modulator Output +FS (Analog Input) -FS (Analog Input) Analog Input Figure 30. Analog Input vs Modulator Output of the ADS1204 16 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 ADS1204 www.ti.com........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009 DIGITAL INTERFACE INTRODUCTION The analog signal connected to the input of the ΔΣ modulator is converted using the clock signal applied to the modulator. The result of the conversion, or modulation, is generated and sent to the OUTx pin from the ΔΣ modulator. In most applications where a direct connection is realized between the ΔΣ modulator and an ASIC or FPGA (each with an implemented filter), the two standard signals per modulator (CLKOUT and OUTx) are provided from the modulator. The output clock signal is equal for all four modulators. If CLKSEL = 1, CLKIN must always be set either high or low. frequency of output data rate fDATA = fCLK/OSR. The –3dB point is located at half the Nyquist frequency or fDATA/4. For some applications, it may be necessary to use another filter type for better frequency response. This performance can be improved, for example, by a cascaded filter structure. The first decimation stage can be a Sinc3 filter with a low OSR and the second stage a high-order filter. For more information, see application note SBAA094, Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications, available for download at www.ti.com. 0 MODES OF OPERATION -20 Gain (dB) The system clock of the ADS1204 is 20MHz by default. The system clock can be provided either from the internal 20MHz RC oscillator or from an external clock source. For this purpose, the CLKIN pin is provided; it is controlled by the mode setting, CLKSEL. The system clock is divided by two for the modulator clock. Therefore, the default clock frequency of the modulator is 10MHz. With a possible external clock range of 1MHz to 32MHz, the modulator operates between 500kHz and 16MHz. The modulator generates only a bitstream, which does not output a digital word like an A/D converter. In order to output a digital word equivalent to the analog input voltage, the bitstream must be processed by a digital filter. A very simple filter, built with minimal effort and hardware, is the Sinc3 filter shown in Equation 2: H(z) = 1 - z-OSR 2 1 - z-1 -30 -40 -50 -60 -70 -80 0 200 400 600 800 1000 1200 1400 1600 Frequency (kHz) Figure 31. Frequency Response of Sinc3 Filter 30k OSR = 32 FSR = 32768 ENOB = 9.9 Bits Settling Time = 3 ´ 1/fDATA = 9.6ms 25k Output Code FILTER USAGE OSR = 32 fDATA = 10MHz/32 = 312.5kHz -3dB: 81.9kHz -10 20k 15k 10k (2) This filter provides the best output performance at the lowest hardware size (for example, a count of digital gates). For oversampling ratios in the range of 16 to 256, this is a good choice. All the characterizations in the data sheet are also done using a Sinc3 filter with an oversampling ratio of OSR = 256 and an output word width of 16 bits. In a Sinc3 filter response (shown in Figure 31 and Figure 32), the location of the first notch occurs at the 5k 0 0 5 10 15 20 25 30 35 40 Number of Output Clocks Figure 32. Pulse Response of Sinc3 Filter (fMOD = 10MHz) Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 17 ADS1204 SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009........................................................................................................................................... www.ti.com The effective number of bits (ENOB) can be used to compare the performance of A/D converters and ΔΣ modulators. Figure 33 shows the ENOB of the ADS1204 with different filter types. In this data sheet, the ENOB is calculated from the SNR as shown in Equation 3: SNR = 1.76dB + 6.02dB ´ ENOB (3) protection, filter types other than Sinc3 might be a better choice. A simple example is a Sinc2 filter. Figure 34 compares the settling time of different filter types. The Sincfast is a modified Sinc2 filter as Equation 4 shows: 1 - z-OSR H(z) = -1 1-z 16 Sinc (4) 10 12 Sinc 10 Sinc 9 2 Sincfast 7 8 6 Sinc Sincfast 3 8 ENOB (Bits) ENOB (Bits) (1 + z-2 ´ OSR) 3 14 4 Sinc 2 6 5 Sinc 4 3 2 2 0 1 10 100 1000 OSR 1 0 0 Figure 33. Measured ENOB vs OSR In motor control applications, a very fast response time for overcurrent detection is required. There is a constraint between 1µs and 5µs with 3 bits to 7 bits resolution. The time for full settling is dependent on the filter order. Therefore, the full settling of the Sinc3 filter needs three data clocks and the Sinc2 filter needs two data clocks. The data clock is equal to the modulator clock divided by the OSR. For overcurrent 18 2 2 4 6 Settling Time (ms) 8 10 Figure 34. Measured ENOB vs Settling Time For more information, see application note SBAA094, Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications, available for download at www.ti.com. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 ADS1204 www.ti.com........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009 LAYOUT CONSIDERATIONS POWER SUPPLIES DECOUPLING An applied external digital filter rejects high-frequency noise. PSRR and CMRR improve at higher frequencies because the digital filter suppresses high-frequency noise. Good decoupling practices must be used for the ADS1204 and for all components in the design. All decoupling capacitors, specifically the 0.1µF ceramic capacitors, must be placed as close as possible to the pin being decoupled. A 1µF and 10µF capacitor, in parallel with the 0.1µF ceramic capacitor, can be used to decouple AVDD to AGND as well as BVDD to BGND. At least one 0.1µF ceramic capacitor must be used to decouple every AVDD to AGND and BVDD to BGND, as well as for the digital supply on each digital component. However, the suppression of the filter is not infinite, so high-frequency noise still influences the conversion result. Inputs to the ADS1204, such as CH x+, CH x–, and CLKIN, should not be present before the power supply is on. Violating this condition could cause latch-up. If these signals are present before the supply is on, series resistors should be used to limit the input current to a maximum of 10mA. Experimentation may be the best way to determine the appropriate connection between the ADS1204 and different power supplies. GROUNDING Analog and digital sections of the design must be carefully and cleanly partitioned. Each section should have its own ground plane with no overlap between them. Do not join the ground planes; instead, connect the two with a moderate signal trace underneath the converter. However, for different applications with DSPs and switching power supplies, this process might be different. The digital supply sets the I/O voltage for the interface and can be set within a range of 2.7V to 5.5V. In cases where both the analog and digital I/O supplies share the same supply source, an RC filter of 10Ω and 0.1µF can be used to help reduce the noise in the analog supply. For multiple converters, connect the two ground planes as close as possible to one central location for all of the converters. In some cases, experimentation may be required to find the best point to connect the two planes together. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 19 ADS1204 SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009........................................................................................................................................... www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (August 2007) to Revision C ................................................................................................ Page • • • • • • • • • Updated document format ..................................................................................................................................................... Extended operating temperature range from +85°C to +105°C throughout document ......................................................... Deleted operating free-air temperature range row from Absolute Maximum Ratings table .................................................. Added free-air temperature range ratings to Recommended Operating Conditions table .................................................... Changed Dissipation Ratings table........................................................................................................................................ Changed typical specification in Input capacitance row of Analog Input section of Electrical Characteristics table ............. Added additional specification for Total Harmonic Distortion in AC Accuracy section of Electrical Characteristics table .... Deleted test condition of VOUT row in Voltage Reference Output section of Electrical Characteristics table ........................ Updated typical characteristic graphs to reflect extended temperature range ...................................................................... 1 1 2 2 3 3 3 3 9 Changes from Revision A (June 2004) to Revision B .................................................................................................... Page • 20 Added note to QFN package ................................................................................................................................................. 6 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS1204IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1204IRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1204IRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1204IRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1204IRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS1204IRHBT QFN RHB 32 250 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1204IRHBR QFN RHB 32 3000 338.1 338.1 20.6 ADS1204IRHBT QFN RHB 32 250 338.1 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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