TI1 LM555JAN Timer Datasheet

LM555JAN
LM555JAN Timer
Literature Number: SNOSAQ8B
LM555JAN
Timer
General Description
The LM555 is a highly stable device for generating accurate
time delays or oscillation. Additional terminals are provided
for triggering or resetting if desired. In the time delay mode of
operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator,
the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The
circuit may be triggered and reset on falling waveforms, and
the output circuit can source or sink up to 200mA or drive TTL
circuits.
Features
■ Direct replacement for SE555/NE555
■ Timing from microseconds through hours
■ Operates in both astable and monostable modes
■
■
■
■
■
Adjustable duty cycle
Output can source or sink 200 mA
Output and supply TTL compatible
Temperature stability better than 0.005% per °C
Normally on and normally off output
Applications
■
■
■
■
■
■
■
Precision timing
Pulse generation
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Linear ramp generator
Ordering Information
NS Part Number
JAN Part Number
JL555SPA
JM38510/10901SPA
NS Package Number
J08A
Package Description
8LD Ceramic Dip
JL555SGA
JM38510/10901SGA
H08A
8LD Metal Can
Connection Diagrams
Dual-In-Line Package
Metal Can Package
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Top View
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Top View
© 2010 National Semiconductor Corporation
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LM555JAN Timer
OBSOLETE
September 27, 2010
LM555JAN
Schematic Diagram
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LM555JAN
Absolute Maximum Ratings (Note 1)
Supply Voltage
Discharge Current
Output Sink Current
Output Source Current
Power Dissipation (Note 2)
Metal Can
CERDIP
Operating Temperature Range
+18V
+200mA
+200mA
−200mA
300mW @ +125°C
370mW @ +125°C
−55°C ≤ TA ≤ +125°C
+175°C
Maximum Junction Temperature (TJmax)
Storage Temperature Range
−65°C ≤ TA ≤ +150°C
300°C
Soldering Information (Soldering 10 Seconds)
Thermal Resistance
θJA
CERDIP Still Air
CERDIP 500LF / Min Air Flow
Metal Can Still Air
Metal Can 500LF / Min Air Flow
123°C/W
69°C/W
171°C/W
92°C/W
θJC
CERDIP
Metal Can
ESD Tolerance (Note 3)
18°C/W
41°C/W
1KV
Recommended Operating Conditions
Supply Voltage Range
+4.5V to +16VDC
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Temp °C
1
Static tests at
25
2
Static tests at
125
3
Static tests at
-55
4
Dynamic tests at
25
5
Dynamic tests at
125
6
Dynamic tests at
-55
7
Functional tests at
25
8A
Functional tests at
125
8B
Functional tests at
-55
9
Switching tests at
25
10
Switching tests at
125
11
Switching tests at
-55
12
Settling time at
25
13
Settling time at
125
14
Settling time at
-55
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LM555JAN
Electrical Characteristics
DC Parameters
Symbol
Parameter
ICC
Power Supply Current
VTrig
Trigger Voltage
Conditions
Notes
Min
VCC = 4.5V
VCC = 16.5V
VCC = 4.5V
VCC = 16.5V
Max
Unit
Subgroups
5.0
mA
1, 2, 3
20
mA
1, 2, 3
1.3
1.8
V
1
1.3
2.1
V
2
1.15
1.8
V
3
5.2
5.8
V
1
5.2
6.1
V
2
5.0
5.8
V
3
µA
1, 2, 3
ITrig
Trigger Current
VCC = 16.5V
-5.0
VTh
Threshold Voltage
VCC = 4.5V
2.7
3.3
V
1
2.6
3.4
V
2, 3
10.7
11.3
V
1
10.6
11.4
V
2, 3
250
nA
1, 2
2,500
nA
3
0.25
V
1
0.35
V
2, 3
2.2
V
1, 2
2.6
V
3
0.15
V
1, 3
0.25
V
2
0.5
V
1, 3
0.7
V
2
2.2
V
1
2.8
V
2, 3
2.6
V
1, 2
2.2
V
3
14.6
V
1, 2
14
V
3
1, 3
VCC = 16.5V
ITh
VOL
Threshold Current
VCC = 16.5V
Logical "0" Output Voltage
VCC = 4.5V, ISink = 5mA
VCC = 4.5V, ISink = 50mA
VCC = 16.5V, ISink = 10mA
VCC = 16.5V, ISink = 50mA
VCC = 16.5V, ISink = 100mA
VOH
Logical "1" Output Voltage
VCC = 4.5V, ISource = -100mA
VCC = 16.5V, ISource = -100mA
ICEX
Discharge Transistor Leakage
Current
VCC = 16.5V
VSat
Discharge Transistor Saturation
Voltage
VCC = 16.5V
VR
Reset Voltage
VCC = 16.5V
IR
Reset Current
VCC = 16.5V
(Note 4),
(Note 5)
0.1
100
nA
3,000
nA
2
0.8
V
1, 3
1.0
V
2
1.3
V
1, 2, 3
mA
1, 2, 3
Max
Unit
Subgroups
800
nS
9, 11
900
nS
10
800
nS
9, 11
900
nS
10
-1.6
AC Parameters
Symbol
tPLH
Parameter
Propagation Delay Time
Conditions
Notes
Min
VCC = 4.5V
VCC = 16.5V
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tPHL
tTLH
tTHL
tDOH
ΔtD / ΔVCC
Max
Unit
Subgroups
VCC = 4.5V
12
µS
9, 10, 11
VCC = 16.5V
12
µS
9, 10, 11
VCC = 4.5V
300
nS
9, 10, 11
VCC = 16.5V
300
nS
9, 10, 11
VCC = 4.5V
300
nS
9, 10, 11
VCC = 16.5V
300
nS
9, 10, 11
Parameter
Conditions
Propagation Delay Time
Transition Time
Transition Time
Notes
Min
Time Delay Output High
RT = 1KΩ
VCC = 4.5V
106.7 113.3
µS
9, 10, 11
VCC = 16.5V
106.7 113.3
µS
9, 10, 11
Time Delay Output High
RT = 100KΩ
VCC = 4.5V
10.67 11.33
mS
9, 10, 11
VCC = 16.5V
10.67 11.33
mS
9, 10, 11
Drift In Time Delay
ΔVCC = 12,
VCC = 4.5V to 16.5V
(Note 6)
-220
220
nS/V
9
-11
11
nS/°C
10, 11
ΔtD / ΔT
Temperature Coefficient of Time VCC = 16.5V
Delay
tCh
Capacitor Charge Time
RT = 1KΩ
VCC = 4.5V
120
156
µS
9, 10, 11
VCC = 16.5V
120
156
µS
9, 10, 11
Capacitor Charge Time
RT = 100KΩ
VCC = 4.5V
11.3
15
mS
9, 10, 11
VCC = 16.5V
11.3
15
mS
9, 10, 11
Capacitor Discharge Time
RT = 1KΩ
VCC = 4.5V
57.5
80
µS
9, 10, 11
VCC = 16.5V
57.5
80
µS
9, 10, 11
Capacitor Discharge Time
RT = 100KΩ
VCC = 4.5V
5.4
7.7
mS
9, 10, 11
VCC = 16.5V
5.4
7.7
mS
9, 10, 11
-820
820
nS/V
9
-68
68
nS/°C
10, 11
1.5
µS
9, 11
2.0
µS
10
Min
Max
Unit
Subgroups
tDis
ΔtCh / ΔVCC Drift In Capacitor Charge Time
ΔVCC = 12,
VCC = 4.5V to 16.5V
ΔtCh / ΔT
Temperature Coefficient
Capacitor Charge Time
VCC = 16.5V
tRes
Reset Time
VCC = 16.5V
(Note 6)
DC Drift Parameters
Delta calculations performed on JAN S devices at Group B, Subgroup 5, only.
Symbol
Parameter
Conditions
Notes
VTrig
Trigger Voltage
VCC = 16.5V
-0.05
0.05
V
1
VTh
Threshold Voltage
VCC = 16.5V
-0.05
0.05
V
1
VOL
Logical "0" Output Voltage
VCC = 16.5V, ISink = 10mA
-0.05
0.05
V
1
ICEX
Discharge Transistor Leakage
Current
VCC = 16.5V
-50
50
nA
1
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/
θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 3: Human body model, 1.5KΩ in series with 100pF.
Note 4: Parameter tested go-no-go, only.
Note 5: Datalog reading of 0.7V will reflect the Reset Voltage levels passing and a reading of 0.5V or 1.5V reflects the Reset voltage levels failing the low level
or high level respectfully.
Note 6: Calculated parameter.
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LM555JAN
Symbol
LM555JAN
Typical Performance Characteristics
Minimum Pulse Width
Required for Triggering
Supply Current vs.
Supply Voltage
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High Output Voltage vs.
Output Source Current
Low Output Voltage vs.
Output Sink Current
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Low Output Voltage vs.
Output Sink Current
Low Output Voltage vs.
Output Sink Current
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LM555JAN
Output Propagation Delay vs.
Voltage Level of Trigger Pulse
Output Propagation Delay vs.
Voltage Level of Trigger Pulse
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Discharge Transistor (Pin 7)
Voltage vs. Sink Current
Discharge Transistor (Pin 7)
Voltage vs. Sink Current
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LM555JAN
during this time by the application of a negative pulse to the
reset terminal (pin 4). The output will then remain in the low
state until a trigger pulse is again applied.
When the reset function is not in use, it is recommended that
it be connected to VCC to avoid any possibility of false triggering.
Figure 3 is a nomograph for easy determination of R, C values
for various time delays.
NOTE: In monostable operation, the trigger should be driven
high before the end of timing cycle.
Applications Information
MONOSTABLE OPERATION
In this mode of operation, the timer functions as a one-shot
(Figure 1). The external capacitor is initially held discharged
by a transistor inside the timer. Upon application of a negative
trigger pulse of less than 1/3 VCC to pin 2, the flip-flop is set
which both releases the short circuit across the capacitor and
drives the output high.
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20153707
FIGURE 1. Monostable
FIGURE 3. Time Delay
The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of which time the
voltage equals 2/3 VCC. The comparator then resets the flipflop which in turn discharges the capacitor and drives the
output to its low state. Figure 2 shows the waveforms generated in this mode of operation. Since the charge and the
threshold level of the comparator are both directly proportional to supply voltage, the timing interval is independent of
supply.
ASTABLE OPERATION
If the circuit is connected as shown in Figure 4 (pins 2 and 6
connected) it will trigger itself and free run as a multivibrator.
The external capacitor charges through RA + RB and discharges through RB. Thus the duty cycle may be precisely set
by the ratio of these two resistors.
20153706
VCC = 5V
TIME = 0.1 ms/DIV.
RA = 9.1kΩ
C = 0.01μF
Top Trace: Input 5V/Div.
Middle Trace: Output 5V/Div.
Bottom Trace: Capacitor Voltage 2V/Div.
20153708
FIGURE 4. Astable
FIGURE 2. Monostable Waveforms
In this mode of operation, the capacitor charges and discharges between 1/3 VCC and 2/3 VCC. As in the triggered
mode, the charge and discharge times, and therefore the frequency are independent of the supply voltage.
During the timing cycle when the output is high, the further
application of a trigger pulse will not effect the circuit so long
as the trigger input is returned high at least 10μs before the
end of the timing interval. However the circuit can be reset
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LM555JAN
Figure 5 shows the waveforms generated in this mode of operation.
20153711
VCC = 5V
Top Trace: Input 4V/Div.
TIME = 20μs/DIV. Middle Trace: Output 2V/Div.
RA = 9.1kΩ
Bottom Trace: Capacitor 2V/Div.
C = 0.01μF
20153709
VCC = 5V
TIME = 20μs/DIV.
RA = 3.9kΩ
RB = 3kΩ
C = 0.01μF
Top Trace: Output 5V/Div.
Bottom Trace: Capacitor Voltage 1V/Div.
FIGURE 7. Frequency Divider
PULSE WIDTH MODULATOR
When the timer is connected in the monostable mode and
triggered with a continuous pulse train, the output pulse width
can be modulated by a signal applied to pin 5. Figure 8 shows
the circuit, and in Figure 9 are some waveform examples.
FIGURE 5. Astable Waveforms
The charge time (output high) is given by:
t1 = 0.693 (RA + RB) C
And the discharge time (output low) by:
t2 = 0.693 (RB) C
Thus the total period is:
T = t1 + t2 = 0.693 (RA +2RB) C
The frequency of oscillation is:
Figure 6 may be used for quick determination of these RC
values.
The duty cycle is:
20153712
FIGURE 8. Pulse Width Modulator
20153713
VCC = 5V
Top Trace: Modulation 1V/Div.
TIME = 0.2 ms/DIV. Bottom Trace: Output Voltage 2V/Div.
RA = 9.1kΩ
C = 0.01μF
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FIGURE 6. Free Running Frequency
FIGURE 9. Pulse Width Modulator
FREQUENCY DIVIDER
The monostable circuit of Figure 1 can be used as a frequency
divider by adjusting the length of the timing cycle. Figure 7
shows the waveforms generated in a divide by three circuit.
PULSE POSITION MODULATOR
This application uses the timer connected for astable operation, as in Figure 10, with a modulating signal again applied
to the control voltage terminal. The pulse position varies with
the modulating signal, since the threshold voltage and hence
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LM555JAN
the time delay is varied. Figure 11 shows the waveforms generated for a triangle wave modulation signal.
20153716
FIGURE 12.
20153714
Figure 13 shows waveforms generated by the linear ramp.
The time interval is given by:
FIGURE 10. Pulse Position Modulator
VBE ≃ 0.6V
20153715
VCC = 5V
TIME = 0.1 ms/DIV.
RA = 3.9kΩ
RB = 3kΩ
C = 0.01μF
Top Trace: Modulation Input 1V/Div.
Bottom Trace: Output 2V/Div.
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VCC = 5V
Top Trace: Input 3V/Div.
TIME = 20μs/DIV. Middle Trace: Output 5V/Div.
R1 = 47kΩ
Bottom Trace: Capacitor Voltage 1V/Div.
R2 = 100kΩ
RE = 2.7 kΩ
C = 0.01 μF
FIGURE 11. Pulse Position Modulator
LINEAR RAMP
When the pull-up resistor, RA, in the monostable circuit is replaced by a constant current source, a linear ramp is generated. Figure 12 shows a circuit configuration that will perform
this function.
FIGURE 13. Linear Ramp
50% DUTY CYCLE OSCILLATOR
For a 50% duty cycle, the resistors RA and RB may be connected as in Figure 14. The time period for the output high is
the same as previous, t1 = 0.693 RA C. For the output low it
is t2 =
Thus the frequency of oscillation is
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ADDITIONAL INFORMATION
Adequate power supply bypassing is necessary to protect
associated circuitry. Minimum recommended is 0.1μF in parallel with 1μF electrolytic.
Lower comparator storage time can be as long as 10μs when
pin 2 is driven fully to ground for triggering. This limits the
monostable pulse width to 10μs minimum.
Delay time reset to output is 0.47μs typical. Minimum reset
pulse width must be 0.3μs, typical.
Pin 7 current switches within 30ns of the output (pin 3) voltage.
20153718
FIGURE 14. 50% Duty Cycle Oscillator
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LM555JAN
Note that this circuit will not oscillate if RB is greater than 1/2
RA because the junction of RA and RB cannot bring pin 2 down
to 1/3 VCC and trigger the lower comparator.
LM555JAN
Revision History
Date Released
Revision
Section
Changes
08/04/05
A
New Release to corporate format
1 MDS datasheet converted into corporate format.
MJLM555-X Rev 1A0 to be archived
07/25/06
B
Applications Information, page 8
Correct a typo in the paragraph after figure 1 (change
the word internal to interval) to reflect same change
made to Commercial data sheet. Revision A will be
Archived.
09/27/2010
C
Obsolete Data Sheet
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End Of Life on Product/NSID Sept. 1998
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LM555JAN
Physical Dimensions inches (millimeters) unless otherwise noted
8LD Ceramic Dip Package (J)
NS Package Number J08A
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LM555JAN
8LD Metal Can Package (H)
NS Package Number H08A
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LM555JAN
Notes
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LM555JAN Timer
Notes
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www.ti.com/audio
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Amplifiers
amplifier.ti.com
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www.ti.com/computers
Data Converters
dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
Energy and Lighting
www.ti.com/energy
DSP
dsp.ti.com
Industrial
www.ti.com/industrial
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Interface
interface.ti.com
Security
www.ti.com/security
Logic
logic.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and Automotive www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
www.ti.com/video
e2e.ti.com
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