LANSDALE MC145564P Pcm codec-filter Datasheet

ML145554
ML145564
ML145557
ML145567
PCM Codec–Filter
Legacy Device: Motorola MC145554, MC145557, MC145564, MC145567
The ML145554, ML145557, ML145564, and ML145567 are all per channel
PCM Codec–Filters. These devices perform the voice digitization and reconstruction as well as the band limiting and smoothing required for PCM systems. They are designed to operate in both synchronous and asynchronous
applications and contain an on–chip precision voltage reference. The
ML145554 (Mu–Law) and ML145557 (A–Law) are general purpose devices
that are offered in 16–pin packages. The ML145564 (Mu–Law) and
ML145567 (A–Law), offered in 20–pin packages, add the capability of analog
loopback and push–pull power amplifiers with adjustable gain.
These devices have an input operational amplifier whose output is the input
to the encoder section. The encoder section immediately low–pass filters the
analog signal with an active R–C filter to eliminate very–high–frequency noise
from being modulated down to the pass band by the switched capacitor filter.
From the active R–C filter, the analog signal is converted to a differential signal. From this point, all analog signal processing is done differentially. This
allows processing of an analog signal that is twice the amplitude allowed by a
single–ended design, which reduces the significance of noise to both the inverted and non–inverted signal paths. Another advantage of this differential design
is that noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This
dramatically improves the power supply rejection ratio.
After the differential converter, a differential switched capacitor filter bandpasses the analog signal from 200 Hz to 3400 Hz before the signal is digitizedby the differential compressing A/D converter.
The decoder accepts PCM data and expands it using a differential D/A converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X compensated by a differential switched capacitor filter. The signal is then filtered
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
These PCM Codec–Filters accept both long–frame and short–frame industry
standard clock formats. They also maintain compatibility with Motorola’s family of TSACs and MC3419/MC34120 SLIC products.
The ML145554/57/64/67 family of PCM Codec–Filters utilizes CMOS due
to its reliable low–power performance and proven capability for complex
analog/digital VLSI functions.
FEATURES
P DIP 16 = EP
PLASTIC DIP
CASE 648
ML145554/57
16
1
16
1
20
1
20
1
SOG 16 = -5P
SOG PACKAGE
CASE 751G
ML145554/57
P DIP 20 = RP
PLASTIC DIP
CASE 738
ML145564/67
SOG 20 = -6P
SOG PACKAGE
CASE 751D
ML145564/67
CROSS REFERENCE/ORDERING INFORMATION
LANSDALE
PACKAGE
MOTOROLA
P DIP 16
SO 16W
P DIP 16
SO 16W
P DIP 20
SO 20W
P DIP 20
SO 20W
MC145554P
MC145554DW
MC145557P
MC145557DW
MC145564P
MC145564DW
MC145567P
MC145567DW
ML145554EP
ML145554-5P
ML145557EP
ML145557-5P
ML145564RP
ML145564-6P
ML145567RP
ML145567-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
ML145554/57(16–Pin Package)
• Fully Differential Analog Circuit Design for Lowest Noise
• Performance Specified for Extended Temperature Range of – 40 to + 85°C
• Transmit Band–Pass and Receive Low–Pass Filters On–Chip
• Active R–C Pre–Filtering and Post–Filtering
• Mu–Law Companding ML145554
• A–Law Companding ML145557
• On–Chip Precision Voltage Reference (2.5 V)
• Typical Power Dissipation of 40 mW, Power Down of 1.0 mW at ±5 V
ML145564/67(20–Pin Package) — All of the Features of the ML145554/57 Plus:
• Mu–Law Companding ML145564
• A–Law Companding ML145567
• Push–Pull Power Drivers with External Gain Adjust
• Analog Loopback
Page 1 of 18
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PIN ASSIGNMENTS
ML145554, ML145557
ML145564, ML145567
VBB
1
16
VFXI +
VPO +
1
20
VBB
GNDA
2
15
VFXI –
GNDA
2
19
VFXI +
VFRO
3
14
GSX
VPO –
3
18
VFXI –
VCC
4
13
TSX
VPI
4
17
GSX
FSR
5
12
FSX
VFRO
5
16
ANLB
DR
6
11
DX
VCC
6
15
TSX
BCLKR/ CLKSEL
7
10
BCLKX
FSR
7
14
FSX
MCLKR/ PDN
8
9
MCLKX
DR
8
13
DX
BCLKR/ CLKSEL
9
12
BCLKX
10
11
MCLKX
MCLKR/ PDN
FUNCTIONAL BLOCK DIAGRAM
GSX
VFXI –
–
VFXI +
+
ANLB*
VCC
GNDA VBB
FSX
FSR MCLKX BCLKX
MCLKR/ BCLKR/
PDN
CLKSEL
INTERNAL SEQUENCING
AND CONTROL
RC ACTIVE
LOW–PASS
FILTER
5–POLE SC
LOW–PASS
FILTER
TSX
3–POLE
HIGH–PASS
AND S/H
COMP
VPO +
*
–1
BAND–GAP
VOLTAGE
REF
4
RDAC
8
SAR
REG
TRANSMIT
SHIFT
REG
DX
RECEIVE
LATCH
RECEIVE
SHIFT
REG
DR
CDAC
–
4
VPO –
*
+
VPI*
VFRO
MUX
8
RC ACTIVE
LOW–PASS
FILTER
5–POLE SC
LOW–PASS
FILTER
S/H
* ML145564 and ML145567 only.
Page 2 of 18
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ML145554, ML145557, ML145564, ML145567
DEVICE DESCRIPTION
A codec–filter is used for digitizing and reconstructing thehuman voice. These devices were developed primarily for the
telephone network to facilitate voice switching and transmission. Once the voice is digitized, it may be switched by digital
switching methods or transmitted long distance (T1,
microwave, satellites, etc.) without degradation. The name
codec is an acronym from “COder” (for the A/D used to digitize voice) and “DECoder” (for the D/A used for reconstructing voice). A codec is a single device that does both the A/D
and D/A conversions.
To digitize intelligible voice requires a signal–to–distortion
ratio of about 30 dB over a dynamic range of about 40 dB.
This can be accomplished with a linear 13–bit A/D and D/A,
but will far exceed the required signal–to–distortion ratio at
amplitudes greater than 40 dB below the peak amplitude. This
excess performance is at the expense of data per sample.
Methods of data reduction are implemented by compressing
the 13–bit linear scheme to companded 8–bit schemes. There
are two companding schemes used: Mu–255 Law specifically
in North America, and A–Law specifically in Europe. These
companding schemes are accepted world wide. These companding schemes follow a segmented or “piecewise–linear”
curve formatted as sign bit, three chord bits, and four step bits.
For a given chord, all sixteen of the steps have the same voltage weighting. As the voltage of the analog input increases, the
four step bits increment and carry to the three chord bits which
increment. When the chord bits increment, the step bits double
their voltage weighting. This results in an effective resolution
of six bits (sign + chord + four step bits) across a 42 dB
dynamic range (seven chords above zero, by 6 dB per chord).
Tables 3 and 4 show the linear quantization levels to PCM
words for the two companding schemes.
In a sampling environment, Nyquist theory says that to properly sample a continuous signal, it must be sampled at a frequency higher than twice the signal’s highest frequency component. Voice contains spectral energy above 3 kHz, but its
absence is not detrimental to intelligibility. To reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 kHz was adopted, consistent with a bandwidth of
3 kHz. This sampling requires a low–pass filter to limit the
high frequency energy above 3 kHz from distorting the
in–band signal. The telephone line is also subject to 50/60 Hz
power line coupling, which must be attenuated from the signal
by a high–pass filter before the A/D converter.
The D/A process reconstructs a staircase version of the
desired in–band signal, which has spectral images of the
in–band signal modulated about the sample frequency and its
harmonics. These spectral images, called aliasing components,
need to be attenuated to obtain the desired signal. The
low–pass filter used to attenuate these aliasing components is
typically called a reconstruction or smoothing filter.
The ML145554/57/64/67 PCM Codec–Filters have the
codec, both presampling and reconstruction filters, and a precision voltage reference on–chip, and require no external components.
Page 3 of 18
PIN DESCRIPTION
DIGITAL
FSR
Receive Frame Sync
This is an 8 kHz enable that must be synchronous with
BCLKR. Following a rising FSR edge, a serial PCM word at
DR is clocked by BCLKR into the receive data register. FSR
also initiates a decode on the previous PCM word. In the absence of FSX, the length of the FSR pulse is used to determine whether the I/O conforms to the Short Frame Sync or
Long Frame Sync convention.
DR
Receive Digital Data Input
BCLKR/CLKSEL
Receive Data Clock and Master Clock Frequency Selector
If this input is a clock, it must be between 128 kHz and
4.096 MHz, and synchronous with FSR. In synchronous applications this pin may be held at a constant level; then BCLKX
is used as the data clock for both the transmit and receive
sides, and this pin selects the assumed frequency of the master
clock (see Table 1 in Functional Description).
MCLKR/PDN
Receive Master Clock and Power–Down Control
Because of the shared DAC architecture used on these
devices, only one master clock is needed. Whenever FSX is
clocking, MCLKX is used to derive all internal clocks, and the
MCLKR/PDN pin merely serves as a power–down control. If
MCLKR/PDN pin is held low or is clocked (and at least one of
the frame syncs is present), the part is powered up. If this pin
is held high, the part is powered down. If FSX is absent but
FSR is still clocking, the device goes into receive half–channel
mode, and MCLKR (if clocking) generates the internal clocks.
MCLKX
Transmit Master Clock
This clock is used to derive the internal sequencing clocks; it
must be 1.536 MHz, 1.544 MHz, or 2.048 MHz.
BCLKX
Transmit Data Clock
BCLKX may be any frequency between 128 kHz and 4.096
MHz, but it should be synchronous with MCLKX.
DX
Transmit Digital Data Output
This output is controlled by FSX and BCLKX to output the
PCM data word; otherwise this pin is in a high–impedance state.
FSX
Transmit Frame Sync
This is an 8 kHz enable that must be synchronous
with BCLKX. A rising FSX edge initiates the transmission of a
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serial PCM word, clocked by BCLKX, out of DX. If the FSX
pulse is high for more than eight BCLKX periods, the DX and
TSX outputs will remain in a low–impedance state until FSX is
brought low. The length of the FSX pulse is used to determine
whether the transmit and receive digital I/O conforms to the
Short Frame Sync or to the Long Frame Sync convention.
TSX
Transmit Time Slot Indicator
This is an open–drain output that goes low whenever the DX
output is in a low–impedance state (i.e., during the transmit
time slot when the PCM word is being output) for enabling a
PCM bus driver.
ANLB
Analog Loopback Control Input (ML145564/67 Only)
When held high, this pin causes the input of the transmit RC
active filter to be disconnected from GSX and connected to
VPO+ for analog loopback testing. This pin is held low in
normal operation.
ANALOG
GSX
Gain–Setting Transmit
This output of the transmit gain–adjust operational amplifier is internally connected to the encoder section of the device.
It must be used in conjunction with VFXI– and VFXI+ to set
the transmit gain for a maximum signal amplitude of 2.5 V
peak. This output can drive a 600 Ω load to 2.5 V peak.
VFXI–
Voice–Frequency Transmit Input (Inverting)
This is the inverting input of the transmit gain–adjust
operational amplifier.
VFXI+
Voice–Frequency Transmit Input (Non–Inverting)
This is the non–inverting input of the transmit gain–adjust
operational amplifier.
VFRO
Voice–Frequency Receive Output
This receive analog output is capable of driving a 600 Ω load
to 2.5 V peak.
VPI
Voltage Power Input (ML145564/67 Only)
This is the inverting input to the first receive power amplifier. Both of the receive power amplifiers can be powered
down by connecting this input to VBB.
VPO–
Voltage Power Output (Inverted) (ML145564/67 Only)
This inverted output of the receive push–pull power amplifiers can drive 300 Ω to 3.3 V peak.
VPO+
Voltage Power Output (Non–Inverted) (ML145554/67 Only)
This non–inverted output of the receive push–pull power
Page 4 of 18
amplifier pair can drive 300 Ω to 3.3 V peak.
POWER SUPPLY
GNDA
Analog Ground
This terminal is the reference level for all signals, both analog and digital. It is 0 V.
VCC
Positive Power Supply
VCC is typically 5 V.
VBB
Negative Power Supply
VBB is typically – 5 V.
FUNCTIONAL DESCRIPTION
ANALOG INTERFACE AND SIGNAL PATH
The transmit portion of these codec–filters includes a
low–noise gain setting amplifier capable of driving a 600 Ω
load. Its output is fed to a three–pole anti–aliasing pre–filter.
This pre–filter incorporates a two–pole Butterworth active
low–pass filter, and a single passive pole. This pre–filter is
followed by a single ended–to–differential converter that is
clocked at 256 kHz. All subsequent analog processing utilizes fully differential circuitry. The next section is a
fully–differential, five–pole switched capacitor low–pass filter with a 3.4 kHz passband. After this filter is a 3–pole
switched–capacitor high–pass filter having a cutoff frequency of about 200 Hz. This high–pass stage has a transmission
zero at DC that eliminates any DC coming from the analog
input or from accumulated operational amplifier offsets in
the preceding filter stages. The last stage of the high–pass
filter is an autozeroed sample and hold amplifier.
One bandgap voltage reference generator and
digital–to–analog converter (DAC) are shared by the transmit
and receive sections. The autozeroed, switched–capacitor
bandgap reference generates precise positive and negative
reference voltages that are independent of temperature and
power supply voltage. A binary–weighted capacitor array
(CDAC) forms the chords of the companding structure,
while a resistor string (RDAC) implements the linear steps
within each chord. The encode process uses the DAC, the
voltage reference, and a frame–by–frame autozeroed comparator to implement a successive–approximation conversion
algorithm. All of the analog circuitry involved in the data
conversion the voltage reference, RDAC, CDAC, and comparator are implemented with a differential architecture.
The receive section includes the DAC described above,
asample and hold amplifier, a five–pole 3400 Hz switchedcapacitor low–pass filter with sinX/X correction, and a
two–pole active smoothing filter to reduce the spectral components of the switched capacitor filter. The output of the
smoothing filter is a power amplifier that is capable of driving a 600 Ω load. The ML145564 and ML145567 add a pair
of power amplifiers that are connected in a push–pull configuration; two external resistors set the gain of both of the
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complementary outputs. The output of the second amplifier may be
internally connected to the input of the transmit anti–aliasing filter by
bringing the ANLB pin high. The power amplifiers can drive unbalanced 300 Ω loads or a balanced 600 Ω load; they may be powered
down independent of the rest of the chip by tying the VPI pin to
VBB.
MASTER CLOCKS
Since the codec–filter design has a single DAC architecture, only
one master clock is used. In normal operation (both frame syncs
clocking), the MCLKX is used as the master clock, regardless of
whether the MCLKR/PDN pin is clocking or low. The same is true if
the part is in transmit half–channel mode (FSX clocking, FSR held
low). But if the codec–filter is in the receive half–channel mode, with
FSR clocking and FSX held low, MCLKR is used for the internal
master clock if it is clocking; if MCLKR is low, then MCLKX is still
used for the internal master clock. Since only one of the master
clocks isused at any given time, they need not be synchronous.
The master clock frequency must be 1.536 MHz, 1.544 MHz, or
2.048 MHz. The frequency that the codec–filter expects depends
upon whether the part is a Mu–Law or an A–Law part, and on the
state of the BCLKR/CLKSEL pin.The allowable options are shown
In Table 1. When a level (rather than a clock) is provided for
BCLKR/CLKSEL, BCLKX is used as the bit clock for both transmit
and receive.
Table 1. Master Clock Frequency Determination
Master Clock Frequency Expected
BCLKR/CLKSEL
Clocked, 1, or Open
ML145554/64
ML145557/67
1.536 MHz
1.544 MHz
2.048 MHz
0
2.048 MHz
1.536 MHz
1.544 MHz
FRAME SYNCS AND DIGITAL I/O
high, the sign bit appears at the DX output. The next seven rising
edges of BCLKX clock out the remaining seven bits of the PCM
word. The DX and TSX outputs return to a high impedance state on
the falling edge of the eighth bit clock or the falling edge of FSX,
whichever comes later. The receive PCM word is clocked into DR on
the eight falling BCLKR edges following an FSR rising edge.
For Short Frame Sync operation, the frame sync pulses must be
one bit clock period long. On the first BCLKX rising edge after the
falling edge of BCLKX has latched FSX high, the DX and TSX outputs are enabled and the sign bit is presented on DX. The next seven
rising edges of BCLKX clock out the remaining seven bits of the
PCM word; on the eighth BCLKX falling edge, the DX and TSX
outputs return to a high impedance state. On the second falling
BCLKR edge following an FSR rising edge, the receive sign bit is
clocked into DR. The next seven BCLKR falling edges clock in the
remaining seven bits of the receive PCM word.
Table 2 shows the coding format of the transmit and receive PCM
words.
HALF–CHANNEL MODES
In addition to the normal full–duplex operating mode, these
codec–filters can operate in both transmit and receive half–channel
modes. Transmit half–channel mode is entered by holding FSR low.
The VFRO output goes to analog ground but remains in a low impedance state (to facilitate a hybrid interface); PCM data at DR is
ignored. Holding FSX low while clocking FSR puts these devices in
the receive half–channel mode. In this state, the transmit input operational amplifier continues to operate, but the rest of the transmit circuitry is disabled; the DX and TSX outputs remain in a high impedance state. MCLKR is used as the internal master clock if it is clocking. If MCLKR is not clocking, then MCLKX is used for the internal
master clock, but in that case it should be synchronous with FSR. If
BCLKR is not clocking, BCLKX will be used for the receive data,
just as in the full–channel operating mode. In receive half–channel
mode only, the length ofthe FSR pulse is used to determine whether
Short Frame Sync or Long Frame Sync timing is used at DR.
POWER–DOWN
These codec–filters can accommodate both of the industry standard
timing formats. The Long Frame Sync mode isused by Lansdale’s
ML145500 family of codec–filters and the UDLT family of digital
loop transceivers. The Short Frame Sync mode is compatible with the
IDL (Interchip Digital Link) serial format used in Motorola and
Lansdale’s ISDN family and by other companies in their telecommunication devices. These codec–filters use the length of the transmit
frame sync (FSX) to determine the timing format for both transmit
and receive unless the part is operating in the receive half–channel
mode.
In the Long Frame Sync mode, the frame sync pulses must be at
least three bit clock periods long. The DX and TSX outputs are
enabled by the logical ANDing of FSX and BCLKX; when both are
Holding both FSX and FSR low causes the part to go into the
power–down state. Power–down occurs approximately 2 ms after the
last frame sync pulse is received. An alternative way to put these
devices in power–down is to hold the MCLKR/PDN pin high. When
the chip is powered down, the DX, TSX, and GSX outputs are high
impedance, the VFRO, VPO–, and VPO+ operational amplifiers are
biased with a trickle current so that their respective outputs remain
stable at analog ground. To return the chip to the power–up state,
MCLKR/PDN must be low or clocking and at least one of the frame
sync pulses must be present. The DX and TSX outputs will remain in
a high–impedance state until the second FSX pulse after power–up.
Table 2. PCM Data Format
Mu–Law (ML145554/64)
Page 5 of 18
A–Law (ML145557/67)
Level
Sign Bit
Chord Bits
Step Bits
Sign Bit
Chord Bits
Step Bits
+ Full Scale
1
000
0000
1
010
1010
+ Zero
1
111
1111
1
101
0101
– Zero
0
111
1111
0
101
0101
– Full Scale
0
000
0000
0
010
1010
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MAXIMUM RATINGS (Voltage Referenced to GNDA)
Rating
Value
Unit
– 0.5 to + 13
– 0.3 to + 7.0
– 7.0 to + 0.3
V
Voltage on Any Analog Input or Output Pin
VBB – 0.3 to
VCC + 0.3
V
Voltage on Any Digital Input or Output Pin
GNDA – 0.3 to
VCC + 0.3
V
TA
– 40 to + 85
°C
Tstg
– 85 to + 150
°C
DC Supply Voltage
Symbol
VCC to VBB
VCC to GNDA
VBB to GNDA
Operating Temperature Range
Storage Temperature Range
This device contains circuitry to protect
against damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to this high impedance circuit.
For proper operation it is recommended that
Vin and Vout be constrained to the range VSS
(Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., VBB,
GNDA, or VCC).
POWER SUPPLY (TA = – 40 to + 85°C)
Characteristic
DC Supply Voltage
VCC
VBB
Min
Typ
Max
Unit
4.75
– 4.75
5.0
– 5.0
5.25
– 5.25
V
Active Power Dissipation (No Load)
ML145554/57
ML145564/67
ML145564/67, VPI = V BB
—
—
—
40
45
40
60
70
60
mW
Power–Down Dissipation (No Load)
ML145554/57
ML145564/67
ML145564/67, VPI = V BB
—
—
—
1.0
2.0
1.0
3.0
5.0
3.0
mW
Symbol
Min
Max
Unit
Input Low Voltage
VIL
—
0.6
V
Input High Voltage
VIH
2.2
—
V
DIGITAL LEVELS (VCC = 5 V ± 5%, VBB = – 5 V ± 5%, GNDA = 0 V, TA = – 40 to + 85°C)
Characteristic
Output Low Voltage
DX or TSX, IOL = 3.2 mA
VOL
—
0.4
V
Output High Voltage
DX, IOH = – 3.2 mA
IOH = – 1.6 mA
VOH
2.4
VCC – 0.5
—
—
V
Input Low Current
GNDA ≤ Vin ≤ VCC
IIL
– 10
+ 10
µA
Input High Current
GNDA ≤ Vin ≤ VCC
IIH
– 10
+ 10
µA
Output Current in High Impedance State
GNDA ≤ DX ≤ VCC
IOZ
– 10
+ 10
µA
Page 6 of 18
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ANALOG ELECTRICAL CHARACTERISTICS
(VCC = + 5 V ± 5%, VBB = – 5 V ± 5%, VFXI – Connected to GSX, TA = – 40 to + 85°C)
Characteristic
Min
Typ
Max
Unit
Input Current (– 2.5 ≤ Vin ≤ + 2.5 V)
VFXI +, VFXI –
—
± 0.05
± 0.2
µA
AC Input Impedance to GNDA (1 kHz)
VFXI +, VFXI –
10
20
—
MΩ
Input Capacitance
VFXI +, VFXI –
—
—
10
pF
Input Offset Voltage of GSX Op Amp
VFXI +, VFXI –
—
—
± 25
mV
Input Common Mode Voltage Range
VFXI +, VFXI –
– 2.5
—
2.5
V
Input Common Mode Rejection Ratio
VFXI +, VFXI –
—
65
—
dB
Unity Gain Bandwidth of GSX Op Amp (Rload ≥ 10 kΩ)
—
1000
—
kHz
DC Open Loop Gain of GSX Op Amp (Rload ≥ 10 kΩ)
75
—
—
dB
Equivalent Input Noise (C–Message) Between VFXI+ and VFXI– at GSX
—
– 20
—
dBrnC0
Output Load Capacitance for GSX Op Amp
0
—
100
pF
Rload = 10 kΩ to GNDA
Rload = 600 Ω to GNDA
– 3.5
– 2.8
—
—
+ 3.5
+ 2.8
V
GSX, VFRO
± 5.0
—
—
mA
Output Impedance VFRO (0 to 3.4 kHz)
—
1
—
Ω
Output Load Capacitance for VFRO
0
—
500
pF
VFRO Output DC Offset Voltage Referenced to GNDA
—
—
± 100
mV
Transmit Power Supply Rejection
Positive, 0 to 100 kHz, C–Message
Negative, 0 to 100 kHz, C–Message
45
45
—
—
—
—
dBC
Receive Power Supply Rejection
Positive, 0 to 100 kHz, C–Message
Positive, 4 kHz to 25 kHz
Positive, 25 kHz to 50 kHz
Negative, 0 to 100 kHz, C–Message
Negative, 4 kHz to 25 kHz
Negative, 25 kHz to 50 kHz
50
50
43
50
45
38
—
—
—
—
—
—
—
—
—
—
—
—
dBC
dB
dB
dBC
dB
dB
Input Current (– 1 V ≤ VPI ≤ + 1 V)
VPI
—
± 0.05
± 0.5
µA
Input Resistance (– 1 V ≤ VPI ≤ + 1 V)
VPI
5
10
—
MΩ
Input Offset Voltage (VPI Connected to VPO–)
VPI
—
—
± 50
mV
VPO+ or VPO–
—
1
—
Ω
VPO–
—
400
—
kHz
VPO+ or VPO– to GNDA
0
—
1000
pF
—
–1
—
V/V
Output Voltage Range for GSX
Output Current (– 2.8 V ≤ Vout ≤ + 2.8 V)
ML145564/67 Power Drivers
Output Resistance, Inverted Unity Gain
Unity Gain Bandwidth, Open Loop
Load Capacitance (∞ Ω ≥ Rload ≥ 300 Ω)
Gain from VPO– to VPO+ (Rload = 300 Ω, VPO+ to GNDA Level at VPO–
= 1.77 Vrms, +3 dBm0)
Maximum 0 dBm0 Level for Better than 0.1 dB Linearity Over the
Range – 10 dBm0 to + 3 dBm0 (For Rload between VPO+
and VPO–)
Rload = 600 Ω
Rload = 1200 Ω
Rload = 10 kΩ
3.3
3.5
4.0
—
—
—
—
—
—
Vrms
Power Supply Rejection of VCC or VBB (VPO– Connected to VPI)
VPO + or VPO – to GNDA
0 to 4 kHz
4 to 50 kHz
55
35
—
—
—
—
dB
Differential Power Supply Rejection of VCC or VBB (VPO– Connected to VPI)
VPO+ to VPO–, 0 to 50 kHz
50
—
—
Page 7 of 18
www.lansdale.com
dB
Issue A
ML145554, ML145557, ML145564, ML145567
LANSDALE Semiconductor, Inc.
ANALOG TRANSMISSION PERFORMANCE
(VCC = + 5 V 5%, VBB = – 5 V ± 5%, GNDA = 0 V, 0 dBm0 = 1.2276 Vrms = + 4 dBm @ 600 Ω, FSX = FSR = 8 kHz,
BCLKX = MCLKX = 2.048 MHz Synchronous Operation, VFXI – Connected to GSX, TA = – 40 to + 85°C Unless Otherwise Noted)
End–to–End
Characteristic
A/D
D/A
Min
Max
Min
Max
Min
Max
Unit
Absolute Gain (0 dBm0 @ 1.02 kHz, TA = 25°C, VCC = 5 V, VBB = – 5 V)
—
—
– 0.25
– 0.25
– 0.25
+ 0.25
dB
Absolute Gain Variation with Temperature
—
—
—
—
—
—
± 0.03
± 0.06
—
—
± 0.03
± 0.06
dB
—
—
—
± 0.02
—
± 0.02
dB
0 to 70°C
– 40 to + 85°C
Absolute Gain Variation with Power Supply (VCC = 5 V, ± 5%,
VBB = – 5 V, 5%)
Gain vs Level Tone (Relative to – 10 dBm0, 1.02 kHz)
+ 3 to – 40 dBm0
– 40 to – 50 dBm0
– 50 to – 55 dBm0
– 0.4
– 0.8
– 1.6
+ 0.4
+ 0.8
+ 1.6
– 0.2
– 0.4
– 0.8
+ 0.2
+ 0.4
+ 0.8
– 0.2
– 0.4
– 0.8
+ 0.2
+ 0.4
+ 0.8
dB
Gain vs Level Pseudo Noise CCITT G.712
(ML145557/67 A–Law Relative to – 10 dBm0)
– 10 to – 40 dBm0
– 40 to – 50 dBm0
– 50 to – 55 dBm0
—
—
—
—
—
—
– 0.25
– 0.30
– 0.45
+ 0.25
+ 0.30
+ 0.45
– 0.25
– 0.30
– 0.45
+ 0.25
+ 0.30
+ 0.45
dB
+ 3 dBm0
0 to – 30 dBm0
– 40 dBm0
– 45 dBm0
– 55 dBm0
33
35
29
24
15
—
—
—
—
—
33
36
30
25
15
—
—
—
—
—
33
36
30
25
15
—
—
—
—
—
dBC
27.5
35
33.1
28.2
13.2
—
—
—
—
—
28
35.5
33.5
28.5
13.5
—
—
—
—
—
28.5
36
34.2
30
15
—
—
—
—
—
dB
—
—
15
– 70
—
—
15
– 70
—
—
7
– 83
dBrnC0
dBm0p
Total Distortion, 1.02 kHz Tone (C–Message)
Total Distortion With Pseudo Noise CCITT G.714
(ML145557/67 A–Law)
– 3 dBm0
– 6 to – 27 dBm0
– 34 dBm0
– 40 dBm0
– 55 dBm0
Idle Channel Noise (For End–End and A/D, Note 1)
(ML145554/64 Mu–Law, C–Message Weighted)
(ML145557/67 A–Law, Psophometric Weighted)
Frequency Response (Relative to 1.02 kHz @ 0 dBm0)
15 Hz
50 Hz
60 Hz
200 Hz
300 to 3000 Hz
3300 Hz
3400 Hz
4000 Hz
4600 Hz
—
—
—
—
– 0.3
– 0.70
– 1.6
—
—
– 40
– 30
– 26
—
0.3
+ 0.3
0
– 28
– 60
—
—
—
– 1.0
– 0.15
– 0.35
– 0.8
—
—
– 40
– 30
– 26
– 0.4
+ 0.15
+ 0.15
0
– 14
– 32
– 0.15
– 0.15
– 0.15
– 0.15
– 0.15
– 0.35
– 0.8
—
—
0
0
0
0
+ 0.15
+ 0.15
0
– 14
– 30
dB
In–Band Spurious
(1.02 kHz @ 0 dBm0, Transmit and Receive)
300 to 3000 Hz
—
– 48
—
– 48
—
– 48
dBm0
Out–of–Band Spurious at VFRO (300 – 3400 Hz @ 0 dBm0 In)
4600 to 7600 Hz
7600 to 8400 Hz
8400 to 100,000 Hz
—
—
—
– 30
– 40
– 30
—
—
—
—
—
—
—
—
—
– 30
– 40
– 30
Idle Channel Noise Selective (8 kHz, Input = GNDA, 30 Hz Bandwidth)
—
– 70
—
—
—
– 70
dBm0
Absolute Delay (1600 Hz)
—
—
—
315
—
215
µs
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
220
145
75
40
75
105
155
– 40
– 40
– 40
– 30
—
—
—
—
—
—
—
90
125
175
µs
Group Delay Referenced to 1600 Hz
500 to 600 Hz
600 to 800 Hz
800 to 1000 Hz
1000 to 1600 Hz
1600 to 2600 Hz
2600 to 2800 Hz
2800 to 3000 Hz
dB
Crosstalk of 1020 Hz @ 0 dBm0 from A/D or D/A (Note 2)
—
—
—
– 75
—
– 75
dB
Intermodulation Distortion of Two Frequencies of Amplitudes
– 4 to – 21 dBm0 from the Range 300 to 3400 Hz
—
– 41
—
– 41
—
– 41
dB
NOTES:
1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement.
2. Selectively measured while the A/D is stimulated with 2667 Hz @ – 50 dBm0.
Page 8 of 18
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML145554, ML145557, ML145564, ML145567
DIGITAL SWITCHING CHARACTERISTICS
(VCC = 5 V
Noted)
5%, VBB = – 5 V
5%, GNDA = 0 V, All Signals Referenced to GNDA; TA = – 40 to + 85°C, Cload = 150 pF Unless Otherwise
Characteristic
Symbol
Min
Typ
Max
Unit
Master Clock Frequency
MCLKX or MCLKR
fM
—
—
—
1.536
1.544
2.048
—
—
—
MHz
Minimum Pulse Width High or Low
MCLKX or MCLKR
tw(M)
100
—
—
ns
Minimum Pulse Width High or Low
BCLKX or BCLKR
tw(B)
50
—
—
ns
FSX or FSR
tw(FL)
50
—
—
ns
Rise Time for all Digital Signals
tr
—
—
50
ns
Fall Time for all Digital Signals
tf
—
—
50
ns
fB
128
—
4096
kHz
Setup Time from BCLKX Low to MCLKR High
tsu(BRM)
50
—
—
ns
Setup Time from MCLKX High to BCLKX Low
tsu(MFB)
20
—
—
ns
Hold Time from BCLKX (BCLKR) Low to FSX (FSR) High
th(BF)
20
—
—
ns
Setup Time for FSX (FSR) High to BCLKX (BCLKR) Low for Long Frame
tsu(FB)
80
—
—
ns
Delay Time from BCLKX High to DX Data Valid
td(BD)
20
60
140
ns
Delay Time from BCLKX High to TSX Low
td(BTS)
20
50
140
ns
Delay Time from the 8th BCLKX Low of FSX Low to DX Output Disabled
td(ZC)
50
70
140
ns
Delay Time to Valid Data from FSX or BCLKX, Whichever is Later
td(ZF)
20
60
140
ns
Setup Time from DR Valid to BCLKX Low
tsu(DB)
0
—
—
ns
Hold Time from BCLKR Low to DR Invalid
th(BD)
50
—
—
ns
Setup Time from FSX (FSR) High to BCLKX (BCLKR) Low in Short Frame
tsu(F)
50
—
—
ns
Hold Time from BCLKX (BCLKR) Low to FSX (FSR) Low in Short Frame
th(F)
50
—
—
ns
Hold Time from 2nd Period of BCLKX (BCLKR) Low to FSX (FSR) Low in
Long Frame
th(BFI)
50
—
—
ns
Minimum Pulse WIdth Low
Bit Clock Data Rate
Page 9 of 18
BCLKX or BCLKR
www.lansdale.com
Issue A
ML145554, ML145557, ML145564, ML145567
LANSDALE Semiconductor, Inc.
TSX
td(BTS)
tw(M)
tw(M)
td(ZC)
MCLKX
MCLKR
tsu(MFB)
tw(B)
tw(B)
tsu(BRM)
BCLKX
1
th(BF)
tsu(F)
2
3
4
5
6
8
7
9
th(F)
FSX
td(ZC)
td(BD)
MSB
DX
BCLKR
1
th(BF)
tsu(F)
CH1
2
CH2
3
CH3
4
ST1
5
ST2
6
ST3
7
LSB
8
9
th(F)
FSR
th(BD)
th(BD)
tsu(DB)
DR
MSB
CH1
CH2
CH3
ST1
ST2
ST3
LSB
Figure 1. Short Frame Sync Timing
Page 10 of 18
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML145554, ML145557, ML145564, ML145567
MCLKX
MCLKR
tsu(MFB)
tsu(BRM)
BCLKX
2
1
3
tsu(FB)
4
5
6
8
7
9
th(BFI)
th(BF)
FSX
td(ZF)
td(BD)
td(ZC)
td(ZC)
td(ZF)
DX
MSB
1
BCLKR
CH1
2
CH2
3
th(BF)
CH3
4
ST1
5
ST3
ST2
6
7
LSB
8
9
th(BFI)
tsu(FB)
FSR
th(BD)
th(BD)
tsu(DB)
DR
MSB
CH1
CH2
CH3
ST1
ST2
ST3
LSB
Figure 2. Long Frame Sync Timing
Page 11 of 18
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML145554, ML145557, ML145564, ML145567
–5V
1
2
ANALOG OUT
+5V
3
4
5
6
7
8
VFXI +
VBB
GNDA
VFRO
VCC
ML145554/57
FSR
DR
BCLKR/ CLKSEL
MCLKR/ PDN
16
15
VFXI –
14
GSX
13
TSX
12
FSX
11
DX
10
BCLKX
9
MCLKX
ANALOG IN
TX TIME SLOT
8 kHz
1
2
3
1.544 MHz/
2.048 MHz
ADCPM IN
POWER–DOWN
4
5
6
MODE
VDD
DDO
EDO
DDE
EOE
DDC
MC145532
DDI
DIE
7
PD/RESET
8 V
SS
16
+5V
15
14
ADPCM OUT
13
EDC
12
EDI
11
EIE
10
SPC
9
ADP
20.48 MHz
Figure 3. ADPCM Transcoder Application
Page 12 of 18
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML145554, ML145557, ML145564, ML145567
MC33120
20
19
1N4002
18
MJD253
15
VDD
VCC
EP PDI/ST2 12
13
ST1
BP
14
VDG
1N4002
– 48 V
0.01 µF
50 V
VAG
100
1/4 W
1k
17
9.1 k 16
TIP
9.1 k
RING
1k
5
4
+5V
+
RXI
+5V
ML145554/7
CN
48.5 k
10
4.7 k
RSI
RFO
MJD243
1N4002
3
2
– 48 V
47.4 k
1 µF
TXO
1N4002
20.6 k
3
8
100
1/4 W
0.01 µF
50 V
5 µF, 16 V
9
CP
TSI
HOOK STATUS/
FAULT INDICATION
1
BN
CF
EN
VQB
VEE
1 µF
11
10 k
7
6
14
49.0 k 16
300 Ω
+
20 Ω
15
1.0 µF, 50 V
10 µF, 50 V
2
VCC
VFRO
FSX
4
12
8 kHz SYNC
5
FSR
10
BCLKX
7
BCLKR
8
MCLKR
9
MCLKX
11
DX
VFXI–
6
DR
GSX
13
VFXI+
TSX
1
GNDA
VBB
DATA CLOCK
ML145554 =
1.544 MHZ
ML145557 =
2.048 MHz
TO PCM HWY
–5V
+
NOTE: Six resistors and two capacitors on the two–wire side can be 5% tolerance.
Figure 4. A Complete Single Party Channel Unit Using ML145554/57 PCM Codec–Filter and MC33120 SLIC
Page 13 of 18
www.lansdale.com
Issue A
ML145554, ML145557, ML145564, ML145567
LANSDALE Semiconductor, Inc.
+5V
S INTERFACE
+5V
7Ω
17
33 k
7Ω
2
21
“S” TRANSCEIVER
MC145474P
VDD
ISET
TE/NT
SYNC
TX+
CLK
+5V
7Ω
RX
7Ω
20
TX
TX–
DREQ
+5V
DGRT
1 kΩ
1 kΩ
2
SEL
RX+
CLK
+5V
1 kΩ
RX
1 kΩ
3
6
RX–
VSS
XTAL
TX
IRQ
RESET
EXTAL
4
8
9
10
11
7
5
15
14
13
12
19
15.36 MHz
30 pF
HANDSET
RJ–1
1
+ RCVR
(WHITE)
ML145554
3
10 kΩ
15
+5V
500 Ω
+ MIC (RED)
– RCVR
(WHITE)
– MIC (BLK)
500 Ω
0.1 µF
14
16
2
VFRO
VFXI–
GSX
VFXI+
GNDA
30 pF
+5V
4
VCC
12, 5
FSX, FSR
10, 7, 8, 9
MCLK, BCLK
11
DX
6
DR
13
TSX
1
VBB
CODEC–FILTER
LAP–D/LAP–B CONTROLLER
ML145488
52, 2, 9
D0 10
VDD
D1 11
D2 12
60, 44
SYNC 0, 1 D3 13
59, 45
CLK 0, 1
D4 14
55, 49
D5 15
TX 0, 1
D6 16
56, 48
RX 0, 1
D7 17
47
DREQ 1
D8 18
46
D9 19
DGNT 1
D10 20
50 SCPE 1
D11 22
D12
23
53
SCPE 0
D13 24
57
SCP CLK D14 25
54
D15 26
MPU
SCP TXD
A1 8
58
BUS
SCP RXD
A2 7
A3 6
A4 5
A5 4
A6 3
A7 1
A8 68
A9 67
A10 66
A11 65
A12 64
A13 63
A14 62
A15 61
OWN0 42
OWN1 43
MCLK 27
CS 28
R/W 29
AS 30
LDS 31
UDS 32
RST 33
IACK 34
IRQ 36
DTACK 37
BERR 38
BR 39
51, 36, 21
VSS
BG 40
BGACK 41
+5V +5V
–5V
Figure 5. ISDN Voice/Data Terminal
Page 14 of 18
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML145554, ML145557, ML145564, ML145567
Table 3. Mu–Law Encode–Decode Characteristics
Chord
Number
Number
of Steps
Step
Size
Normalized
Encode
Decision
Levels
Digital Code
1
2
3
4
5
6
7
8
Sign
Chord
Chord
Chord
Step
Step
Step
Step
Normalized
Decode
Levels
1
0
0
0
0
0
0
0
8031
1
0
0
0
1
1
1
1
4191
1
0
0
1
1
1
1
1
2079
1
0
1
0
1
1
1
1
1023
1
0
1
1
1
1
1
1
495
1
1
0
0
1
1
1
1
231
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
2
1
1
1
1
1
1
1
1
0
8159
256
…
16
…
8
…
7903
4319
7
16
128
…
…
…
4063
2143
6
16
64
…
…
…
2015
1055
5
16
32
…
…
…
991
511
4
16
16
…
…
…
479
239
3
16
8
…
…
…
223
103
99
2
16
4
…
…
…
95
35
33
1
15
2
…
…
…
31
3
1
1
1
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inversion of all magnitude bits.
Page 15 of 18
www.lansdale.com
Issue A
ML145554, ML145557, ML145564, ML145567
LANSDALE Semiconductor, Inc.
Table 4. A–Law Encode–Decode Characteristics
Chord
Number
Number
of Steps
Step
Size
Normalized
Encode
Decision
Levels
Digital Code
1
2
3
4
5
6
7
8
Sign
Chord
Chord
Chord
Step
Step
Step
Step
Normalized
Decode
Levels
1
0
1
0
1
0
1
0
4032
1
0
1
0
0
1
0
1
2112
1
0
1
1
0
1
0
1
1056
1
0
0
0
0
1
0
1
528
1
0
0
1
0
1
0
1
264
1
1
1
0
0
1
0
1
132
1
1
1
1
0
1
0
1
1
1
0
1
0
1
0
1
4096
128
…
16
…
7
…
3968
2176
6
16
64
…
…
…
2048
1088
5
16
32
…
…
…
1024
544
4
16
16
…
…
…
512
272
3
16
8
…
…
…
256
136
2
16
4
…
…
…
128
68
66
1
32
2
…
…
…
64
2
1
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes alternate bit inversion, as specified by CCITT.
Page 16 of 18
www.lansdale.com
Issue A
ML145554, ML145557, ML145564, ML145567
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 16 = EP
(ML145554EP, ML145557EP)
PLASTIC DIP
CASE 648–08
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
SEATING
PLANE
–T–
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
10
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
10
0.51
1.01
SOG 16 = -5P
(ML145554-5P, ML145557-5P)
SOG PACKAGE
CASE 751G–02
–A–
16
9
–B–
8X
P
0.010 (0.25)
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45
C
–T–
14X
Page 17 of 18
G
K
SEATING
PLANE
M
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DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0
7
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0
7
0.395
0.415
0.010
0.029
Issue A
ML145554, ML145557, ML145564, ML145567
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 20 = RP
(ML145564RP, ML145567RP)
PLASTIC DIP
CASE 738–03
-A20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
C
-T-
L
DIM
A
B
C
D
E
F
G
J
K
L
M
N
K
SEATING
PLANE
M
E
G
N
F
J 20 PL
0.25 (0.010)
D 20 PL
0.25 (0.010)
M
T A
M
T B
M
M
INCHES
MIN
MAX
1.010 1.070
0.240 0.260
0.150 0.180
0.015 0.022
0.050 BSC
0.050 0.070
0.100 BSC
0.008 0.015
0.110 0.140
0.300 BSC
15°
0°
0.020 0.040
MILLIMETERS
MIN
MAX
25.66 27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0°
15°
0.51
1.01
SOG 20 = -6P
(ML145564-6P, ML145567-6P)
SOG PACKAGE
CASE 751D–04
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
20
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R
C
–T–
18X
G
K
SEATING
PLANE
X 45
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0
7
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0
7
0.395
0.415
0.010
0.029
M
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described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 18 of 18
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Issue A