Holtek HT48C50- 8-bit microcontroller Datasheet

HT48C50-1
8-Bit Microcontroller
Preliminary
Features
·
·
·
·
·
·
·
·
·
Operating voltage:
fSYS=4MHz: 2.4V~5.5V
fSYS=8MHz: 4.5V~5.5V
Low voltage reset function
35 bidirectional I/O lines (max.)
1 interrupt input shared with an I/O line
8-bit programmable timer/event counter with
overflow interrupt and 8-stage prescaler
16-bit programmable timer/event counter
and overflow interrupts
On-chip RC oscillator, external crystal and
RC oscillator
32768Hz crystal oscillator for timing
purposes only
Watchdog Timer
·
·
·
·
·
·
·
·
·
·
·
4096´15 program memory ROM
160´8 data memory RAM
Buzzer driving pair and PFD supported
Halt function and wake-up feature reduce
power consumption
6-level subroutine nesting
Up to 0.5ms instruction cycle with 8MHz
system clock at VDD=5V
Bit manipulation instruction
15-bit table read instruction
63 powerful instructions
All instructions in one or two machine
cycles
28-pin SKDIP and 40-pin DIP package
General Description
remote controllers, fan/light controllers, washing machine controllers, scales, toys and various subsystem controllers. A HALT feature is
included to reduce power consumption.
The device is an 8-bit high performance
RISC-like microcontroller designed for multiple I/O product applications. The device is particularly suitable for use in products such as
1
June 14, 2000
Preliminary
HT48C50-1
Block Diagram
M
T M R 1 C
IN T /P G 0
M
T M R 1
U
P ro g ra m
R O M
IN T C
/4
U
P r e s c a le r
T M R 0
X
M
U
fS
Y S
X
T M R 0 C
P G 0
In s tr u c tio n
R e g is te r
Y S
T M R 1
M
T M R 0
P ro g ra m
C o u n te r
fS
X
X
In te rru p t
C ir c u it
S T A C K
U
M
M P
U
X
S Y S C L K /4
E N /D IS
W D T S
D A T A
M e m o ry
W D T P r e s c a le r
W D T
M
U
R T C
X
O S C
W D T O S C
P A C
M U X
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
S h ifte r
O S
P
R
V
V
C 1 /
G 1
E S
D D
S S
P A 0 ~ P A 7
B Z /B Z
S T A T U S
P B C
P G 1
P G 2
P O R T B
P B
P C C
O S C 2 /
P G 2
P O R T A
P A
P O R T C
P C
A C C
P D C
In te rn a l
R C O S C
P O R T D
P D
P G C
P G
2
P O R T G
P B 0 ~ P B 7
P C 0 ~ P C 7
P D 0 ~ P D 7
P G 0 ~ P G 2
June 14, 2000
Preliminary
HT48C50-1
Pin Assignment
P B 5
1
4 0
P B 6
P B 4
2
3 9
P B 7
P A 3
3
3 8
P A 4
P A 2
4
3 7
P A 5
P A 1
5
3 6
P A 6
P A 0
6
3 5
P A 7
P B 5
1
2 8
P B 6
P B 3
7
3 4
O S C 2 /P G 2
P B 4
2
2 7
P B 7
P B 2
8
3 3
O S C 1 /P G 1
P A 3
3
2 6
P A 4
P B 1 /B Z
9
3 2
V D D
P A 2
4
2 5
P A 5
P B 0 /B Z
1 0
3 1
R E S
P A 1
5
2 4
P A 6
P D 7
1 1
3 0
T M R 1
P A 0
6
2 3
P A 7
P D 6
1 2
2 9
P D 3
P B 3
7
2 2
O S C 2 /P G 2
P D 5
1 3
2 8
P D 2
P B 2
8
2 1
O S C 1 /P G 1
P D 4
1 4
2 7
P D 1
P B 1 /B Z
9
2 0
V D D
V S S
1 5
2 6
P D 0
P B 0 /B Z
1 0
1 9
R E S
P G 0 /IN T
1 6
2 5
P C 7
V S S
1 1
1 8
P C 5 /T M R 1
T M R 0
1 7
2 4
P C 6
P G 0 /IN T
1 2
1 7
P C 4
P C 0
1 8
2 3
P C 5
P C 0 /T M R 0
1 3
1 6
P C 3
P C 1
1 9
2 2
P C 4
P C 1
1 4
1 5
P C 2
P C 2
2 0
2 1
P C 3
H T 4 8 C 5 0 -1 -A
2 8 S K D IP
H T 4 8 C 5 0 -1
4 0 D IP
Pad Assignment
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
4
P B 0 /B Z
5
P D 7
6
2 7
7
P D 5
8
P D 4
2 9
O S C 2 /P G 2
2 8
O S C 1 /P G 1
(0 , 0 )
P D 6
V S S
P B 5
3
P B 1 /B Z
P B 4
2
P B 2
P A 3
P B 3
P A 2
1
P A 1
P A 0
4 0
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
V D D
2 6
R E S
2 5
T M R 1
2 4
P D 3
2 3
P D 2
2 2
P D 1
P G 0 /IN T
T M R 0
P C 0
P C 1
P C 2
P C 3
P C 4
P C 5
P C 6
P C 7
P D 0
* The IC substrate should be connected to VSS in the PCB layout artwork.
3
June 14, 2000
Preliminary
HT48C50-1
Pad Description
Pad
No.
Pad Name I/O
Mask Option
Description
1,
40~38, PA0~PA7
33~30
Bidirectional 8-bit input/output port. Each bit can be
Pull-high*
configured as a wake-up input by mask option. SoftWake-up
ware instructions determine the CMOS output or
I/O
CMOS/schmitt
schmitt trigger or CMOS input with pull-high resistor
trigger input
(determined by pull-high options).
5
4
3, 2,
37~34
PB0/BZ
PB1/BZ
PB2~PB7
Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or schmitt
trigger input with pull-high resistor (determined by
Pull-high*
pull-high options).
I/O or BZ/BZ
The PB0 and PB1 are pin-shared with the BZ and BZ,
I/O
CMOS/schmitt
respectively. Once the PB0 and PB1 are selected as
trigger input
buzzer driving outputs, the output signals come from
an internal PFD generator (shared with timer/event
counter 0).
21~24,
PD0~PD7
9~6
Bidirectional I/O lines. Software instructions deterPull-high*
I/O CMOS/schmitt mine the CMOS output or schmitt trigger input with
trigger input pull-high resistor (determined by pull-high options).
10
¾
VSS
¾
Negative power supply, ground
I/O
Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS output or schmitt trigger input with
pull-high resistor (determined by pull-high options).
This external interrupt input is pin-shared with PG0.
The external interrupt input is activated on a high to
low transition.
I
¾
Timer/event counter 0 schmitt trigger input (without
pull-high resistor)
11
PG0/INT
12
TMR0
13~20
PC0~PC7
25
TMR1
I
¾
Timer/event counter 1 schmitt trigger input (without
pull-high resistor)
26
RES
I
¾
Schmitt trigger reset input. Active low
27
VDD
¾
¾
Positive power supply
Pull-high*
Bidirectional I/O lines. Software instructions deterI/O CMOS/schmitt mine the CMOS output or schmitt trigger input with
trigger input pull-high resistor (determined by pull-high options).
4
June 14, 2000
Preliminary
Pad
No.
HT48C50-1
Pad Name I/O
Mask Option
OSC1/PG1
OSC2/PG2
OSC1, OSC2 are connected to an RC network or Crystal (determined by mask option) for the internal system clock. In the case of RC operation, OSC2 is the
Pull-high*
output terminal for 1/4 system clock. These two pins
can also be optioned as an RTC oscillator (32768Hz) or
Crystal
I/O lines. In these two cases, the system clock comes
or RC
or Int. RC+I/O from an internal RC oscillator whose frequency has 4
options (3.2MHz, 1.6MHz, 800kHz, 400kHz). If the I/O
or Int.
option is selected, the pull-high options can also be enRC+RTC
abled or disabled. Otherwise the PG1 and PG2 are
used as internal registers (pull-high resistors are always disabled).
28
29
I
O
Description
Note: * The pull-high resistors of each I/O port (PA, PB, PC, PD, PG) are controlled by options.
Absolute Maximum Ratings
Supply Voltage ...............VSS-0.3V to VSS+5.5V
Storage Temperature.................-50°C to 125°C
Input Voltage .................VSS-0.3V to VDD+0.3V
Operating Temperature ..............-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD1
Operating Voltage
¾
fSYS=4MHz
2.4
¾
5.5
V
VDD2
Operating Voltage
¾
fSYS=8MHz
4.5
¾
5.5
V
IDD1
Operating Current
(Crystal OSC)
5V
IDD2
Operating Current
(RC OSC)
IDD3
Operating Current
(Crystal OSC)
ISTB1
Standby Current
(WDT Enabled RTC Off)
3V
ISTB2
Standby Current
(WDT Disabled RTC Off)
3V
3V
3V
5V
5V
5V
5V
No load, fSYS=4MHz
No load, fSYS=4MHz
No load, fSYS=8MHz
No load, system HALT
No load, system HALT
5
¾
1
2
mA
¾
3
5
mA
¾
1
2
mA
¾
3
5
mA
¾
4
8
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
June 14, 2000
Preliminary
Symbol
Parameter
Test Conditions
Conditions
VDD
3V
HT48C50-1
Min.
Typ.
Max.
Unit
¾
¾
5
mA
¾
¾
10
mA
ISTB3
Standby Current
(WDT Disabled, RTC On)
VIL1
Input Low Voltage for
I/O Ports
¾
¾
0
¾
0.2VDD
V
VIH1
Input High Voltage for
I/O Ports
¾
¾
0.8VDD
¾
VDD
V
VIL2
Input Low Voltage
(RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage
(RES)
¾
¾
0.9VDD
¾
VDD
V
IOL
I/O Port Sink Current
5V
No load, system HALT
3V
VOL=0.1VDD
6
12
¾
mA
5V
VOL=0.1VDD
10
25
¾
mA
3V
VOH=0.9VDD
-3
-6
¾
mA
5V
VOH=0.9VDD
-5
-10
¾
mA
IOH
I/O Port Source
Current
RPH
Pull-high Resistance
VLVR1
Low Voltage Reset
¾
VLVR2
Low Voltage Reset
¾
3V
¾
40
60
80
kW
5V
¾
10
30
50
kW
2.2V option
2.0
2.2
2.4
V
3.3V option
3.0
3.3
3.6
V
A.C. Characteristics
Symbol
Parameter
fSYS1
System Clock
(Crystal OSC)
fSYS2
System Clock (RC OSC)
fSYS3
System Clock (Internal RC)
fTIMER
Timer I/P Frequency
(TMR0/TMR1)
tWDTOSC
Watchdog Oscillator
tWDT1
Watchdog Time-out Period
(WDT OSC)
Ta=25°C
Test Conditions
VDD
Conditions
Min. Typ. Max. Unit
3V
¾
400
¾
4000
kHz
5V
¾
400
¾
8000
kHz
3V
¾
400
¾
4000
kHz
5V
¾
400
¾
3V
5V
3.2MHz option
8000
kHz
1600 2500 3500
kHz
2000 3200 4500
kHz
3V
¾
0
¾
4000
kHz
5V
¾
0
¾
8000
kHz
3V
¾
43
86
168
ms
5V
¾
35
65
130
ms
11
22
43
ms
9
17
35
ms
3V
5V
Without WDT
prescaler
6
June 14, 2000
Preliminary
Symbol
HT48C50-1
Test Conditions
Parameter
Min. Typ. Max. Unit
Conditions
VDD
tWDT2
Watchdog Time-out Period
(System Clock)
¾
Without WDT
prescaler
¾
1024
¾
tSYS
tWDT3
Watchdog Time-out Period
(RTC OSC)
¾
Without WDT
prescaler
¾
7.812
¾
ms
tRES
External Reset Low Pulse
Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer
Period
¾
Power-up, reset or
wake-up from HALT
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Functional Description
specify a full range of program memory.
Execution flow
After accessing a program memory word to fetch
an instruction code, the contents of the program
counter are incremented by one. The program
counter then points to the memory word containing the next instruction code.
The system clock for the microcontroller is derived from either a crystal or an RC oscillator.
The system clock is internally divided into four
non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
When executing a jump instruction, conditional
skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC
manipulates the program transfer by loading
the address corresponding to each instruction.
Instruction fetching and execution are
pipelined in such a way that a fetch takes an instruction cycle while decoding and execution
takes the next instruction cycle. However, the
pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to complete the instruction.
The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current
instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction.
Program counter - PC
The program counter (PC) controls the sequence in which the instructions stored in the
program ROM are executed and its contents
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 1
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
P C + 2
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution flow
7
June 14, 2000
Preliminary
The lower byte of the program counter (PCL) is
a readable and writeable register (06H).
Moving data into the PCL performs a short
jump. The destination will be within 256 locations.
0 0 0 H
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r 0
In te r r u p t S u b r o u tin e
0 0 C H
Program memory - ROM
T im e r /E v e n t C o u n te r 1
In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
The program memory is used to store the program instructions which are to be executed. It
also contains data, table, and interrupt entries,
and is organized into 4096´15 bits, addressed
by the program counter and table pointer.
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
Certain locations in the program memory are
reserved for special usage:
1 5 b its
N o te : n ra n g e s fro m
· Location 000H
0 to F
Program memory
This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H.
· Location 008H
This area is reserved for the timer/event counter 0 interrupt service program. If a timer interrupt results from a timer/event counter 0
overflow, and if the interrupt is enabled and the
stack is not full, the program begins execution
at location 008H .
· Location 004H
This area is reserved for the external interrupt service program. If the INT input pin is
activated, the interrupt is enabled and the
stack is not full, the program begins execution
at location 004H.
Mode
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
When a control transfer takes place, an additional dummy cycle is required.
HT48C50-1
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0
Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1
Overflow
0
0
0
0
0
0
0
0
1
1
0
0
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
PC+2
Program counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
@7~@0: PCL bits
8
June 14, 2000
Preliminary
· Location 00CH
until the TBLH has been backed up. All table
related instructions require two cycles to complete the operation. These areas may function
as normal program memory depending upon
the requirements.
This location is reserved for the timer/event
counter 1 interrupt service program. If a
timer interrupt results from a timer/event
counter 1 overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at location 00CH.
Stack register - STACK
This is a special part of the memory which is
used to save the contents of the program counter (PC) only. The stack is organized into 6 levels and is neither part of the data nor part of the
program space, and is neither readable nor
writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program
counter are pushed onto the stack. At the end of
a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the program counter is restored to its previous value
from the stack. After a chip reset, the SP will
point to the top of the stack.
· Table location
Any location in the ROM space can be used as
look-up tables. The instructions "TABRDC
[m]" (the current page, 1 page=256 words)
and "TABRDL [m]" (the last page) transfer
the contents of the lower-order byte to the
specified data memory, and the higher-order
byte to TBLH (08H). Only the destination of
t h e l ow er- or d er b y t e i n t he t a b l e i s
well-defined, the other bits of the table word
are transferred to the lower portion of TBLH,
and the remaining 1-bit words are read as "0".
The Table Higher-order byte register (TBLH)
is read only. The table pointer (TBLP) is a
read/write register (07H), which indicates the
table location. Before accessing the table, the
location must be placed in the TBLP. The
TBLH is read only and cannot be restored. If
the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the
main routine are likely to be changed by the
table read instruction used in the ISR. Errors
can occur. In other words, using the table read
instruction in the main routine and the ISR
simultaneously should be avoided. However,
if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the
table read instruction. It will not be enabled
Instruction
HT48C50-1
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be
recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented
(by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure
more easily. In a similar case, if the stack is full
and a "CALL" is subsequently executed, stack
overflow occurs and the first entry will be lost
(only the most recent 6 return addresses are
stored).
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
9
June 14, 2000
Preliminary
The special function registers include the indirect addressing registers (00H, 02H),
timer/event counter 0 (TMR0;0DH),
timer/event counter 0 control register
(TMR0C;0EH), timer/event counter 1 higher
order byte register (TMR1H;0FH), timer/event
counter 1 lower order byte register
(TMR1L;10H), timer/event counter 1 control
register (TMR1C;11H), program counter
lower-order byte register (PCL;06H), memory
pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer
(TBLP;07H), table higher-order byte register
(TBLH;08H), status register (STATUS;0AH),
interrupt control register (INTC;0BH), Watchd o g Ti m e r o p t i o n s e t t i n g r e g i s t e r
(WDTS;09H), I/O registers (PA;12H, PB;14H,
PC;16H, PD;18H, PG;1EH) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H,
PDC;19H, PGC;1FH). The remaining space before the 60H is reserved for future expanded
usage and reading these locations will get
"00H". The general purpose data memory, addressed from 60H to FFH, is used for data and
control information under instruction commands.
Data memory - RAM
The data memory is designed with 184´8 bits.
The data memory is divided into two functional groups: special function registers and
general purpose data memory (160´8). Most
are read/write, but some are read only.
0 0 H
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
S p e c ia l P u r p o s e
D A T A M E M O R Y
All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate
operations directly. Except for some dedicated
bits, each bit in the data memory can be set and
reset by "SET [m].i" and "CLR [m].i". They are
also indirectly accessible through memory
pointer registers (MP0 or MP1).
: U n u s e d
1 A H
1 B H
Indirect addressing register
R e a d a s "0 0 "
1 C H
Location 00H and 02H are indirect addressing
registers that are not physically implemented.
Any read/write operation of [00H] ([02H]) will
access data memory pointed to by MP0 (MP1).
Reading location 00H (02H) itself indirectly
will return the result 00H. Writing indirectly
results in no operation.
1 D H
1 E H
P G
1 F H
2 0 H
P G C
HT48C50-1
5 F H
6 0 H
G e n e ra l P u rp o s e
D A T A M E M O R Y
(1 6 0 B y te s )
The memory pointer registers (MP0 and MP1)
are 8-bit registers.
F F H
RAM mapping
10
June 14, 2000
Preliminary
HT48C50-1
watchdog time-out flag (TO). It also records the
status information and controls the operation
sequence.
Accumulator
The accumulator is closely related to ALU operations. It is also mapped to location 05H of the
data memory and can carry out immediate data
operations. The data movement between two
data memory locations must pass through the
accumulator.
With the exception of the TO and PD flags,
bits in the status register can be altered by
instructions like most other registers. Any
data written into the status register will not
change the TO or PD flag. In addition operations related to the status register may give
different results from those intended. The
TO flag can be affected only by system
power-up, a WDT time-out or executing the
"CLR WDT" or "HALT" instruction. The PD
flag can be affected only by executing the
"HALT" or "CLR WDT" instruction or during
a system power-up.
Arithmetic and logic unit - ALU
This circuit performs 8-bit arithmetic and logic
operations. The ALU provides the following functions:
Arithmetic operations (ADD, ADC, SUB, SBC,
DAA)
· Logic operations (AND, OR, XOR, CPL) Rota-
tion (RL, RR, RLC, RRC)
The Z, OV, AC and C flags generally reflect the
status of the latest operations.
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
In addition, on entering the interrupt sequence
or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are
important and if the subroutine can corrupt the
status register, precautions must be taken to
save it properly.
The ALU not only saves the results of a data operation but also changes the status register.
Status register - STATUS
This 8-bit register (0AH) contains the zero flag
(Z), carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PD), and
Labels
Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or no
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared by system power-up or executing the "CLR WDT" instruction. PD
is set by executing the "HALT" instruction.
TO
5
TO is cleared by system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out.
¾
6
Undefined, read as "0"
¾
7
Undefined, read as "0"
Status register
11
June 14, 2000
Preliminary
onto the stack. If the contents of the register or
status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be
saved in advance.
Interrupt
The device provides an external interrupt and
internal timer/event counter interrupts. The
Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags.
External interrupts are triggered by a high to
low transition of the INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set.
When the interrupt is enabled, the stack is not
full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be
cleared to disable other interrupts.
Once an interrupt subroutine is serviced, all
the other interrupts will be blocked (by clearing
the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding
bit of the INTC may be set to allow interrupt
nesting. If the stack is full, the interrupt request
will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack must
be prevented from becoming full.
The internal timer/event counter 0 interrupt is
initialized by setting the timer/event counter 0
interrupt request flag (T0F; bit 5 of INTC),
caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F
bit is set, a subroutine call to location 08H will
occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable
further interrupts.
All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control
transfer occurs by pushing the program counter
onto the stack, followed by a branch to a subroutine at specified location in the program
memory. Only the program counter is pushed
Register
INTC
(0BH)
Bit No.
HT48C50-1
The internal timer/even counter 1 interrupt is
initialized by setting the timer/event counter 1
interrupt request flag (T1F;bit 6 of INTC),
caused by a timer 1 overflow. When the inter-
Label
Function
0
EMI
Controls the master (global) interrupt
(1= enabled; 0= disabled)
1
EEI
Controls the external interrupt
(1= enabled; 0= disabled)
2
ET0I
Controls the timer/event counter 0 interrupt
(1= enabled; 0= disabled)
3
ET1I
Controls the timer/event counter 1 interrupt
(1= enabled; 0= disabled)
4
EIF
External interrupt request flag
(1= active; 0= inactive)
5
T0F
Internal timer/event counter 0 request flag
(1= active; 0= inactive)
6
T1F
Internal timer/event counter 1 request flag
(1= active; 0= inactive)
7
¾
Unused bit, read as "0"
INTC register
12
June 14, 2000
Preliminary
HT48C50-1
rupt is enabled, the stack is not full and the T1F
is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F)
will be reset and the EMI bit cleared to disable
further interrupts.
prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F,
T1F, EIF) are set, they will remain in the INTC
register until the interrupts are serviced or
cleared by a software instruction.
During the execution of an interrupt subroutine,
other interrupt acknowledge signals are held
until the "RETI" instruction is executed or the
EMI bit and the related interrupt control bit are
set to 1 (if the stack is not full). To return from
the interrupt subroutine, "RET" or "RETI" may
be invoked. RETI will set the EMI bit to enable
an interrupt service, but RET will not.
It is recommended that a program does not
use the "CALL subroutine" within the interrupt subroutine. Interrupts often occur in an
unpredictable manner or need to be serviced
immediately in some applications. If only one
stack is left and enabling the interrupt is not
well controlled, the original control sequence will
be damaged once the "CALL" operates in the interrupt subroutine.
Interrupts, occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the
following table shows the priority that is applied. These can be masked by resetting the
EMI bit.
Oscillator configuration
There are 3 oscillator circuits in the
microcontroller.
V
No. Interrupt Source Priority Vector
a
External Interrupt
1
04H
b
Timer/event
Counter 0 Overflow
2
08H
c
Timer/event
Counter 1 Overflow
3
0CH
O S C 1
R T C
4 7 0 p F
O S C 2
C r y s ta l O s c illa to r
( In c lu d e 3 2 7 6 8 H z )
fS Y S /4
N M O S O p e n D r a in
O S C 1
O S C 2
R C O s c illa to r
System oscillator
The timer/event counter 0/1 interrupt request
flag (T0F/T1F), external interrupt request flag
(EIF), enable timer/event counter 0/1 interrupt
bit (ET0I/ET1I), enable external interrupt bit
(EEI) and enable master interrupt bit (EMI)
constitute an interrupt control register (INTC)
which is located at 0BH in the data memory.
EMI, EEI, ET0I and ET1I are used to control
the enabling/disabling of interrupts. These bits
S y s te m
D D
All of them are designed for system clocks,
namely the external RC oscillator, the external
Crystal oscillator and the internal RC
oscillator, which are determined by mask option. No matter what oscillator type is selected,
the signal provides the system clock. The HALT
mode stops the system oscillator and ignores an
external signal to conserve power.
C lo c k /4
O S C
W D T
O S C
R O M
C o d e
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
13
June 14, 2000
Preliminary
If an RC oscillator is used, an external resistor
between OSC1 and VDD is required and the
resistance must range from 51kW to 1MW. The
system clock, divided by 4, is available on
OSC2, which can be used to synchronize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency
of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing
sensitive operations where an accurate oscillator frequency is desired.
HT48C50-1
is first divided by 256 (8-stage) to get the nominal time-out period of 16.6ms/5V. This time-out
period may vary with temperatures, VDD and
process variations. By invoking the WDT
prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0
of the WDTS) can give different time-out periods.
If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum
time-out period is 2.2s/5V seconds. If the WDT oscillator is disabled, the WDT clock may still come
from the instruction clock and operates in the
same manner except that in the HALT state the
WDT may stop counting and lose its protecting
purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit
3 of the WDTS are reserved for user's defined
flags, which can be used to indicate some specified status.
If the Crystal oscillator is used, a crystal across
OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator.
No other external components are required. In
stead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors
in OSC1 and OSC2 are required. If the internal
RC oscillator is used, the OSC1 and OSC2 can
be selected as general I/O lines or an 32768Hz
crystal oscillator (RTC OSC). Also, the frequencies of the internal RC oscillator can be
3.2MHz, 1.6MHz, 800kHz and 400kHz (depends on the options).
If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) or
32kHz crystal oscillator (RTC OSC) is strongly
recommended, since the HALT will stop the system clock.
The WDT oscillator is a free running on-chip RC
oscillator, and no external components are required. Even if the system enters the power down
mode, the system clock is stopped, but the WDT
oscillator still works within a period of 78ms. The
WDT oscillator can be disabled by mask option to
conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator), RTC
clock or instruction clock (system clock divided
by 4), determines the mask option. This timer is
designed to prevent a software malfunction or
sequence from jumping to an unknown location
with unpredictable results. The Watchdog
Timer can be disabled by mask option. If the
Watchdog Timer is disabled, all the executions
related to the WDT result in no operation. The
RTC clock is enabled only in the internal
RC+RTC mode.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS register
The WDT overflow under normal operation will
initialize "chip reset" and set the status bit
"TO". But in the HALT mode, the overflow will
initialize a ²warm reset² and only the PC and
SP are reset to zero. To clear the contents of
WDT (including the WDT prescaler), three
methods are adopted; external reset (a low level
to RES), software instruction and a "HALT" instruction. The software instruction include
"CLR WDT" and the other set - "CLR WDT1"
and "CLR WDT2". Of these two types of instruc-
Once the internal WDT oscillator (RC oscillator
with a period of 65ms/5V normally) is selected, it
14
June 14, 2000
Preliminary
tion, only one can be active depending on the
mask option - "CLR WDT times selection option". If the "CLR WDT" is selected (i.e.
CLRWDT times equal one), any execution of
the "CLR WDT" instruction will clear the WDT.
In the case that "CLR WDT1" and "CLR WDT2"
are chosen (i.e. CLRWDT times equal two),
these two instructions must be executed to
clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
abled and the stack is not full, the regular interrupt response takes place. If an interrupt
request flag is set to "1" before entering the
HALT mode, the wake-up function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation.
In other words, a dummy period will be inserted
after a wake-up. If the wake-up results from an
interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the
next instruction execution, this will be executed
immediately after the dummy period is finished.
Power down operation - HALT
The HALT mode is initialized by the "HALT" instruction and results in the following...
· The system oscillator will be turned off but
·
·
·
·
HT48C50-1
To minimize power consumption, all the I/O
pins should be carefully managed before entering the HALT status. The RTC oscillator still
runs in the HALT mode (if the RTC oscillator is
enabled).
the WDT oscillator remains running (if the
WDT oscillator is selected).
The contents of the on chip RAM and registers remain unchanged.
WDT and WDT prescaler will be cleared and
recounted again (if the WDT clock is from the
WDT oscillator).
All of the I/O ports maintain their original status.
The PD flag is set and the TO flag is cleared.
Reset
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
The system can leave the HALT mode by means
of an external reset, an interrupt, an external
falling edge signal on port A or a WDT overflow.
An external reset causes a device initialization
and the WDT overflow performs a "warm reset". After the TO and PD flags are examined,
the reason for chip reset can be determined.
The PD flag is cleared by system power-up or
executing the "CLR WDT" instruction and is set
when executing the "HALT" instruction. The
TO flag is set if the WDT time-out occurs, and
causes a wake-up that only resets the PC and
SP; the others remain in their original status.
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a "warm reset" that resets only the PC
and SP, leaving the other circuits in their original state. Some registers remain unchanged
during other reset conditions. Most registers
are reset to the ²initial condition² when the reset conditions are met. By examining the PD
and TO flags, the program can distinguish between different "chip resets".
TO PD
The port A wake-up and interrupt methods can
be considered as a continuation of normal execution. Each bit in port A can be independently
selected to wake up the device by mask option.
Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two
sequence may occur. If the related interrupt is
disabled or the interrupt is enabled but the
stack is full, the program will resume execution
at the next instruction. If the interrupt is en-
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal
operation
1
1
WDT wake-up HALT
Note: "u" stands for "unchanged"
15
June 14, 2000
Preliminary
The functional unit chip reset status are shown
below.
To guarantee that the system oscillator is
started and stabilized, the SST (System
Start-up Timer) provides an extra-delay of 1024
system clock pulses when the system reset
(power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is
added during the reset period. Any wake-up
from HALT will enable the SST delay.
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
HT48C50-1
PC
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/event
Counter
Off
Input/output
Ports
Input mode
SP
Points to the top of
the stack
R e s e t
Reset timing chart
V
D D
R E S
Reset circuit
H A L T
W a rm
R e s e t
W D T
R E S
O S C 1
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
C o ld
R e s e t
R e s e t
Reset configuration
16
June 14, 2000
Preliminary
HT48C50-1
The states of the registers is summarized in the table.
Reset
(Power On)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
Program
Counter
000H
000H
000H
000H
000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PG
---- -111
---- -111
---- -111
---- -111
---- -uuu
PGC
---- -111
---- -111
---- -111
---- -111
---- -uuu
Register
Note: "*" stands for "warm reset"
"u" stands for "unchanged"
"x" stands for "unknown"
17
June 14, 2000
Preliminary
may come from an external source or from the
system clock divided by 4 or RTC.
Timer/event counter
Two timer/event counters (TMR0, TMR1) are
implemented in the microcontroller. The
timer/event counter 0 contains an 8-bit programmable count-up counter and the clock may
come from an external source or from the system
clock or RTC.
Using the internal clock sources, there are 2
reference time-bases for timer/event counter 0.
The internal clock source can be selected as
coming from fSYS (can always be optioned) or
fRTC (enabled only system oscillator in the Int.
RC+RTC mode) by mask option. The external
clock input allows the user to count external
events, measure time intervals or pulse widths,
The timer/event counter 1 contains an 16-bit
programmable count-up counter and the clock
Label (TMR0C)
PSC0~PSC2
Bits
0~2
HT48C50-1
Function
To define the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS/2 or fRTC/2
001: fINT=fSYS/4 or fRTC/4
010: fINT=fSYS/8 or fRTC/8
011: fINT=fSYS/16 or fRTC/16
100: fINT=fSYS/32 or fRTC/32
101: fINT=fSYS/64 or fRTC/64
110: fINT=fSYS/128 or fRTC/128
111: fINT=fSYS/256 or fRTC/256
TE
3
To define the TMR0 active edge of timer/event counter 0
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer 0 counting
(0=disabled; 1=enabled)
5
Unused bit, read as"0"
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
¾
TM0
TM1
TMR0C register
fS
Y S
fR
T C
M
U
X
8 - s ta g e p r e s c a le r
f IN
8 -1 M U X
D a ta B u s
T
T M 1
T M 0
m a s k o p tio n
P S C 2 ~ P S C 0
T M R 0
T im e r /E v e n t C o u n te r 0
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T im e r /e v e n t
C o u n te r 0
O v e r flo w
to In te rru p t
1 /2
B Z
B Z
Timer/event counter 0
18
June 14, 2000
Preliminary
HT48C50-1
(Timer0/Timer1).
or to generate an accurate time base and PFD
signals.
In the event count or timer mode, once the
timer/event counter 0/1 starts counting, it will
count from the current contents in the
timer/event counter 0/1 to FFH or FFFFH. Once
overflow occurs, the counter is reloaded from the
timer/event counter 0/1 preload register and generates the interrupt request flag (T0F/T1F; bit
5/6 of INTC) at the same time.
Using the internal clock sources, there are 2
reference time-bases for timer/event counter 1.
The internal clock source can be selected as
coming from fSYS/4 (can always be optioned) or
fRTC (enable only the system oscillator in the
Int. RC+RTC mode) by mask option. The external clock input allows the user to count external
events, measure time intervals or pulse widths
or to generate an accurate time base.
In the pulse width measurement mode with
the TON and TE bits equal to one, once the
TMR0/TMR1 has received a transient from low
to high (or high to low if the TE bits is "0") it will
start counting until the TMR0/TMR1 returns to
the original level and resets the TON. The measured result will remain in the timer/event
counter 0/1 even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON,
the cycle measurement will function again as
long as it receives further transient pulse. Note
that, in this operating mode, the timer/event
counter 0/1 starts counting not according to the
logic level but according to the transient edges.
In the case of counter overflows, the counter 0/1
is reloaded from the timer/event counter 0/1
preload register and issues the interrupt request just like the other two modes. To enable
the counting operation, the timer ON bit (TON;
bit 4 of TMR0C/TMR1C) should be set to 1. In
the pulse width measurement mode, the TON
will be cleared automatically after the measurement cycle is completed. But in the other
two modes the TON can only be reset by instructions. The overflow of the timer/event
counter 0/1 is one of the wake-up sources. No
matter what the operation mode is, writing a 0
to ET0I/ET1I can disable the corresponding interrupt services.
There are 2 registers related to the timer/event
counter 0; TMR0 ([0DH]), TMR0C ([0EH]). Two
physical registers are mapped to TMR0 location;
writing TMR0 makes the starting value be placed
in the timer/event counter 0 preload register and
reading TMR0 gets the contents of the timer/event
counter 0. The TMR0C is a timer/event counter
controlregister,whichdefinessomeoptions.
There are 3 registers related to timer/event
counter 1; TMR1H (0FH), TMR1L (10H),
TMR1C (11H). Writing TMR1L will only put
the written data to an internal lower-order byte
buffer (8 bits) and writing TMR1H will transfer
the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L
preload registers, respectively. The timer/event
counter 1 preload register is changed by each
writing TMR1H operations. Reading TMR1H
will latch the contents of TMR1H and TMR1L
counters to the destination and the lower-order
byte buffer, respectively. Reading the TMR1L
will read the contents of the lower-order byte
buffer. The TMR1C is the timer/event counter 1
control register, which defines the operating
mode, counting enable or disable and active
edge.
The TM0, TM1 bits define the operating mode.
The event count mode is used to count external
events, which means the clock source comes
from an external (TMR0/TMR1) pin. The timer
mode functions as a normal timer with the
clock source coming from the fINT clock/instruction clock or RTC clock (Timer0/Timer1). The
pulse width measurement mode can be used to
count the high or low level duration of the external
signal (TMR0/TMR1). The counting is based on
the fINT clock/instruction clock or RTC clock
In the case of timer/event counter 0/1 OFF condition, writing data to the timer/event counter
0/1 preload register will also reload that data to
the timer/event counter 0/1. But if the
timer/event counter 0/1 is turned on, data written to it will only be kept in the timer/event
counter 0/1 preload register. The timer/event
counter 0/1 will still operate until overflow occurs (a timer/event counter 0/1 reloading will oc19
June 14, 2000
Preliminary
ready at the T2 rising edge of instruction "MOV
A,[m]" (m=12H, 14H, 16H, 18H or 1EH). For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
cur at the same time). When the timer/event
counter 0/1 (reading TMR0/TMR1) is read, the
clock will be blocked to avoid errors. As clock
blocking may results in a counting error, this
must be taken into consideration by the programmer.
Each I/O line has its own control register (PAC,
PBC, PCC, PDC, PGC) to control the input/output configuration. With this control register,
CMOS output or schmitt trigger input with or
without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under
software control. To function as an input, the
corresponding latch of the control register must
write "1". The input source also depends on the
control register. If the control register bit is "1",
the input will read the pad state. If the control
register bit is "0", the contents of the latches
will move to the internal bus. The latter is possible in the "read-modify-write" instruction.
The bit0~bit2 of the TMR0C can be used to define the pre-scaling stages of the internal clock
sources of timer/event counter 0. The definitions are as shown. The overflow signal of
timer/event counter 0 can be used to generate
PFD signals for buzzer driving.
Input/output ports
There are 35 bidirectional input/output lines in
the microcontroller, labeled from PA to PD and
PG, which are mapped to the data memory of
[12H], [14H], [16H], [18H] and [1EH] respectively. All of these I/O ports can be used for input
and output operations. For input operation, these
ports are non-latching, that is, the inputs must be
Label (TMR1C)
Bits
¾
0~2
HT48C50-1
For output function, CMOS is the only configuration. These control registers are mapped to
locations 13H, 15H, 17H, 19H and 1FH.
Function
Unused bit, read as"0"
TE
3
To define the TMR1 active edge of timer/event counter 1
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer 1 counting
(0=disabled; 1=enabled)
5
Unused bit, read as"0"
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
¾
TM0
TM1
TMR1C register
fS
Y S /4
fR
T C
M
U
D a ta B u s
T M 1
T M 0
X
T M R 1
m a s k o p tio n
1 6 B its
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
L o w B y te
B u ffe r
1 6 B its
T im e r /E v e n t C o u n te r
(T M R 1 H /T M R 1 L )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/event counter 1
20
June 14, 2000
Preliminary
HT48C50-1
There is a pull-high option available for all I/O
lines (bit option). Once the pull-high option of
an I/O line is selected, the I/O line have
pull-high resistor. Otherwise, the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode
will cause a floating state.
After a chip reset, these input/output lines remain at high levels or floating state (depending
on the pull-high options). Each bit of these input/output latches can be set or cleared by "SET
[m].i" and "CLR [m].i" (m=12H, 14H, 16H, 18H
or 1EH) instructions.
Some instructions first input data and then follow the output operations. For example, "SET
[m].i", "CLR [m].i", "CPL [m]", "CPLA [m]" read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or the accumulator.
The PB0 and PB1 are pin-shared with BZ and
BZ signal, respectively. If the BZ/BZ option is
selected, the output signal in output mode of
PB0/PB1 will be the PFD signal generated by
timer/event counter 0 overflow signal. The input mode always remain in its original functions. Once the BZ/BZ option is selected, the
buzzer output signals are controlled by the PB0
data register only. The I/O functions of
PB0/PB1 are shown below.
Each line of port A has the capability of waking-up the device. The highest 5-bit of port G are
not physically implemented; on reading them a
"0" is returned whereas writing then results in
no-operation. See Application note.
PB0 I/O
I
I
O
O
O
O
O
O
O
O
PB1 I/O
I
O
I
I
I
O
O
O
O
O
PB0 Mode
x
x
C
B
B
C
B
B
B
B
PB1 Mode
x
C
x
x
x
C
C
C
B
B
PB0 Data
x
x
D
0
1
D0
0
1
0
1
PB1 Data
x
D
x
x
x
D1
D
D
x
x
PB0 Pad Status
I
I
D
0
B
D0
0
B
0
B
PB1 Pad Status
I
D
I
I
I
D1
D
D
0
B
Note: ²I² input, ²O² output, ²D, D0, D1² data,
²B² buzzer option, BZ or BZ, ²x² don't care
²C² CMOS output
21
June 14, 2000
Preliminary
HT48C50-1
will ignore it and do not perform a reset function.
· The LVR uses the ²OR² function with the external RES signal to perform chip reset.
The PG0 is pin-shared with INT.
In case of ²Internal RC+I/O² system oscillator,
the PG1 and PG2 are pin-shared with OSC1
and OSC2 pins. Once the ²Internal RC+I/O²
mode is selected, the PC3 and PC4 can be used
as general purpose I/O lines. Otherwise, the
pull-high resistors and I/O functions of PG1
and PG2 will be disabled.
The relationship between VDD and VLVR is
shown below.
V D D
5 .5 V
It is recommended that unused or not bonded
out I/O lines should be set as output pins by
software instruction to avoid consuming power
under input floating state.
V
O P R
5 .5 V
V
2 .2 V
Low voltage reset - LVR
2 .0 V
The microcontroller provides low voltage reset
circuit in order to monitor the supply voltage of
the device. If the supply voltage of the device is
within the range 0.9V~VLVR (2.2V or 3.3V),
such as changing a battery, the LVR will automatically reset the device internally.
L V R
o r 3 .3 V
o r 3 .0 V
0 .9 V
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in
their original state to exceed 1ms. If the low
voltage state does not exceed 1ms, the LVR
P G 1 /P G 2 I/O
C o n tr o l B it
D a ta B u s
C K
P U
S
P A 0
P B 0
P C 0
P D 0
P G 0
D a ta B it
Q
D
C K
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
P B 0
E X T
~ P A
~ P B
~ P C
~ P D
~ P G
7
7
7
7
2
Q B
S
( P B 0 , P B 1 O n ly )
D D
Q B
C h ip R e s e t
R e a d C o n tr o l R e g is te r
V
Q
D
W r ite C o n tr o l R e g is te r
m o d e o n ly
M
M
U
X
U
X
E X T E N
( P B 0 , P B 1 O n ly )
O P 0 ~ O P 7
IN T fo r P G 0 O n ly
E X T = B Z fo r P B 0 o n ly , E X T = B Z fo r P B 1 o n ly , c o n tr o l= P B 0 d a ta r e g is te r
Input/output ports
22
June 14, 2000
Preliminary
V
HT48C50-1
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low voltage reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of
1024 system clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms
delay enters the reset mode.
Mask option
The following table shows all kinds of mask option in the microcontroller. All of the mask options
must be defined to ensure proper system functioning.
Items
Option
1
WDT clock source: WDTOSC/fTID/RTCOSC/disable
2
CLRWDT instructions: 1 or 2 instructions
3
Timer/event counter 0 clock sources: fSYS or RTCOSC
4
Timer/event counter 1 clock sources: fSYS/4 or RTCOSC
5
PA wake-up
6
PA, PB, PC, PD CMOS/SCHMITT input
7
PA, PB, PC, PD, PG pull-high enable/disable
8
BZ/BZ enable/disable
9
LVR enable/disable
10
LVR voltage: 2.2V or 3.3V
11
System oscillator
Ext. RC, Ext.crystal, Int.RC+RTC or Int.RC+PC3/PC4
12
Int.RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz
23
June 14, 2000
Preliminary
HT48C50-1
Application Circuits
RC oscillator for multiple I/O applications
V
Crystal or ceramic resonator for multiple I/O
applications
V
D D
P A 0 ~ P A 7
V D D
1 0 0 k W
C 1
P D 0 ~ P D 7
4 7 0 p F
N M O S
o p e n d r a in
0 .1 m F
0 .1 m F
O S C 2 /P G 2
P B 0 /B Z
O S C 1 /P G 1
P D 0 ~ P D 7
O S C 2 /P G 2
P B 0 /B Z
P B 1 /B Z
R E S
V S S
T M R 0
IN T /P G 0
P C 0 ~ P C 7
C 2
0 .1 m F
P B 1 /B Z
R E S
V S S
P B 2 ~ P B 7
1 0 0 k W
P C 0 ~ P C 7
O S C 1 /P G 1
P A 0 ~ P A 7
V D D
P B 2 ~ P B 7
5 1 k W ~
1 M W
0 .1 m F
D D
T M R 0
IN T /P G 0
T M R 1
H T 4 8 C 5 0 -1
T M R 1
H T 4 8 C 5 0 -1
Note: C1=C2=300pF if fSYS<1MHz
Otherwise, C1=C2=0
Internal RC oscillator for multiple I/O
applications
V
Internal RC oscillator with RTC for multiple I/O
applications
V
D D
P A 0 ~ P A 7
V D D
P A 0 ~ P A 7
V D D
P B 2 ~ P B 7
1 0 0 k W
P B 2 ~ P B 7
1 0 0 k W
P C 0 ~ P C 7
O S C 1 /P G 1
P C 0 ~ P C 7
P D 0 ~ P D 7
0 .1 m F
0 .1 m F
D D
0 .1 m F
O S C 2 /P G 2
P B 0 /B Z
0 .1 m F
P B 1 /B Z
R E S
V S S
P D 0 ~ P D 7
O S C 2 /P G 2
P B 0 /B Z
3 2 7 6 8 H z
P B 1 /B Z
R E S
V S S
T M R 0
IN T /P G 0
O S C 1 /P G 1
T M R 0
IN T /P G 0
T M R 1
H T 4 8 C 5 0 -1
T M R 1
H T 4 8 C 5 0 -1
Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure
that the VDD is stable and remains within a valid operating voltage range before bringing
RES to high.
24
June 14, 2000
Preliminary
HT48C50-1
Instruction Set Summary
Mnemonic
Description
Instruction
Cycle
Flag
Affected
1
1(1)
1
1
1(1)
1
1
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
1
1(1)
Z,C,AC,OV
Z,C,AC,OV
1(1)
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1(1)
1
1(1)
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to register with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data
memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result
in data memory
Decimal adjust ACC for addition with result in data
memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
25
June 14, 2000
Preliminary
HT48C50-1
Instruction
Cycle
Flag
Affected
1
1(1)
1
None
None
C
1(1)
1
1(1)
1
C
None
None
C
1(1)
C
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement
ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result
ACC
Skip if decrement data memory is zero with result
ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data
ACC
Return from interrupt
to
2
1(2)
1(2)
None
None
None
in
1(2)
1(2)
1(3)
1(3)
1(2)
None
None
None
None
None
in
1(2)
None
to
2
2
2
None
None
None
2
None
Mnemonic
Description
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in
ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in
ACC
Rotate data memory left through carry
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
26
June 14, 2000
Preliminary
Mnemonic
Description
HT48C50-1
Instruction
Cycle
Flag
Affected
2(1)
None
2(1)
None
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PD
TO(4),PD(4)
TO(4),PD(4)
None
None
TO,PD
Table Read
TABRDC [m] Read ROM code (current page) to data memory and
TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
Note: x: 8 bits immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed
for one more cycle (four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by
executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared.
Otherwise the TO and PD flags remain unchanged.
27
June 14, 2000
Preliminary
HT48C50-1
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving
the result in the accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
28
June 14, 2000
Preliminary
HT48C50-1
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise
logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC "AND" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC "AND" x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise
logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC "AND" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
29
June 14, 2000
Preliminary
HT48C50-1
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated
address. The program counter increments once to obtain the address of the
next instruction, and pushes this onto the stack. The indicated address is
then loaded. Program execution continues with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT and the WDT Prescaler are cleared (re-counting from 0). The
power down bit (PD) and time-out bit (TO) are cleared.
Operation
WDT and WDT Prescaler ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
0
¾
¾
¾
¾
30
June 14, 2000
Preliminary
HT48C50-1
CLR WDT1
Preclear Watchdog Timer
Description
The TD, PD flags, WDT and the WDT Prescaler has cleared (re-counting
from 0), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction just sets the
indicated flag which implies this instruction has been executed and the TO
and PD flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting
from 0), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and
PD flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1's complement). Bits which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
31
June 14, 2000
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HT48C50-1
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1's complement). Bits which previously contained a 1 are changed to 0 and vice-versa.
The complemented result is stored in the accumulator and the contents of
the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Code Decimal) code.
The accumulator is divided into two nibbles. Each nibble is adjusted to the
BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the
original value if the original value is greater than 9 or a carry (AC or C) is set;
otherwise the original value remains unchanged. The result is stored in the
data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
32
June 14, 2000
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HT48C50-1
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in
the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The
contents of the RAM and registers are retained. The WDT and prescaler are
cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is
cleared.
Operation
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
INC [m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
1
¾
¾
¾
¾
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in
the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
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HT48C50-1
JMP addr
Directly jump
Description
Bits of the program counter are replaced with the directly-specified address
unconditionally, and control is passed to this destination.
Operation
PC ¬ addr
Affected flag(s)
MOV A,[m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one
of the data memories).
Operation
[m] ¬ ACC
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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June 14, 2000
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HT48C50-1
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data
memories) perform a bitwise logical_OR operation. The result is stored in the
accumulator.
Operation
ACC ¬ ACC "OR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR
operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC "OR" x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator
perform a bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ ACC "OR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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June 14, 2000
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HT48C50-1
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded
with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled
by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0;
register INTC).
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into
bit 0, leaving the rotated result in the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
36
June 14, 2000
Preliminary
HT48C50-1
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit
left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0
position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit
7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the
data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0
rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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June 14, 2000
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HT48C50-1
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into
bit 7, leaving the rotated result in the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated
into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right.
Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7
position. The rotated result is stored in the accumulator. The contents of the
data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
38
June 14, 2000
Preliminary
HT48C50-1
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the data
memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result
is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
39
June 14, 2000
Preliminary
HT48C50-1
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result
is 0, the next instruction is skipped. The result is stored in the accumulator
but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and
a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m].i
Set bit of data memory
Description
Bit "i" of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result
is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction
(2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
40
June 14, 2000
Preliminary
HT48C50-1
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result
is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and
a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit "i" of the data memory is not 0
Description
If bit "i" of the specified data memory is not 0, the next instruction is skipped.
If bit "i" of the data memory is not 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the
next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
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June 14, 2000
Preliminary
HT48C50-1
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of
the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the
data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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June 14, 2000
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HT48C50-1
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If
the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1
cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit "i" of the data memory is 0
Description
If bit "i" of the specified data memory is 0, the following instruction, fetched
during the current instruction execution, is discarded and a dummy cycle is
replaced to get the proper instruction (2 cycles). Otherwise proceed with the
next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer
(TBLP) is moved to the specified data memory and the high byte transferred
to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP)
is moved to the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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June 14, 2000
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HT48C50-1
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise
logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC "XOR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise
logical Exclusive_OR operation. The result is stored in the data memory. The
0 flag is affected.
Operation
[m] ¬ ACC "XOR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is
affected.
Operation
ACC ¬ ACC "XOR" x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
44
June 14, 2000
Preliminary
HT48C50-1
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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June 14, 2000