FEATURES True rms-to-dc conversion Laser trimmed to high accuracy ±0.2% maximum error (AD536AK) ±0.5% maximum error (AD536AJ) Wide response capability Computes rms of ac and dc signals 450 kHz bandwidth: V rms > 100 mV 2 MHz bandwidth: V rms > 1 V Signal crest factor of 7 for 1% error dB output with 60 dB range Low power: 1.2 mA quiescent current Single- or dual-supply operation Monolithic integrated circuit −55°C to +125°C operation (AD536AS) GENERAL DESCRIPTION The AD536A is a complete monolithic integrated circuit that performs true rms-to-dc conversion. It offers performance comparable or superior to that of hybrid or modular units costing much more. The AD536A directly computes the true rms value of any complex input waveform containing ac and dc components. A crest factor compensation scheme allows measurements with 1% error at crest factors up to 7. The wide bandwidth of the device extends the measurement capability to 300 kHz with less than 3 dB errors for signal levels greater than 100 mV. An important feature of the AD536A, not previously available in rms converters, is an auxiliary dB output pin. The logarithm of the rms output signal is brought out to a separate pin to allow the dB conversion, with a useful dynamic range of 60 dB. Using an externally supplied reference current, the 0 dB level can be conveniently set to correspond to any input level from 0.1 V to 2 V rms. The AD536A is laser trimmed to minimize input and output offset voltage, to optimize positive and negative waveform symmetry (dc reversal error), and to provide full-scale accuracy at 7 V rms. As a result, no external trims are required to achieve the rated unit accuracy. The input and output pins are fully protected. The input circuitry can take overload voltages well beyond the supply levels. Loss of supply voltage with the input connected to external circuitry does not cause the device to fail. The output is short-circuit protected. FUNCTIONAL BLOCK DIAGRAM AD536A +VS VIN ABSOLUTE VALUE COM SQUARER/ DIVIDER dB + CAV CURRENT MIRROR 25kΩ RL IOUT BUFFER IN BUF 25kΩ 80kΩ BUFFER OUT 00504-001 Data Sheet Integrated Circuit True RMS-to-DC Converter AD536A –VS Figure 1. The AD536A is available in two accuracy grades (J and K) for commercial temperature range (0°C to 70°C) applications, and one grade (S) rated for the −55°C to +125°C extended range. The AD536AK offers a maximum total error of ±2 mV ± 0.2% of reading, while the AD536AJ and AD536AS have maximum errors of ±5 mV ± 0.5% of reading. All three versions are available in a hermetically sealed 14-lead DIP or a 10-pin TO-100 metal header package. The AD536AS is also available in a 20-terminal leadless hermetically sealed ceramic chip carrier. The AD536A computes the true root-mean-square level of a complex ac (or ac plus dc) input signal and provides an equivalent dc output level. The true rms value of a waveform is a more useful quantity than the average rectified value because it relates directly to the power of the signal. The rms value of a statistical signal also relates to its standard deviation. An external capacitor is required to perform measurements to the fully specified accuracy. The value of this capacitor determines the low frequency ac accuracy, ripple amplitude, and settling time. The AD536A operates equally well from split supplies or a single supply with total supply levels from 5 V to 36 V. With 1 mA quiescent supply current, the device is well suited for a wide variety of remote controllers and battery-powered instruments. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1976–2012 Analog Devices, Inc. All rights reserved. Powered by TCPDF (www.tcpdf.org) IMPORTANT LINKS for the AD536A* Last content update 09/07/2013 04:37 pm PARAMETRIC SELECTION TABLES DESIGN COLLABORATION COMMUNITY Find Similar Products By Operating Parameters Collaborate Online with the ADI support team and other designers about select ADI products. DOCUMENTATION AD536A Military Data Sheet AN-653: Improving Temperature, Stability, and Linearity of High Dynamic Range RMS RF Power Detectors AN-214: Ground Rules for High Speed Circuits AN-268: RMS-to-DC Converters Ease Measurement Tasks RMS-to-DC Application Guide Second Edition Follow us on Twitter: www.twitter.com/ADI_News Like us on Facebook: www.facebook.com/AnalogDevicesInc * Section I: RMS-DC Conversion - Theory * Section II: RMS-DC Conversion - Basic Design Considerations * Section III: RMS Application Circuits * Appendix A: Testing the Critical Parameters of RMS Converters * Appendix B: Input Buffer Amplifier Requirements * Appendix C: Computer Programs for Determining Computational Errors, Output Ripple, and 1% Settling Time of RMS Converter * Appendix D: New Products Appendix to the RMS-to-DC Conversion Application Guide (October 2002) * Download the entire guide in .zip format Introduction to Analog RMS-to-DC Technology: Converters and Applications Audio Version Introduction to Analog RMS-to-DC Technology: Converters and Applications Non-Audio Version ADI Warns Against Misuse of COTS Integrated Circuits Space Qualified Parts List Linear and Data Converters Embedded Processing and DSP DESIGN SUPPORT Submit your support request here: Telephone our Customer Interaction Centers toll free: Americas: Europe: China: India: Russia: 1-800-262-5643 00800-266-822-82 4006-100-006 1800-419-0108 8-800-555-45-90 Quality and Reliability Lead(Pb)-Free Data SAMPLE & BUY AD536A View Price & Packaging Request Evaluation Board Request Samples Check Inventory & Purchase Find Local Distributors DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE AD536A SPICE Macro Model EVALUATION KITS & SYMBOLS & FOOTPRINTS Symbols and Footprints * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page (labeled 'Important Links') does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. AD536A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Frequency Response .....................................................................9 General Description ......................................................................... 1 AC Measurement Accuracy and Crest Factor ...........................9 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 11 Revision History ............................................................................... 2 Typical Connections .................................................................. 11 Specifications..................................................................................... 3 Optional External Trims For High Accuracy ......................... 11 Absolute Maximum Ratings ............................................................ 5 Single-Supply Operation ........................................................... 12 ESD Caution .................................................................................. 5 Choosing the Averaging Time Constant ................................. 12 Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions ....................................................................... 14 Theory of Operation ........................................................................ 8 Ordering Guide .......................................................................... 15 Connections for dB Operation ................................................... 8 REVISION HISTORY 7/12—Rev. D to Rev. E Reorganized Layout ............................................................ Universal Changes to Figure 1 .......................................................................... 1 Changes to Figure 6 .......................................................................... 8 Changes to Figure 7 .......................................................................... 9 Changes to Figure 13, Figure 14, and Figure 15 ......................... 11 Changes to Figure 16, Figure 17, and Single-Supply Operation Section .............................................................................................. 12 Changes to Figure 21 ...................................................................... 13 Updated Outline Dimensions ....................................................... 14 8/08—Rev. C to Rev. D Changes to Features Section............................................................ 1 Changes to General Description Section ...................................... 1 Changes to Figure 1 .......................................................................... 1 Changes to Table 2 ............................................................................ 5 Change to Figure 2 ........................................................................... 5 Changes to Figure 15 ...................................................................... 10 Changes to Connections for dB Operation Section ................... 11 Changes to Figure 17 ...................................................................... 12 Changes to Frequency Response Section .................................... 12 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 15 3/06—Rev. B to Rev. C Updated Format .................................................................. Universal Changed Product Description to General Description ................1 Changes to General Description .....................................................1 Changes to Table 1.............................................................................3 Changes to Table 2.............................................................................5 Added Pin Configurations and Function Descriptions ...............6 Changed Standard Connection to Typical Connections .............8 Changed Single Supply Connection to Single Supply Operation............................................................................................9 Changes to Connections for dB Operation................................. 11 Changes to Figure 17...................................................................... 12 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 15 6/99—Rev. A to Rev. B 1/76—Revision 0: Initial Version Rev. E | Page 2 of 16 Data Sheet AD536A SPECIFICATIONS TA = +25°C and ±15 V dc, unless otherwise noted. Table 1. Parameter TRANSFER FUNCTION CONVERSION ACCURACY Total Error, Internal Trim 1 (See Figure 13) vs. Temperature TMIN to +70°C +70°C to +125°C vs. Supply Voltage AD536AJ Typ Max VOUT = √Avg(VIN)2 Min AD536AK Typ Max VOUT = √Avg(VIN)2 mV ± % of rdg ±0.1 ± 0.01 ±0.05 ± 0.005 ±0.1 ± 0.005 ±0.3 ± 0.005 mV ± % of rdg/°C mV ± % of rdg/°C mV ± % of rdg/°C ±0.1 ± 0.01 ±0.1 ±0.01 ±0.2 ±3 ± 0.3 ±0.1 ±2 ± 0.1 Specified accuracy −0.1 −1.0 mV ± % of rdg mV ± % of rdg Specified accuracy −0.1 −1.0 % of rdg % of rdg 5 45 120 5 45 120 5 45 120 kHz kHz kHz 90 450 2.3 25 90 450 2.3 25 90 450 2.3 25 kHz kHz MHz ms/µF 0 to 7 ±20 0 to 2 V rms V peak V rms 0 to 2 ±7 ±7 V peak ±25 ±25 ±25 V peak 20 ±2 kΩ mV ±2 mV ±0.2 mV/°C mV/V V V ±0.6 dB mV/dB dB/°C 20 ±2 ±1 ±2 ±0.1 ±0.1 +12.5 +0.33 20 ±20 ±7 16.67 0.8 ±0.4 −3 −0.033 0 to 7 ±20 0 to 2 5 1 Unit ±5 ± 0.5 0 to 7 0 to +11 0 to +2 AD536AS Typ Max VOUT = √Avg(VIN)2 ±2 ± 0.2 Specified accuracy −0.1 −1.0 13.33 Min ±5 ± 0.5 ±0.1 ±0.01 ±0.2 ±3 ± 0.3 dc Reversal Error Total Error, External Trim1 (See Figure 16) ERROR VS. CREST FACTOR 2 Crest Factor 1 to Crest Factor 2 Crest Factor = 3 Crest Factor = 7 FREQUENCY RESPONSE 3 Bandwidth for 1% Additional Error (0.09 dB) VIN = 10 mV VIN = 100 mV VIN = 1 V ±3 dB Bandwidth VIN = 10 mV VIN = 100 mV VIN = 1 V AVERAGING TIME CONSTANT (See Figure 19) INPUT CHARACTERISTICS Signal Range, ±15 V Supplies Continuous RMS Level Peak Transient Input Continuous RMS Level, VS = ±5 V Peak Transient Input, VS = ±5 V Maximum Continuous Nondestructive Input Level (All Supply Voltages) Input Resistance Input Offset Voltage OUTPUT CHARACTERISTICS Offset Voltage, VIN = COM (See Figure 13) vs. Temperature vs. Supply Voltage Voltage Swing, ±15 V Supplies ± 5 V Supply dB OUTPUT, 0 dB = 1 V rms (See Figure 7) Error, 7 mV < VIN < 7 V rms Scale Factor Scale Factor Temperature Coefficient Uncompensated IREF for 0 dB = 1 V rms IREF Range Min 13.33 0 to +11 0 to +2 ±0.6 80 100 16.67 0.5 20 ±1 ±0.5 ±1 ±0.1 ±0.1 +12.5 ±0.2 −3 −0.033 5 1 +0.33 20 Rev. E | Page 3 of 16 13.33 0 to +11 0 to +2 ±0.3 80 100 16.67 0.8 ±0.2 +12.5 ±0.5 −3 −0.033 5 1 +0.33 20 80 100 % of rdg/°C µA µA AD536A Parameter IOUT TERMINAL IOUT Scale Factor IOUT Scale Factor Tolerance Output Resistance Voltage Compliance BUFFER AMPLIFIER Input and Output Voltage Range Input Offset Voltage, RS = 25 kΩ Input Bias Current Input Resistance Output Current Short-Circuit Current Output Resistance Small-Signal Bandwidth Slew Rate 4 POWER SUPPLY Voltage Rated Performance Dual Supply Single Supply Quiescent Current Total VS, 5 V to 36 V, TMIN to TMAX TEMPERATURE RANGE Rated Performance Storage NUMBER OF TRANSISTORS Data Sheet Min 20 AD536AJ Typ Max 40 ±10 ±20 25 30 −VS to (+VS − 2.5 V) −VS to (+VS − 2.5V) Min AD536AK Typ Max 40 ±10 ±20 25 30 −VS to (+VS − 2.5 V) 20 −VS to (+VS − 2.5V) ±0.5 20 108 ±4 60 (+5 mA, −130 µA) 0 −55 1 5 ±15 ±3.0 +5 2 +70 +150 65 0.5 1 5 ±15 ±4 60 20 0.5 1 5 µA/V rms % kΩ V V ±0.5 20 108 20 ±18 +36 40 ±10 ±20 25 30 −VS to (+VS − 2.5 V) Unit mV nA Ω (+5 mA, −130 µA) 0.5 1.2 20 ±4 60 (+5 mA, −130 µA) ±3.0 +5 AD536AS Typ Max −VS to (+VS − 2.5V) ±0.5 20 108 20 Min ±15 ±18 +36 1.2 0 −55 2 +70 +150 65 1 ±3.0 +5 1.2 −55 −55 65 Accuracy is specified for 0 V to 7 V rms, dc or 1 kHz sine wave input with the AD536A connected as in the figure referenced. Error vs. crest factor is specified as an additional error for 1 V rms rectangular pulse input, pulse width = 200 μs. Input voltages are expressed in volts rms, and error is expressed as a percentage of the reading. 4 With 2kΩ external pull-down resistor. 2 3 Rev. E | Page 4 of 16 mA Ω MHz V/µs ±18 +36 V V V 2 mA +125 +150 °C °C Data Sheet AD536A ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Dual Supply Single Supply Internal Power Dissipation Maximum Input Voltage Buffer Maximum Input Voltage Maximum Input Voltage Storage Temperature Range Operating Temperature Range AD536AJ/AD536AK AD536AS Lead Temperature (Soldering, 60 sec) ESD Rating Thermal Resistance θJA1 10-Pin Header (H-10 Package) 20-Terminal LCC (E-20 Package) 14-Lead SBDIP (D-14 Package) 14-Lead CERDIP (Q-14 Package) ±18 V +36 V 500 mW ±25 V peak ±VS ±25 V peak −55°C to +150°C ESD CAUTION 0°C to +70°C −55°C to +125°C 300°C 1000 V 150°C/W 95°C/W 95°C/W 95°C/W θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. 0.1315 (3.340) COM 10 +VS 14 RL 9 IOUT 8 0.0807 (2.050) VIN 1A1 VIN 1B1 BUF IN 7 –VS CAV dB BUF OUT 3 4 5 6 PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE TO-100 14-LEAD CERAMIC DIP PACKAGE. 1BOTH PADS SHOWN MUST BE CONNECTED TO V . IN THE AD536A IS AVAILABLE IN LASER-TRIMMED CHIP FORM. SUBSTRATE CONNECTED TO –VS. Figure 2. Die Dimensions and Pad Layout Dimensions shown in inches and (millimeters) Rev. E | Page 5 of 16 00504-002 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating AD536A Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VIN 1 14 +VS NC 2 13 NC 12 NC –VS 3 AD536A TOP VIEW 11 NC (Not to Scale) 10 COM dB 5 BUF OUT 6 9 RL BUF IN 7 8 IOUT NC = NO CONNECT 00504-003 CAV 4 Figure 3. D-14 and Q-14 Packages Pin Configuration Table 3. D-14 and Q-14 Packages Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic VIN NC −VS CAV dB BUF OUT BUF IN IOUT RL COM NC NC NC +VS Description Input Voltage No Connection Negative Supply Voltage Averaging Capacitor Log (dB) Value of the RMS Output Voltage Buffer Output Buffer Input RMS Output Current Load Resistor Common No Connection No Connection No Connection Positive Supply Voltage IOUT BUF IN 10 1 COM 2 9 AD536A TOP VIEW (Not to Scale) +VS 3 4 VIN 8 BUF OUT 7 dB 6 5 CAV –VS 00504-004 RL Figure 4. H-10 Package Pin Configuration Table 4. H-10 Package Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic RL COM +VS VIN −VS CAV dB BUF OUT BUF IN IOUT Description Load Resistor Common Positive Supply Voltage Input Voltage Negative Supply Voltage Averaging Capacitor Log (dB) Value of the RMS Output Voltage Buffer Output Buffer Input RMS Output Current Rev. E | Page 6 of 16 +VS NC 2 1 20 19 –VS 4 NC 5 AD536A CAV 6 TOP VIEW (Not to Scale) NC 7 9 10 11 12 13 BUF OUT BUF IN NC IOUT RL dB 8 18 NC 17 NC 16 NC 15 NC 14 COM NC = NO CONNECT 00504-005 VIN 3 NC AD536A NC Data Sheet Figure 5. E-20 Package Pin Configuration Table 5. E-20 Package Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic NC VIN NC −VS NC CAV NC dB BUF OUT BUF IN NC IOUT RL COM NC NC NC NC NC +VS Description No Connection Input Voltage No Connection Negative Supply Voltage No Connection Averaging Capacitor No Connection Log (dB) Value of the RMS Output Voltage Buffer Output Buffer Input No Connection RMS Output Current Load Resistor Common No Connection No Connection No Connection No Connection No Connection Positive Supply Voltage Rev. E | Page 7 of 16 AD536A Data Sheet THEORY OF OPERATION The AD536A embodies an implicit solution of the rms equation that overcomes the dynamic range as well as other limitations inherent in a straightforward computation of rms. The actual computation performed by the AD536A follows the equation V 2 V rms = Avg IN V rms VOUT = 2R2 × I rms = VIN rms Figure 6 is a simplified schematic of the AD536A. Note that it is subdivided into four major sections: absolute value circuit (active rectifier), squarer/divider, current mirror, and buffer amplifier. The input voltage (VIN), which can be ac or dc, is converted to a unipolar current (I1) by the active rectifiers (A1, A2). I1 drives one input of the squarer/divider, which has the transfer function 2 I4 = II /I3 The output current, I4, of the squarer/divider drives the current mirror through a low-pass filter formed by R1 and the externally connected capacitor, CAV. If the R1 CAV time constant is much greater than the longest period of the input signal, then I4 is effectively averaged. The current mirror returns a current I3, which equals Avg[I4], back to the squarer/divider to complete the implicit rms computation. Thus, I4 = Avg[II2/I4] = II rms CURRENT MIRROR 14 +VS 10 COM 4 A3 I2 I1 VIN Q3 Q2 A1 12kΩ Q4 R2 25kΩ RL 25kΩ ONE-QUADRANT SQUARER/DIVIDER NOTES 1. PINOUTS ARE FOR 14-LEAD DIP. Figure 6. Simplified Schematic 80kΩ The dB output is derived from the emitter of Q3 because the voltage at this point is proportional to –log VIN. The emitter follower, Q5, buffers and level shifts this voltage so that the dB output voltage is zero when the externally supplied emitter current (IREF) to Q5 approximates I3. CONNECTIONS FOR dB OPERATION The logarithmic (or decibel) output of the AD536A is one of its most powerful features. The internal circuit computing dB works accurately over a 60 dB range. The connections for dB measurements are shown in Figure 7. Select the 0 dB level by adjusting R1 for the proper 0 dB reference current (which is set to cancel the log output current from the squarer/divider at the desired 0 dB point). The external op amp provides a more convenient scale and allows compensation of the +0.33%/°C scale factor drift of the dB output pin. The temperature-compensating resistor, R2, is available online in several styles from Precision Resistor Company, Inc., (Part Number AT35 and Part Number ST35). The average temperature coefficients of R2 and R3 result in the +3300 ppm required to compensate for the dB output. The linear rms output is available at Pin 8 on the DIP or Pin 10 on the header device with an output impedance of 25 kΩ. Some applications require an additional buffer amplifier if this output is desired. 5 For dB calibration, 6 1. 2. 3. 4. Q5 A2 12kΩ 9 8 IOUT BUF IN BUFFER dB OUT 7 A4 Q1 |VIN|R–1 1 R3 25kΩ R1 0.4mA 25kΩ FS I3 BUF OUT 3 –VS 00504-106 0.2mA FS ABSOLUTE VALUE; VOLTAGE-CURRENT CONVERTER R4 50kΩ The current mirror also produces the output current, IOUT, which equals 2I4. IOUT can be used directly or can be converted to a voltage with R2 and buffered by A4 to provide a low impedance voltage output. The transfer function of the AD536A results in the following: Set VIN = 1.00 V dc or 1.00 V rms. Adjust R1 for dB output = 0.00 V. Set VIN = +0.1 V dc or 0.10 V rms. Adjust R5 for dB output = −2.00 V. Any other desired 0 dB reference level can be used by setting VIN and adjusting R1 accordingly. Note that adjusting R5 for the proper gain automatically provides the correct temperature compensation. Rev. E | Page 8 of 16 Data Sheet AD536A VIN NC 2 –VS –VS + C1, CAV +VS C2 CAV dB 0.1µF BUF OUT dB OUT 3mV/dB BUF IN ABSOLUTE VALUE 1 14 +VS 4.6V TO 18V +E AD536A 13 NC SQUARER/ DIVIDER 3 +VS 12 NC EOUT AD580J 2.5V R4 33.2kΩ 11 NC 4 CURRENT MIRROR 5 6 10 9 25kΩ 8 BUF 7 COM RL IOUT –E R1 500kΩ 0dB REF ADJUST dB SCALE FACTOR ADJUST +VS 7 R6 24.9kΩ LINEAR rms OUTPUT R5 5kΩ 2 R3 60.4Ω OP77 6 TEMPERATURE COMPENSATED dB OUTPUT +100mV/dB 3 4 R21 1kΩ 00504-107 –VS 1SPECIAL TC COMPENSATION RESISTOR, +3300ppm/°C, PRECISION RESISTOR COMPANY PART NUMBER AT 35 OR PART NUMBER ST35. Figure 7. dB Connection FREQUENCY RESPONSE The AD536A utilizes a logarithmic circuit in performing the implicit rms computation. As with any log circuit, bandwidth is proportional to signal level. The solid lines in the graph of Figure 8 represent the frequency response of the AD536A at input levels from 10 mV rms to 7 V rms. The dashed lines indicate the upper frequency limits for 1%, 10%, and ±3 dB of reading additional error. For example, note that a 1 V rms signal produces less than 1% of reading additional error up to 120 kHz. A 10 mV signal can be measured with 1% of reading additional error (100 µV) up to only 5 kHz. Figure 9 illustrates a curve of reading error for the AD536A for a 1 V rms input signal with crest factors from 1 to 11. A rectangular pulse train (pulse width = 100 µs) was used for this test because it is the worst-case waveform for rms measurement (all of the energy is contained in the peaks). The duty cycle and peak amplitude were varied to produce crest factors from 1 to 11 while maintaining a constant 1 V rms input amplitude. T өO η = DUTY CYCLE = CF = 1/√η өIN (rms) = 1 V rms VP 0 100µs T 100µs 1 VOUT (V) 10% ±3dB 1V rms INPUT 0.1 100mV rms INPUT 0.01 1k 10k 100k FREQUENCY (Hz) 1M 10M 00504-016 10mV rms INPUT 0 –1 –2 –3 –4 1 2 3 4 Figure 8. High Frequency Response 5 6 7 CREST FACTOR 8 9 10 Figure 9. Error vs. Crest Factor Crest factor is often overlooked when determining the accuracy of an ac measurement. The definition of crest factor is the ratio of the peak signal amplitude to the rms value of the signal (CF = VP/V rms). Most common waveforms, such as sine and triangle waves, have relatively low crest factors (<2). Waveforms that resemble low duty cycle pulse trains, such as those occurring in switching power supplies and SCR circuits, have high crest factors. For example, a rectangular pulse train with a 1% duty cycle has a crest factor of 10 (CF = 1√n). Rev. E | Page 9 of 16 INCREASE IN ERROR (% OF READING) AC MEASUREMENT ACCURACY AND CREST FACTOR 10 1V rms CF = 10 1 0.1 1µs 1V rms CF = 3 10µs 100µs PULSE WIDTH (µs) 1000µs Figure 10. Error vs. Pulse Width Rectangular Pulse 11 00504-017 1% 1 00504-018 7V rms INPUT INCREASE IN ERROR (% of Reading) 10 AD536A Data Sheet 25 ±PEAK INPUT OR OUTPUT (V) 20 VIN 15 10 VOUT 5 20 VIN 15 VOUT 10 5 0 ±6 ±10 ±16 VOLTS (DUAL SUPPLY) ±18 0 5 10 20 30 VOLTS (SINGLE SUPPLY) Figure 12. Input and Output Voltage Ranges vs. Single Supply Figure 11. Input and Output Voltage Ranges vs. Dual Supply Rev. E | Page 10 of 16 00504-022 2.5 00504-019 ±PEAK INPUT OR OUTPUT (V) 25 Data Sheet AD536A APPLICATIONS INFORMATION NC The AD536A is simple to connect to for the majority of high accuracy rms measurements, requiring only an external capacitor to set the averaging time constant. The standard connection is shown in Figure 13 through Figure 15. In this configuration, the AD536A measures the rms of the ac and dc levels present at the input, but shows an error for low frequency input as a function of the filter capacitor, CAV, as shown in Figure 19. Thus, if a 4 µF capacitor is used, the additional average error at 10 Hz is 0.1%; at 3 Hz, the additional average error is 1%. CAV AD536A 1 NC 2 –VS –VS 3 dB 5 BUF OUT 13 NC SQUARER/ DIVIDER 12 NC 11 NC 7 10 25kΩ BUF 9 RL 8 IOUT Figure 13. 14-Lead Standard RMS Connection IOUT RL BUF IN 25kΩ AD536A CURRENT MIRROR +VS BUF BUF OUT VOUT SQUARER/ DIVIDER +VS VIN CAV dB CAV –VS 1 NC 20 19 ABSOLUTE VALUE 4 NC 5 CAV AD536A SQUARER/ DIVIDER 6 CURRENT MIRROR 11 12 13 RL 10 NC 9 BUF IN VOUT 25kΩ BUF dB 8 IOUT NC 7 18 NC 17 NC 16 NC 15 NC COM 14 Figure 15. 20-Terminal Standard RMS Connection The input and output signal ranges are a function of the supply voltages; these ranges are shown in Figure 11 and Figure 12. The AD536A can also be used in an unbuffered voltage output mode by disconnecting the input to the buffer. The output then appears unbuffered across the 25 kΩ resistor. The buffer amplifier can then be used for other purposes. Further, the AD536A can be used in a current output mode by disconnecting the 25 kΩ resistor from ground. The output current is available at Pin 8 (IOUT, Pin 10 on the H-10 package) with a nominal scale of 40 μA per V rms input positive output. The accuracy and offset voltage of the AD536A is adjustable with external trims, as shown in Figure 16. R4 trims the offset. Note that the offset trim circuit adds 365 Ω in series with the internal 25 kΩ resistor. This causes a 1.5% increase in scale factor, which is compensated for by R1. The scale factor adjustment range is ±1.5%. The trimming procedure is as follows: 1. 2. ABSOLUTE VALUE 00504-020 COM –VS –VS 2 OPTIONAL EXTERNAL TRIMS FOR HIGH ACCURACY COM CURRENT MIRROR 6 BUF IN +VS 14 4 CAV VOUT +VS ABSOLUTE VALUE 00504-006 VIN 3 +VS NC BUF OUT The accuracy at higher frequencies is according to specification. To reject the dc input, add a capacitor in series with the input, as shown in Figure 17. Note that the capacitor must be nonpolar. If the AD536A supply rails contain a considerable amount of high frequency ripple, it is advisable to bypass both supply pins to ground with 0.1 µF ceramic capacitors, located as close to the device as possible. VIN VIN CAV 00504-021 TYPICAL CONNECTIONS 3. Figure 14. 10-Pin Standard RMS Connection Ground the input signal, VIN, and adjust R4 to provide 0 V output from Pin 6. Alternatively, adjust R4 to provide the correct output with the lowest expected value of VIN. Connect the desired full-scale input level to VIN, either dc or a calibrated ac signal (1 kHz is the optimum frequency). Trim R1 to provide the correct output at Pin 6. For example, 1.000 V dc input provides 1.000 V dc output. A ±1.000 V peak-to-peak sine wave should provide a 0.707 V dc output. Any residual errors are caused by device nonlinearity. The major advantage of external trimming is to optimize device performance for a reduced signal range; the AD536A is internally trimmed for a 7 V rms full-scale range. Rev. E | Page 11 of 16 AD536A Data Sheet CAV CAV 1 R1 500Ω –VS NC 2 –VS CAV VOUT dB BUF OUT 3 ABSOLUTE VALUE AD536A SQUARER/ DIVIDER 7 12 NC 11 NC CURRENT MIRROR 6 BUF IN 13 NC 4 5 14 25kΩ BUF 25kΩ 10 9 8 COM RL C2 1µF VIN +VS +VS NONPOLARIZED R4 OFFSET 50kΩ ADJUST VIN –VS CAV R3 750kΩ dB VOUT R2 365Ω BUF OUT RL BUF IN 10kΩ TO 1kΩ IOUT 1 NC 2 –VS 00504-007 VIN +VS 3 ABSOLUTE VALUE +VS 13 NC SQUARER/ DIVIDER 12 NC 20kΩ 11 NC CURRENT MIRROR 6 7 +VS 0.1µF AD536A 4 5 14 25kΩ 10 9 8 BUF COM 0.1µF RL 10kΩ IOUT 00504-008 SCALE FACTOR ADJUST Figure 17. Single-Supply Connection Figure 16. Optional External Gain and Output Offset Trims SINGLE-SUPPLY OPERATION CHOOSING THE AVERAGING TIME CONSTANT Refer to Figure 17 for single supply-rail configurations between 5 V and 36 V. When powered from a single supply, the input stage (VIN pin) is internally biased at a voltage between ground and the supply, and the input signal ac coupled. Biasing the device between the supply and ground is simply a matter of connecting the COM pin to an external resistor divider and bypassing to ground. The resistor values are large, minimizing power consumption, as the COM pin current is only 5 μA. The AD536A computes the rms of both ac and dc signals. If the input is a slowly varying dc signal, the output of the AD536A tracks the input exactly. At higher frequencies, the average output of the AD536A approaches the rms value of the input signal. The actual output of the AD536A differs from the ideal output by a dc (or average) error and some amount of ripple, as shown in Figure 18. EO Note that the 10 kΩ and 20 kΩ resistors connected to the COM pin (Figure 17) are asymmetrical, that is, the voltage at the COM pin is 1/3 of the supply. This ratio of input bias to supply is optimum for the precision rectifier (aka absolute value circuit) input circuit employed for rectifying ac input waveforms and ensures full input symmetry for low signal voltages. DC ERROR = EO – EO (IDEAL) DOUBLE FREQUENCY RIPPLE AVERAGE EO – EO TIME 00504-009 Capacitor C2 is required for AC input coupling, however an external dc return is unnecessary because biasing occurs internally. SelectC2 for the desired low frequency breakpoint using an input resistance of 16.7 kΩ for the 1/ωRC calculation; C2 = 1 μF for a cutoff at 10 Hz. Figure 11 and Figure 12 show the input and output signal ranges for dual and single supply configurations, respectively. The load resistor, RL, provides a path to sink output sink current when an input signal is disconnected. IDEAL EO Figure 18. Typical Output Waveform for Sinusoidal Input The dc error is dependent on the input signal frequency and the value of CAV. Use Figure 19 to determine the minimum value of CAV, which yields a given percentage of dc error above a given frequency using the standard rms connection. The ac component of the output signal is the ripple. There are two ways to reduce the ripple. The first method involves using a large value of CAV. Because the ripple is inversely proportional to CAV, a tenfold increase in this capacitance affects a tenfold reduction in ripple. When measuring waveforms with high crest factors, such as low duty cycle pulse trains, the averaging time constant should be at least 10 times the signal period. For example, a 100 Hz pulse rate requires a 100 ms time constant, which corresponds to a 4 μF capacitor (time constant = 25 ms per μF). Rev. E | Page 12 of 16 Data Sheet AD536A The primary disadvantage in using a large CAV to remove ripple is that the settling time for a step change in input level is increased proportionately. Figure 19 illustrates that the relationship between CAV and 1% settling time is 115 ms for each microfarad of CAV. The settling time is twice as great for decreasing signals as it is for increasing signals. The values in Figure 19 are for decreasing signals. Settling time also increases for low signal levels, as shown in Figure 20. % 01 0. 10 R R O R ER R 1 O R ER R VALUES FOR CAV AND 1% SETTLING TIME 0.1 FOR STATED % OF READING AVERAGING ERROR1 ACCURACY ± 20% DUE TO COMPONENT TOLERANCE 0.1 0.01 10 1 100 1k INPUT FREQUENCY (Hz) 10k For a more detailed explanation of these topics, refer to the RMS to DC Conversion Application Guide, 2nd Edition, available online from Analog Devices, Inc., at www.analog.com. –VS NC –VS CAV 0.01 100k 1 2 3 dB BUF OUT Figure 19. Error/Settling Time Graph for Use with the Standard RMS Connection (See Figure 13 Through Figure 15) BUF IN + – 10.0 ABSOLUTE VALUE AD536A 5 +VS 12 NC 11 NC CURRENT MIRROR 6 7 +VS 14 13 NC SQUARER/ DIVIDER 4 CAV 1PERCENT DC ERROR AND PERCENT RIPPLE (PEAK) 25kΩ 9 8 BUF Rx 24kΩ C2 10 COM RL IOUT – C31 + Vrms OUT 1FOR SINGLE POLE, SHORT Rx, REMOVE C3. 7.5 Figure 21. Two-Pole Postfilter 2.5 1m 10m 100m 1 rms INPUT LEVEL (V) 10 00504-011 1.0 Figure 20. Settling Time vs. Input Level A better method to reduce output ripple is the use of a postfilter. Figure 21 shows a suggested circuit. If a single-pole filter is used (C3 removed, RX shorted) and C2 is approximately twice the value of CAV, the ripple is reduced, as shown in Figure 22, and settling time is increased. For example, with CAV = 1 µF and C2 = 2.2 μF, the ripple for a 60 Hz input is reduced from 10% of reading to approximately 0.3% of reading. Rev. E | Page 13 of 16 DC ERROR OR RIPPLE (% of Reading) 5.0 10 PEAK-TO-PEAK RIPPLE CAV = 1µF PEAK-TO-PEAK RIPPLE (ONE POLE) CAV = 1µF, C2 = 2.2µF 1 Rx = 0Ω DC ERROR CAV = 1µF (ALL FILTERS) PEAK-TO-PEAK RIPPLE CAV = 1µF C2 = C3 = 2.2µF (TWO-POLE) 0.1 10 100 1k 10k FREQUENCY (Hz) Figure 22. Performance Features of Various Filter Types (See Figure 13 to Figure 15 for Standard RMS Connection) 00504-013 SETTLING TIME RELATIVE TO 1V rms INPUT SETTLING TIME VIN VIN 00504-010 O R ER 1% 1 % 10 REQUIRED CAV (µF) O R ER 1% 0. 10 FOR 1% SETTLING TIME IN SECONDS MULTIPLY READING BY 0.115 100 The two-pole postfilter uses an active filter stage to provide even greater ripple reduction without substantially increasing the settling times over a circuit with a one-pole filter. The values of CAV, C2, and C3 can then be reduced to allow extremely fast settling times for a constant amount of ripple. Caution should be exercised in choosing the value of CAV, because the dc error is dependent on this value and is independent of the postfilter. 00504-012 100 The settling time, however, is increased by approximately a factor of 3. Therefore, the values of CAV and C2 can be reduced to permit faster settling times while still providing substantial ripple reduction. AD536A Data Sheet OUTLINE DIMENSIONS 0.005 (0.13) MIN 0.080 (2.03) MAX 8 14 1 PIN 1 0.310 (7.87) 0.220 (5.59) 7 0.100 (2.54) BSC 0.765 (19.43) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 0.070 (1.78) 0.030 (0.76) 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR \REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 23. 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-14) Dimensions shown in inches and (millimeters) 0.200 (5.08) REF 0.100 (2.54) REF 0.015 (0.38) MIN 0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) 19 18 0.358 (9.09) 0.342 (8.69) SQ 0.358 (9.09) MAX SQ 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37) 3 20 4 0.028 (0.71) 0.022 (0.56) 1 BOTTOM VIEW 0.050 (1.27) BSC 8 14 13 9 45° TYP 0.055 (1.40) 0.045 (1.14) 0.150 (3.81) BSC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 24. 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20-1) Dimensions shown in inches and (millimeters) 0.005 (0.13) MIN 14 1 PIN 1 0.098 (2.49) MAX 8 0.310 (7.87) 0.220 (5.59) 7 0.100 (2.54) BSC 0.785 (19.94) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15° 0° 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 25. 14-Lead Ceramic Dual In-Line Package [CERDIP] (Q-14) Dimensions shown in inches and (millimeters) Rev. E | Page 14 of 16 022106-A 0.100 (2.54) 0.064 (1.63) Data Sheet AD536A REFERENCE PLANE 0.500 (12.70) MIN 0.185 (4.70) 0.165 (4.19) 0.160 (4.06) 0.110 (2.79) 0.335 (8.51) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 6 7 5 0.021 (0.53) 0.016 (0.40) 0.115 (2.92) BSC 8 4 9 0.045 (1.14) 0.025 (0.65) 3 2 0.040 (1.02) MAX BASE & SEATING PLANE 10 1 0.034 (0.86) 0.025 (0.64) 0.230 (5.84) BSC 36° BSC DIMENSIONS PER JEDEC STANDARDS MO-006-AF CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 022306-A 0.050 (1.27) MAX Figure 26. 10-Pin Metal Header Package [TO-100] (H-10) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model 1 AD536AJD AD536AJDZ AD536AKD AD536AKDZ AD536AJH AD536AJHZ AD536AKH AD536AKHZ AD536AJQ AD536AKQ AD536ASD AD536ASD/883B AD536ASE/883B AD536ASH AD536ASH/883B AD536ASCHIPS 5962-89805012A 5962-8980501CA 5962-8980501IA 1 Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C Package Description 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 10-Pin Metal Header Package [TO-100] 10-Pin Metal Header Package [TO-100] 10-Pin Metal Header Package [TO-100] 10-Pin Metal Header Package [TO-100] 14-Lead Ceramic Dual In-Line Package [CERDIP] 14-Lead Ceramic Dual In-Line Package [CERDIP] 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 20-Terminal Ceramic Leadless Chip Carrier [LCC] 10-Pin Metal Header Package [TO-100] 10-Pin Metal Header Package [TO-100] Die 20-Terminal Ceramic Leadless Chip Carrier [LCC] 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 10-Pin Metal Header Package [TO-100] Z = RoHS Compliant Part. Rev. E | Page 15 of 16 Package Option D-14 D-14 D-14 D-14 H-10 H-10 H-10 H-10 Q-14 Q-14 D-14 D-14 E-20-1 H-10 H-10 E-20-1 D-14 H-10 AD536A Data Sheet NOTES ©1976–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00504-0-7/12(E) Rev. E | Page 16 of 16