LINER LTC1390CS 8-channel analog multiplexer with serial interface Datasheet

LTC1390
8-Channel
Analog Multiplexer
with Serial Interface
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DESCRIPTIO
FEATURES
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■
■
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The LTC®1390 is a high performance CMOS 8-to-1 analog
multiplexer. It features a 3-wire digital interface with a
bidirectional data retransmission feature, allowing it to be
wired in series with a serial A/D converter while using only
one serial port. The interface also allows several LTC1390s
to be wired in series or parallel, increasing the number of
MUX channels available using only a single digital port. All
the above features are also valid when LTC1390 operates
as a demultiplexer such as with a D/A converter.
3-Wire Serial Digital Interface
Data Retransmission Allows Series Connection
with Serial A/D Converters
Single 3V to ±5V Supply Operation
Analog Inputs May Extend to Supply Rails
Low Charge Injection
Low RON: 75Ω Max
Low Leakage: ±5nA Max
Guaranteed Break-Before-Make
TTL/CMOS Compatible for All Digital Inputs
Cascadable to Allow Additional Channels
Can Be Used as a Demultiplexer
The LTC1390 features a typical RON of 45Ω, typical switch
leakage of 50pA, and guaranteed break-before-make operation. Charge injection is ±10pC maximum. All digital
inputs are TTL and CMOS compatible when operated from
single or dual supplies. The inputs can withstand 100mA
fault currents.
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APPLICATI
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S
Data Acquisition Systems
Communication Systems
Signal Multiplexing/Demultiplexing
The LTC1390 is available in 16-pin PDIP and narrow SO
packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATI
VCC VEE
ON-Resistance vs
Analog Input Voltage
VCC
2
3
4
ANALOG
INPUTS
5
6
7
8
V+
S0
S1
S2
LTC1390
D
V–
S3
DATA 2
S4
DATA 1
S5
CS
S6
CLK
S7
GND
16
OPTIONAL A/D
INPUT FILTER
1
15
2
14
3
13
12
CS
VCC
9
CLK
LTC1096
6
DOUT
4
5
VREF
GND
+IN
–IN
VCC
DATA
CLK
CS
200
V + = 3V
V – = 0V
150
100
50
47k
3-WIRE
SERIAL
INTERFACE
TO MUX AND ADC
TA = 25°C
7
11
10
250
8
ON-RESISTANCE (Ω)
1
0
LTC1390 • TA01
V + = 5V
V – = – 5V
–5 –4 –3 –2 –1 0 1 2 3 4
ANALOG INPUT VOLTAGE, VS (V)
5
LTC1390 • TA02
1
LTC1390
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RATI GS
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ABSOLUTE
PACKAGE/ORDER I FOR ATIO
(Note 1)
Total Supply Voltage (V + to V –) .............................. 15V
Input Voltage
Analog Inputs ........................ V – – 0.3V to V + + 0.3V
Digital Inputs ........................................ – 0.3V to 15V
Digital Outputs............................ – 0.3V to V + + 0.3V
Power Dissipation ............................................. 500mW
Operating Temperature Range ..................... 0°C to 70°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
TOP VIEW
S0
1
16 V +
S1
2
15 D
S2
3
14 V –
S3
4
13 DATA 2
S4
5
12 DATA 1
S5
6
11 CS
S6
7
10 CLK
S7
8
9
N PACKAGE
16-LEAD PDIP
LTC1390CN
LTC1390CS
GND
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 70°C/ W (N)
TJMAX = 150°C, θJA = 100°C/ W (S)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
V + = 5V, V – = – 5V, GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VANALOG
Analog Signal Range
(Note 2)
RON
On Resistance
VS = ±3.5V, ID = 1mA
TMIN
25°C
TMAX
MIN
TYP
MAX
UNITS
Switch
IS(OFF)
●
–5
45
5
V
75
75
120
Ω
Ω
Ω
∆RON vs VS
20
%
∆RON vs Temperature
0.5
%/°C
0.05
±5
±50
nA
nA
0.05
±5
±50
nA
nA
0.05
±5
±50
nA
nA
VS = 4V, VD = – 4V; VS = – 4V, VD = 4V
Channel Off
●
VS = 4V, VD = – 4V; VS = – 4V, VD = 4V
Channel Off
●
VS = VD = ±4V
Channel On
●
High Level Input Voltage
V+ = 5.25V
●
VINL
Low Level Input Voltage
V+
●
0.8
V
IINL, IINH
Low or High Level Current
VIN = 5V, VIN = 0V
●
±1
µA
VOH
High Level Output Voltage
V+ = 4.75V, IO = 10µA
V+ = 4.75V, IO = 360µA
●
V+ = 4.75V, IO = 0.5mA
●
ID(OFF)
ID(ON)
Off Input Leakage
Off Output Leakage
On Channel Leakage
Input
VINH
VOL
2
Low Level Output Voltage
= 4.75V
2.4
2.4
V
4.74
4.50
0.16
V
V
0.8
V
LTC1390
ELECTRICAL CHARACTERISTICS
V + = 5V, V – = – 5V, GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Dynamic
fCLK
Clock Frequency
5
tON
Enable Turn-On Time
VS = 2.5V, RL = 1k, CL = 35pF
260
400
ns
tOFF
Enable Turn-Off Time
VS = 2.5V, RL = 1k, CL = 35pF
100
200
ns
tOPEN
Break-Before-Make Interval
OIRR
Off Isolation
VS = 2VP-P, RL = 1k, f = 100kHz
70
OINJ
Charge Injection
RS = 0, CL = 1000pF, VS = 1V (Note 2)
±2
CS(OFF)
Source Off Capacitance
5
pF
CD(OFF)
Drain Off Capacitance
10
pF
35
155
MHz
ns
dB
±10
pC
Supply
I+
Positive Supply Current
All Logic Inputs Tied Together, VIN = 0V or VIN = 5V
●
15
40
µA
I–
Negative Supply Current
All Logic Inputs Tied Together, VIN = 0V or VIN = 5V
●
15
40
µA
TYP
MAX
V + = 3V, V – = GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VANALOG
Analog Signal Range
(Note 2)
RON
On Resistance
VS = 1.2V, ID = 1mA
TMIN
25°C
TMAX
MIN
UNITS
Switch
●
0
200
∆RON vs VS
●
VS = 2.5V, VD = 0.5V; VS = 0.5V, VD = 2.5V (Note 3)
Channel Off
●
VS = VD = 0.5V, VS = VD = 2.5V (Note 3)
Channel On
●
High Level Input Voltage
V+ = 3.3V
●
VINL
Low Level Input Voltage
V+
●
IINL, IINH
Low or High Level Current
VIN = 3V, VIN = 0V
VOH
High Level Output Voltage
V+ = 2.7V, IO = 20µA
V+ = 2.7V, IO = 400µA
●
V+ = 2.7V, IO = 20µA
V+ = 2.7V, IO = 300µA
●
ID(ON)
Off Output Leakage
On Channel Leakage
255
255
300
Ω
Ω
Ω
%
0.5
VS = 2.5V, VD = 0.5V; VS = 0.5V, VD = 2.5V (Note 3)
Channel Off
ID(OFF)
Off Input Leakage
V
20
∆RON vs Temperature
IS(OFF)
3
%/°C
±0.05
±5
±50
nA
nA
±0.05
±5
±50
nA
nA
±0.05
±5
±50
nA
nA
Input
VINH
VOL
Low Level Output Voltage
= 2.7V
2.4
V
●
2
0.8
V
±1
µA
2.68
2.27
0.01
0.15
V
V
0.8
V
V
3
LTC1390
ELECTRICAL CHARACTERISTICS
V + = 3V, V – = GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Dynamic
fCLK
Clock Frequency
5
tON
Enable Turn-On Time
VS = 1.5V, RL = 1k, CL = 35pF (Note 4)
490
700
ns
tOFF
Enable Turn-Off Time
VS = 1.5V, RL = 1k, CL = 35pF (Note 4)
190
300
ns
tOPEN
Break-Before-Make Interval
(Note 4)
OIRR
Off Isolation
VS = 2VP-P, RL = 1k, f = 100kHz
70
OINJ
Charge Injection
RS = 0, CL = 1000pF, VS = 1V (Note 2)
±1
CS(OFF)
Source Off Capacitance
5
pF
CD(OFF)
Drain Off Capacitance
10
pF
125
MHz
290
ns
dB
±5
pC
Supply
I+
Positive Supply Current
All Logic Inputs Tied Together, VIN = 0V or VIN = 3V
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute maximum ratings are those beyond which the safety of
the device may be impaired.
Note 2: Guaranteed by design.
0.2
●
µA
2
Note 3: Leakage current with a single 3V supply is guaranteed by
correlation with the leakage current of the ±5V supply.
Note 4: Timing specifications with a single 3V supply is guaranteed by
correlation with the timing specifications of the ±5V supply.
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TYPICAL PERFORMANCE CHARACTERISTICS
Driver Output Low Voltage
vs Output Current
ON-Resistance vs Temperature
6
5
OUTPUT CURRENT (mA)
ON-RESISTANCE (Ω)
250
V + = 3V
V – = 0V
VS = 1.2V
200
150
V + = 5V
V – = – 5V
VS = 0V
100
50
0
TA = 25°C
V + = 5V
V – = –5V
–1
OUTPUT CURRENT (mA)
300
4
DATA 1
3
2
DATA 2
1
0
10
40
30
50
20
TEMPERATURE (˚C)
60
70
LTC1390 • G01
TA = 25°C
V + = 5V
V – = –5V
DATA 2
–2
–3
–4
DATA 1
–5
–6
0
0
4
Driver Output High Voltage
vs Output Current
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT VOLTAGE (V)
LTC1390 • G02
–7
2.0
2.5
4.0
3.5
3.0
OUTPUT VOLTAGE (V)
4.5
5.0
LTC1390 • G03
LTC1390
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PIN FUNCTIONS
S0 to S7 (Pins 1 to 8): Analog Multiplexer Inputs/Analog
Demultiplexer Outputs.
analog signal transmission and allows data transfer from
Data 2 to Data 1.
GND (Pin 9): Digital Ground. Connect to system ground.
Data 1 (Pin 12): Bidirectional Digital Input/Output (TTL/
CMOS Compatible). Input for the channel selection bits.
CLK (Pin 10): System Clock (TTL/CMOS Compatible). The
clock synchronizes the channel selection bits and the
serial data transfer from Data 1 to Data 2.
CS (Pin 11): Chip Select Input (TTL/CMOS Compatible). A
logic high on this input enables LTC1390 to read in the
channel selection bits and allow data transfer from Data 1
to Data 2. A logic low enables the desired channel for
Data 2 (Pin 13): Bidirectional Digital Input/Output (TTL/
CMOS Compatible).
V – (Pin 14): Negative Supply.
D (Pin 15): Analog Multiplexer Output/Analog
Demultiplexer Input.
V + (Pin 16): Positive Supply.
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APPLICATIO S I FOR ATIO
Multiplexer Operation
Figure 1 shows the block diagram of the components
within the LTC1390 required for MUX operation. The
LTC1390 uses Data 1 to select its 8 channels and a chip
select input CS to switch on the selected channel as shown
in Figure 2.
CLK
DATA 1
CS
CONTROL
LOGIC
4-BIT SHIFT
REGISTER
ANALOG
INPUT
MUX
BLOCK
ANALOG
OUTPUT
LTC1390 • F01
Figure 1: Simplified Block Diagram of the MUX Operation
When CS is high, the input data on the Data 1 pin is latched
into the 4-bit shift register on each rising clock edge. The
input data consists of an “EN” bit and a string of three bits
for channel selection. If “EN” bit is logic high as illustrated
in the first input data sequence, it enables the selected
channel. To ensure correct operation, the CS must be
pulled low before the next rising clock edge.
Once the CS is pulled low, all channels are simultaneously
switched off to ensure a break-before-make interval. After
a delay of tON, the selected channel is switched on allowing
signal transmission. The selected channel remains on
until the next falling edge of CS, and after a delay of tOFF,
it terminates the analog signal transmission and subsequently allows the selection of the next channel. If “EN” bit
is logic low, as illustrated in the second data sequence, it
disables all channels and there will be no analog signal
CLK
CS
EN = LOW
EN = HIGH
DATA 1
B2
B1
B2
B0
B1
B0
ANY
ANALOG
INPUTS
D
LTC1390 • F02
tON
tOFF
Figure 2: Multiplexer Operation
5
LTC1390
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APPLICATIO S I FOR ATIO
transmission. Table 1 shows the various bit combinations
for channel selection.
Table 1. Logic Table for Channel Selection
CHANNEL STATUS
All Off
S0
S1
S2
S3
S4
S5
S6
S7
EN
0
1
1
1
1
1
1
1
1
B2
X
0
0
0
0
1
1
1
1
B1
X
0
0
1
1
0
0
1
1
B0
X
0
1
0
1
0
1
0
1
selection or to Data 2 via Buffer 1 for data transfer. Data
appears at Data 2 after the fourth rising edge of the clock.
When CS is low, Buffer 2 is enabled and Buffer 1 is
disabled, thus digital input data is directly transferred from
Data 2 to Data 1 without any clock delay.
Multiplexer Expansion
Several LTC1390s can be daisy-chained to expand the
number of multiplexer inputs. No additional interface
ports are required for the expansion. Figure 5 shows two
LTC1390s connected at their analog outputs to form a 16to-1 multiplexer at the input to an LTC1286 A/D converter.
VCC VEE
VCC
Digital Data Transfer Operation
The block diagram of Figure 3 shows the components
contained within the LTC1390 required for digital data
transfer. Digital data transfer operation can be performed
from Data 1 to Data 2 and vice versa as shown in Figure 4.
When CS is high, Buffer 1 is enabled and Buffer 2 is
disabled. The digital input data is fed into the 4-bit shift
register and then shifted to the MUX switches for channel
CLK
4-BIT SHIFT
REGISTER
16
1
15
S1 LTC1390 D
3
14
A
S2
V–
4
13
S3
DATA 2
ANALOG
5
12
INPUTS
S4
DATA 1
6
11
S5
CS
7
10
S6
CLK
8
9
S7
GND
2
1
2
1
2
DATA 2
3
4
S0
S1
S2
S3
ANALOG
INPUTS 5 S4
6
S5
7
S6
8
S7
CS
DATA 1
V+
VCC
VREF
8
7
CLK
LTC1286
3
6
–IN
DOUT
4
5
CS
GND
+IN
VCC
MUX
SWITCHES
BUFFER 1
S0
BUFFER 2
16
V+
15
LTC1390 D
14
–
B
V
13
DATA 2
12
DATA 1
11
CS
10
CLK
9
GND
47k
DATA
CS
CLK
LTC1390 • F05
LTC1390 • F03
Figure 3. Simplified Block Diagram of the Digital Data
Transfer Operation
CLK
1
2
3
4
CS
DATA 1
DATA 2
Hi-Z
DATA OUT
DATA IN
DATA IN
DATA OUT
LTC1390 • F04
Figure 4. Digital Data Transfer Operation
6
Figure 5. Daisy-Chaining Two LTC1390s for Expansion
To ensure that only one channel is switched on at any one
time, two sets of channel selection bits are needed for Data
as shown in Figure 6. The first data sequence is used to
switch off one MUX and the second data sequence is used
to select one channel from the other MUX, or vice versa.
In other words, if bit “ENA” is high and bit “ENB” is low,
one channel of MUX A is switched on and all channels of
MUX B are switched off. If bit “ENA” is low and bit “ENB”
is high, all channels of MUX A are switched off and one
channel of MUX B is switched on.
LTC1390
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APPLICATIO S I FOR ATIO
CLK
1
2
3
4
5
6
7
8
CS
DATA
ENA
A2
A1
A0
ENB
B2
B1
NULL
BIT D11
B0
D10
D9
D8
D7
tSMPL
D6
D5
D4
D3
D2
D1
D0
tDATA
tCONV
DIGITAL INPUT FROM LTC1390
Hi-Z
DIGITAL OUTPUT FROM LTC1286
LTC1390 • F06
Figure 6. Timing Diagram for Figure 5
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TYPICAL APPLICATIONS N
Daisy-Chaining Five LTC1390s
BYPASS CAPACITOR FROM V + TO GND AND
V – TO GND REQUIRED FOR EACH LTC1390
VCC VEE
1
S0
V+
2
ANALOG
INPUTS
S0
V+
1
16
2
15
3
S1 LTC1390 D
3
14
A
S2
V–
4
13
S3
DATA 2
5
12
S4
DATA 1
6
11
S5
CS
7
10
S6
CLK
8
9
S7
GND
1
VCC
VREF
+IN
VCC
8
VCC
7
CLK
LTC1286
6
–IN
DOUT
4
5
CS
GND
47k
16
ANALOG
INPUTS
15
S1 LTC1390 D
3
14
–
B
S2
V
4
13
S3
DATA 2
5
12
S4
DATA 1
6
11
S5
CS
7
10
S6
CLK
8
9
S7
GND
VCC VEE
2
1
S0
V+
1
ANALOG
INPUTS
16
V+
16
15
S1 LTC1390 D
3
14
D
S2
V–
4
13
S3
DATA 2
5
12
S4
DATA 1
6
11
S5
CS
7
10
S6
CLK
8
9
S7
GND
2
ANALOG
INPUTS
15
S1 LTC1390 D
3
14
C
S2
V–
4
13
S3
DATA 2
5
12
S4
DATA 1
6
11
S5
CS
7
10
S6
CLK
8
9
S7
GND
S0
2
1
2
3
4
ANALOG
INPUTS
5
6
7
8
S0
V+
16
15
S1 LTC1390 D
14
E
S2
V–
13
S3
DATA 2
12
S4
DATA 1
11
S5
CS
10
S6
CLK
9
S7
GND
DATA*
CS
CLK
*REQUIRES FIVE 4-BIT CHANNEL
SELECTION DATA BYTES
LTC1390 • TA03
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
7
LTC1390
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TYPICAL APPLICATIONS N
Interfacing LTC1390 with LTC1257 for Demultiplex Operation
VCC VEE
1
S1
3
4
ANALOG
OUTPUTS
V+
S0
2
5
6
7
8
LTC1390
D
S2
V–
S3
DATA 2
S4
DATA 1
S5
CS
S6
CLK
S7
GND
OPTIONAL D/A
OUTPUT FILTER
16
15
VCC
VCC
14
13
1
8
VCC
CLK
LTC1257
7
VOUT
DIN
3
6
LOAD
VREF
4
5
GND
DOUT
47k
2
12
11
10
9
DATA
CLK
CS
LTC1390 • F03
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N Package
16-Lead Plastic DIP
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
0.015
(0.381)
MIN
+0.635
8.255
–0.381
)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.255 ± 0.015*
0.065 (6.477 ± 0.381)
(1.651)
TYP
0.125
(3.175)
MIN
+0.025
0.325 –0.015
0.770*
(19.558)
MAX
0.045 – 0.065
(1.143 – 1.651)
0.045 ± 0.015
(1.143 ± 0.381)
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).
S Package
16-Lead Plastic SOIC
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.053 – 0.069
(1.346 – 1.752)
0.008 – 0.010
(0.203 – 0.254)
0.004 – 0.010
(0.101 – 0.254)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0° – 8° TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.150 – 0.157*
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
1
2
3
4
5
6
7
8
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC201A/LTC202/LTC203
Micropower, Low Charge Injection, Quad CMOS Analog Switches
Each Channel is Independently Controlled
LTC221/LTC222
Micropower, Low Charge Injection, Quad CMOS Analog Switches
with Data Latches
Parallel Controlled with Data Latches
LTC128x/LTC129x
Serial A/Ds with Integral MUXs
8
Linear Technology Corporation
LT/GP 0695 10K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
 LINEAR TECHNOLOGY CORPORATION 1995
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