LINER LTC4224IMS-2-TRPBF Compact dual low voltage hot swap controller Datasheet

LTC4224-1/LTC4224-2
Compact Dual Low
Voltage Hot Swap Controller
FEATURES
DESCRIPTION
n
The LTC®4224 Dual Low Voltage Hot Swap™ controller
allows a board to be safely inserted and removed from a
live backplane. It controls two supplies with external Nchannel MOSFETs and operates with one supply as low
as 1V provided the other supply is 2.7V or greater. The
LTC4224 can ramp up the supplies in any order and at
adjustable ramp rates. To minimize the number of external
components and PCB area, the gate capacitor is optional,
all timing delays are generated internally, and the ON pins
have integrated pull-up currents.
n
n
n
n
n
n
n
n
n
n
Allows Safe Board Insertion and Removal from a
Live Backplane
Controls Load Voltages from 1V to 6V
No Gate Components Required
Adjustable Current Limit with Circuit Breaker
Limits Peak Fault Current in ≤1μs
No External Timing Capacitor Required
Adjustable Supply Voltage Power-Up Rate
Gate Drive for External N-channel MOSFET
LTC4224-1: Latchoff After Fault
LTC4224-2: Automatic Retry After Fault
10-Lead MSOP and 3mm × 2mm DFN Packages
Protection against overcurrent faults is provided by a fastacting current limit and timed circuit breakers. A FAULT pin
signals overcurrent faults. The LTC4224-1 remains off after
a fault, while the LTC4224-2 automatically tries to apply
power again after a four second cool-down period.
APPLICATIONS
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Optical Networking
Low Voltage Hot Swap
Electronic Circuit Breakers
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
TYPICAL APPLICATION
Normal Power-Up Waveform
FDS6911
0.015Ω
5V
1A
5V
0.010Ω
3.3V
2A
3.3V
VCC1 SENSE1 VCC2
FAULT
VOUT2
5V/DIV
SENSE2 GATE1 GATE2
LTC4224
LTC4224
VOUT1
5V/DIV
IIN1
2A/DIV
ON1
ON2
GND
GND
CONNECTOR PLUG-IN
CARD
IIN2
2A/DIV
CLOAD = 150μF
0.5ms/DIV
422412 TA01b
422412 TA01a
422412fa
1
LTC4224-1/LTC4224-2
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCCn) .................................. –0.3V to 9V
Input Voltages
SENSEn, ONn........................................... –0.3V to 9V
Output Voltages
GATEn – VCC (Note 4) .............................. –0.3V to 5V
FAULT....................................................... –0.3V to 9V
Operating Temperature Range
LTC4224C ................................................ 0°C to 70°C
LTC4224I.............................................. –40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature Range (Soldering, 10 sec)
MSOP Package ................................................. 300°C
PIN CONFIGURATION
TOP VIEW
SENSE1 1
GATE1 3
TOP VIEW
10 SENSE2
VCC1 2
11
SENSE1
VCC1
GATE1
FAULT
ON1
9 VCC2
8 GATE2
FAULT 4
7 GND
ON1 5
6 ON2
1
2
3
4
5
10
9
8
7
6
SENSE2
VCC2
GATE2
GND
ON2
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 160°C/W
DDB PACKAGE
10-LEAD (3mm × 2mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) PCB GND CONNECTION OPTIONAL
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4224CDDB-1#PBF
LTC4224CDDB-1#TRPBF
LDTT
10-Lead (3mm × 2mm) Plastic DFN
0°C to 70°C
LTC4224CDDB-2#PBF
LTC4224CDDB-2#TRPBF
LDNV
10-Lead (3mm × 2mm) Plastic DFN
0°C to 70°C
LTC4224IDDB-1#PBF
LTC4224IDDB-1#TRPBF
LDTT
10-Lead (3mm × 2mm) Plastic DFN
–40°C to 85°C
LTC4224IDDB-2#PBF
LTC4224IDDB-2#TRPBF
LDNV
10-Lead (3mm × 2mm) Plastic DFN
–40°C to 85°C
LTC4224CMS-1#PBF
LTC4224CMS-1#TRPBF
LTDTV
10-Lead Plastic MSOP
0°C to 70°C
LTC4224CMS-2#PBF
LTC4224CMS-2#TRPBF
LTDNW
10-Lead Plastic MSOP
0°C to 70°C
LTC4224IMS-1#PBF
LTC4224IMS-1#TRPBF
LTDTV
10-Lead Plastic MSOP
–40°C to 85°C
LTC4224IMS-2#PBF
LTC4224IMS-2#TRPBF
LTDNW
10-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
422412fa
2
LTC4224-1/LTC4224-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range. TA = 25°C, VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VCC
VCC Supply Range
VCC = Max (VCC1, VCC2)
MIN
TYP
MAX
UNITS
Supplies
l
2.7
l
6
V
1.4
3
mA
2.4
2.65
V
6
V
40
100
μA
ICC
VCC Supply Current
VCC(UVL)
VCC Undervoltage Lockout
VCC Rising
l
2.2
VCCLO
VCCLO Supply Range
VCCLO = Min (VCC1, VCC2),
VCC ≥ 2.7V
l
1
ICCLO
VCCLO Supply Current
VCCLO(UVL)
VCCLO Undervoltage Lockout
VCCLO Falling
l
0.76
0.8
0.84
V
ΔVGATE
Gate Drive
(VGATEn – VCC)
IGATEn = 0μA, –1μA
l
4.5
5.5
7
V
IGATE(UP)
Gate Pull-Up Current
Gate Drive On, VGATEn = 1V
l
–7
–10
–13
μA
IGATE(DN)
Gate Pull-Down Current
VONn = 1V, VGATEn = 10V
l
0.5
1.5
3
mA
IGATE(FPD)
Gate Fast Pull-Down Current
Fast Turn-Off, VGATEn = 10V
l
50
125
200
mA
l
22.5
25
27.5
mV
40
100
μA
0.8
0.84
V
l
External Gate Drive
Current Limit
ΔVSENSE(CB)
Circuit Breaker Trip Sense Voltage
(VCCn – SENSEn)
ISENSE
SENSE Input Current
VSENSE1 = 5V, VSENSE2 = 3.3V
l
VON(TH)
ONn Threshold Voltage
VONn Rising
l
0.76
l
15
30
50
mV
–5
–10
–15
μA
0.2
0.4
V
5
7.5
ms
0.4
1
μs
10
15
ms
8
16
μs
ms
Inputs and Outputs
ΔVON(HYST)
ONn Hysteresis
ION(IN)
ONn Pull-Up Current
VONn = 1V
l
VOL
Output Low Voltage (FAULT)
IFAULT = 3mA
l
Delay
l
tCB
Circuit Breaker Delay
tPHL(SENSE)
Sense Voltage, (VCCn – SENSEn) High to
GATE Low
tPLH(GATE)
ONn Low or Input Supply High to GATEn
High Prop Delay
l
tPLH(UVL)
VCCn Low to GATEn Low Prop Delay
l
tD(UV)
UV Turn-On Delay
VCC Out of UV
l
80
160
240
tD(COOL)
Auto-Retry Cooling Delay
Note 3
l
2
4
6
tBLANK
Start-Up Circuit Breaker Blanking Delay
l
2.5
5
7.5
ΔVSENSE = 200mV, CGATE = 10nF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
2.5
l
5
s
ms
Note 3: LTC4224-2 only.
Note 4: The greater of VCC1 and VCC2 is the internal supply voltage (VCC).
An internal clamp limits the GATE pin to a minimum 5V above VCC. Driving
this pin beyond the clamp may damage the device.
422412fa
3
LTC4224-1/LTC4224-2
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are TA = 25°C, VCC1 = 5V, VCC2 = 3.3V, unless otherwise specified.
Circuit Breaker Trip Voltage
vs VCC
ICC vs VCC
1.5
Circuit Breaker Delay vs VCC
26.0
5.5
25.5
1.4
5.4
1.2
tCB (ms)
VCB (mV)
ICC (mA)
25.0
1.3
24.5
5.3
5.2
24.0
1.1
5.1
23.5
1.0
2.5
3.5
3
4.5
4
VCC (V)
5
5.5
23.0
6
1
2
3
4
5
422412 G02
5
5.60
4
5.55
3
5.50
2
5.45
1
5.40
–2
–4
–6
–8
IGATE (μA)
–10
–12
5.35
–50
0
25
50
TEMPERATURE (°C)
75
Gate Fast Pull-Down Current
vs Gate Voltage
120
110
8
9
10
11
VGATE (V)
12
1.4
1.2
100
13
422412 G07
8
9
10
11
VGATE (V)
12
13
422412 G06
FAULT Voltage
vs FAULT Sink Current
1.5
500
1.2
400
T = 90°C
0.9
VOL (mV)
ACTIVE CURRENT LIMIT DELAY (μs)
GATE FAST PULL-DOWN CURRENT (mA)
130
100
1.6
Active Current Limit Delay
vs Sense Voltage
150
6
1.8
422412 G05
422412 G04
140
5.5
2.0
1.0
–25
5
Gate Pull-Down Current
vs Gate Voltage
GATE NORMAL PULL-DOWN CURRENT (mA)
5.65
ΔVGATE (V)
ΔVGATE (V)
6
4
4.5
VCC (V)
422412 G03
Gate Drive vs Temperature
Gate Drive vs IGATE
0
3.5
3
VCC (V)
422412 G01
0
5.0
2.5
6
0.6
300
T = 25°C
200
T = –60°C
0.3
0.0
100
25
50
75
100
125
SENSE VOLTAGE (mV)
150
422412 G08
0
0
1
2
3
IFAULT (mA)
4
5
422412 G09
422412fa
4
LTC4224-1/LTC4224-2
PIN FUNCTIONS
SENSE1, SENSE2 (Pins 1,10): Current Sense Input. Connect this pin to an external sense resistor. The current limit
circuit controls GATEn to limit the voltage between VCCn
and SENSEn to 25mV. An Electronic Circuit Breaker (ECB)
is active during current limiting and trips after 5ms. To
disable current limit, connect this pin to VCCn.
ground. During short-circuits, a 125mA pulldown current
is activated to discharge GATE to ground.
FAULT (Pin 4): Fault Status Output. Open-drain output
that is normally pulled high to VCC1 or VCC2 by an external resistor. It is pulled low when the ECB trips due to an
overcurrent condition at either supply. This pin may be
left open if unused.
VCC1, VCC2 (Pins 2, 9): Supply Voltage and Current Sense
Input. An undervoltage lockout circuit disables the part
until VCC , the higher of VCC1 and VCC2, exceeds 2.4V. The
lower supply is disabled until it exceeds 0.8V.
ON1, ON2 (Pins 5, 6): On Control Input. A falling edge
turns on the external N-channel MOSFET and a rising edge
turns it off. A low to high transition on this pin resets an
ECB fault for the corresponding channel. Internally pulled
up to VCC by a 10μA current source.
GATE1, GATE2 (Pins 3, 8): Gate Drive for External N-channel
MOSFET. A charge pump sources 10μA from GATE to turn
on the external MOSFET. An internal clamp limits the gate
voltage to 5.5V above the higher of VCC1 and VCC2. During
turn-off, a 1.5mA pulldown current discharges GATE to
GND (Pin 7): Device Ground.
Exposed Pad (DFN Package Only): Exposed Pad may be
left open or connected to device ground.
FUNCTIONAL DIAGRAM
SENSE1
5.5V
CHARGE
PUMP
–
25mV
+
–
VCC1
VCC
10μA
ACL1
GATE1
VCC
+
GATE
PULLDOWN
+
ON1
ECB1
0.8V
–
0.8V
FAULT
+
2.4V
VCC
LOGIC
CONTROL
–
10μA
VCC2 UV
ON2
ECB2
+
–
CHARGE
PUMP
+
–
GATE
PULLDOWN
10μA
25mV
+
ACL2
ON2
+
–
0.8V
VCC2
ON1
+
–
VCC1 UV
VCC
10μA
0.8V
GATE2
5.5V
VCC
–
SENSE2
GND
422412 FD
422412fa
5
LTC4224-1/LTC4224-2
OPERATION
Each supply is continuously monitored for undervoltage
and overcurrent conditions. The undervoltage monitor
shuts off the external MOSFET when the corresponding
supply is too low.
The LTC4224 is designed to control power on a live backplane, allowing boards to be safely inserted and removed. It
controls two supplies (VCC1, VCC2) with operating voltages
between 1V and 6V via two external N-channel MOSFETs.
For applications where the total load current is 5A or less,
dual MOSFETs such as the FDS6911 can be used to save
board area. The two supplies can be turned on and off
independently using the active low ON1 and ON2 pins.
Internal 10μA current sources pull these pins to VCC.
Current is monitored by an active current limit amplifier
(ACL) and a timed electronic circuit breaker (ECB). Like
all timing delays in the LTC4224, the ECB delay of 5ms is
generated internally without requiring any external timing
capacitors. The ECB threshold is slightly below the ACL
threshold and shuts off the external MOSFET after 5ms.
FAULT is latched low to indicate an overcurrent fault.
Pulling the ON pin low turns on a charge pump which
sources 10μA at the GATE pin thereby ramping up the gate
of the external MOSFET. When the MOSFET turns on, the
inrush current is limited at a level set by an external sense
resistor. Inrush current can be further reduced, if desired,
by adding a capacitor from GATE to GND. To protect the
external MOSFET, the GATE pins are clamped to about
5.5V above the higher of the two supplies.
The LTC4224-1 remains latched off until reset by either
turning off and then on the affected supply or its ON pin.
The LTC4224-2 automatically restarts after four seconds
to allow time for the MOSFET to cool down.
APPLICATIONS INFORMATION
The basic LTC4224 application circuit is shown in Figure 1.
The following sections cover VCC selection, the normal
turn-on and turn-off sequence, various fault conditions
and recovery from fault situations. External component
selection is discussed in detail in the Design Example
section.
The typical LTC4224 application is in a high availability
system where two positive supply voltages are distributed
to power individual cards. The LTC4224 detects board
presence during insertion and removal, allowing power
to be delivered in a controlled manner without damaging
the connector. It reports overcurrent faults to the system
controller through its FAULT pin, which can light an LED
or can be monitored by a system controller.
R1
0.015Ω
FDS6911
5V
1A
5V
Q1
BULK SUPPLY
BYPASS CAPACITOR
R2
0.010Ω
3.3V
2A
3.3V
BULK SUPPLY
BYPASS CAPACITOR
Q2
R3
390
VCC1
SENSE1
VCC2
SENSE2
GATE1 GATE2
MOD DETECT
ON1
D1
LTC4224
FAULT
ON2
RMOD_DET
1k
GND
GND
CONNECTOR
PLUG-IN CARD
Figure 1. Typical Application
422412fa
6
LTC4224-1/LTC4224-2
APPLICATIONS INFORMATION
VCC Selection
The LTC4224 is powered from the higher of its two supply
pins, VCC1 and VCC2.This allows the part to control a supply voltage as low as 1V, while the other supply is 2.7V or
greater. If both supplies are tied together, the part derives
its power from both equally. The Functional Diagram shows
the VCC selection circuit in an ideal diode OR-ing arrangement. It is designed to ensure swift and smooth internal
power switchover from one supply to the other.
Turn-On Sequence
Separate ON1 and ON2 pins allow the VCC1 and VCC2
supplies to be turned on in any order. The power supplies
delivered to a plug-in card are controlled by external Nchannel MOSFETs, Q1 and Q2. For X2/XENPAK defined
optical transceiver modules, it has been specified that the
MOD DETECT pin pulls low inside the module through a
1k resistor (RMOD_DET), as shown in Figure 1. Several
conditions must be satisfied to turn on the MOSFETs.
First, VCC1 or VCC2 must exceed the 2.4V VCC undervoltage
lockout level for longer than an internal UV turn-on delay
of 160ms. Next, if VCCn is greater than 0.8V and ONn is
low (<0.8V), a debounce delay of 10ms is started. If VCCn
drops below 0.8V or ONn goes high before the end of the
10ms debounce delay, the debounce delay is restarted the
next time these pins are properly conditioned.
When the 10ms debounce delay expires, the external
MOSFET is turned on by charging up the GATE with a
10μA charge pump generated current source. When the
GATE voltage reaches the MOSFET threshold voltage, the
inrush current can build up quickly as the GATE continues
to rise. The ACL amplifier actively controls the gate voltage to maintain 25mV across the sense resistor. In this
condition, the inrush current is given by:
25mV
IINRUSH =
RSENSE
As the inrush current charges up the load capacitor, the
output rises with a corresponding increase in gate voltage.
When the supply is no longer in current limit, an internal
charge pump pulls the gate to 5.5V above the higher of VCC1
or VCC2 to achieve a low resistance power path. Figure 2
shows a typical start-up sequence with CLOAD1 = CLOAD2
= 150μF, RLOAD1 = 4.7Ω and RLOAD2 = 2Ω.
The inrush current can be reduced to below the current
limit level by adding an external gate capacitor as shown
in Figure 3.
GATE capacitor CGATE provides gate slew rate control to limit
the inrush current. However, CGATE could cause parasitic
high frequency self oscillation in Q1. A 10Ω resistor, RG, as
shown in Figure 3 can be used to prevent the oscillation.
To be effective, RG needs to be laid out close to Q1.
The voltage at the GATE pin rises with a slope equal to IGATE /
CGATE. For a given supply inrush current IINRUSH and load
capacitor CLOAD, CGATE can be calculated according to:
CGATE =
IGATE
IINRUSH
• CLOAD
ON1/2
2V/DIV
R1
0.015Ω
Q1
5V
VOUT1
5V/DIV
CLOAD
VOUT2
5V/DIV
VCC1 SENSE1
RG
10Ω
IGATE
GATE1
5V/DIV
CGATE
GATE1
GATE2
5V/DIV
LTC4224
5ms/DIV
422412 F02
Figure 2. Normal Power-Up Sequence
422412 F03
Figure 3. Inrush Current Control by Gate Capacitor
422412fa
7
LTC4224-1/LTC4224-2
APPLICATIONS INFORMATION
If the voltage across the sense resistor R1 becomes too
high, the inrush current is limited by the internal current
limit circuitry.
ON1
2V/DIV
VOUT1
5V/DIV
Turn-Off Sequence
The MOSFETs can be turned off by the conditions summarized in Table 1.
GATE1
5V/DIV
Table 1. Turn-Off Conditions
CONDITION
RESULT
CHANNEL 1 CHANNEL 2
CLEARED BY
ON1 Goes High
Turns Off
No Effect
ON1 Low
ON2 Goes High
No Effect
Turns Off
ON2 Low
UVLO on VCC
Turns Off
Turns Off
VCC > UVLO
UVLO on VCC1
Turns Off
No Effect
VCC1 > UVLO
UVLO on VCC2
No Effect
Turns Off
VCC2 > UVLO
CH1 Overcurrent Fault
Turns Off
No Effect
ON1 High,
UVLO on VCC1
CH2 Overcurrent Fault
No Effect
Turns Off
ON2 High,
UVLO on VCC2
0.2ms/DIV
422412 F04
Figure 4. Normal Power-Down Sequence
the external sense resistor is monitored by the active current limit (ACL) amplifier and the electronic circuit breaker
(ECB) comparator. An overcurrent condition results in the
current being limited by the ACL amplifier. During current
limiting, the ECB is activated and initiates a chain of logic
and timing events to handle the fault.
When ON1 or ON2 is pulled high, the corresponding GATE
pin is pulled to ground by 1.5mA. With the MOSFET off,
the load current discharges the load capacitor. Figure 4
shows VCC1 supply turning off by pulling ON1 high with
RLOAD1 = 4.7Ω discharging CLOAD1 = 150μF.
Figure 5 illustrates the LTC4224’s response to an overcurrent
condition on one supply output. Start-up and overcurrent
control for the two supplies are independent. Before time
point t1, the ON pin is high and the part is in reset. When
the ON pin goes low, a 10ms debounce delay is started.
After 10ms (time point t2), the external MOSFET is turned
on by charging GATE with 10μA. The load capacitor starts
to charge up and the output voltage increases. At the same
Overcurrent Fault
The LTC4224 features an adjustable current limit with circuit
breaker function that protects external MOSFETs against
short circuits or excessive load current. The voltage across
ON
VOUT
ILIMIT
IOUT
ILIMIT
FAULT
5ms START-UP
10ms DEBOUNCE DELAY BLANKING DELAY
RESET
t1
t2
OVERCURRENT 5ms
ECB BLANKING DELAY 5ms ECB Arm
IDLE
t3
t4
t5
t6
422412 F05
Figure 5. Fault Handling Sequence
422412fa
8
LTC4224-1/LTC4224-2
APPLICATIONS INFORMATION
GATE1
5V/DIV
ON1
2V/DIV
FAULT
5V/DIV
VOUT1
5V/DIV
IOUT1
1A/DIV
IOUT1
1A/DIV
GATE1
5V/DIV
5ms/DIV
2ms/DIV
422412 F06
Figure 7. Overcurrent Fault on Output
Figure 6. Start-Up with Short at Output
time, a 5ms start-up blanking delay begins during which
the circuit breaker is not allowed to latchoff the MOSFET.
If the ECB is tripped at the end of 5ms (time point t3), the
MOSFET is latched off by pulling GATE down with 1.5mA
and FAULT is latched low. The waveform in Figure 6 shows
an unsuccessful start-up due to a short circuit at the output.
To ensure start-up, the load capacitor must be charged
up sufficiently to exit current limit before the end of the
5ms blanking delay. For large load capacitors, it may be
necessary to connect an external capacitor from GATE to
GND as described in the Turn-On Sequence section.
After start-up, any transient overcurrent faults lasting
less than 100μs are ignored. Any overcurrent condition
lasting more than 100μs will initiate the 5ms ECB blanking delay (time point t4). After the ECB blanking delay,
the ECB is armed for the following 5ms (time point t5 to
t6). Any 100μs overcurrent pulse during this time latches
off the MOSFET. In summary, for 5ms to 10ms after a
100μs or greater overcurrent fault is detected, a second
100μs fault condition causes the MOSFET to latchoff. If
no overcurrent condition is detected during this time, the
part re-enters the IDLE state and another blanking delay
following an overcurrent condition is again required before
the MOSFET latches off. Figure 7 shows how the output
latches off following an overcurrent fault.
During a severe short-circuit (see Figure 8), the output load
current can briefly surge to tens of amperes. The LTC4224
rapidly brings the current under control by discharging
422412 F07
GATE2
5V/DIV
VOUT2
5V/DIV
IOUT2
8A/DIV
0.5μs/DIV
422412 F08
Figure 8. Severe Short-Circuit on Output
the MOSFET’s gate with 125mA towards ground. After a
short delay, the ACL amplifier regulates the gate voltage
until the ECB trips at the end of 5ms.
Undervoltage Fault
An undervoltage fault occurs if either VCC1 or VCC2 falls
below 0.8V for longer than 8μs. This turns off the affected
supply’s switch by discharging GATE with 1.5mA and
clears its fault latch. An undervoltage fault on one supply
does not affect the operation of the other supply. If VCC,
the higher of VCC1 and VCC2, falls below 2.4V for more
than 12μs, all supply switches are turned off and all fault
latches are cleared.
422412fa
9
LTC4224-1/LTC4224-2
APPLICATIONS INFORMATION
If there is significant supply lead inductance, a severe
output short may collapse the input to ground before the
LTC4224 can bring the current under control. In this case,
the undervoltage lockout activates after an 8μs filter delay,
and the GATE is pulled down by 1.5mA.
Resetting Faults
Following an overcurrent fault, the LTC4224-1 latches
off while the LTC4224-2 automatically restarts after a
four second cool down period. An overcurrent fault on
either supply causes the ECB for that supply to turn off
the MOSFET and pull the FAULT pin low. Faults are reset
by pulling the ON pin high for at least 20μs, after which
the FAULT pin releases and the turn-on sequence begins.
Taking the lower supply below VCCLO(UVL) clears only that
supply’s fault and the turn-on sequence commences immediately. Pulling the higher supply below VCC(UVL) clears
both supplies’ faults and the turn-on sequence begins after
a 160ms UV turn-on delay. When both supplies are above
2.5V, either supply going low only resets its own fault.
For the auto-retry version (LTC4224-2), if the fault is not
cleared within four seconds, the latched fault will be cleared
automatically. FAULT will go high and the turn-on sequence
will begin. A persistent fault results in an auto-retry duty
cycle of about 0.1%. Figure 9 shows an auto-retry sequence
as a result of an overcurrent fault.
Gate Pin Voltage
The gate drive is compatible with logic level MOSFETs, but
caution is required if one supply is low. The guaranteed
range of gate drive is 4.5V to 7V, with a typical value of
5.5V. Each GATE pin is clamped with respect to VCC, the
higher of the two input supplies. When VCC is at 5V, both
GATE pins can be as high as 12V above ground. If the
lower supply is at 0V, the gate-to-source voltage of its
MOSFET can be 12V. In such applications, MOSFETs with
gate-to-source breakdown ratings of 12V or greater are
recommended.
Active Current Loop Compensation
The active current loop is compensated by the parasitic
capacitance of the external MOSFET. No further compensation components are normally required. In the case where a
MOSFET with less than 600pF of gate capacitance is chosen,
a 600pF compensation capacitor connected between the
GATE pin and ground may be required.
Supply Transient Protection
In applications where the supply inputs are fed directly
from the regulated output of the backplane supply, bulk
bypassing assures a spike-free operating environment.
In other applications where bulk bypassing is located far
from the LTC4224, spikes generated during output shortcircuit events could exceed the absolute maximum ratings
for VCC. To minimize such spikes, use wider traces or
heavier trace plating to reduce the power trace inductance.
FAULT
5V/DIV
R2
0.010Ω
Q2
FDS6911
VCC2
IOUT
1A/DIV
+
VCC2 SENSE2
Z1
SMAJ5.0A
RSNUB
10Ω
CSNUB
0.1μF
GATE
2V/DIV
1s/DIV
VOUT
CLOAD2
GATE2
LTC4224
GND
422412 F10
422412 F09
Figure 9. Auto-Retry After Overcurrent Fault
Figure 10. Input Supply Transient Protection
Network for Applications without Input Capacitance
422412fa
10
LTC4224-1/LTC4224-2
APPLICATIONS INFORMATION
VCC2
1
SENSE2 10
2
VCC2 9
3
GATE2 8
4
GND 7
5
6
LTC4224
RSNUB
Z1
SNUBBER
NETWORK
CSNUB
VIAS TO
GND PLANE
422412 F11
Figure 11. Recommended Layout for Input
Supply Transient Protection Network
Also, bypass locally with a 10μF electrolytic and 100nF
ceramic, or alternatively clamp the input with a transient
voltage suppressor (Z1) as shown in Figure 10. A 10Ω,
100nF snubber damps the response and eliminates ringing. A recommended layout of the transient protection
devices Z1, RSNUB and CSNUB around the LTC4224 is
shown in Figure 11.
PCB Layout Considerations
For proper operation of the LTC4224’s electronic circuit
breaker, Kelvin connections to the sense resistors are
strongly recommended. The PCB layout should be balanced
and symmetrical to minimize wiring errors. In addition, the
3.3V
5V
R2
R1
8
11
5
2
6
1
9
7
8
10
PCB layout for the sense resistors and the power MOSFETs
should include good thermal management techniques for
optimal device power dissipation. A recommended PCB
layout for the sense resistors and the power MOSFET
around the LTC4224 is illustrated in Figure 12. Note that
it is important to keep the trace from the LTC4224’s GATE
pin to the FDS6911’s gate short.
In Hot Swap applications where load currents can be 10A,
wide PCB traces are recommended to minimize resistance
and temperature rise. The suggested trace width for 1oz
copper foil is 0.03" for each ampere of DC current to keep
PCB trace resistance, voltage drop and temperature rise to
a minimum. Note that the sheet resistance of 1oz copper
foil is approximately 0.5mΩ/square and voltage drops
due to trace resistances add up quickly in high current
applications.
In most applications, it is necessary to use plated-through
vias to make circuit connections from component layers to
power and ground layers internal to the PCB. For 1oz copper foil plating, a general rule is 1A of DC current per via.
Consult your PCB fabrication facility for design rules
pertaining to other plating thicknesses.
Design Example
As a design example, consider the following specifications:
VCC1 = 5V, VCC2 = 3.3V, ILOAD1(MAX) = 1A, ILOAD2(MAX) = 2A,
CLOAD1 = CLOAD2 = 150μF (see Figure 1).
First, select the sense resistor for each supply. Calculate
the R1 and R2 values based on the maximum load current and the minimum circuit breaker threshold limit,
ΔVSENSE(CB)(MIN).
If a 1% tolerance is assumed for the sense resistors, then
the following values of resistance should suffice:
FDS6911
3
4
3
5
2
4
6
1
7
LTC4224
BOTTOM SIDE
TOP SIDE
422412 F12
Figure 12. Recommended Layout for
Power MOSFET and Sense Resistors
Table 2. Sense Resistor Values
SUPPLY VOLTAGE
RSENSE (1%)
ITRIP(MIN)
ITRIP(MAX)
5V
15mΩ
1.49A
1.85A
3.3V
10mΩ
2.23A
2.78A
For proper operation, ITRIP(MIN) must exceed the maximum load current with margin, so RSENSE1 = 15mΩ and
RSENSE2 = 10mΩ should suffice for the VCC1 and VCC2
supplies respectively.
422412fa
11
LTC4224-1/LTC4224-2
APPLICATIONS INFORMATION
Next, assume that there is no load current at start-up,
and calculate the inrush current required to charge the
load capacitor. As there is no gate capacitor, the supplies
start-up in current limit. Compute the time, tSU, it takes
to fully charge the load capacitor:
t SU =
VCC • CLOAD
ITRIP
Table 3 lists the worst-case tSU values assuming 30%
tolerance for load capacitances.
Table 3. Worst-Case tSU
VOLTAGE SUPPLY
tSU(MIN)
tSU(MAX)
5V
0.53ms
0.65ms
3.3V
0.23ms
0.29ms
The start-up ECB blanking delay is guaranteed to be at least
2.5ms, which is longer than the tSU tabulated in Table 3.
Hence, both supplies can start up successfully.
Next, verify that the thermal ratings of the selected external
MOSFETs are not exceeded during power-up or an output
short-circuit. Assuming the MOSFET dissipates power only
due to inrush current charging the load capacitor, the energy
dissipated in the MOSFET during power-up is the same
as that stored in the load capacitor after power-up. The
average power dissipated in the MOSFET is given by:
PAVG =
The worst-case PAVG is calculated to be 4.6W for both the 5V
supply and the 3.3V supply. In this example, the FDS6911
MOSFET offers a good solution. Since this MOSFET is a dual
N-channel in a single SO8 package, it must be able to tolerate
the combined power dissipation of both supplies during
the tSU start-up time. The increase in steady-state junction
temperature due to power dissipated in the MOSFET is
ΔT = PAVG•ZTH where ZTH is the thermal impedance.
Under this condition, the FDS6911 datasheet’s Transient
Thermal Impedance plot indicates that the junction temperature will increase by 6.4°C using ZTHJC = 0.7°C/W
(single pulse). The FDS6911’s on-resistance is 17mΩ at
VGS = 4.5V, 25°C.
The magnitude of the power pulse that results during a
severe overload is calculated to be 9.25W for the 5V supply and 9.2W for the 3.3V supply under the worst case
conditions. Assuming a worst-case circuit breaker timeout
period of 7.5ms, the junction temperature will increase by
25°C, with one supply short-circuited. If both supplies are
short-circuited, the junction temperature will increase by
50°C in the worst-case. During auto-retry (LTC4224-2), in
the event of persistent faults at both supplies, the ample
four second cooling delay limits the increase in junction
temperature to 50°C. The SOA curves of the FDS6911
indicate that the above conditions are safe.
CLOAD • VOUT 2
2 • t SU
422412fa
12
LTC4224-1/LTC4224-2
TYPICAL APPLICATION
5V and 3.3V Card Resident Application
R1
0.004Ω
Q1
Si7336ADP
5V
RSNUB1
10Ω
CSNUB1
100nF
Z1
R2
0.004Ω
3.3V
RSNUB2
10Ω
CSNUB2
100nF
Z2
R3
10k
VCC1
PWRFLT
FAULT
PWREN
ON1
SENSE1
VCC2
SENSE2
5V
5A
Q2
Si7336ADP
GATE1
3.3V
5A
GATE2
LTC4224
ON2
GND
GND
BACKPLANE
CONNECTOR
CARD
CONNECTOR
Z1: SMAJ6.5A
Z2: SMAJ5.0A
422412 TA02
Hot Swap Application for Two Add-In Cards
R1
0.004Ω
Q1
Si7336ADP
5V
PRSNT1
R3
10k
VCC1
SENSE1
GATE1
FAULT
ON1
LTC4224
BACKPLANE
CONNECTOR1
CARD
CONNECTOR1
BACKPLANE
CONNECTOR2
CARD
CONNECTOR2
ON2
GND
VCC2
5V
5A
SENSE2
GATE2
PRSNT2
R2
0.004Ω
Q2
Si7336ADP
5V
5A
422412 TA03
422412fa
13
LTC4224-1/LTC4224-2
PACKAGE DESCRIPTION
DDB Package
10-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1722)
0.64 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
R = 0.05
TYP
R = 0.115
TYP
6
0.40 ± 0.10
10
0.70 ±0.05
2.55 ±0.05
1.15 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
2.39 ±0.05
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
2.00 ±0.10
(2 SIDES)
0.75 ±0.05
0.64 ± 0.05
(2 SIDES)
5
0.25 ± 0.05
0 – 0.05
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
1
(DDB10) DFN 0905 REV Ø
0.50 BSC
2.39 ±0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
422412fa
14
LTC4224-1/LTC4224-2
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.497 ± 0.076
(.0196 ± .003)
REF
0° – 6° TYP
GAUGE PLANE
1 2 3 4 5
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS) 0307 REV E
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
422412fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC4224-1/LTC4224-2
TYPICAL APPLICATION
X2/XENPAK Hot Swap Application
R1
0.010Ω
FDS6911
APS
2A
APS
Q1
BULK SUPPLY
BYPASS CAPACITOR
R2
0.010Ω
3.3V
2A
3.3V
BULK SUPPLY
BYPASS CAPACITOR
Q2
R3
390
VCC1
SENSE1
VCC2
SENSE2
GATE1 GATE2
ON1
D1
LTC4224
FAULT
ON2
1k
GND
GND
APS: 1V TO 1.8V
CONNECTOR
PLUG-IN
CARD
422412 TA04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1421
Two Channel Hot Swap Controller
Operates from 3V to 12V and Supports –12V
LTC1645
Dual Channel Hot Swap Controller
Operates from 3V to 12V, Power Sequencing
LTC1647
Dual Channel Hot Swap Controller
Operates from 2.7V to 16.5V, Separate ON Pins to Sequence
LTC4210
Single Channel Hot Swap Controller
Operates from 2.7V to 16.5V, Active Current Limiting
LTC4211
Single Channel Hot Swap Controller
2.5V to 16.5V, Multifunction Current Control
LTC4212
Single Channel How Swap Controller
2.5V to 16.5V, Multifunction Current Control with Power Good Input
LTC4213
Electronic Circuit Breaker
Operates from 2.3V to 6V, No RSENSE™ Electronic Circuit Breaker
LTC4215
Single Channel Hot Swap Controller
Operates from 2.9V to 15V, I2C Compatible Monitoring
LTC4216
Single Channel Hot Swap
Operates from 0V to 6V
LTC4218
Single Channel Hot Swap Controller
Operates from 2.9V to 26.5V, Adjustable, 5% Accurate (15mV) Current Limit
LTC4221
Dual Channel Hot Swap Controller
Operates from 1V to 13.5V, Multifunction Current Control
LTC4223
Dual Supply Hot Swap Controller
Controls 12V and 3.3V for AMC and μTCA
422412fa
16 Linear Technology Corporation
LT 1108 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
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